CN116960012A - Method for distinguishing dark current reasons by WAT layer - Google Patents
Method for distinguishing dark current reasons by WAT layer Download PDFInfo
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- CN116960012A CN116960012A CN202211425496.8A CN202211425496A CN116960012A CN 116960012 A CN116960012 A CN 116960012A CN 202211425496 A CN202211425496 A CN 202211425496A CN 116960012 A CN116960012 A CN 116960012A
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 238000012545 processing Methods 0.000 claims abstract description 28
- 238000005516 engineering process Methods 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 24
- 238000000407 epitaxy Methods 0.000 claims description 23
- 238000002513 implantation Methods 0.000 claims description 21
- 238000001259 photo etching Methods 0.000 claims description 21
- 230000007547 defect Effects 0.000 claims description 16
- 238000002347 injection Methods 0.000 claims description 11
- 239000007924 injection Substances 0.000 claims description 11
- 238000000151 deposition Methods 0.000 claims description 9
- 239000000758 substrate Substances 0.000 claims description 9
- 238000000137 annealing Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 claims description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical group [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 238000004140 cleaning Methods 0.000 claims description 3
- 238000007599 discharging Methods 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 238000001883 metal evaporation Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 238000002474 experimental method Methods 0.000 abstract description 6
- 238000012937 correction Methods 0.000 abstract description 2
- 238000004904 shortening Methods 0.000 abstract description 2
- 230000001550 time effect Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 19
- 238000013461 design Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000001459 lithography Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001066 destructive effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
Abstract
The invention discloses a method for distinguishing dark current reasons by a WAT layer, which comprises the following steps: processing at least one group of WAT devices on the wafer, wherein the WAT devices comprise a first WAT device WAT-1 and at least one second WAT device, the first WAT device WAT-1 is processed by adopting the same processing technology of an active device, the second WAT device is processed by adopting the same processing technology of the active device and intentionally lacks one structure, and the second WAT devices are different in structure; the WAT device is tested for high dark current. The reason for the dark current of the active device is distinguished according to the high and low layers of the dark current on different WAT devices. The invention can instantly identify the main reason causing the high dark current of the active device, thereby finding out the corresponding process steps, aiming at the process steps, implementing correction and improvement measures, shortening the time effect of improving the yield, and greatly reducing the experiment cost without implementing complex DOE experiments.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a method for distinguishing dark current causes of a WAT layer.
Background
Dark current (otherwise known as leakage current) is an important device parameter when fabricating active devices on semiconductors. It is desirable to reduce the dark current of the device as much as possible, and many potential factors may cause high dark current during the process steps of manufacturing the device, but an effective monitoring method cannot be found in the inline monitor of each process step, and the electrical test is generally performed until the complete process is completed, so that the dark current result is obtained. Once the dark current is high, even with advanced destructive analysis (such as SEM or TEM), it is difficult to immediately identify the cause of the high dark current. Generally, a liquid crystal hot spot detection technique (Liquid Crystal Hot Spot Detection) is used to find the rough location of the dark current, but it is difficult to accurately determine the actual process steps that result in device defects, and solve the problem.
WAT (Wafer Acceptance Test), also called wafer acceptance test, is to determine whether the wafer is in specification. The WAT inspection step is performed after wafer pre-production is completed and before wafer dicing and packaging. The main design of WAT comprises: 1) Devices identical to the products; 2) Being able to intercept individual important parameters (e.g. contact resistance value, sheet resistance value); 3) Judging whether the key process is abnormal (such as metal wire breakage); 4) And process windows are collected to design future new generation devices, etc. But rarely, the WAT step directly separates the device to cause the technical problem of unqualified device characteristics.
Disclosure of Invention
The invention provides a method for distinguishing the cause of dark current in a WAT layer, which has the advantages that the main cause of high dark current of an active device can be distinguished in real time in the WAT stage of a wafer, so that corresponding process steps are found, corrective improvement measures are implemented aiming at the process steps, the timeliness of improving the yield can be shortened, complex DOE experiments are not needed, and the experimental cost is greatly reduced.
The technical scheme of the invention is as follows:
a method for distinguishing dark current causes by a WAT layer, comprising:
processing at least one group of WAT devices on the wafer, wherein the WAT devices comprise a first WAT device WAT-1 and at least one second WAT device, the first WAT device WAT-1 is processed by adopting the same processing technology of an active device, the second WAT device is processed by adopting the same processing technology of the active device and intentionally lacks one structure, and the second WAT devices are different in structure;
the WAT device is tested for high dark current.
Further, the active device includes a receiver, modulator, amplifier, heater, temperature sensor, piN, or APD fabricated on the wafer.
Further, the reasons for high dark current of the active device include epitaxy defects, waveguide etching damage, metal residues, dielectric layer stress and PIN injection defects, which occur on the epitaxial cavity pattern, waveguide pattern, contact hole pattern, dielectric layer and PIN structure of the active device, respectively.
Furthermore, the second WAT device is provided with four WAT-2, WAT-3, WAT-4 and WAT-5, and the epitaxial cavity pattern, the waveguide pattern, the contact hole pattern and the dielectric layer structure are respectively absent at the processing time.
Further, when the first WAT device has high dark current, the active device has high dark current;
the second WAT device WAT-2 lacks epitaxy, and if epitaxy is the primary cause of dark current, the dark current of WAT-2 will be relatively low;
the second WAT device WAT-3 lacks a ridge waveguide, and if etching damage is the main cause of dark current, the dark current of WAT-3 will be relatively low;
the second WAT device WAT-4 lacks a contact hole pattern, if metal residue is not the main cause of dark current, the path of the dark current is blocked, and the dark current of WAT-4 is relatively low;
the second WAT device WAT-5 lacks a dielectric layer on the waveguide so that if the dielectric layer is the primary cause of dark current, the dark current of WAT-5 will be relatively low.
Further, the reason for the dark current of the active device is distinguished according to the high and low layers of the dark current on different WAT devices:
1) WAT devices WAT-1, WAT-3 and WAT-5 have high dark current, but WAT-2 and WAT-4 have low dark current, so that the main reason for the dark current is epitaxy defect;
2) WAT devices WAT-1, WAT-2 and WAT-5 have high dark current, but WAT-3 and WAT-4 have low dark current, and the main reason for the dark current is waveguide etching line ;
3) WAT devices WAT-1, WAT-2, WAT-3, WAT-4 and WAT-5 all have high dark current, and the main reason for the dark current is metal residue;
4) WAT devices WAT-1, WAT-2 and WAT-3 have high dark current, but WAT-4 and WAT-5 have low dark current, and the main reason for the dark current is the stress of a dielectric layer;
5) WAT devices WAT-1, WAT-2, WAT-3 and WAT-5 have high dark current, but WAT-4 has low dark current, and the dark current can be judged by using a discharging method, and the main reason for the dark current is PIN injection defect.
Further, the processing technology of the active device comprises the following steps: 1) Forming an epitaxial cavity pattern on an SOI wafer substrate; 2) Growing epitaxy; 3) Forming a ridge waveguide pattern; 4) P-type injection; 5) N-type injection; 6) Depositing a dielectric layer; 7) Forming a contact hole pattern; 8) Depositing metal; 9) Forming a metal pattern; 10) Depositing a dielectric layer; 11) Forming a bonding pad window pattern.
Further, the step 1) forms an epitaxial cavity pattern on the SOI wafer substrate, including: and photoetching the epitaxial cavity, etching the substrate and removing the photoresist.
Further, the step 2) is to grow epitaxy, wherein the epitaxy is germanium-silicon, pure germanium, indium phosphide, or gallium arsenide.
Further, the step 3) of forming a ridge waveguide pattern includes: and photoetching the ridge waveguide, etching epitaxy, and removing photoresist.
Further, the step 4) of P-type implantation includes: p-type implantation photoetching, P-type implantation, photoresist removal and annealing.
Further, the step 5) of N-type implantation includes: and (3) carrying out N-type implantation photoetching, N-type implantation, photoresist removal and annealing.
Further, the P-type implantation in the step 4) is replaced by P-type diffusion; and step 5), N-type implantation is replaced by N-type diffusion.
Further, the step 7) of forming a contact hole pattern includes: and photoetching the contact hole, etching the dielectric layer and removing the photoresist.
Further, the step 9) forms a metal pattern, including: and (5) metal photoetching, etching the metal layer and removing the photoresist.
Further, the step 9) forms a metal pattern, instead of metal lift-off, the metal lift-off includes: metal photoetching, metal evaporation, stripping and cleaning.
Further, step 11) forming a pad window pattern, including: and photoetching a welding pad window, etching the dielectric layer, and removing the photoresist.
In summary, the beneficial effects of the invention are as follows: the invention can instantly layer out the main reason causing the high dark current of the active device in the wafer WAT stage, thereby finding out the corresponding process steps, aiming at the process steps, implementing correction and improvement measures, shortening the time effect of improving the yield, and greatly reducing the experiment cost without implementing complex DOE experiment.
Drawings
FIG. 1 is a schematic diagram of an active device after processing in step 1), wherein FIG. 1a is a cross-sectional view and FIG. 1b is a schematic diagram of a lithographic plate design;
FIG. 2 is a schematic diagram of an active device of the present invention after processing in step 2);
FIG. 3 is a schematic diagram of an active device after processing in step 3), wherein FIG. 3a is a cross-sectional view and FIG. 3b is a schematic diagram of a lithographic plate design;
FIG. 4 is a schematic diagram of an active device after processing in step 4), wherein FIG. 4a is a cross-sectional view and FIG. 4b is a schematic diagram of a lithographic plate design;
FIG. 5 is a schematic diagram of an active device after processing in step 5) according to the present invention, wherein FIG. 5a is a cross-sectional view and FIG. 5b is a schematic diagram of a lithographic plate design;
FIG. 6 is a schematic diagram of an active device of the present invention after processing in step 6);
FIG. 7 is a schematic diagram of an active device after processing in step 7), wherein FIG. 7a is a cross-sectional view and FIG. 7b is a schematic diagram of a lithographic plate design;
FIG. 8 is a schematic diagram of an active device of the present invention after processing in step 8);
FIG. 9 is a schematic diagram of an active device after processing in step 9) according to the present invention, wherein FIG. 9a is a cross-sectional view and FIG. 9b is a schematic diagram of a lithographic plate design;
FIG. 10 is a schematic diagram of an active device of the present invention after processing at step 10);
FIG. 11 is a schematic diagram of an active device after processing in step 11), wherein FIG. 11a is a cross-sectional view and FIG. 11b is a schematic diagram of a lithographic plate design;
FIG. 12 is a schematic diagram of an active device dark current path in the present invention;
FIG. 13 is a cross-sectional illustration of device WAT-2 of the present invention;
FIG. 14 is a cross-sectional schematic view of device WAT-3 of the present invention;
FIG. 15 is a cross-sectional illustration of device WAT-4 of the present invention;
FIG. 16 is a cross-sectional view of device WAT-5 of the present invention.
Detailed Description
The following describes in detail the embodiments of the present invention with reference to the drawings.
Examples: a WAT layer is used for the reason that the layer causes the high dark current of an active device on a silicon photon, and in the silicon photon process, the WAT layer comprises an active device such as a receiver, a modulator, an amplifier, a heater, a temperature sensor, a Pin or an APD, and the like, wherein the possible reason for the high dark current of the active device is not an epitaxial defect, the waveguide etching is a defect , metal residues, dielectric layer stress and PIN injection defect, and the five are main reasons for the high dark current of the active device in the process.
In the silicon photonics process, referring to fig. 1-11, the active device fabrication process includes the steps of:
1) Forming an epitaxial cavity pattern on an SOI wafer substrate, comprising: etching the substrate by epitaxial cavity lithography (comprising photoresist coating, exposure and development) to remove the photoresist;
2) Growing epitaxy, wherein the epitaxy is germanium-silicon, pure germanium, indium phosphide or gallium arsenide;
3) Forming a ridge waveguide pattern, including ridge waveguide photoetching (including photoresist coating, exposure and development), etching epitaxy, and removing photoresist;
4) P-type implant, comprising: p-type injection lithography (comprising photoresist coating, exposure and development), P-type injection, photoresist removal and annealing;
5) An N-type implant comprising: n-type implantation lithography (including photoresist coating, exposure, development), N-type implantation, photoresist removal, annealing;
the P-type implantation in step 4) can be replaced by P-type diffusion; the N-type implantation in step 5) is replaced by N-type diffusion;
6) Depositing a dielectric layer;
7) Forming a contact hole pattern, comprising: photoetching the contact hole, etching the dielectric layer, and removing photoresist;
8) Depositing metal;
9) Forming a metal pattern, comprising: etching the metal layer by metal photoetching, and removing photoresist;
step 9) forming a metal pattern, alternatively metal stripping, the metal stripping comprising: metal photoetching, metal evaporation, stripping and cleaning.
10 A) depositing a dielectric layer;
11 Forming a pad window pattern, comprising: and photoetching a welding pad window, etching the dielectric layer, and removing the photoresist.
It has been mentioned that possible reasons for high dark current in silicon photonics processes include: 1) Defects of epitaxy; 2) The waveguide etch would ; 3) Metal residue; 4) Dielectric layer stress; 5) The PIN is injected into the defect. The dark current paths caused by the different causes are shown by arrows in fig. 12, and numbers in the arrows correspond to the causes of the high dark current, respectively, described above.
The method for distinguishing the dark current cause by the WAT layer comprises the following steps:
processing at least one group of WAT devices on a wafer, wherein one group of WAT devices comprises a first WAT device WAT-1 and at least four second WAT devices WAT-2, WAT-3, WAT-4 and WAT-5, the first WAT device WAT-1 is processed by adopting the same processing technology of an active device, the second WAT devices are processed by adopting the same processing technology of the active device and intentionally lack one structure, and different second WAT devices lack different structures; and the second WAT devices WAT-2, WAT-3, WAT-4 and WAT-5 are respectively free of epitaxial cavity patterns, waveguide patterns, contact hole patterns and dielectric layer structures at the processing time.
The first WAT device WAT-1 is a complete device and comprises the above process steps and patterns.
The second WAT devices WAT-2, WAT-3, WAT-4, WAT-5 belong to the specific WAT devices.
The device WAT-2 contains complete process steps and patterns, but does not include epitaxial cavity patterns. That is, step 1) is still performed to form an epitaxial cavity pattern on the wafer substrate, but no epitaxial cavity pattern is formed on the device WAT-2. The resulting device is shown in cross-section in fig. 13.
The device WAT-3 contains complete process steps and patterns, but does not include ridge waveguide patterns. I.e. step 3) is still performed to form a ridge waveguide pattern, but no waveguide pattern is present on the device WAT-3. The resulting device is shown in cross-section in fig. 14.
The device WAT-4 includes the above process steps and patterns, but does not include a contact hole pattern. That is, step 7) is still performed to form a contact hole pattern, but no contact hole pattern is formed on the device WAT-4. The resulting device is shown in cross-section in fig. 15.
The device WAT-5 includes the above process steps and patterns, and additionally, a pad window pattern is added to the ridge waveguide. That is, in performing step 11) to form a pad window pattern, a pad window pattern is added to the WAT-5 ridge waveguide at a position above the WAT. In the etching step of forming the pad window, the dielectric layer on the waveguide is almost etched away, and the cross-sectional view of the finally formed device is shown in fig. 16.
The WAT device is tested for high dark current.
When no high current exists on the active device, the fact that all process parameters are correct is indicated, and the device WAT-1 processed by the same process also has no high dark current.
When there is a high dark current on the first WAT device, there is a high dark current on the active device, at which time:
the second WAT device WAT-2 lacks epitaxy, and if epitaxy is the primary cause of dark current, the dark current of WAT-2 will be relatively low;
the second WAT device WAT-3 lacks a ridge waveguide, and if etching damage is the main cause of dark current, the dark current of WAT-3 will be relatively low;
the second WAT device WAT-4 lacks a contact hole pattern, if metal residue is not the main cause of dark current, the path of the dark current is blocked, and the dark current of WAT-4 is relatively low;
the second WAT device WAT-5 lacks a dielectric layer on the waveguide so that if the dielectric layer is the primary cause of dark current, the dark current of WAT-5 will be relatively low.
The reason for the dark current of the active device is distinguished according to the high and low layers of the dark current on different WAT devices:
1) WAT devices WAT-1, WAT-3 and WAT-5 have high dark current, but WAT-2 and WAT-4 have low dark current, so that the main reason for the dark current is epitaxy defect;
2) WAT devices WAT-1, WAT-2 and WAT-5 have high dark current, but WAT-3 and WAT-4 have low dark current, and the main reason for the dark current is waveguide etching line ;
3) WAT devices WAT-1, WAT-2, WAT-3, WAT-4 and WAT-5 all have high dark current, and the main reason for the dark current is metal residue;
4) WAT devices WAT-1, WAT-2 and WAT-3 have high dark current, but WAT-4 and WAT-5 have low dark current, and the main reason for the dark current is the stress of a dielectric layer;
5) WAT devices WAT-1, WAT-2, WAT-3 and WAT-5 have high dark current, but WAT-4 has low dark current, and the dark current can be judged by using a discharging method, and the main reason for the dark current is PIN injection defect.
The reasons for the high dark current and the dark current on the devices WAT-1, WAT-2, WAT-3, WAT-4 and WAT-5 are corresponding to the following table. According to the following table, the reasons for high dark current can be quickly distinguished by detecting the dark current on the devices WAT-1, WAT-2, WAT-3, WAT-4 and WAT-5, so that corresponding process steps are found, corrective improvement measures are implemented for the process steps, the timeliness of improving the yield can be shortened, complex DOE experiments are not needed, and the experimental cost is greatly reduced.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and improvements could be made by those skilled in the art without departing from the inventive concept, which falls within the scope of the present invention.
Claims (17)
1. A method for distinguishing dark current causes by a WAT layer, comprising:
processing at least one group of WAT devices on the wafer, wherein the WAT devices comprise a first WAT device WAT-1 and at least one second WAT device, the first WAT device WAT-1 is processed by adopting the same processing technology of an active device, the second WAT device is processed by adopting the same processing technology of the active device and intentionally lacks one structure, and the second WAT devices are different in structure;
the WAT device is tested for high dark current.
2. The method of claim 1, wherein the active device comprises a receiver, modulator, amplifier, heater, temperature sensor, piN, or APD fabricated on a wafer.
3. The method of claim 1 or 2, wherein the high dark current causes of the active device include epitaxy defects, waveguide etch damage, metal residues, dielectric layer stress, and PIN implantation defects, respectively, on the epitaxial cavity pattern, waveguide pattern, contact hole pattern, dielectric layer, and PIN structure of the active device.
4. The method for distinguishing dark current causes of WAT layers according to claim 3, wherein the second WAT device is provided with four WAT-2, WAT-3, WAT-4, WAT-5, each of which is free of epitaxial cavity patterns, waveguide patterns, contact hole patterns, and dielectric layer structures at the time of processing.
5. The method of claim 4, wherein when there is a high dark current on the first WAT device, there is a high dark current on the active device;
the second WAT device WAT-2 lacks epitaxy, and if epitaxy is the primary cause of dark current, the dark current of WAT-2 will be relatively low;
the second WAT device WAT-3 lacks a ridge waveguide, and if etching damage is the main cause of dark current, the dark current of WAT-3 will be relatively low;
the second WAT device WAT-4 lacks a contact hole pattern, if metal residue is not the main cause of dark current, the path of the dark current is blocked, and the dark current of WAT-4 is relatively low;
the second WAT device WAT-5 lacks a dielectric layer on the waveguide so that if the dielectric layer is the primary cause of dark current, the dark current of WAT-5 will be relatively low.
6. The method for distinguishing dark current causes of WAT layers according to claim 5, wherein the causes of dark current of active devices are distinguished according to the high and low layers of dark current on different WAT devices:
1) WAT devices WAT-1, WAT-3 and WAT-5 have high dark current, but WAT-2 and WAT-4 have low dark current, so that the main reason for the dark current is epitaxy defect;
2) WAT devices WAT-1, WAT-2 and WAT-5 have high dark current, but WAT-3 and WAT-4 have low dark current, and the main reason for the dark current is waveguide etching line ;
3) WAT devices WAT-1, WAT-2, WAT-3, WAT-4 and WAT-5 all have high dark current, and the main reason for the dark current is metal residue;
4) WAT devices WAT-1, WAT-2 and WAT-3 have high dark current, but WAT-4 and WAT-5 have low dark current, and the main reason for the dark current is the stress of a dielectric layer;
5) WAT devices WAT-1, WAT-2, WAT-3 and WAT-5 have high dark current, but WAT-4 has low dark current, and the dark current can be judged by using a discharging method, and the main reason for the dark current is PIN injection defect.
7. The method of claim 6, wherein the processing of the active device comprises the steps of: 1) Forming an epitaxial cavity pattern on an SOI wafer substrate; 2) Growing epitaxy; 3) Forming a ridge waveguide pattern; 4) P-type injection; 5) N-type injection; 6) Depositing a dielectric layer; 7) Forming a contact hole pattern; 8) Depositing metal; 9) Forming a metal pattern; 10) Depositing a dielectric layer; 11) Forming a bonding pad window pattern.
8. The method of claim 7, wherein the step 1) of forming an epitaxial cavity pattern on the SOI wafer substrate comprises: and photoetching the epitaxial cavity, etching the substrate and removing the photoresist.
9. The method of claim 7, wherein the step 2) is to grow an epitaxy, the epitaxy is germanium-silicon, pure germanium, indium phosphide, or gallium arsenide.
10. The method for distinguishing dark current causes at WAT layer according to claim 7, wherein said step 3) forms a ridge waveguide pattern comprising: and photoetching the ridge waveguide, etching epitaxy, and removing photoresist.
11. The method of claim 7, wherein the step 4) P-type implantation comprises: p-type implantation photoetching, P-type implantation, photoresist removal and annealing.
12. The method of claim 7, wherein said step 5) of N-type implantation comprises: and (3) carrying out N-type implantation photoetching, N-type implantation, photoresist removal and annealing.
13. The method of claim 7, 11 or 12, wherein the step 4) P-type implantation is replaced by P-type diffusion; the N-type implantation in the step 5) is replaced by N-type diffusion.
14. The method for distinguishing dark current causes by WAT layer according to claim 7, wherein said step 7) forms a contact hole pattern comprising: and photoetching the contact hole, etching the dielectric layer and removing the photoresist.
15. The method for distinguishing dark current causes according to claim 7, wherein the step 9) forms a metal pattern, comprising: and (5) metal photoetching, etching the metal layer and removing the photoresist.
16. The method for distinguishing dark current causes in WAT layers according to claim 7 or 15, wherein said step 9) forms a metal pattern instead of metal lift-off, the metal lift-off comprising: metal photoetching, metal evaporation, stripping and cleaning.
17. The method of claim 7, wherein step 11) forming a pad window pattern comprises: and photoetching a welding pad window, etching the dielectric layer, and removing the photoresist.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202211425496.8A CN116960012A (en) | 2022-11-15 | 2022-11-15 | Method for distinguishing dark current reasons by WAT layer |
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| CN202211425496.8A CN116960012A (en) | 2022-11-15 | 2022-11-15 | Method for distinguishing dark current reasons by WAT layer |
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| CN116960012A true CN116960012A (en) | 2023-10-27 |
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| CN202211425496.8A Pending CN116960012A (en) | 2022-11-15 | 2022-11-15 | Method for distinguishing dark current reasons by WAT layer |
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