CN116954676A - Remote upgrade system, method and equipment for automobile controller and readable storage medium - Google Patents
Remote upgrade system, method and equipment for automobile controller and readable storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/544—Buffers; Shared memory; Pipes
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/54—Interprogram communication
- G06F9/547—Remote procedure calls [RPC]; Web services
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W8/00—Network data management
- H04W8/22—Processing or transfer of terminal data, e.g. status or physical capabilities
- H04W8/24—Transfer of terminal data
- H04W8/245—Transfer of terminal data from a network towards a terminal
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Abstract
The invention provides a remote upgrading system, a remote upgrading method, remote upgrading equipment and a readable storage medium of an automobile controller. The main control end is used for dividing the upgrade program into a plurality of data packets and sequentially transmitting the data packets to the first processor core. The first processor core is used for writing one received data packet into the shared memory, calling inter-core communication after writing, and receiving and writing the next data packet. The second processor core is used for reading the data packet from the shared memory after the inter-core communication is evoked, erasing the flash memory and writing the data packet into the flash memory. According to the invention, the operation of the data transmission part and the operation of the flash memory erasing part and the data writing part can be executed in parallel, so that the time is saved, and the execution efficiency of the controller is improved.
Description
Technical Field
The present invention relates to the field of remote upgrade technologies, and in particular, to a system, a method, an apparatus, and a readable storage medium for remote upgrade of an automobile controller.
Background
The remote upgrade (OTA) technology refers to a technology for remotely managing an automobile controller through a mobile communication network, and is simply implemented in three steps: firstly, uploading an upgrade program to a main control end, then the main control end wirelessly transmits the upgrade program to a controller end, and finally the controller end automatically updates software. The operations executed by the controller end comprise the steps of receiving upgrade data, erasing Flash memory (Flash), writing the upgrade data into the Flash memory and checking the Flash memory. At present, the operations of the controller end are sequentially executed, the next operation can be continuously executed after the last step is completed, the execution efficiency is low, and if the upgrading program is large, the time consumption is too long, so that the user experience is affected.
Disclosure of Invention
The invention mainly aims to provide a remote upgrading system, method and equipment for an automobile controller and a readable storage medium, and aims to solve the technical problems of low execution efficiency and long time consumption of a controller end during remote upgrading in the prior art.
In a first aspect, the present invention provides an automobile controller remote upgrade system, where the automobile controller remote upgrade system includes a main control end and a controller end, and the controller end includes a first processor core, a second processor core, a shared memory and a flash memory;
the main control end is used for dividing the upgrade program into a plurality of data packets and sequentially transmitting the data packets to the first processor core;
the first processor core is used for writing one received data packet into the shared memory, calling inter-core communication after writing is finished, and receiving and writing the next data packet;
the second processor core is used for reading the data packet from the shared memory after inter-core communication is evoked, erasing the flash memory and writing the data packet into the flash memory.
Further, in an embodiment, the master control end is configured to divide each compiled data block of the upgrade program into a plurality of data packets and sequentially send the data packets to the first processor core.
In one embodiment, the second processor core is further configured to verify the flash memory after writing the last data packet of each compiled data block into the flash memory.
Further, in an embodiment, the second processor core is further configured to record a breakpoint address after verification is completed;
the first processor core and the second processor core are also used for interrupting work when errors occur and feeding back error information to the main control end;
and the main control end is also used for sending the data packet to the first processor core again from the breakpoint address after receiving the error information.
Further, in an embodiment, the shared memory is divided into a plurality of memory units;
the first processor core is used for sequentially writing each received data packet into the idle memory unit in sequence and recording the number of the memory unit;
the second processor core is used for finding out the corresponding memory unit according to the number of the memory unit after the inter-core communication is evoked and reading the data packet in the memory unit;
the second processor core is further configured to empty the corresponding memory unit after the data packet is read.
Further, in an embodiment, the first processor core is further configured to receive and write the i+2th data packet after receiving and writing the i+1th data packet is completed, and the second processor core completes reading and writing the i+1th data packet, where i is a positive integer.
Further, in an embodiment, the first processor core invokes inter-core communication through a software interrupt.
In a second aspect, the present invention further provides a remote upgrade method for an automobile controller, which is applied to a remote upgrade system for an automobile controller including a main control end and a controller end, where the controller end includes a first processor core, a second processor core, a shared memory and a flash memory, and the remote upgrade method for an automobile controller includes:
the main control end divides the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core;
the first processor core writes one received data packet into the shared memory, and after the writing is finished, inter-core communication is evoked, and the next data packet is received and written;
and the second processor core reads the data packet from the shared memory after the inter-core communication is evoked, erases the flash memory and writes the data packet into the flash memory.
In a third aspect, the present invention further provides an automobile controller remote upgrade apparatus, where the automobile controller remote upgrade apparatus includes a processor, a memory, and an automobile controller remote upgrade program stored on the memory and executable by the processor, where the steps of the foregoing automobile controller remote upgrade method are implemented when the automobile controller remote upgrade program is executed by the processor.
In a fourth aspect, the present invention further provides a readable storage medium, where a remote upgrade program for an automobile controller is stored on the readable storage medium, where the remote upgrade program for an automobile controller implements the steps of the remote upgrade method for an automobile controller when executed by a processor.
The invention divides the upgrade program into a plurality of data packets, and distributes a first processor core to receive the data packets and write the data packets into the shared memory by utilizing inter-core communication means, and a second processor core reads the data packets from the shared memory and performs flash memory erasing and data writing. Therefore, the first processor core can perform flash memory erasing and data writing on the data packet which is written before when receiving and writing the subsequent data packet, namely, the operation of the data transmission part and the operation of the flash memory erasing and data writing part can be executed in parallel, so that the time is saved, and the execution efficiency of the controller end is improved.
Drawings
FIG. 1 is a schematic diagram of a remote upgrade system for an automobile controller according to an embodiment of the present invention;
FIG. 2 is a schematic diagram illustrating a workflow of a remote upgrade system for an automobile controller according to an embodiment of the present invention;
FIG. 3 is a timing diagram illustrating operations of a first processor core and a second processor core according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating operations of a first processor core and a second processor core according to another embodiment of the present invention;
FIG. 5 is a flowchart of a remote upgrade method of an automobile controller according to an embodiment of the invention;
fig. 6 is a schematic hardware structure of a remote upgrade apparatus for an automobile controller according to an embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In a first aspect, an embodiment of the present invention provides a remote upgrade system for an automobile controller.
Fig. 1 is a schematic structural diagram of a remote upgrade system of an automotive controller according to an embodiment of the present invention, and fig. 2 is a schematic workflow diagram of the remote upgrade system of the automotive controller according to an embodiment of the present invention.
Referring to fig. 1 and 2, in an embodiment, a remote upgrade system for an automobile controller includes a main control end and a controller end, where the controller end includes a first processor core, a second processor core, a shared memory, and a flash memory. The main control end is used for dividing the upgrade program into a plurality of data packets and sequentially transmitting the data packets to the first processor core. The first processor core is used for writing one received data packet into the shared memory, calling inter-core communication after writing, and receiving and writing the next data packet. The second processor core is used for reading the data packet from the shared memory after the inter-core communication is evoked, erasing the flash memory and writing the data packet into the flash memory.
The main control end is used for issuing an upgrade program, and the controller end is an automobile controller. In this embodiment, the automobile controller as the controller end adopts a processor with a multi-core architecture, and multiple cores share the same physical memory area, so as to realize sharing and communication of data. Inter-core communication refers to the process of information transfer and data exchange between different cores in a multi-core processor system, and refers to data exchange through a shared memory. The inter-core communication can fully utilize a mechanism provided by hardware, and the communication efficiency is high. Optionally, the first processor core invokes inter-core communication through a software interrupt.
In order to save the space of the shared memory, save the transmission time and meet the upper limit requirement of single transmission data, the main control end also needs to compress the data packet and then issue the data packet, the first processor core writes the compressed data packet into the shared memory, the second processor core needs to decompress the data packet after reading the compressed data packet, and then writes the decompressed data into the flash memory.
For example, when the remote upgrading system of the automobile controller upgrades the gateway controller, a Tbox (vehicle-mounted networking terminal) is a main control end, and the gateway controller is a controller end. The Tbox issues the upgrade procedure to the gateway via the uds protocol, the gateway receives and responds to the Tbox via the uds protocol, and the gateway tells the Tbox that it can receive the maximum value of the transmitted data packet (e.g., 512 bytes) each time when responding to 36 services. The Tbox divides the to-be-issued hex file into data packets with the maximum byte size according to the maximum value fed back by the gateway, and each data packet is compressed through a compression algorithm. The Tbox sends a plurality of data packets to a first processor core of the gateway controller in sequence, the first processor core writes one received data packet into the shared memory, communication between the cores is evoked after writing is finished, and the next data packet is received and written. After communication between cores is evoked, the second processor core of the gateway controller decompresses the data packet in the shared memory according to the instruction of the first processor core, and erases and writes the flash memory of the gateway controller.
In this embodiment, the upgrade program is divided into a plurality of data packets, and the inter-core communication means is used to allocate the first processor core to receive the data packets and write the data packets into the shared memory, and the second processor core reads the data packets from the shared memory and performs flash memory erasure and data writing. Therefore, the first processor core can perform flash memory erasing and data writing on the data packet which is written before when receiving and writing the subsequent data packet, namely, the operation of the data transmission part and the operation of the flash memory erasing and data writing part can be executed in parallel, so that the time is saved, and the execution efficiency of the controller end is improved.
In addition, the remote upgrade system of the automobile controller often requires that an upgrade data packet can be issued in the driving process, at this time, the flash memory of the automobile controller needs to be operated, and the operation time for reading/writing a large amount of flash memory data is long, if the flash memory is sequentially executed by a single core, that is, other real-time tasks need to be executed after the flash memory operation is completed, and the real-time performance of the system is affected. If the single core preempts execution, scheduling time among tasks needs to be planned. Moreover, the risk of flash operation is higher, and a higher operation priority is required, but other operations in the driving process may require a higher priority, which contradicts with the improvement of the flash operation priority. In this embodiment, the flash memory operation is performed in the second processor core, and the first processor core may perform other operations besides data transmission, so that the real-time performance of the system is not affected, complex scheduling planning is not required, and the problem of priority contradiction is not generated.
Further, in an embodiment, the master control end is configured to divide each compiled data block of the upgrade program into a plurality of data packets and sequentially send the data packets to the first processor core.
During compilation, a compiler will convert source code into machine code and organize the machine code into blocks (blocks). Each block typically contains an associated set of instructions and data. These blocks may be a combination of code and data for functions, global variables, constants, etc. For example, a typical "hex file" contains a plurality of compiled data blocks, each consisting of addresses and data. These data blocks may represent program code, variable initialization values, device configuration, etc. In this embodiment, the data packet is defined by taking the compiled data block as an object, which is helpful for orderly performing data transmission, data reading and data writing.
In one embodiment, the second processor core is further configured to verify the flash memory after writing the last packet of each compiled data block into the flash memory.
With continued reference to fig. 2, in this embodiment, the second processor core is further configured to verify the flash memory, and the compiled data block needs to be used as a whole during verification. Specifically, each time the second processor core writes a data packet into the flash memory, it needs to determine whether the data packet is the last data packet of the current compiled data block, and only after the last data packet of the current compiled data block is written, the flash memory is checked. It can be understood that while the second processor core checks the flash memory, the first processor core may perform receiving and writing of the data packet, that is, in this embodiment, the operation of the data transmission portion and the operation of the flash memory erase, data write, and flash memory check portion may be performed in parallel, so as to further save time and improve the execution efficiency of the controller.
Further, in an embodiment, the second processor core is further configured to record the breakpoint address after the verification is completed. The first processor core and the second processor core are also used for interrupting work when errors occur and feeding error information back to the main control end. The main control end is also used for sending the data packet to the first processor core again from the breakpoint address after receiving the error information.
In this embodiment, after checking the breakpoint address after the flash memory, each data packet of the compiled data block before the breakpoint address is written successfully, and the compiled data block passes the check as a whole, and in the process of transmitting and writing the next compiled data block into the flash memory one by one in units of data packets, if an error occurs, the main control terminal starts breakpoint transmission from the breakpoint address, thereby saving time and ensuring user experience. The error condition includes that the first processor core receives the data packet from the main control end or writes the data packet into the shared memory, or the second processor reads the data packet from the shared memory, erases the flash memory, writes the flash memory or checks the flash memory.
Further, in one embodiment, the shared memory is divided into a plurality of memory cells. The first processor core is used for sequentially writing each received data packet into the idle memory unit and recording the number of the memory unit. The second processor core is used for finding the corresponding memory unit according to the number of the memory unit after the inter-core communication is evoked and reading the data packet in the memory unit. The second processor core is further configured to empty the corresponding memory unit after the data packet is read.
In this embodiment, the storage area of the shared memory is divided to obtain a plurality of memory units, where the size of the storage space of each memory unit is greater than or equal to the size of the data packet, and one memory unit is used for storing a completely received data packet, and the data packet of the memory unit cannot be emptied until the data packet of the memory unit is read out, so that the data packet can be used for storing the subsequently received data packet.
On the one hand, the first processor core finds the idle memory units according to the sequence of the memory units to write the corresponding data packets, and the second processor core finds the memory units storing the corresponding data packets according to the numbers of the memory units sent by the first processor core to read the data, so that the target position can be found quickly and accurately, and the execution efficiency is improved.
On the other hand, as the target positions of the first processor core and the second processor core for executing each operation in the shared memory are determined, the working beats of the first processor core and the second processor core can be freely distributed according to the actual processing condition, no specific corresponding relation exists, the first processor core can start receiving and writing of the next data packet after finishing writing the current data packet and calling inter-core communication, the second processor core does not need to wait for the second processor core to read the previous data packet and start the action again, the time utilization rate is improved, and the first processor core can process other works by using the saved time.
Fig. 3 shows a timing diagram of operations of the first processor core and the second processor core according to an embodiment of the invention, and fig. 4 shows a timing diagram of operations of the first processor core and the second processor core according to another embodiment of the invention.
The following is an illustration of the operation of the two cases. Referring to fig. 3, under the condition that the shared memory is not divided, a specific correspondence exists between the working beats of the first processor core and the second processor core, that is, when the first processor core writes the current data packet, the second processor core reads the previous data packet, and even if the first processor core finishes writing the current data packet first, the second processor core needs to wait for receiving and writing the next data packet after finishing reading the previous data packet. For example, in fig. 3, the write packet 2 and the read packet 1 are in the same time period, the write packet 3 and the read packet 2 are in the same time period, the write packet 4 and the read packet 3 are in the same time period, and so on.
Thus, in an embodiment, the first processor core is further configured to receive and write the i+2th data packet after completing the receiving and writing of the i+1th data packet, and the second processor core completes the reading and writing of the i+1th data packet, where i is a positive integer.
Referring to fig. 4, in the case of dividing the shared memory, the working beats of the first processor core and the second processor core do not have a specific correspondence, and after the first processor core finishes writing the current data packet and arouses inter-core communication, the receiving and writing of the next data packet can be started, without waiting for the second processor core to read the previous data packet and then starting the operation. For example, in fig. 4, during the period when the second processor core reads the data packet 1, the first processor core completes not only the writing of the data packet 2 but also the partial writing of the data packet 3, the second processor core reads the data packet 2, the first processor core completes the writing of the remaining part of the data packet 3, and the partial writing of the data packet 4.
In summary, the upgrade program is divided into a plurality of data packets, and the inter-core communication means is utilized to allocate the first processor core to receive the data packets and write the data packets into the shared memory, and the second processor core reads the data packets from the shared memory and performs flash memory erasure and data writing. Therefore, the first processor core can perform flash memory erasing and data writing on the data packet which is written before when receiving and writing the subsequent data packet, namely, the operation of the data transmission part and the operation of the flash memory erasing and data writing part can be executed in parallel, so that the time is saved, and the execution efficiency of the controller end is improved.
In a second aspect, an embodiment of the present invention further provides a remote upgrade method for an automobile controller, where the remote upgrade method is applied to an automobile controller remote upgrade system including a main control end and a controller end, and the controller end includes a first processor core, a second processor core, a shared memory and a flash memory.
Fig. 5 is a flow chart illustrating a remote upgrade method of an automobile controller according to an embodiment of the invention.
Referring to fig. 5, in an embodiment, a remote upgrade method for an automobile controller includes:
s11, dividing an upgrade program into a plurality of data packets by a main control end and sequentially transmitting the data packets to a first processor core;
s12, the first processor core writes one received data packet into the shared memory, and after the writing is finished, inter-core communication is evoked, and the next data packet is received and written;
s13, the second processor core reads the data packet from the shared memory after the inter-core communication is evoked, erases the flash memory and writes the data packet into the flash memory.
Further, in an embodiment, step S11 specifically includes:
and the main control end divides each compiled data block of the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core.
Further, in an embodiment, the remote upgrade method of the automobile controller further includes:
and the second processor core writes the last data packet of each compiled data block into the flash memory, and then checks the flash memory.
In one embodiment, after the second processor core writes the last packet of each compiled data block into the flash memory, the step of verifying the flash memory further includes:
the second processor core records the breakpoint address after the verification is finished;
the first processor core and the second processor core interrupt work when errors occur, and error information is fed back to the main control end;
and after receiving the error information, the main control end starts to send the data packet to the first processor core again from the breakpoint address.
Further, in one embodiment, the shared memory is divided into a plurality of memory units;
the first processor core sequentially writes each received data packet into an idle memory unit in sequence, and records the number of the memory unit;
the second processor core finds out the corresponding memory unit according to the number of the memory unit after the inter-core communication is evoked, reads the data packet in the memory unit, and clears the corresponding memory unit after the data packet is read.
Further, in an embodiment, after the first processor core completes receiving and writing of the i+1th data packet, and the second processor core completes reading and writing of the i+2th data packet, the first processor core receives and writes the i+1th data packet, where i is a positive integer.
Further, in one embodiment, the first processor core invokes inter-core communication through a software interrupt.
The analysis of each step in the remote upgrading method of the automobile controller corresponds to the functions and implementation processes of each component in the remote upgrading system of the automobile controller, and the analysis is not repeated here.
In a third aspect, an embodiment of the present invention provides an apparatus for remotely upgrading an automobile controller, where the apparatus for remotely upgrading an automobile controller may be a device having a data processing function, such as a Personal Computer (PC), a notebook computer, a server, or the like.
Fig. 6 is a schematic diagram showing a hardware structure of a remote upgrade apparatus for an automobile controller according to an embodiment of the present invention.
Referring to fig. 6, in an embodiment of the present invention, an automotive controller remote upgrade apparatus may include a processor 1001 (e.g., a central processor CentralProcessingUnit, CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. Wherein the communication bus 1002 is used to enable connected communications between these components; the user interface 1003 may include a Display screen (Display), an input unit such as a Keyboard (Keyboard); the network interface 1004 may optionally include a standard wired interface, a WIreless interface (e.g., WIreless-FIdelity, WI-FI interface); the memory 1005 may be a high-speed Random Access Memory (RAM) or a stable memory (non-volatile memory), such as a disk memory, and the memory 1005 may alternatively be a storage device independent of the processor 1001. Those skilled in the art will appreciate that the hardware configuration shown in fig. 6 is not limiting of the invention and may include more or fewer components than shown, or may combine certain components, or a different arrangement of components.
With continued reference to fig. 6, an operating system, a network communication module, a user interface module, and a remote upgrade program for an automobile controller may be included in the memory 1005 of fig. 6, which is a type of computer storage medium. The apparatus of the present invention calls the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001 and performs the following operations:
the main control end divides the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core;
the first processor core writes one received data packet into the shared memory, and after the writing is finished, inter-core communication is evoked, and the next data packet is received and written;
the second processor core reads the data packet from the shared memory after the inter-core communication is invoked, erases the flash memory and writes the data packet into the flash memory.
The device of the present invention invokes the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001, and also performs the following operations:
and the main control end divides each compiled data block of the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core.
The device of the present invention invokes the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001, and also performs the following operations:
and the second processor core writes the last data packet of each compiled data block into the flash memory, and then checks the flash memory.
The device of the present invention invokes the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001, and also performs the following operations:
the second processor core records the breakpoint address after the verification is finished;
the first processor core and the second processor core interrupt work when errors occur, and error information is fed back to the main control end;
and after receiving the error information, the main control end starts to send the data packet to the first processor core again from the breakpoint address.
The device of the present invention invokes the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001, and also performs the following operations:
the first processor core sequentially writes each received data packet into an idle memory unit in sequence, and records the number of the memory unit;
after the communication between the cores is evoked, the second processor core finds out the corresponding memory unit according to the number of the memory unit and reads the data packet in the memory unit, and after the data packet is read, the corresponding memory unit is emptied;
wherein the shared memory is divided into a plurality of memory units.
The device of the present invention invokes the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001, and also performs the following operations:
and after the first processor core finishes receiving and writing the (i+1) th data packet and the second processor core finishes reading and writing the (i+2) th data packet, the first processor core receives and writes the (i+2) th data packet, wherein i is a positive integer.
The device of the present invention invokes the remote upgrade program of the car controller stored in the memory 1005 through the processor 1001, and also performs the following operations:
the first processor core invokes inter-core communication through a software interrupt.
In a fourth aspect, embodiments of the present invention also provide a readable storage medium.
The invention stores the remote upgrade program of the automobile controller on the readable storage medium, wherein the remote upgrade program of the automobile controller realizes the following operations when being executed by a processor:
the main control end divides the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core;
the first processor core writes one received data packet into the shared memory, and after the writing is finished, inter-core communication is evoked, and the next data packet is received and written;
the second processor core reads the data packet from the shared memory after the inter-core communication is invoked, erases the flash memory and writes the data packet into the flash memory.
Further, the remote upgrade program of the automobile controller, when executed by the processor, further performs the following operations:
and the main control end divides each compiled data block of the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core.
Further, the remote upgrade program of the automobile controller, when executed by the processor, further performs the following operations:
and the second processor core writes the last data packet of each compiled data block into the flash memory, and then checks the flash memory.
Further, the remote upgrade program of the automobile controller, when executed by the processor, further performs the following operations:
the second processor core records the breakpoint address after the verification is finished;
the first processor core and the second processor core interrupt work when errors occur, and error information is fed back to the main control end;
and after receiving the error information, the main control end starts to send the data packet to the first processor core again from the breakpoint address.
Further, the remote upgrade program of the automobile controller, when executed by the processor, further performs the following operations:
the first processor core sequentially writes each received data packet into an idle memory unit in sequence, and records the number of the memory unit;
after the communication between the cores is evoked, the second processor core finds out the corresponding memory unit according to the number of the memory unit and reads the data packet in the memory unit, and after the data packet is read, the corresponding memory unit is emptied;
wherein the shared memory is divided into a plurality of memory units.
Further, the remote upgrade program of the automobile controller, when executed by the processor, further performs the following operations:
and after the first processor core finishes receiving and writing the (i+1) th data packet and the second processor core finishes reading and writing the (i+2) th data packet, the first processor core receives and writes the (i+2) th data packet, wherein i is a positive integer.
Further, the remote upgrade program of the automobile controller, when executed by the processor, further performs the following operations:
the first processor core invokes inter-core communication through a software interrupt.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or system. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or system that comprises the element.
The foregoing embodiment numbers of the present invention are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
From the above description of the embodiments, it will be clear to those skilled in the art that the above-described embodiment method may be implemented by means of software plus a necessary general hardware platform, but of course may also be implemented by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) as described above, comprising several instructions for causing a terminal device to perform the method according to the embodiments of the present invention.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, but rather is intended to cover any equivalents of the structures or equivalent processes disclosed herein or in the alternative, which may be employed directly or indirectly in other related arts.
Claims (10)
1. The remote upgrading system for the automobile controller is characterized by comprising a main control end and a controller end, wherein the controller end comprises a first processor core, a second processor core, a shared memory and a flash memory;
the main control end is used for dividing the upgrade program into a plurality of data packets and sequentially transmitting the data packets to the first processor core;
the first processor core is used for writing one received data packet into the shared memory, calling inter-core communication after writing is finished, and receiving and writing the next data packet;
the second processor core is used for reading the data packet from the shared memory after inter-core communication is evoked, erasing the flash memory and writing the data packet into the flash memory.
2. The remote upgrade system of the automobile controller of claim 1, wherein the master control terminal is configured to divide each compiled data block of the upgrade program into a plurality of data packets and sequentially send the data packets to the first processor core.
3. The remote upgrade system of claim 2, wherein the second processor core is further configured to verify the flash memory after writing the last of the data packets of each of the compiled data blocks to the flash memory.
4. The remote upgrade system of the vehicle controller of claim 3, wherein the second processor core is further configured to record a breakpoint address after verification is complete;
the first processor core and the second processor core are also used for interrupting work when errors occur and feeding back error information to the main control end;
and the main control end is also used for sending the data packet to the first processor core again from the breakpoint address after receiving the error information.
5. The remote upgrade system of an automobile controller of claim 1, wherein the shared memory is divided into a plurality of memory cells;
the first processor core is used for sequentially writing each received data packet into the idle memory unit in sequence and recording the number of the memory unit;
the second processor core is used for finding out the corresponding memory unit according to the number of the memory unit after the inter-core communication is evoked and reading the data packet in the memory unit;
the second processor core is further configured to empty the corresponding memory unit after the data packet is read.
6. The remote upgrade system of claim 1, wherein the first processor core is further configured to receive and write the i+2th data packet after completing the receiving and writing of the i+1th data packet, and the second processor core completes the reading and writing of the i+1th data packet, where i is a positive integer.
7. The vehicle controller remote upgrade system of any one of claims 1-6, wherein the first processor core invokes inter-core communication via a software interrupt.
8. The remote upgrading method for the automobile controller is characterized by being applied to a remote upgrading system for the automobile controller, comprising a main control end and a controller end, wherein the controller end comprises a first processor core, a second processor core, a shared memory and a flash memory, and the remote upgrading method for the automobile controller comprises the following steps:
the main control end divides the upgrade program into a plurality of data packets and sequentially transmits the data packets to the first processor core;
the first processor core writes one received data packet into the shared memory, and after the writing is finished, inter-core communication is evoked, and the next data packet is received and written;
and the second processor core reads the data packet from the shared memory after the inter-core communication is evoked, erases the flash memory and writes the data packet into the flash memory.
9. An automotive controller remote upgrade apparatus comprising a processor, a memory, and an automotive controller remote upgrade program stored on the memory and executable by the processor, wherein the automotive controller remote upgrade program, when executed by the processor, performs the steps of the automotive controller remote upgrade method of claim 8.
10. A readable storage medium having stored thereon an automotive controller remote upgrade program, wherein the automotive controller remote upgrade program, when executed by a processor, implements the steps of the automotive controller remote upgrade method of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310924163.8A CN116954676A (en) | 2023-07-26 | 2023-07-26 | Remote upgrade system, method and equipment for automobile controller and readable storage medium |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310924163.8A CN116954676A (en) | 2023-07-26 | 2023-07-26 | Remote upgrade system, method and equipment for automobile controller and readable storage medium |
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| CN116954676A true CN116954676A (en) | 2023-10-27 |
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| CN202310924163.8A Pending CN116954676A (en) | 2023-07-26 | 2023-07-26 | Remote upgrade system, method and equipment for automobile controller and readable storage medium |
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| Country | Link |
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| CN (1) | CN116954676A (en) |
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