CN116954341A

CN116954341A - Mainboard, computing equipment and control method

Info

Publication number: CN116954341A
Application number: CN202310755084.9A
Authority: CN
Inventors: 刘造
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2023-06-25
Filing date: 2023-06-25
Publication date: 2023-10-27

Abstract

The embodiment of the application provides a main board, a computing device and a control method, wherein the main board comprises: a control circuit and a plurality of partitions, each partition of the plurality of partitions including at least one load; the control circuit is used for determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; when the power supply current of the ith partition is larger than the overcurrent threshold, disconnecting the power supply path of the ith partition; the i-th partition is any one of a plurality of partitions. The load is partitioned according to the power of the power module, corresponding overcurrent thresholds are set according to the specification of the load of each partition, and different overcurrent thresholds can be set by different partitions, so that the load is protected from overcurrent effectively.

Description

Mainboard, computing equipment and control method

Technical Field

The embodiment of the application relates to the technical field of servers, in particular to a mainboard, computing equipment and a control method.

Background

Currently, with the continuous upgrade of computing power demands, the number of servers included in a data center is huge, for example, an 8MW data center generally places up to 9000PCS servers, and meanwhile, for safety, the data center deploys smoke detectors. If the server has the faults of carbonization, board burning or smoking and the like in operation, the smoke detector can be triggered to cause the action of an automatic water spraying system of the data center, and the equipment and the service in the machine room are greatly influenced.

Therefore, the server needs to avoid too much current provided to the motherboard, so that the load of the motherboard is over-current, and the security of the motherboard is threatened. The components such as the CPU and the memory of the traditional server are powered from the main board of the server, and the pluggable components such as the fan, the hard disk and the like have respective back boards, but the source of power taking is also the main board, so that the traditional server is designed for preventing carbonization of the main board. When the power supply current of the load of the main board exceeds the overcurrent threshold, the power supply path of the load is cut off, but the overcurrent threshold in the prior art is constant, and the load cannot be effectively protected.

Disclosure of Invention

The embodiment of the application provides a main board, computing equipment and a control method, which can set corresponding overcurrent thresholds according to the actual conditions of various partitions and effectively protect the load overcurrent of the various partitions.

In a first aspect, an embodiment of the present application provides a motherboard, including: a control circuit and a plurality of partitions, each partition of the plurality of partitions including at least one load; the control circuit is used for determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; when the power supply current of the ith partition is larger than the overcurrent threshold, disconnecting the power supply path of the ith partition; the i-th partition is any one of a plurality of partitions.

According to the mainboard provided by the embodiment of the application, the corresponding overcurrent threshold can be set for each partition according to the specification of the load of each partition, but the overcurrent thresholds of all the partitions are not set identically, so that the overcurrent threshold of each partition is matched with the corresponding load, and further, the load overcurrent can be better protected. In different application scenarios, the specification of the load of each partition of the motherboard may be different, for example, if the motherboard does not include a PCIE card, the overcurrent threshold of the load of the corresponding partition may be set to a smaller value. According to the mainboard provided by the embodiment of the application, the load is partitioned according to the power size of the power module, the corresponding overcurrent threshold is set according to the specification of the load of each partition, and different overcurrent thresholds can be set by different partitions, so that the mainboard is more flexible, and the load is effectively protected from overcurrent.

One possible implementation includes sampling circuitry and switching circuitry for each partition; the sampling circuit and the switching circuit are connected in series and then connected between the power input end of the main board and the load of the corresponding partition; the control circuit is used for setting the maximum voltage of the sampling circuit of the ith partition according to the overcurrent threshold corresponding to the specification of the load of the ith partition; and when the voltage at two ends of the sampling circuit of the ith partition is greater than or equal to the maximum voltage of the ith partition, the switching circuit of the ith partition is controlled to be opened. According to the scheme, the overcurrent threshold is set in a software mode, a complex hardware circuit is not required to be set, so that the area of a main board can be saved, and the hardware cost is reduced.

In one possible implementation, the control circuit includes: the controller and N slow start chips of N partitions; n is an integer greater than or equal to 2, and each partition comprises a slow start chip; the controller is used for setting a corresponding overcurrent threshold according to the specification of the load of the ith partition and sending the maximum voltage corresponding to the overcurrent threshold of the ith partition to the slow start chip of the ith partition; and the slow start chip of the ith partition is used for controlling the controllable switch tube of the ith partition to be disconnected when the voltage at two ends of the sampling resistor of the ith partition is greater than or equal to the maximum voltage of the ith partition. Each partition comprises a slow start chip, so that the slow start chip of each partition can accurately control the overcurrent condition of the respective partition.

One possible implementation includes an adjustable sampling resistor network for each partition; the switching circuit and the adjustable sampling resistor network are connected in series and then connected between the power input end of the main board and the load; the adjustable sampling resistor network comprises at least two resistors and at least one switch; the control circuit is specifically used for controlling the state of the switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network according to the overcurrent threshold of the ith partition so as to set the maximum voltage corresponding to the overcurrent threshold of the adjustable sampling resistor network of the ith partition; and when the voltage at two ends of the adjustable sampling resistor network of the ith partition is greater than or equal to the maximum voltage, the switching circuit of the ith partition is controlled to be disconnected. According to the scheme, the overcurrent threshold values of all the partitions can be set through the hardware circuit, the hardware circuit acts reliably, and the speed response speed is high.

One possible implementation way, the adjustable sampling resistor network comprises M sampling resistors and M-1 switches; m is an integer greater than or equal to 2; two ends of a first sampling resistor in the M sampling resistors are respectively connected with a power input end and a switching circuit; the M-1 sampling resistors which are remained in the M sampling resistors are respectively connected with the M-1 switches in series and then connected with the first sampling resistor in parallel. According to the scheme, the resistance value can be adjusted by adding only a plurality of switches and resistors, so that the voltage at two ends of the adjustable sampling resistor network can be adjusted, and the overcurrent threshold can be adjusted.

One possible implementation includes an adjustable sampling resistor network for each partition; the adjustable sampling resistor network is connected between the power input end of the main board and the load; the adjustable sampling resistor network comprises M resistors and M switches; m is an integer greater than or equal to 2; m resistors and M switches are connected in series respectively in one-to-one correspondence and then connected in parallel; the control circuit is specifically used for controlling the state of the switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network according to the overcurrent threshold of the ith partition so as to set the maximum voltage of the adjustable sampling resistor network of the ith partition; and when the voltage at two ends of the adjustable sampling resistor network of the ith partition is greater than or equal to the maximum voltage, controlling M switches of the ith partition to be opened. According to the scheme, the switch has double functions, so that the equivalent resistance can be adjusted, and the power supply channel can be disconnected during overcurrent.

In one possible implementation, the control circuit includes: the device comprises a central processing unit, a baseboard management controller BMC, a complex programmable logic device CPLD and a south bridge chip PCH connected with the central processing unit; the power input end of the main board is used for supplying power to the BMC; the load of each partition is connected with a CPLD, and the CPLD obtains load in-place information of each partition; the BMC and the CPLD are communicated to obtain load bit information of each partition; a PCH for obtaining a specification of a partial load of each partition from a central processor and directly obtaining a specification of a partial load of each partition; and the BMC is used for obtaining the specification of the corresponding load from the PCH according to the load bit information. The scheme can utilize the existing electronic devices on the main board to obtain the specification of the load of each partition, and new hardware equipment is not required to be added.

In one possible implementation, the control circuit includes: a baseboard management controller BMC and a complex programmable logic device CPLD; the load of each partition is connected with the CPLD; the BMC is specifically configured to send a control instruction to the CPLD according to the overcurrent of the ith partition, and the CPLD controls the state of the switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network according to the control instruction. The scheme can directly control the state of the switch by using the CPLD or the FPGA, and is simple to realize and reliable to control.

In one possible implementation, the central processor includes a first central processor CPU1 and a second central processor CPU2; the load includes: PCIE standard card, CPU1, CPU2, mechanical hard disk HDD and fan; the CPU1 is used for obtaining the specification of the PCIE standard card through the PCIE interface; a CPU2, configured to obtain a specification of the CPU1 and a specification of a PCIE standard card; PCH for obtaining the specification of HDD and the specification of CPU2, the specification of CPU1, and the specification of PCIE standard card from CPU 2.

One possible implementation, for easier calculation, is to equalize the resistances of the resistors in the adjustable sampling resistor network.

In a second aspect, an embodiment of the present application further provides a computing device, including the motherboard described above.

In a third aspect, an embodiment of the present application further provides a method for controlling a motherboard, including: determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; the ith partition is any one partition among a plurality of partitions; and when the power supply current of the ith partition is larger than the overcurrent threshold, disconnecting the power supply path of the ith partition.

One possible implementation manner of determining the overcurrent threshold of the ith partition according to the specification of the load of the ith partition specifically includes: determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; setting the maximum voltage of the sampling resistor of the ith partition according to the overcurrent threshold of the ith partition; each partition comprises a sampling resistor and a controllable switch tube; the sampling resistor and the controllable switch tube are connected in series and then connected between the power input end of the main board and the corresponding load.

One possible implementation manner of determining the overcurrent threshold of the ith partition according to the specification of the load of the ith partition specifically includes: obtaining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition, and controlling the state of a switch of the ith partition to change the resistance value of the adjustable sampling resistor network so as to set the maximum voltage corresponding to the overcurrent threshold of the adjustable sampling resistor network of the ith partition; each partition comprises a controllable switch tube and an adjustable sampling resistor network; the controllable switch tube and the adjustable sampling resistor network are connected in series and then connected between the power input end of the main board and the load; the adjustable sampling resistor network includes at least two resistors and at least one switch.

Drawings

FIG. 1 is a diagram of a power supply architecture of a server motherboard according to an embodiment of the present application;

fig. 2 is a schematic diagram of a motherboard according to an embodiment of the present application;

FIG. 3 is a schematic diagram of a control circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an adjustable sampling resistor network according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a control circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another control circuit according to an embodiment of the present application;

FIG. 7 is a schematic diagram of a control circuit according to an embodiment of the present application;

FIG. 8 is a schematic diagram of a control circuit according to an embodiment of the present application;

fig. 9 is a schematic diagram of another motherboard according to an embodiment of the present application;

FIG. 10 is a schematic diagram of a computing device provided by an embodiment of the present application;

fig. 11 is a flowchart of a control method of a motherboard according to an embodiment of the present application;

fig. 12 is a flowchart of another control method of a motherboard according to an embodiment of the present application.

Detailed Description

The computing device provided by the embodiment of the application is not particularly limited to the application scene, for example, the computing device is described by taking a server as an example, and is not particularly limited to the type of the server, for example, the computing device can be a rack server or an edge server. The server may be located in a data center or other areas, and the embodiment of the present application is not limited specifically.

Servers, which are one type of computing device, run faster and are more highly loaded than ordinary computers. The server provides computing or application services to other clients (e.g., PCs, smartphones, etc.) in the network. The server has high-speed CPU operation capability, long-time reliable operation, strong external data throughput capability and better expansibility. Servers are classified from the external form into rack-type, blade-type, tower-type and cabinet-type.

The server generally includes a main board and a power supply for supplying power to respective loads of the main board. The embodiment of the application is not particularly limited to the voltage level of the power supply supplied to the main board, and is described by taking direct current 12V as an example.

The embodiment of the application does not particularly limit the application scene of the mainboard, and is specifically introduced by taking the mainboard in the server as an example. The main board is an important circuit board in the server, and comprises a Central Processing Unit (CPU), a controller, a memory, a connector and other components, and the interface of the controller is limited, so that the interface can be expanded through the connector, and peripheral equipment such as a USB port can be conveniently connected, and equipment such as a mouse and a keyboard can be conveniently connected; and the serial data interface is expanded and connected with devices such as a display card. The controller may be one or more of a micro control unit (Micro Controller Unit, MCU), a complex programmable logic device (Complex Programming Logic Device, CPLD), a field programmable gate array (Field Programmable Gate Array, FPGA).

The motherboard generally includes various loads, such as a CPU, a fan, and a memory, and embodiments of the present application are not particularly limited to a specific type of memory, such as, but not limited to, the following types of memory: dual-Inline Memory Modules (DIMMs), mechanical Hard Disk Drives (HDDs), and high-speed serial computer expansion bus standard PCI-Express (Peripheral Component Interconnect Express), etc. In addition, the motherboard may include one CPU or a plurality of CPUs.

A baseboard management controller (Baseboard Manager Controller, BMC) is an essential component of a server for monitoring the operating conditions of the server, such as temperature, fan speed, power supply conditions, operating system status, etc. The BMC is independent of the operation of the server, is not influenced by the server, can perform firmware upgrade, check machine equipment, remotely control the machine to start and other operations on the server in a state that the server is not started, and can record key logs when the server crashes.

Local buses (Local buses), also known as system buses, are electronic buses that connect between a CPU and other devices (e.g., memory, hard disk, graphics card, etc.). It allows for fast transfer of data within the system to support efficient system operation. Local Bus is typically implemented on a motherboard through which a user can communicate with other hardware devices. It is a high-speed and low-latency data bus that is used inside the system so that the various hardware components in the system can communicate quickly and efficiently. Different types of computing devices and electronic devices may use different types of Local Bus, such as PCI Express, (Industry Standard Architecture, ISA) Bus, (Versa Module Europe, VME) Bus, and so forth. Each Local Bus has a dedicated Bus control chip and protocol standard to manage data transmission and communication to ensure the correctness and integrity of data transmission.

For convenience of understanding, the following specifically describes an overcurrent protection manner of the motherboard provided by the embodiment of the present application.

The main board can divide the load into a plurality of partitions according to the magnitude of the load current. It should be understood that the above partitions are not representative of partitioning with all of the electronic devices on the motherboard. In one implementation, all of the electronics on the server motherboard may be partitioned, and in another implementation, some of the electronics on the server motherboard may be partitioned. Illustratively, the overcurrent threshold of one partition may be set to 100A, and if the overcurrent threshold exceeds 100A, the partition may be added, and the power input terminal of each partition includes a slow-start overcurrent protection circuit. The above over-current threshold of 100A is merely illustrative, and other over-current thresholds may be set according to the specific situation, but in the conventional method, the over-current threshold of each partition is equal, for example, 100A. The slow-start overcurrent protection circuit comprises a sampling resistor, a slow-start chip and a controllable switch tube, for example, the controllable switch is described by taking a Metal-Oxide-semiconductor field effect transistor (MOS) as an example, and the controllable switch tube can also be other controllable switch tubes. Referring specifically to fig. 1, a diagram of a power supply architecture of a server motherboard in an embodiment is shown.

In order to realize uninterrupted power supply of a load, a general power supply includes two power supply modules that are backup to each other, a first power supply module 10 and a second power supply module 20, so that when one of the power supply modules fails, the other power supply module can continue to supply power to the load.

As can be seen from fig. 1, the first power module 10 and the second power module 20 both supply power to the load of the motherboard, and fig. 1 is described by taking four partitions of the load of the motherboard including A, B, C and D as an example, and the number of the load partitions is not specifically limited in the embodiment of the present application.

For example, partition A includes load CPU0 and DIMM, partition B includes load CPU1 and DIMM, partition C includes load FAN FAN, and partition D includes load HDD and PCIE.

In addition, the partitions a and B further include a voltage regulator drop (VRD, voltage Regulator Down) for dropping the voltage supplied from the first power module 10 and the second power module 20 and supplying the dropped voltage to the load, for example, dropping 12V to 3.3V.

As can be seen from fig. 1, each partition of the motherboard includes a sampling resistor R, MOS tube and a buffer chip. And the slow start chip is used for controlling the MOS tube to be disconnected when the current flowing through the sampling resistor R is more than or equal to the overcurrent threshold 100A, so that the power supply path of the partition load is disconnected. In practical application, the slow start chip is used for collecting voltages at two ends of the sampling resistor R, and the current flowing through the R can be obtained because the resistance value of the R is known. In addition, the slow start chip can also directly compare the voltage at two ends of R with the threshold voltage to judge whether the MOS tube needs to be controlled to be disconnected, namely, the slow start chip can obtain the threshold voltage at two ends of R through the resistance value of R and the overcurrent threshold value (100A).

In the embodiment of the present application, only one slow start chip is included in each partition. It should be understood that the slow start chip of each partition may be implemented by other controllers or processors, so long as the voltage across the sampling resistor R can be obtained and compared with the threshold voltage, and the state of the MOS transistor is controlled according to the comparison result.

However, in practical applications, there are occasions in which the loads of the partitions on the motherboard are relatively small, for example, some clients do not configure PCIE cards, only configure one HDD, and the current of the partition is generally 2A, and when the current threshold of the overcurrent is not reached, the current bearing capacity of the load is exceeded, for example, when the supply current reaches 10A, load damage is caused. However, if the overcurrent threshold is set according to 100A, the power supply current has burnt the load, and the MOS transistor has not been disconnected to cut off the power supply path.

The main board provided by the embodiment of the application can flexibly set the corresponding overcurrent thresholds for each partition according to the actual in-place condition of the load of each partition on the main board, namely, the overcurrent thresholds of different partitions can be set with different values, and then the load of each partition is effectively overcurrent-protected by matching the corresponding overcurrent thresholds according to the actual load of each partition.

In order to enable those skilled in the art to better understand the technical solutions provided by the embodiments of the present application, the following detailed description is provided with reference to the accompanying drawings.

Referring to fig. 2, a schematic diagram of a motherboard according to an embodiment of the present application is shown.

An embodiment of the present application provides a motherboard, including: control circuitry 201 and a plurality of partitions, for ease of description, a first partition a and a second partition B are illustrated as two partitions. Each partition of the plurality of partitions includes at least one load; the first partition includes Load1, and the second partition includes Load2.

A control circuit 201 for determining an overcurrent threshold of the i-th partition according to the specification of the load of the i-th partition; when the power supply current of the ith partition is greater than or equal to the overcurrent threshold, disconnecting the power supply path of the ith partition; the i-th partition is any one of a plurality of partitions.

The control circuit 201 needs to obtain the specification of the load of each partition, and further sets an overcurrent threshold value matching the specification of the load for each partition. Here, the specification of the load includes a resistance value of the load. In some other implementations, the specifications of the load may also generally include one or more of model number, nominal value, nominal foot value, and allowable deviation. For example, a relatively large overcurrent threshold may be set with a relatively large load and a large power consumption. Less load, less power consumption, and a relatively small overcurrent threshold may be set. And the control circuit 201 separately determines, for each partition, whether the power supply current is greater than the overcurrent threshold, and if so, opens the power supply path of the partition, which can be implemented by opening a switch connected in series to the power supply path, so as to protect the load from overcurrent damage.

The embodiment of the present application is not particularly limited to the manner in which the control circuit 201 sets the overcurrent threshold for each partition, and the overcurrent threshold may be set by means of hardware setting, or may be set by means of software setting.

According to the mainboard provided by the embodiment of the application, the corresponding overcurrent threshold can be set for each partition according to the specification of the load of each partition, but the overcurrent thresholds of all the partitions are not set identically, so that the overcurrent threshold of each partition is matched with the corresponding load, and further, the load overcurrent can be better protected. In different application scenarios, the specification of the load of each partition of the motherboard may be different, for example, if the motherboard does not include a PCIE card, the overcurrent threshold of the load of the corresponding partition may be set to a smaller value.

The following first describes, with reference to the accompanying drawings, a case where the control circuit adjusts the overcurrent threshold of each partition by means of hardware setting.

Each partition of the main board provided by the embodiment of the application comprises a controllable switch tube and an adjustable sampling resistor network; the controllable switch tube and the adjustable sampling resistor network are connected in series and then connected between the power input end of the main board and the load.

The adjustable sampling resistor network comprises at least two resistors and at least one switch; the embodiment of the application does not specifically limit the number of the resistors included in the adjustable sampling resistor network, and at least two resistors are required to be included, so that the resistance value of the adjustable sampling resistor network, namely the external presented impedance, is changed by adjusting the state of the switch.

The control circuit is specifically used for controlling the state of the switch of the ith partition to change the resistance value of the adjustable sampling resistor network according to the overcurrent threshold of the ith partition so as to set the maximum voltage of the adjustable sampling resistor network of the ith partition; and when the voltage at two ends of the adjustable sampling resistor network of the ith partition is greater than or equal to the maximum voltage, the controllable switch tube of the ith partition is controlled to be disconnected.

The application is also not particularly limited to the number of switches comprised by the adjustable sampling resistor network, for example, one possible case is that the adjustable sampling resistor network may comprise two resistors connected in parallel by the action of the switches, or that the adjustable sampling resistor network may comprise only one resistor.

The embodiment of the application does not specifically limit whether the number of the resistors of each partition is the same, and whether the resistance values of the resistors between each partition and inside a single partition are the same, for convenience in calculating the overcurrent threshold of each partition, for example, the number of the resistors included in each partition may be set to be the same, and the resistance values of all the resistors are also the same.

Referring to fig. 3, a schematic diagram of a control circuit according to an embodiment of the present application is shown.

The main board provided by the embodiment of the application is characterized in that an adjustable sampling resistor network comprises M sampling resistors and M-1 switches; m is an integer greater than or equal to 2; in the embodiment of the present application, the description is given by taking M as 4 as an example, where M may also take a larger value, for example, 5 or 6, and the larger the number of M, the larger the number of adjustable resistance values, the larger the number of corresponding adjustable values of the overcurrent threshold, and the value of M may be set according to actual needs.

In the embodiment of the application, the controllable switch tube is taken as an MOS tube for introduction. And the switch in the adjustable sampling resistor network is also introduced by taking the MOS tube as an example.

Two ends of a first sampling resistor IN the M sampling resistors are respectively connected with a power input end and a controllable switch tube, and two ends of a first sampling resistor R1 IN the figure are respectively connected with a power input end IN and a controllable switch tube MOS4; the remaining M-1 sampling resistors in the M sampling resistors are respectively connected with M-1 switches in series and then connected with the first sampling resistor in parallel, namely, the remaining 3 sampling resistors R2, R3 and R4 in the 4 sampling resistors are respectively connected with corresponding switches MOS1, MOS2 and MOS3 in series and then connected with R1 in parallel.

Wherein the MOS4 functions to disconnect the power supply path of the load of the present zone when the power supply current of the zone flows. And the MOS1, the MOS2 and the MOS3 are used for adjusting the equivalent resistance value presented by the adjustable sampling resistor network.

For example, the control circuit includes: a central processing unit (not shown), a baseboard management controller BMC200, and a complex programmable logic device CPLD100; it should be understood that the CPLD may be replaced by an FPGA, and in the embodiment of the present application, the CPLD is merely described as an example. In the embodiment of the present application, the CPLD is used as an example for all partitions to be connected, and when the load quantity is large, a plurality of CPLDs can be set. The load of each partition is connected with CPLD100, and CPLD100 obtains load in-place information of each partition; BMC200 communicates with CPLD100 to obtain load bit information of each partition; BMC200 is configured to obtain, from the central processing unit, a specification of a corresponding load according to the load bit information.

BMC200 sets the overcurrent threshold of each partition according to the specification of the load of each partition, specifically, the load of each partition is connected with CPLD100; the BMC200 is specifically configured to send a control instruction to the CPLD100 according to the overcurrent threshold of the ith partition, where the CPLD100 controls the state of the switch of the ith partition to change the equivalent resistance of the adjustable sampling resistor network according to the control instruction, that is, the CPLD100 controls the state of the switch in the adjustable sampling resistor network to change the equivalent resistance of the adjustable sampling resistor network.

The following description will take a partition as an example, and continue taking four resistors connected in parallel as an example in fig. 3.

MOS1, MOS2 and MOS3 all connect the IO1 of CPLD100, IO2 and IO3 interface, CPLD100 can be through the state of IO interface output different level control switch, and the state of switch includes two kinds of on and off. For example, when CPLD100 outputs a high level, the corresponding MOS transistor is turned on, and when CPLD100 outputs a low level, the corresponding MOS transistor is turned off. For example, when MOS1 and MOS2 are on and MOS3 is off, the adjustable sampling resistor network includes R1, R2, and R3 connected in parallel. As shown in fig. 4, when MOS1, MOS2, and MOS3 are all on, the adjustable sampling resistor network includes R1, R2, R3, and R4 connected in parallel.

For example, when the voltage across the adjustable sampling resistor network is greater than 25mV, the slow start chip 102A needs to control the MOS4 to turn off, with each of the four resistors having a resistance of 1mΩ, and one resistor allows a maximum current of 25mV/1mΩ=25a. MOS1, MOS2 and MOS3 are all on, and four resistors are all connected in parallel, so that the overcurrent threshold=25ax4=100deg.A; turning off the 1 MOS transistor, the overcurrent threshold=25ax3=75a; turning off 2 MOS transistors, the overcurrent threshold=25a2=50a, and turning off three MOS transistors, the overcurrent threshold=25a1=25a, i.e. the overcurrent threshold can be dynamically adjusted according to 4 steps, and referring to fig. 5, the description is continued by taking the load as four partitions, partition a includes load CPU1 and DIMM, partition B includes load CPU2 and DIMM, partition C includes FAN, and partition D includes PCIE and HDD. Since the specifications of the loads of the four partitions are different, different overcurrent thresholds can be set according to the specifications of the loads of each partition. In fig. 5, the adjustable sampling resistor network is illustrated only by R, and the interior of R includes at least two resistors and at least one switch, for example, R1-R3 and MOS1-MOS3 shown in fig. 3.

The comparison situation that the scheme provided by the embodiment of the application is the same with the traditional overcurrent threshold set by each partition is shown in table 1.

TABLE 1

For example, as shown in fig. 5, if the overcurrent threshold of partition a is 25A, CPLD100 is required to control all of MOS1-MOS3 in R to be turned off. The slow start chip 102A is configured to detect voltages across R of the partition a to determine whether to control the MOS4 of the partition a to be turned off.

If the overcurrent threshold of partition B is 50A, CPLD100 is required to control all of MOS1-MOS2 in R to be turned off. The slow start chip 102B is configured to detect voltages at two ends of R of the partition B to determine whether to control the MOS4 of the partition B to be turned off.

If the overcurrent threshold of partition C is 75A, CPLD100 is required to control MOS1 in R to be turned off. The slow start chip 102C is configured to detect voltages across R of the partition C to determine whether to control the MOS4 of the partition C to be turned off.

If the overcurrent threshold of partition D is 100A, CPLD100 is required to control all of MOS1 to MOS3 in R to be on. When the equivalent resistance value of the four resistors connected in parallel is 0.25 mOhm, and the slow start chip 102D detects that the voltage at two ends of the adjustable sampling resistor network exceeds 25mV, the slow start chip 102D needs to control the MOS4 of the partition D to be disconnected.

The overcurrent threshold of each partition is represented by Imax, the slow start voltage of each partition is represented by Vmax, the resistance value of each resistor is R, and the parallel number is n. The BMC calculates the overcurrent threshold of each partition by querying the number and specification (or model) of the actual load of each partition.

(1) An overcurrent threshold imax=vmax×n/R for each partition to be restarted;

(2) The adjustable gear of the overcurrent threshold of each partition is i1=vmax/R, i2=vmax=2vmax/R, …, in=n×vmax/R;

(3) The overcurrent threshold of each partition is equal to the sum of the maximum currents of all loads of that partition, i.e., the I-th partition imax=i1+i2+ … +im. Wherein I1-Im represent the currents of the m loads, respectively.

The above description is that the adjustable sampling resistor network comprises M resistors and M-1 switches, and the following description describes another implementation case, wherein the controllable switching tube for controlling the current path is not independently arranged any more, but is directly realized by using the switches in the adjustable sampling resistor network.

Referring to fig. 6, a schematic diagram of another control circuit according to an embodiment of the present application is shown.

According to the mainboard provided by the embodiment of the application, each subarea comprises an adjustable sampling resistor network; the adjustable sampling resistor network is connected between the power input end of the main board and the load;

the adjustable sampling resistor network comprises M resistors and M switches; m is an integer greater than or equal to 2; the description will be continued with reference to fig. 6, in which M is 4. The 4 resistors are R1-R4 respectively, and the 4 switches are MOS1-MOS4 respectively.

M resistors and M switches are connected in series respectively in one-to-one correspondence and then connected in parallel; as shown in fig. 6, after R1 is connected in series with MOS1, R2 is connected in series with MOS2, R3 is connected in series with MOS3, and R4 is connected in series with MOS4, they are connected in parallel.

The state of the switches may determine the number of resistors connected in parallel, e.g. 4 switches are all on, and 4 resistors are connected in parallel. And 3 switches are turned on and 1 switch is turned off, and then 3 resistors are connected in parallel. 2 switches are turned on and 2 switches are turned off, and then 2 resistors are connected in parallel. 1 switch on 3 switches off, then there is only one resistor.

The control circuit is specifically used for controlling the state of the switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network according to the overcurrent threshold of the ith partition so as to set the maximum voltage of the adjustable sampling resistor network of the ith partition; and when the voltage at two ends of the adjustable sampling resistor network of the ith partition is greater than or equal to the maximum voltage, controlling M switches of the ith partition to be opened.

The control circuit comprises a slow start chip 102A, CPLD and a BMC200, and four different IO ports of the CPLD100 are respectively used for controlling states of 4 switches, namely IO1-IO4 are respectively used for controlling MOS1-MOS4. The slow start chip 102A is configured to obtain voltages at two ends of the adjustable sampling resistor network, inform the CPLD100 of the voltages, and the CPLD100 controls states of the MOS1-MOS4, for example, when an overcurrent threshold of the partition is 50A, the CPLD100 controls 2 MOS transistors to be turned off and 2 MOS transistors to be turned on. However, when the power supply current is greater than or equal to 50A, the voltage at both ends of the adjustable sampling resistor network is greater than or equal to 25mv, and the 2 MOS transistors that the cpld100 needs to control to be turned on are also turned off, i.e., all the MOS transistors are turned off, so as to cut off the power supply path of the load.

The embodiment of the application is not particularly limited to the type of the slow start chip, and can be realized by adopting TPS24711, for example, and can also be realized by adopting other chips with the function of the slow start chip related to the embodiment of the application.

The above description is that the control circuit adjusts the magnitude of the overcurrent threshold of each partition through a hardware setting mode, and the following description is that the control circuit adjusts the magnitude of the overcurrent threshold of each partition through a software setting mode with reference to the accompanying drawings.

Each partition of the main board provided by the embodiment of the application comprises a sampling circuit and a switching circuit; the sampling circuit and the switching circuit are connected in series and then connected between the power input end of the main board and the corresponding load. The control circuit is specifically used for setting the maximum voltage of the sampling circuit of the ith partition according to the overcurrent threshold of the ith partition; when the voltage at two ends of the sampling circuit is larger than or equal to the maximum voltage, the switch circuit of the ith partition is controlled to be disconnected, namely the power supply path is cut off. Since the control circuit has obtained the overcurrent thresholds of the respective partitions, when the load specifications of the respective partitions are different, the corresponding overcurrent thresholds are different. It should be appreciated that in embodiments of the present application, when a partition includes multiple loads, the overcurrent threshold of the partition is determined by the sum of the loads of the partition.

For example, referring to fig. 7, a schematic diagram of still another control circuit according to an embodiment of the present application is shown.

In fig. 7, the sampling circuit is described by taking an example of including a sampling resistor, and the switching circuit is described by taking an example of including a controllable switching transistor.

The control circuit includes: the controller 202 and N slow start chips of N partitions; n is an integer greater than or equal to 2, and each partition comprises a slow start chip; the description will continue taking 4 as an example, i.e., 4 partitions. The first partition A includes a slow start chip 102A, the second partition B includes a slow start chip 102B, the third partition C includes a slow start chip 102C, and the fourth partition D includes a slow start chip 102D. In fig. 7, R of each partition may be a resistor or a plurality of resistors, but is a fixed resistance, and the inside of the partition does not need to include a switch, so that the size of the resistance does not need to be adjusted, and the hardware setting is simpler.

A controller 202, configured to determine a corresponding overcurrent threshold according to a specification of a load of the ith partition, and send a maximum voltage corresponding to the overcurrent threshold of the ith partition to a slow-start chip of the ith partition; embodiments of the present application are not particularly limited to the implementation of controller 202, for example, controller 202 may be implemented by a BMC.

And the slow start chip of the ith partition is used for controlling the controllable switch tube of the ith partition to be disconnected when the voltage at two ends of the sampling resistor of the ith partition is greater than or equal to the maximum voltage of the ith partition.

As can be seen from fig. 7, the controller 202 is connected to the slow start chips 102A-102D, that is, the controller 202 may perform data interaction with each slow start chip, and the controller 202 may send the maximum voltage corresponding to the overcurrent threshold of each partition to the corresponding slow start chip, so that when the slow start chip determines that the voltage at two ends of the sampling resistor R is greater than or equal to the maximum voltage, the slow start chip controls the corresponding MOS transistor to be disconnected, and cuts off the power supply path of the load.

For example, the controller 202 may calculate the actual maximum current for each zone based on the number of loads actually configured for each zone and the specification. The controller 202 may directly establish a communication path with the slow start chip of each partition, and dynamically modify the maximum voltage Vmax of the slow start chip to dynamically adjust the overcurrent threshold of the slow start chip. For example, in the fourth partition D, for example, a slow start chip is used, the model number is TPS24711, vmax=25 mV, the resistance is 0.25mΩ, and the default overcurrent threshold imax=25/0.25=100A. Partition a is actually matched with 20A, the controller 202 can adjust Vmax of the slow start chip from 25mV to 6.25mV, the resistance is still 0.25 mohm, imax=6.25/0.25=25a, and therefore, the controller 202 can dynamically adjust the overcurrent threshold of the slow start chip.

TABLE 2

Comparing fig. 5 and fig. 7, it can be found that the hardware is used to set the overcurrent threshold or the maximum voltage in fig. 5, the software is directly used to set the overcurrent threshold or the maximum voltage in fig. 7, the requirement of the corresponding hardware in fig. 5 is higher, and the requirement of the software in fig. 7 is higher. The embodiment of the application is not particularly limited to a specific setting mode of the overcurrent threshold, and can be selected according to actual needs.

In addition, the embodiment of the application also provides a main board, which can set the overcurrent threshold in a software mode and can set the overcurrent threshold in a hardware mode, and particularly can refer to fig. 8, which is a schematic diagram of another control circuit provided by the embodiment of the application. The internal structure of R of each partition in fig. 8 can be seen in fig. 4 and 6.

In this embodiment, the BMC is used to send the maximum voltage corresponding to the overcurrent threshold to the slow-start chip of each partition. Meanwhile, the BMC200 can also send a control instruction to the CPLD100, and the CPLD100 controls the state of a switch in the adjustable sampling resistor network to change the equivalent resistance value of the adjustable sampling resistor network, so as to adjust the voltages at two ends of the adjustable sampling resistor network, thereby realizing that the overcurrent threshold of each partition is dynamically adjustable from the aspects of software and hardware.

An implementation of the control circuit to obtain specifications of the respective partition loads is described below.

The control circuit of the main board provided by the embodiment of the application comprises: the device comprises a central processing unit, a baseboard management controller BMC and a complex programmable logic device CPLD; the load of each partition is connected with a CPLD, and the CPLD obtains load in-place information of each partition; the BMC and the CPLD are communicated to obtain load bit information of each partition; and the BMC is used for obtaining the specification of the corresponding load from the central processing unit according to the load bit information.

For example, the motherboard provided in the embodiment of the present application includes two CPUs, which are a partition of the first CPU1 and the second CPU2, the CPU1 and its memory DIMM, a partition of the CPU2 and its memory DIMM, and the HDD and PCIE card are divided into one or 2 areas according to the total power consumption of the full configuration, for example, the HDD and PCIE are located in the same partition, and the fan is a single partition.

The control circuit further includes: a south bridge chip PCH connected with the central processing unit; PCH, is used for obtaining the specification of the load of each partition; the BMC is specifically used for obtaining the specification of the load of each partition from the south bridge chip.

The load includes: PCIE standard card, CPU1, CPU2, mechanical hard disk HDD and fan;

The CPU1 is used for obtaining the specification of the PCIE standard card through the PCIE interface;

a CPU2, configured to obtain a specification of the CPU1 and a specification of a PCIE standard card;

PCH for obtaining the specification of HDD and the specification of CPU2, the specification of CPU1, and the specification of PCIE standard card from CPU 2.

Referring to fig. 9, a schematic diagram of another motherboard according to an embodiment of the present application is shown.

Because each load is connected to CPLD100, the IO interface of CPLD100 may obtain the in-place information of each load, for example, the GPIO interface of CPLD100 may detect the in-place condition of the load by detecting a level signal. The CPLD100 uses internal registers to store the in-place information of the load, the BMC200 accesses the corresponding registers of the CPLD100 through the Local bus interface, and obtains the specific configuration of the server by obtaining the in-place conditions of the loads such as the CPU1, the CPU2, the DIMM, HDD, PCIE standard card, the FAN and the like.

The specification of the PCIE standard card can be sent to the CPU1 through a PCIE interface; the specification of the CPU1, the specification of the memory DIMM controlled by the CPU1 and the specification of the PCIE standard card are shared to the CPU2 through a UPI bus (Ultra Path Interconnect) between the CPU1 and the CPU2, and the specification of the CPU2 and the specification of the control memory DIMM are transmitted to the PCH300 through a direct media interface (Direct Media Interface, DMI) bus; the HDD specification is sent to PCH300 via a Serial Attached SCSI (SAS)/Serial hard disk (Serial Advanced Technology Attachment, SATA) interface. The BMC100 can obtain specifications of loads such as HDD, PCIE, CPU and CPU2 and respective DIMMs via the PCIE1 bus with the PCH300. The specification of the fan is generally not changed after the initial design is determined, and the number of configurations is not changed, i.e., the BMC200 knows that the specification of the fan is a fixed amount.

According to the mainboard provided by the embodiment of the application, the BMC200 detects the in-place condition of each partition load, if the load is in place, the specification of each load is continuously queried, namely the detailed configuration information of the server is obtained, so that the power consumption of the load and the actual maximum current of the load are obtained, the general overcurrent threshold is set to be slightly higher than the actual maximum current, for example, the voltage of the power supply module for supplying power to the mainboard is direct current 12V, and the rated power P of the load can be obtained from the specification of the load, so that the actual maximum current I=P/12 of the load.

After the main Board completes the subareas of each load, the BMC stores the subareas x in advance according to the Board ID, the overcurrent threshold value of each subarea is Imax, the maximum voltage Vmax of each subarea, the resistance value of the adjustable sampling resistor, the number n of parallel resistors and the adjustable gear.

According to the mainboard provided by the embodiment of the application, the overcurrent threshold matched with the load can be set for each partition according to the load condition of each partition, so that the overcurrent of each partition can be finely prevented, and the load of each partition is effectively protected.

Based on the motherboard provided in the above embodiment, the embodiment of the present application further provides a computing device, and the embodiment of the present application does not specifically limit the type of the computing device, for example, may be a server, and the embodiment of the present application also does not specifically limit the specific type of the server. The following detailed description refers to the accompanying drawings.

Referring to fig. 10, a schematic diagram of a computing device according to an embodiment of the present application is provided.

The computing device provided by the embodiment of the application includes the main board 1000 described in the above embodiment, and further includes the power panel 2000.

The main board 1000 includes: control circuitry 201 and a plurality of partitions, for ease of description, a first partition a and a second partition B are illustrated as two partitions. Each partition of the plurality of partitions includes at least one load; the first partition includes Load1, and the second partition includes Load2.

For redundant backup power, the power panel 2000 generally includes at least two power modules, a first power module 10 and a second power module 20.

According to the computing device provided by the embodiment of the application, the corresponding overcurrent thresholds can be flexibly set for each partition according to the actual in-place condition of the load of each partition on the main board, namely, the overcurrent thresholds of different partitions can be set with different values, and then the load of each partition is effectively overcurrent-protected by matching the corresponding overcurrent thresholds according to the actual load of each partition.

Based on the motherboard and the computing device provided in the foregoing embodiments, the embodiments of the present application further provide a control method for the motherboard, which is described in detail below with reference to the accompanying drawings.

Referring to fig. 11, the flowchart of a control method of a motherboard according to an embodiment of the present application is shown.

The control method of the main board provided by the embodiment of the application comprises the following steps:

s1101: determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; the i-th partition is any one of a plurality of partitions.

S1102: and when the power supply current of the ith partition is larger than the overcurrent threshold, disconnecting the power supply path of the ith partition.

According to the control method of the main board, corresponding overcurrent thresholds can be flexibly set for all the partitions according to actual in-place conditions of loads of all the partitions on the main board, namely, the overcurrent thresholds of different partitions can be set to different values, and then the loads of all the partitions are effectively overcurrent-protected according to the fact that the actual loads of all the partitions are matched with the corresponding overcurrent thresholds.

Two implementations of adjusting the partition's overcurrent threshold are described below.

First kind:

according to the control method of the main board, each partition of the main board comprises a sampling resistor and a controllable switch tube; the sampling resistor and the controllable switch tube are connected in series and then connected between the power input end of the main board and the corresponding load. It should be appreciated that in embodiments of the present application, when a partition includes multiple loads, the overcurrent threshold of the partition is determined by the sum of the loads of the partition.

Determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition, wherein the method specifically comprises the following steps of:

determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; the maximum voltage of the sampling resistor of the ith partition is set according to the overcurrent threshold of the ith partition.

Second kind:

according to the control method of the main board, each partition of the main board comprises a controllable switch tube and an adjustable sampling resistor network; the controllable switch tube and the adjustable sampling resistor network are connected in series and then connected between the power input end of the main board and the load; the adjustable sampling resistor network includes at least two resistors and at least one switch.

obtaining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition, and controlling the state of a switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network so as to set the maximum voltage corresponding to the overcurrent threshold of the adjustable sampling resistor network of the ith partition;

an embodiment of a specific control process will be described below taking the above second example.

Referring to fig. 12, a flowchart of another control method of a motherboard is provided in an embodiment of the present application.

S1201: the BMC queries the ID (Board ID) of the motherboard; the motherboard of the server has an ID. For example, a server may have multiple motherboards, each with an ID, and the number of partitions for different motherboards may be different.

S1202: and the BMC obtains the partition number of the main board according to the main board ID. After the main Board completes the partition of each load, the BMC stores the partition number in advance according to the Board ID.

S1203: the BMC queries the load real-distribution situation of each partition according to the partition number; the load real-world situation includes the number of loads.

S1204: the BMC obtains load in-place information of each partition; in order to accurately obtain the load in-place situation, if detection of an in-place signal is performed. If the load is in place, the BMC obtains the specification of each load again.

S1205: the BMC obtains the specification of each load where each partition is in place. The specifications of the load include the model, nominal value, rated value, etc. of the load.

S1206: the BMC calculates the real maximum current of each load in place of each partition according to the specification of each load and the voltage of the power module. Specifically, the BMC obtains detailed configuration information of the server, so as to obtain power consumption of the load and its actual maximum current, for example, the voltage of the power module supplying power to the motherboard is dc 12V, and the rated power P of the load can be obtained from the specification of the load, so that the actual maximum current i=p/12V of the load.

S1207: obtaining an overcurrent threshold of each partition according to the actual distribution maximum current of each partition; the over-current threshold is typically set slightly higher than the actual maximum current.

S1208: the BMC obtains the maximum voltage corresponding to each partition and the resistance value of the adjustable resistor according to the overcurrent threshold; the resistance value of each resistor is known, and the number of the switches is known, namely, the resistance values of the corresponding adjustable resistors in different combinations of the switches can be obtained according to the actual structure of the adjustable sampling resistor network. When the resistance value and the overcurrent threshold are known, a corresponding maximum voltage can be obtained.

S1209: and the BMC obtains adjustable gears corresponding to the overcurrent thresholds of the various subareas according to the maximum voltage and the resistance value of the adjustable resistor. The adjustable gear can be prestored, and in actual working, the adjustable gear is directly inquired according to the load condition.

S1210: and the BMC determines the switch regulation condition of each partition according to the overcurrent threshold of each partition. The corresponding relation between each overcurrent threshold and each switch adjustment is already known, and only the inquiry is needed at this time.

S1211: the BMC adjusts the switch through the GPIO interface of the CPLD according to the switch adjusting condition, so that the resistance value of the adjustable sampling resistor is dynamically adjustable, and the overcurrent threshold is adjusted. Namely, the BMC sends a control instruction to the CPLD, and the CPLD controls the state of the switch according to the control instruction.

According to the control method of the main board, which is provided by the embodiment of the application, the overcurrent threshold matched with the load can be set for each partition according to the load condition of each partition, so that the overcurrent of each partition can be finely prevented, and the load of each partition is effectively protected.

The above description is only of the preferred embodiment of the present application, and is not intended to limit the present application in any way. While the application has been described with reference to preferred embodiments, it is not intended to be limiting. Any person skilled in the art can make many possible variations and modifications to the technical solution of the present application or modifications to equivalent embodiments using the methods and technical contents disclosed above, without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present application still fall within the scope of the technical solution of the present application.

Claims

1. A motherboard, comprising: a control circuit and a plurality of partitions, each partition of the plurality of partitions including at least one load;

The control circuit is used for determining an overcurrent threshold of the ith partition according to the specification of the load of the ith partition; when the power supply current of the ith partition is larger than the overcurrent threshold, disconnecting a power supply path of the ith partition; the ith partition is any one partition among the plurality of partitions.

2. The motherboard of claim 1, wherein each partition comprises a sampling circuit and a switching circuit;

the sampling circuit and the switching circuit are connected in series and then connected between the power input end of the main board and the load of the corresponding partition;

the control circuit is used for setting the maximum voltage of the sampling circuit of the ith partition according to the overcurrent threshold corresponding to the specification of the load of the ith partition; and when the voltage at two ends of the sampling circuit of the ith partition is greater than or equal to the maximum voltage of the ith partition, the switching circuit of the ith partition is controlled to be disconnected.

3. The motherboard of claim 2, wherein the control circuit comprises: the controller and N slow start chips of N partitions; n is an integer greater than or equal to 2, and each partition comprises one slow start chip;

The controller is used for setting a corresponding overcurrent threshold according to the specification of the load of the ith partition and sending the maximum voltage corresponding to the overcurrent threshold of the ith partition to the slow start chip of the ith partition;

the slow start chip of the ith partition is used for controlling the controllable switch tube of the ith partition to be disconnected when the voltage at two ends of the sampling resistor of the ith partition is greater than or equal to the maximum voltage of the ith partition.

4. A motherboard according to claim 2 or 3, wherein each partition comprises an adjustable sampling resistor network; the switching circuit and the adjustable sampling resistor network are connected in series and then connected between the power input end of the main board and a load;

the adjustable sampling resistor network comprises at least two resistors and at least one switch;

the control circuit is specifically configured to control, according to the overcurrent threshold of the ith partition, a state of the switch of the ith partition to change an equivalent resistance value of the adjustable sampling resistor network, so as to set a maximum voltage corresponding to the overcurrent threshold of the adjustable sampling resistor network of the ith partition; and when the voltage at two ends of the adjustable sampling resistor network of the ith partition is greater than or equal to the maximum voltage, the switching circuit of the ith partition is controlled to be disconnected.

5. The motherboard of claim 4, wherein the adjustable sampling resistor network comprises M sampling resistors and M-1 switches; m is an integer greater than or equal to 2;

two ends of a first sampling resistor in the M sampling resistors are respectively connected with the power input end and the switching circuit; and the remaining M-1 sampling resistors in the M sampling resistors are respectively connected with the M-1 switches in series and then connected with the first sampling resistor in parallel.

6. A motherboard according to claim 2 or 3, wherein each partition comprises an adjustable sampling resistor network; the adjustable sampling resistor network is connected between the power input end of the main board and the load;

the adjustable sampling resistor network comprises M resistors and M switches; m is an integer greater than or equal to 2;

the M resistors and the M switches are connected in series respectively in one-to-one correspondence and then connected in parallel;

the control circuit is specifically configured to control the state of the switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network according to the overcurrent threshold of the ith partition, so as to set the maximum voltage of the adjustable sampling resistor network of the ith partition; and when the voltage at two ends of the adjustable sampling resistor network of the ith partition is greater than or equal to the maximum voltage, controlling the M switches of the ith partition to be opened.

7. The motherboard of any of claims 1-6, wherein the control circuit comprises: the device comprises a central processing unit, a baseboard management controller BMC, a complex programmable logic device CPLD and a south bridge chip PCH connected with the central processing unit; the power input end of the main board is used for supplying power to the BMC;

the load of each partition is connected with the CPLD, and the CPLD obtains the load in-place information of each partition; the BMC and the CPLD are communicated to obtain the load bit information of each partition;

the PCH is used for obtaining the specification of the partial load of each partition from the central processing unit and directly obtaining the specification of the partial load of each partition;

and the BMC is used for obtaining the specification of the corresponding load from the PCH according to the load bit information.

8. The motherboard of any of claims 4-6, wherein the control circuit comprises: a baseboard management controller BMC and a complex programmable logic device CPLD;

the load of each partition is connected with the CPLD;

the BMC is specifically configured to send a control instruction to the CPLD according to the overcurrent of the ith partition, and the CPLD controls the state of the switch of the ith partition to change the equivalent resistance value of the adjustable sampling resistor network according to the control instruction.

9. A computing device comprising the motherboard of any of claims 1-8.

10. A control method of a motherboard, comprising:

determining an overcurrent threshold of an ith partition according to the specification of the load of the ith partition; the ith partition is any one partition in the plurality of partitions;

and when the power supply current of the ith partition is larger than the overcurrent threshold, disconnecting the power supply path of the ith partition.