WO2020018094A1

WO2020018094A1 - Selectively enabling power lines to usb ports

Info

Publication number: WO2020018094A1
Application number: PCT/US2018/042734
Authority: WO
Inventors: Binh T. Truong; Mengistu TAYE; Kevin J. Broussard
Original assignee: Hewlett-Packard Development Company, L.P.
Priority date: 2018-07-18
Filing date: 2018-07-18
Publication date: 2020-01-23

Abstract

A computing device that includes a basic input/output system (BIOS), an integrated circuit comprising a power switch communicatively coupled to the BIOS, an enable input pin on the integrated circuit to receive a signal to selectively enable and disable a power line to a USB port communicatively coupled to the integrated circuit.

Description

SELECTIVELY ENABLING POWER LINES TO USB PORTS

BACKGROUND

[0001] Computing devices may include a number of ports to allow external hardware devices to interface with the computing device. These hardware devices may include smartphones, mice, keyboards, external data storage devices, CD/DVD/Blu-ray readable/writable devices, and flash drives, among others. These external hardware devices may gain access to the power supply and/or data lines associated with the computing device.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The accompanying drawings illustrate various examples of the principles described herein and are part of the specification. The illustrated examples are given merely for illustration, and do not limit the scope of the claims.

[0003] Fig. 1 is a block diagram of a computing device according to an example of the principles described herein.

[0004] Fig. 2 is a block diagram of a power switch according to an example of the principles described herein.

[0005] Fig. 3 is a block diagram of an integrated circuit coupled to a processor of a computing device and a universal serial bus (USB) port according to an example of the principles described herein.

[0006] Fig. 4 is a circuit diagram of a power switch according to an example of the principles described herein. [0007] Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements. The figures are not necessarily to scale, and the size of some parts may be exaggerated to more clearly illustrate the example shown. Moreover, the drawings provide examples and/or implementations consistent with the description; however, the description is not limited to the examples and/or implementations provided in the drawings.

DETAILED DESCRIPTION

[0008] External hardware devices may be communicatively coupled to a computing device via, for example, a universal serial bus (USB) port. The USB port may include a power line to supply power to the external hardware device, a data line to provide access to the processing powers and/or data storage devices on the computing device, or both. In some instances, these computing devices may be presented to a user prior to purchase in order for the user to determine the capabilities of the computing device. Additionally, in some examples a purchased computing device may be left on a desk or table with access to the USB ports open for use by another user. Leaving the power and/or data lines available on these ports may pose security risks to the computing device if a USB device, such as a flash drive is interfaced with the USB port.

[0009] The present specification describes, a computing device that includes a basic input/output system (BIOS), an integrated circuit comprising a power switch communicatively coupled to the BIOS, an enable input pin on the integrated circuit to receive a signal to selectively enable and disable a power line to a USB port communicatively coupled to the integrated circuit.

[0010] The present specification further describes a power switch that includes an enable input pin to receive a signal from a basic input/output system (BIOS) to selectively enable and disable a power line to a USB port

communicatively coupled to the power switch and a Vout pin to supply power to the USB port. [0011] The present specification also describes an integrated circuit communicatively coupled to a processor of a computing device and a universal serial bus (USB) port that includes a voltage in pin to receive a voltage from the processor and an enable input pin to receive a signal from the processor after executing the BIOS to selectively enable and disable a power line to a USB port communicatively coupled to the integrated circuit.

[0012] T urning now to the figures, Fig. 1 is a block diagram of a computing device (100) according to an example of the principles described herein. The computing device (100) may include a basic input/output system (BIOS) (105) and an integrated circuit (1 10) to disable a power line to a USB port communicatively coupled to the integrated circuit (1 10) as described herein. The integrated circuit (1 10) may, via a power switch (1 15) on the integrated circuit (1 10), may receive a signal at an enable input pin (120) of the power switch (1 15) from the BIOS (105) to disable the power line to the USB port.

[0013] In any example presented herein, the integrated circuit (1 10) with its power switch (1 15) and enable input pin (120) may be a stand-alone integrated circuit (1 10) that may be coupled to a central processing unit or any other processor of the computing device (100) executing the BIOS (105). In any example presented herein, the integrated circuit (1 10) may form part of a motherboard of the computing device (100) and may have the power switch (1 15) with its enable input pin (120) formed into the printed circuit board (PCB) of the motherboard.

[0014] In any example presented herein, the power switch (1 15) may receive a signal from the execution of the BIOS (105) at the enable input pin (120) to disable a power line to a USB port communicatively coupled to the power switch (1 15) on the integrated circuit (1 10). In some examples, an add- on peripheral component interconnect express (PCIe) powered universal serial bus (PUSB) card may be communicatively coupled to the processor executing the BIOS (105) of the computing device (100). In an example, the PUSB card may provide a 12V lead to a power pin at the USB port. In an example, the PUSB card may provide a 24V lead to a power pin at the USB port. In some examples, the individual PUSB ports may not be managed by the motherboard and therefor may be accessed by any user with any type of external hardware device. This may pose a security issue if, for example, a flash drive is used to interface with the PUSB port in order to upload or execute nefarious program code that could harm or damage the computing device (100). In an example, the execution of the BIOS (105), by pressing a function key for example, may allow a user to selectively turn on or off the power to these PUSB ports. In this example, a user may be presented, via a display device, an option to turn off power to the PUSB port. This option, as provided by execution of the BIOS (105) by the computing device (100), may send a signal to the enable input pin (120) of the power switch (1 15) on the integrated circuit (1 10) in order to disable the power lines to any of the PUSB ports regardless of their communication with any PCIe PUSB cards.

[0015] In an example, upon execution of the BIOS (105) by the processor of the computing device (100), a user may be presented with a further interface to select whether a data line associated with a PUSB port is disabled or not. In this example, the enable input pin (120) on the integrated circuit (1 10) may also receive a signal to disable or enable the data pines at the PUSB ports regardless of whether the PUSB ports are communicatively coupled to a PCIe PUSB card or not.

[0016] In an example, the enable input pin (120) among other pins of the integrated circuit (1 10) may be general-purpose input/output (GPIO) pins. The GPIO pins may control the PUSB and/or USB differential data line, 5V power line, and/or the 12V/24V PUSB power line. In this example, the integrated circuit (1 10) may route to both the PUSB ports directly coupled to the integrated circuit (1 10) and those communicatively coupled to the, for example, a PCIe PUSB card to be controlled as described. In any of the examples presented herein, however, when the signal is received by the enable input pin (120), a Vout pin is de-asserted and cut off from power output to the power pins of the PUSB and/or USB ports. In any example presented herein, the power switch (1 15) may also assert an overcurrent (OC) pin when an overcurrent is present on the Vout pin. In this example, Vout power is then cut-off through the de- assertion of the enable input pin (120) signal. [0017] Fig. 2 is a block diagram of a power switch (200) according to an example of the principles described herein. The power switch (200) may include an enable input pin (205) and a Vout pin (215) that coordinate to selectively enable and disable a power line (210) to a USB port communicatively coupled to the power switch (200).

[0018] In an example presented herein, the Vout pin (215) may be directly coupled to a power pin of a USB or PUSB port. As a consequence, the power may be selectively disabled and enabled by the user. In an example, the power switch (200) may receive, at the enable input pin (205), a signal from a processor of a computing device to assert the Vout pin (215) in order to de- assert the Vout pin (215). In an example, the processor executes a BIOS of the computing device so as to present, to a user, an option to either enable or disable the Vout pin (215) via assertion of the enable input pin (205). The user may implement a hardware device such as a mouse to make a selection on a user interface to cause either the enablement or disablement of the Vout pin (215), and consequently, the power line (210) to any of the USB and/or PUSB ports.

[0019] In any example presented herein, the power switch (200) may further include a data line communicatively coupled to each of the USB and/or PUSB ports. In a similar fashion as the Vout pin (215), a BIOS of a computing device, after a user-selection, may cause a signal to be sent to the enable input pin (205). The enable input pin (205), when asserted, may further cause the data output pin of the power switch (200) to be de-asserted. In this way, the power switch (200) may, via execution of a BIOS and signals received from a processor of a computing device, selectively cause the enablement and disablement of the power line (210) and/or data line to a USB and/or PUSB port.

[0020] Fig. 3 is a block diagram of an integrated circuit (300) coupled to a processor of a computing device and a universal serial bus (USB) port according to an example of the principles described herein. In an example, the integrated circuit (300) may include a voltage in (Vin) pin (305) to receive a voltage from the processor of a computing device. In this example, the voltage may be used to power an external hardware device at a USB or PUSB port as described herein. In this example, the integrated circuit (300) may further include a voltage out (Vout) pin to, when enabled, provide a voltage to a power line at the USB or PUSB port.

[0021] The integrated circuit (300) may further include an enable input pin (310) to receive a signal from the processor after executing the BIOS to selectively enable and disable a power line to a USB port communicatively coupled to the integrated circuit. In an example, the enable input pin (205) on the integrated circuit (300) receives a signal to selectively enable and disable a data line to the USB port communicatively coupled to the integrated circuit. In this way, the integrated circuit (300) may implement the enablement and/or disablement of both the power and data lines to the USB and or PUSB ports.

[0022] In nay example presented herein, the enable input pin (120) on the integrated circuit (300) receives a signal to disable a 5V power line to the USB port, a 12V power line to the USB port, a 24V power line to the USB port, or combinations thereof. By preventing the powering of the USB ports, the user may be capable of adding additional security to the computing device thereby preventing the powering of an external hardware device such as a flash drive.

[0023] In any example presented herein, the integrated circuit (300) may include an overcurrent pin that prevents power to a Vout pin on integrated circuit (300) when an overcurrent is detected. In an example, the power may be prevented from reaching the Vout pin by de-asserting the enable input pin (205).

[0024] Any number of hardware configurations may be realized in the present specification that communicatively couple the integrated circuit (300) to the USB and/or PUSB ports as well as the processor of the computing device as described herein. I an example, the signal presented to the enable input pin (205) to asset or de-assert the Vout pin of the integrated circuit (300) is received from a platform controller hub of the computing device. In another example, the signal presented to the enable input pin (205) to asset or de-assert the Vout pin of the integrated circuit (300) is received from a serial input/output (SIO) system. Although specific examples have been presented herein, the present

specification contemplates the use of any hardware configuration to send signals to the enable input pin (205) of the integrated circuit (300) so as to selectively assert and de-assert the Vout pin of the integrated circuit (300).

[0025] Fig. 4 is a circuit diagram of a power switch (400) according to an example of the principles described herein. Although Fig. 4 shows a specific layout of any pins described herein, the present circuit diagram of the power switch (400) is meant as an example. Thus, the present specification contemplates the use of any circuit that accomplishes the processes and principles described herein.

[0026] In the example shown in Fig. 4, the power switch (400) may include a Vin pin (405), a Vout pin (410), an enable input pin (415), a ground pin (420), and a flag pin (425). As described herein, the Vin pin (405) may receive a voltage from a computing device or other power source. The enable input pin (415) receives signals from a processing device of a computing device descriptive of either enabling or disenabling the Vout pin (410) depending on whether the user has selected the voltage to run to the voltage pin of a USB and/or PUSB port. The flag pin (425) may provide for situations where an overcurrent is presented in the power switch (400). In this example, when an overcurrent is detected on the Vout pin (410), Vout power may be cut-off through the de-assertion of the enable input signal received from the processor.

[0027] The integrated circuit (300) and power switch (400) may be implemented in an electronic device. Examples of electronic devices include servers, desktop computers, laptop computers, personal digital assistants (PDAs), mobile devices, smartphones, gaming systems, and tablets, among other electronic devices.

[0028] To achieve its desired functionality, the computing device (100) with its integrated circuit (300) and power switch (400) may include various hardware components. Among these hardware components may be a number of processors as described herein, a number of data storage devices, a number of peripheral device adapters, and a number of network adapters. These hardware components may be interconnected through the use of a number of busses and/or network connections. In one example, the processor, data storage device, peripheral device adapters, and a network adapter may be communicatively coupled via a bus.

[0029] The processor may include the hardware architecture to retrieve executable code from the data storage device such as a BIOS and execute the executable code. The executable code may, when executed by the processor, cause the processor to implement at least the functionality of providing a signal to the power switch (400) in order to selectively enable and disenable the voltage output line to a USB and/or PUSB port according to the methods of the present specification described herein. In the course of executing code, the processor may receive input from and provide output to a number of the remaining hardware units.

[0030] The data storage device may store data such as executable program code that is executed by the processor or other processing device.

The data storage device may include various types of memory modules, including volatile and nonvolatile memory. For example, the data storage device of the present example includes Random Access Memory (RAM), Read Only Memory (ROM), and Hard Disk Drive (HDD) memory. Many other types of memory may also be utilized, and the present specification contemplates the use of many varying type(s) of memory in the data storage device as may suit a particular application of the principles described herein. In certain examples, different types of memory in the data storage device may be used for different data storage needs. For example, in certain examples the processor may boot from Read Only Memory (ROM), maintain nonvolatile storage in the Hard Disk Drive (HDD) memory, and execute program code stored in Random Access Memory (RAM).

[0031] The hardware adapters in the computing device (100) enable the processor (101 ) to interface with various other hardware elements, external and internal to the computing device (100). For example, the peripheral device adapters may provide an interface to input/output devices, such as, for example, display device, a mouse, or a keyboard. The peripheral device adapters may also provide access to other external devices such as an external storage device, a number of network devices such as, for example, servers, switches, and routers, client devices, other types of computing devices, and combinations thereof.

[0032] The display device may be provided to allow a user of the computing device (100) to interact with and implement the functionality of the power switch (400). The peripheral device adapters may also create an interface between the processor and the display device, a printer, or other media output devices. The network adapter may provide an interface to other computing devices within, for example, a network, thereby enabling the transmission of data between the computing device (100) and other devices located within the network.

[0033] The display device may, upon executed of the BIOS by the processor, display the number of graphical user interfaces (GUIs) on thereon associated with the BIOS code. The GUIs may include aspects of the executable code including presentation to a user of options to enable and disenable a Vout and/or data line to a USB and/or PUSB port. The GUIs may display, for example, any number of selections describing the functions of the power switch (400) and allowing the user to enable and disenable a Vout and/or data line to a USB and/or PUSB port. Additionally, via making a number of interactive gestures on the GUIs of the display device, a user may make a selection in order to enable and disenable a Vout and/or data line to a USB and/or PUSB port. Examples of display devices include a computer screen, a laptop screen, a mobile device screen, a personal digital assistant (PDA) screen, and a tablet screen, among other display devices.

[0034] Aspects of the present system and method are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to examples of the principles described herein. Each block of the flowchart illustrations and block diagrams, and combinations of blocks in the flowchart illustrations and block diagrams, may be implemented by computer usable program code. The computer usable program code may be provided to a processor of a general- purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer usable program code, when executed via, for example, the processor of the computing device (100) or other programmable data processing apparatus, implement the functions or acts specified in the flowchart and/or block diagram block or blocks. In one example, the computer usable program code may be embodied within a computer readable storage medium; the computer readable storage medium being part of the computer program product. In one example, the computer readable storage medium is a non-transitory computer readable medium.

[0035] The specification and figures describe a power switch that enables a user to enable or disenable the voltage output to a USB and/or PUSB port. Additionally, the data line may be selectively enabled and disenabled. Thus, the security of the computing device may be increased resulting in better security to the hardware and data within the computing device.

[0036] The preceding description has been presented to illustrate and describe examples of the principles described. This description is not intended to be exhaustive or to limit these principles to any precise form disclosed. Many modifications and variations are possible in light of the above teaching.

Claims

CLAIMS WHAT IS CLAIMED IS:

1. A computing device, comprising:

a basic input/output system (BIOS);

an integrated circuit comprising a power switch communicatively coupled to the BIOS;

an enable input pin on the integrated circuit to receive a signal to selectively enable and disable a power line to a USB port communicatively coupled to the integrated circuit.

2. The computing device of claim 1 , wherein the enable input pin on the integrated circuit receives a signal to selectively enable and disable a data line to the USB port communicatively coupled to the integrated circuit.

3. The computing device of claim 1 , wherein the enable input pin on the integrated circuit receives a signal to disable a 5V power line to the USB port, a 12V power line to the USB port, a 24V power line to the USB port, or combinations thereof.

4. The computing device of claim 1 , further comprising a graphical user interface to present to a user the option to selectively enable and disable a data line to a USB port communicatively coupled to the integrated circuit.

5. The computing device of claim 4, wherein the graphical user interface presents to a user the option to selectively enable and disable the power line to a USB port communicatively coupled to the integrated circuit.

6. The computing device of claim 1 , wherein the integrated circuit further comprises an overcurrent pin that prevent power to a Vout pin on the integrated circuit when an overcurrent is detected by de-asserting the enable input pin.

7. A power switch, comprising:

an enable input pin to receive a signal from a basic input/output system (BIOS) to selectively enable and disable a power line to a USB port

communicatively coupled to the power switch; and

a Vout pin to supply power to the USB port.

8. The power switch of claim 7, wherein the enable input pin receives a signal to disable a 5V power line to the USB port, a 12V power line to the USB port, a 24V power line to the USB port, or combinations thereof.

9. The power switch of claim 7, wherein the enable input pin is

communicatively coupled to a processing device executing the BIOS.

10. An integrated circuit communicatively coupled to a processor of a computing device and a universal serial bus (USB) port, comprising:

a voltage in pin to receive a voltage from the processor;

an enable input pin to receive a signal from the processor after executing the BIOS to selectively enable and disable a power line to a USB port communicatively coupled to the integrated circuit.

1 1. The integrated circuit of claim 10, wherein the enable input pin on the integrated circuit receives a signal to selectively enable and disable a data line to the USB port communicatively coupled to the integrated circuit.

12. The integrated circuit of claim 10, wherein the enable input pin on the integrated circuit receives a signal to disable a 5V power line to the USB port, a 12V power line to the USB port, a 24V power line to the USB port, or combinations thereof.

13. The integrated circuit of claim 10, wherein the integrated circuit further comprises an overcurrent pin that prevent power to a Vout pin on the integrated circuit when an overcurrent is detected by de-asserting the enable input pin.

14. The integrated circuit of claim 10, wherein the signal to the enable input pin is received from a platform controller hub.

15. The integrated circuit of claim 10, wherein the signal to the enable input pin is received from a serial input/output (SIO) system.