CN116949568A - Method for obtaining epitaxial layer process conditions and epitaxial layer forming method - Google Patents

Method for obtaining epitaxial layer process conditions and epitaxial layer forming method Download PDF

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Publication number
CN116949568A
CN116949568A CN202310835203.1A CN202310835203A CN116949568A CN 116949568 A CN116949568 A CN 116949568A CN 202310835203 A CN202310835203 A CN 202310835203A CN 116949568 A CN116949568 A CN 116949568A
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epitaxial layer
heating assembly
wafer
process temperature
heating
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丁科允
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Jiangsu Tianxin Micro Semiconductor Equipment Co ltd
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Jiangsu Tianxin Micro Semiconductor Equipment Co ltd
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    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/16—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/10—Heating of the reaction chamber or the substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Vapour Deposition (AREA)

Abstract

The invention relates to a method for obtaining epitaxial layer process conditions, which comprises the following steps: s1, providing an epitaxial device, wherein the epitaxial device comprises a cavity, an upper heating component arranged above the cavity, and a lower heating component arranged below the cavity; s2, providing a wafer; s3, setting a first process temperature; s4, setting power parameters of the upper heating assembly and the lower heating assembly; s5, adjusting the first process temperature to a second process temperature, and simultaneously introducing process gas into the cavity to grow an epitaxial layer; s6, selecting a plurality of points on the surface of the wafer, measuring the thickness of the epitaxial layer of each point, judging whether the thickness of each point meets the preset condition, if not, adjusting the power parameters of the upper heating assembly and the lower heating assembly, and re-executing the steps S4 to S6; if yes, executing step S7; s7, recording the final power parameters and the corresponding first and second process temperatures to form the epitaxial layer. The process conditions obtained by the method can avoid the relaxation phenomenon of the wafer.

Description

Method for obtaining epitaxial layer process conditions and epitaxial layer forming method
Technical Field
The invention relates to the field of semiconductor epitaxial layer manufacturing, in particular to a method for obtaining epitaxial layer process conditions and a method for forming an epitaxial layer.
Background
Typically, the susceptor of the epitaxial apparatus is made of graphite, the wafer is typically monocrystalline silicon, and the specific heat capacities of the two are different, and the temperature will be different during heating. In addition, the front surface and the back surface of the wafer are heated by heat radiation obtained by heating the upper lamp set, the back surface of the wafer is irradiated on the base through the lower lamp set, then the base absorbs heat, the heat is transferred to the back surface of the wafer for heating in a heat conduction mode, and the heat conducted by the base is different at all positions of the back surface of the wafer, so that the lifting speed of the wafer in the lifting temperature process is different, the temperature of the wafer is different at all positions when the temperature of the wafer is lifted in the epitaxial layer growing process, and the problem of relaxation and stress generation in the epitaxial layer is caused.
It is therefore highly desirable to provide a countermeasure to the temperature variation problem across the wafer.
Disclosure of Invention
The invention aims to provide a method for obtaining epitaxial layer process conditions, which can ensure that the temperatures of all positions of a wafer are consistent.
The invention provides a method for obtaining epitaxial layer process conditions, which comprises the following steps:
s1, providing an epitaxial device, wherein the epitaxial device comprises a cavity and a heating assembly, and the heating assembly comprises an upper heating assembly arranged above the cavity and a lower heating assembly arranged below the cavity;
s2, providing a wafer;
s3, setting a first process temperature;
s4, setting power parameters of the upper heating assembly and the lower heating assembly;
s5, forming an epitaxial layer: adjusting the first process temperature to a second process temperature, simultaneously introducing process gas into the cavity, and growing an epitaxial layer on the surface of the wafer;
s6, thickness measurement: selecting a plurality of point positions on the surface of the wafer, measuring the thickness of an epitaxial layer of each point position, judging whether the thickness of each point position meets a preset condition, if not, adjusting the power parameters of the upper heating assembly and the lower heating assembly, and re-executing the steps S4 to S6; if yes, executing step S7;
s7, recording the final power parameters and the corresponding first and second process temperatures to obtain the process conditions of the epitaxial layer.
Preferably, the power parameter includes an upper and lower power ratio.
Preferably, the upper heating assembly comprises an upper inner ring heating assembly and an upper outer ring heating assembly; the upper inner ring heating assembly is used for heating the inner ring of the wafer, and the upper outer ring heating assembly is used for heating the outer ring of the wafer; the lower heating assembly comprises a lower inner ring heating assembly and a lower outer ring heating assembly, the lower inner ring heating assembly is used for heating the inner ring of the base of the cavity, and the lower outer ring heating assembly is used for heating the outer ring of the base of the cavity; the upper inner ring heating assembly, the upper outer ring heating assembly, the lower inner ring heating assembly and the lower outer ring heating assembly respectively comprise a plurality of fan-shaped heating areas with independent temperature control.
Preferably, the power parameter includes upper and lower power duty ratios and power distribution of each heating zone.
Preferably, the adjusting the first process temperature to the second process temperature in the step S5 includes:
heating from a first process temperature to a second process temperature; or alternatively, the process may be performed,
cooling from the first process temperature to a second process temperature.
Preferably, when the first process temperature is raised to a second process temperature, the second process temperature is 650-900 ℃; or (b)
When the first process temperature is reduced to the second process temperature, the second process temperature is 625-800 ℃.
Preferably, in the step S6, selecting the points on the surface of the wafer includes selecting the points on the diameter of the surface of the wafer along the first direction.
Preferably, in the step S6, selecting a plurality of points on the surface of the wafer further includes selecting a plurality of points on the diameter of the surface of the wafer along the second direction; the first direction and the second direction form an included angle, and the included angle is more than 40 degrees and less than or equal to 90 degrees.
Preferably, in the step S6, the determining whether the thickness of each point location meets the preset condition is: judging whether the thickness uniformity of each point along the first direction meets a preset condition and/or judging whether the thickness uniformity of each point along the second direction meets the preset condition.
Preferably, the preset condition is thickness uniformity of 2.2% or less.
Preferably, the number of spots is 20 to 200.
Preferably, the process gas comprises a silicon source gas comprising SiH 4 、SiHCl 3 、SiH 2 Cl 2 And SiCl 4 One or more of them.
Preferably, in step S2, a silicon germanium epitaxial layer is disposed on the surface of the wafer; in step S5, the grown epitaxial layer is a silicon epitaxial layer.
In addition, the invention also provides an epitaxial layer forming method, and the epitaxial layer is prepared through the process conditions obtained by the method for obtaining the process conditions of the epitaxial layer.
The invention has the following beneficial effects:
1. the process conditions obtained by the invention can ensure the consistency of the growth of the epitaxial layer at each point in time and space in the subsequent epitaxial layer growth process, and avoid the problems of relaxation and stress.
2. According to the invention, the silicon source gas is introduced to grow the silicon epitaxial layer in the temperature raising and lowering process, so that the thickness presentation during process gas decomposition can be reflected.
3. The fan-shaped heating area corresponds to the thicknesses of the point positions in the first direction and the second direction, and can be used for adjusting proper power parameters. The temperature rising and falling rates of the upper surface and the lower surface of the wafer are consistent by changing the upper power and the lower power of the heating component. By controlling the power distribution of each fan-shaped heating zone, the uniformity of the wafer growth rate in space is realized.
Drawings
FIG. 1 is a block diagram of an epitaxial apparatus of the present invention;
FIG. 2 is a schematic view of a heating assembly in zones;
FIG. 3 is a schematic view of a wafer taking measurement sites;
FIG. 4 is a graph of heating temperature at a point on a wafer;
fig. 5 is a flow chart of a method of forming process conditions for epitaxial layers according to the present invention.
Detailed Description
The method for obtaining the process conditions of the epitaxial layer and the forming method of the epitaxial layer according to the present invention are described in further detail below with reference to the accompanying drawings and the detailed description.
The invention mainly provides a method for obtaining epitaxial layer process conditions, wherein the process conditions comprise relevant parameters such as process temperature, process gas, power parameters and the like. The growth rate of the epitaxial layer is different under different process temperature conditions based on the epitaxial equipment; and at different points on the surface of the wafer, the growth rate is different due to different temperatures; in addition, at different moments, temperature changes can cause temperature overcharging, which can spatially and temporally lead to problems of relaxation or stress within the epitaxial layer.
In order to ensure that the temperature difference at each point on the surface (front surface and back surface) of the wafer is minimum and prevent the problem of relaxation inside the epitaxial layer, the invention provides a method for obtaining the process conditions of the epitaxial layer so as to reduce the influence of temperature fluctuation on the quality of the epitaxial layer.
Referring to fig. 1, the epitaxial apparatus of the present invention includes a chamber and a heating assembly, wherein the chamber 100 includes a sidewall, an upper flange, a lower flange, an upper dome 101 and a lower dome 102 made of quartz, and the upper dome 101 and the lower dome 102 are fixed on the sidewall through the upper flange and the lower flange so as to form a chamber 100 in a sealing manner; the chamber 100 also includes a graphite base 103 disposed within the chamber, the graphite base 103 being supported by a support bar structure 104, and a wafer 107 being disposed on top of the graphite base 103. Heating assemblies 105 are arranged above and below the outer side of the cavity 100, and the heating assemblies 105 comprise an upper heating assembly arranged above the cavity and a lower heating assembly arranged below the cavity; optionally, the heating component is a halogen heating lamp, which can radiate heat to the interior of the cavity 100 for heating. Wherein the upper heating assembly 105 disposed above the chamber and the lower heating assembly 105 disposed below the chamber are individually controllable for heating the upper and lower portions of the graphite substrate 103 within the chamber, respectively. The upper and lower sides of the cavity are also provided with thermometers 106 for monitoring the surface temperatures of the graphite substrate 103 and the wafer 107.
The epitaxial layer growth process is a process gas pyrolysis recombination process, and the process temperature directly affects the rate of progress of the process. At different temperatures, the epitaxial layer growth rates are different, and the temperature difference across the wafer surface can cause relaxation and stress problems inside the epitaxial layer. In this regard, the present invention proposes a method for obtaining epitaxial layer process conditions, referring to fig. 5, the method comprises the following steps:
s1, providing an epitaxial device, for example, selecting the epitaxial device shown in the above figure 1, wherein the epitaxial device comprises a cavity 100 and a heating assembly 105, and the heating assembly comprises an upper heating assembly arranged above the cavity and a lower heating assembly arranged below the cavity;
s2, providing a wafer; placing the wafer on a graphite substrate 103 for epitaxial layer growth;
s3, setting a first process temperature;
s4, setting power parameters of the upper heating assembly and the lower heating assembly;
s5, forming an epitaxial layer: adjusting the first process temperature to a second process temperature, simultaneously introducing process gas into the cavity, and growing an epitaxial layer on the surface of the wafer; the growth process is synchronized with a temperature change from a first process temperature to a second process temperature;
s6, thickness measurement: selecting a plurality of points on the surface of the wafer, measuring the thickness of the epitaxial layer of the points, judging whether the thickness of each point meets the preset condition, if not, adjusting the power parameters of the upper heating assembly and the lower heating assembly, and re-executing the steps S4 to S6; if yes, executing step S7;
s7, recording the final power parameters and the corresponding first and second process temperatures to obtain the process conditions of the epitaxial layer.
Optionally, the number of the points is 10 to 200; in the step S6, it is determined whether the thickness of each point location satisfies a preset condition: judging whether the thickness uniformity of each point position meets the preset condition, preferably, the preset condition is that the thickness uniformity is less than or equal to 2.2%, and the preset condition can ensure that the temperature difference of each point position is small, thereby preventing the problems of relaxation and stress generation in the epitaxial layer.
Wherein thickness uniformity= (maximum thickness-minimum thickness)/maximum thickness×100%.
It should be noted that the power parameter includes an upper power ratio and a lower power ratio, that is, a ratio of the power of the upper heating component to the total power and a ratio of the power of the lower heating component to the total power.
The temperature change in step S5 may be a temperature raising process or a temperature lowering process, that is, the adjustment of the first process temperature to the second process temperature includes: heating from a first process temperature to a second process temperature; or cooling from the first process temperature to the second process temperature. Ideally, the temperature change curve of the wafer during the process temperature adjustment is a smoothly rising or falling curve, and when the preset second process temperature is reached, the temperature of the wafer fluctuates in a small range. Referring to fig. 4, a temperature change curve of a wafer is shown by a dashed line, but due to different heating modes of the front surface and the back surface of the wafer, a temperature overcharge phenomenon occurs in the temperature change process, that is, when the temperature reaches a preset second process temperature value, the temperature will cross the second process temperature and then return to the second process temperature, the solid line in the figure is the temperature overcharge curve, and the deposition quality of the epitaxial layer of the wafer will be affected by the temperature overcharge, resulting in the occurrence of relaxation. In order to alleviate the temperature overcharge phenomenon, the power parameters of the heating components on the upper side and the lower side of the cavity need to be adjusted, mainly, the upper power duty ratio and the lower power duty ratio of the heating components are adjusted, alternatively, the power duty ratio can be changed or unchanged in time, for example, the upper power duty ratio and the lower power duty ratio are always unchanged in the process from time t1 to time t 2; or the up-down power ratio at the time t1 is P1, the up-down power ratio at the time t2 is P2, the up-down power ratio at the time t3 is P3, etc., that is, the up-down power ratio is changed in time in the process from the first process temperature to the second process temperature. And after each power parameter adjustment, performing the steps S4-S6, and recording corresponding process conditions after the thickness uniformity is measured to be ideal (i.e. the thickness uniformity meets the preset conditions). The advantages are that: the temperature difference of the wafer can be adjusted spatially (i.e., the upper and lower surfaces of the wafer) and temporally to prevent the occurrence of relaxation.
In this example, the more suitable process temperatures are: when the first process temperature is raised to the second process temperature, the second process temperature is 650-900 ℃; or when the first process temperature is reduced to a second process temperature, the second process temperature is 625-800 ℃.
Preferably, referring to fig. 1, the upper heating assembly 105 includes an upper inner ring heating assembly and an upper outer ring heating assembly; the upper inner ring heating assembly is used for heating the inner ring of the wafer, and the upper outer ring heating assembly is used for heating the outer ring of the wafer; the lower heating assembly 105 comprises a lower inner ring heating assembly and a lower outer ring heating assembly, wherein the lower inner ring heating assembly is used for heating an inner ring of the base of the cavity, and the lower outer ring heating assembly is used for heating an outer ring of the base of the cavity; referring to fig. 2, the upper inner ring heating assembly, the upper outer ring heating assembly, the lower inner ring heating assembly and the lower outer ring heating assembly are all formed by a plurality of heating lamps in an annular arrangement, and the upper inner ring heating assembly, the upper outer ring heating assembly, the lower inner ring heating assembly and the lower outer ring heating assembly respectively comprise a plurality of fan-shaped heating zones with independent temperature control, for example, three heating lamps in a dotted line in fig. 2 form a fan-shaped heating zone, so that the total number of the 12 heating lamps can form 4 fan-shaped heating zones, the 4 fan-shaped heating zones can respectively independently control the temperature without influencing each other, the total number of the heating lamps and the number of the heating lamps of the fan-shaped heating zone are not limited, and the number is only illustrative. Further, the power parameters include upper and lower power duty ratios and power distribution of each heating area, and the power distribution of each heating area is mainly adjusted by means of epitaxial layer thickness data of each point. Of course, alternatively, the power duty cycle and the power distribution of the heating zones may be time-varying or constant, as already explained in detail above, and not specifically explained here.
The selecting the plurality of points on the surface of the wafer includes selecting the plurality of points along a first direction on a diameter of the surface of the wafer. In other examples, referring to fig. 3, selecting points on the surface of the wafer further includes selecting points on the diameter of the surface of the wafer along the second direction; the first direction and the second direction form an included angle, and the included angle is more than 40 degrees and less than or equal to 90 degrees. The first direction and the second direction represent different fan-shaped heating zones respectively, and the power distribution of the heating components of each fan-shaped heating zone can be controlled independently according to the point position data of the two directions. Therefore, determining whether the thickness of each point location satisfies the preset condition includes determining whether the thickness uniformity of each point location along the first direction satisfies the preset condition, and determining whether the thickness uniformity of each point location along the second direction satisfies the preset condition, or determining whether the thickness uniformity of all point locations along the first direction and the second direction satisfies the preset condition. And comparing each point in the first direction with each point in the second direction, the influence of the corresponding fan-shaped heating zone on the epitaxial layer quality can be known, and therefore the power distribution of different heating zones can be adjusted.
In this example, the process gas comprises a silicon source gas comprising SiH 4 、SiHCl 3 、SiH 2 Cl 2 And SiCl 4 One or more of them.
Further, in step S2, a silicon germanium epitaxial layer is disposed on the surface of the wafer; in step S5, the grown epitaxial layer is a silicon epitaxial layer, and the silicon germanium epitaxial layer is first formed on the wafer surface in order to facilitate measurement of the thickness of the silicon epitaxial layer. And the wafer also needs to be baked before the epitaxial layer is grown. In this example, siH is used to form the SiGe epitaxial layer 4 、SiHCl 3 、SiH 2 Cl 2 And SiCl 4 At least one silicon-containing gas and GeH-containing gas 4 、Ge 2 H 6 At least one mixed gas of germanium-containing gas is formed by vapor deposition on the surface of the wafer. The thickness of the silicon germanium epitaxial layer is 10 nanometers to 100 nanometers.
In addition, the invention also provides a method for forming the epitaxial layer, which adopts the process conditions obtained in the step S7 to grow the epitaxial layer, so that the grown epitaxial layer does not relax.
According to the invention, the silicon source gas is introduced in the temperature raising and reducing process to grow the silicon epitaxial layer, and the temperature raising and reducing rate of the wafer in space and time is consistent by changing the power parameter of the heating component, so that the relaxation is prevented.
While the present invention has been described in detail through the foregoing description of the preferred embodiment, it should be understood that the foregoing description is not to be considered as limiting the invention. Many modifications and substitutions of the present invention will become apparent to those of ordinary skill in the art upon reading the foregoing. Accordingly, the scope of the invention should be limited only by the attached claims.

Claims (14)

1. A method for obtaining epitaxial layer process conditions, comprising the steps of:
s1, providing an epitaxial device, wherein the epitaxial device comprises a cavity and a heating assembly, and the heating assembly comprises an upper heating assembly arranged above the cavity and a lower heating assembly arranged below the cavity;
s2, providing a wafer;
s3, setting a first process temperature;
s4, setting power parameters of the upper heating assembly and the lower heating assembly;
s5, forming an epitaxial layer: adjusting the first process temperature to a second process temperature, simultaneously introducing process gas into the cavity, and growing an epitaxial layer on the surface of the wafer;
s6, thickness measurement: selecting a plurality of point positions on the surface of the wafer, measuring the thickness of an epitaxial layer of each point position, judging whether the thickness of each point position meets a preset condition, if not, adjusting the power parameters of the upper heating assembly and the lower heating assembly, and re-executing the steps S4 to S6; if yes, executing step S7;
s7, recording the final power parameters and the corresponding first and second process temperatures to obtain the process conditions of the epitaxial layer.
2. The method of obtaining epitaxial layer process conditions of claim 1, wherein the power parameter comprises an upper and lower power ratio.
3. The method of obtaining epitaxial layer process conditions of claim 1, wherein the upper heating assembly comprises an upper inner ring heating assembly and an upper outer ring heating assembly; the upper inner ring heating assembly is used for heating the inner ring of the wafer, and the upper outer ring heating assembly is used for heating the outer ring of the wafer; the lower heating assembly comprises a lower inner ring heating assembly and a lower outer ring heating assembly, the lower inner ring heating assembly is used for heating the inner ring of the base of the cavity, and the lower outer ring heating assembly is used for heating the outer ring of the base of the cavity; the upper inner ring heating assembly, the upper outer ring heating assembly, the lower inner ring heating assembly and the lower outer ring heating assembly respectively comprise a plurality of fan-shaped heating areas with independent temperature control.
4. A method of obtaining epitaxial layer process conditions according to claim 3 wherein said power parameters include upper and lower power duty cycles and power distribution for each heating zone.
5. The method of obtaining epitaxial layer process conditions of claim 1, wherein adjusting the first process temperature to the second process temperature in step S5 comprises:
heating from a first process temperature to a second process temperature; or alternatively, the process may be performed,
cooling from the first process temperature to a second process temperature.
6. The method of obtaining epitaxial layer process conditions of claim 5, wherein when the first process temperature is raised to a second process temperature, the second process temperature is 650-900 ℃; or (b)
When the first process temperature is reduced to the second process temperature, the second process temperature is 625-800 ℃.
7. The method of claim 1, wherein selecting a plurality of points on the surface of the wafer in the step S6 comprises selecting a plurality of points on a diameter of the surface of the wafer along a first direction.
8. The method of claim 7, wherein selecting a plurality of points on the surface of the wafer in the step S6 further comprises selecting a plurality of points on the diameter of the surface of the wafer along the second direction; the first direction and the second direction form an included angle, and the included angle is more than 40 degrees and less than or equal to 90 degrees.
9. The method for obtaining the epitaxial layer process conditions according to claim 7 or 8, wherein in the step S6, determining whether the thickness of each point location satisfies the preset condition is: judging whether the thickness uniformity of each point position meets the preset condition.
10. The method of claim 9, wherein the predetermined condition is a thickness uniformity of 2.2% or less.
11. The method of obtaining epitaxial layer process conditions of claim 1, wherein the number of sites is 20 to 200.
12. The method of obtaining epitaxial layer process conditions of claim 1, wherein the process gas comprises a silicon source gas comprising SiH 4 、SiHCl 3 、SiH 2 Cl 2 And SiCl 4 One or more of them.
13. The method of obtaining epitaxial layer process conditions of claim 1, wherein in step S2, the wafer surface is provided with a silicon germanium epitaxial layer; in step S5, the grown epitaxial layer is a silicon epitaxial layer.
14. A method of forming an epitaxial layer, characterized in that the epitaxial layer is grown by the process conditions obtained by the method of obtaining the process conditions of an epitaxial layer according to any one of claims 1 to 13.
CN202310835203.1A 2023-07-07 2023-07-07 Method for obtaining epitaxial layer process conditions and epitaxial layer forming method Pending CN116949568A (en)

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CN202310835203.1A CN116949568A (en) 2023-07-07 2023-07-07 Method for obtaining epitaxial layer process conditions and epitaxial layer forming method

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