CN116939052A - High-flux trusted data communication system and method based on PCIE-SRIO - Google Patents
High-flux trusted data communication system and method based on PCIE-SRIO Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L63/00—Network architectures or network communication protocols for network security
- H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
- H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/40—Network security protocols
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Abstract
The invention discloses a high-throughput trusted data communication system and method based on PCIE-to-SRIO, which belong to the technical field of communication and comprise a PCIE processing module, a protocol conversion module, a trusted security module and an SRIO processing module which are sequentially connected in series; the PCIE processing module is used for sending and receiving PCIE messages and carrying out data communication with the upstream equipment through a PCIE bus; the protocol conversion module performs data conversion on the PCIE protocol and the SRIO protocol; the trusted security module encrypts and decrypts the communication data of the SRIO packet to ensure the security and credibility of the data; the SRIO processing module is used for sending and receiving SRIO protocol data and is connected with the opposite terminal equipment through the SRIO bus for communication. The invention realizes the effective data transmission communication of 20Gbps on 4 pairs of differential lines, and the data can be trusted and safe.
Description
Technical Field
The invention relates to the technical field of communication, in particular to a high-throughput trusted data communication system and method based on PCIE-SRIO.
Background
PCIE (Peripheral Component Interconnect Express, PCI express) buses are a third type of high performance I/O bus that interconnects peripheral devices in computer and communication platform applications, and are widely used for I/O device interconnect in embedded technology, desktop computers, mobile platforms, and communication platforms. SRIO (Serial Rapid I/O) bus technology is mainly oriented to communication interconnection of high-performance embedded systems.
The traditional PCIE-SRIO bridge chip has single function and low expansibility, and meanwhile, along with the wide application of PCIE and SRIO buses in the fields of aerospace, military electronics and the like, the requirements of people on communication safety are higher and higher. Therefore, there is a need for a high-throughput trusted data communication system based on PCIE to SRIO.
Disclosure of Invention
The invention aims to provide a high-throughput trusted data communication system and method based on PCIE-SRIO, which are used for solving the problems of single function, low expansibility and low communication security of the traditional PCIE-SRIO bridge chip.
In order to solve the technical problems, the invention provides a high-throughput trusted data communication system based on PCIE-to-SRIO, which comprises a PCIE processing module, a protocol conversion module, a trusted security module and an SRIO processing module;
one side of the PCIE processing module is connected with a PCIE bus, the other side of the PCIE processing module is connected with one side of the protocol conversion module, the other side of the protocol conversion module is connected with one side of the trusted security module, the other side of the trusted security module is connected with one side of the SRIO processing module, and the other side of the SRIO processing module is connected with an SRIO bus;
the PCIE processing module is used for sending and receiving PCIE messages and carrying out data communication with upstream equipment through a PCIE bus;
the protocol conversion module performs data conversion on PCIE protocol and SRIO protocol;
the trusted security module encrypts and decrypts the communication data of the SRIO packet to ensure the security and the credibility of the data;
the SRIO processing module is used for sending and receiving SRIO protocol data and is connected with the opposite terminal equipment through an SRIO bus for communication;
the high-throughput trusted data communication system based on PCIE-SRIO also comprises a clock module, a reset module, a configuration module and a debugging module; the clock module provides a normal working clock of the whole system; the reset module provides reset of each internal logic; the configuration module is used for configuring the operation mode of the whole system; the debugging module is used for providing function debugging of each module in the whole system.
In one embodiment, the PCIE processing module includes a PCIE physical interface module and a PCIE logical processing module; the PCIE physical interface module is used for connecting upstream equipment of a PCIE bus, supporting PCIE2.1 protocol, supporting x4/x2/x1 links, and enabling the highest data flux to reach 20Gbps; the PCIE logic processing module is configured to process TPL packets sent and received by the upstream device, and implement functions of classification filtering, buffer queuing and priority arbitration of TLP packets.
In one embodiment, the protocol conversion module includes a Message engine, a Mapping engine, a DMa engine, and an inter engine; the Message engine module is used for realizing conversion between PCIE packets and SRIO Message packets; the Mapping engine is used for realizing conventional packet conversion between PCIE and SRIO; the DMa engine is used for realizing a DMA function and improving the conversion efficiency of data; the inter engine is configured to implement conversion of an Interrupt request of an SRIO to the PCIE processing module.
In one embodiment, the trusted security module includes data encryption and data decryption, and adopts a trusted communication cryptographic algorithm standard conforming to the international standard to meet the characteristics of confusion and diffusion of the cryptographic algorithm.
In one embodiment, the SRIO processing module includes an SRIO physical interface module and an SRIO logic processing module; the SRIO physical interface module is used for connecting the physical connection of the SRIO equipment at the opposite end, supporting the SRIO2.2 protocol, supporting the x4/x2/x1 link, and enabling the highest data flux to reach 25Gbps; the SRIO logic processing module is used for realizing doorbell, message, DMA, nread/Nwrite various data communication functions of the SRIO protocol.
In one embodiment, the clock module includes two sets of clock differential inputs, one set for use by the PCIE processing module and the other set for use by the SRIO processing module.
In one embodiment, the debug module supports JTAG boundary scan, and an external JTAG emulator accesses all configuration space of the overall system and supports breakpoint debug functions through the debug module.
In one embodiment, the configuration module supports an I2C bus protocol to implement a function of loading configuration information from an EEPROM, where the loaded configuration information includes: the method comprises a starting mode, an SRIO working mode, a data communication bit width and the complexity of an encryption and decryption algorithm.
The invention also provides an initialization operation flow method based on PCIE-SRIO, which is applied to the high-flux trusted data communication system based on PCIE-SRIO, and comprises the following steps:
step S1: after the system is normally powered on, firstly, a configuration module loads configuration information from the EEPROM through an I2C bus protocol, and the system operates a corresponding mode according to the configuration information;
step S2: the PCIE processing module completes the function configuration of the PCIE processing module by receiving and sending a main control TLP (protocol message) from the PCIE, wherein the function configuration comprises PCIE equipment enumeration, BAR (Bus address space allocation) and Bus allocation functions;
step S3: the protocol conversion module realizes PCIE and SRIO data packet conversion, performs protocol conversion on a TLP (protocol packet transfer protocol) sent by the PCIE processing module to the SRIO processing module, and converts the TLP into a Message data packet, a conventional data packet, nread/Nwrite and an Interrupt Message through a Message engine, a Mapping engine, a DMa engine and an inter engine according to different data types in the TLP; for the PCIE processing module to receive the data packet of the SRIO processing module, converting the SRIO data packets of the Message data packet, the conventional data packet, the Nread/Nwrite and the interrupt Message into TLPs with different data types, and sending the TLPs to an upstream PCIE main controller through the PCIE processing module to realize protocol conversion of PCIE and SRIO;
step S4: the trusted security module encrypts and decrypts the data content of the SRIO message by adopting a trusted communication cryptographic algorithm standard conforming to the international standard, so as to realize the trusted security of the data;
step S5: the SRIO processing module processes the encrypted SRIO data packet and sends the encrypted SRIO data packet to the opposite-end SRIO equipment; meanwhile, data sent by the SRIO equipment at the opposite end are processed, and are uploaded to a trusted security module for decryption processing, so that doorbell, message, DMA, nread/Nwrite multiple data communication functions of the SRIO are completed.
The high-throughput trusted data communication system and method based on PCIE-to-SRIO provided by the invention have the following beneficial effects:
(1) The high-throughput communication is realized, and the effective transmission data communication of 20Gbps can be realized on 4 pairs of differential lines by PCIE and SRIO high-speed buses and adopting a high-performance LVDS technology;
(2) The trusted secure communication is realized, the communication data is encrypted and decrypted through the trusted secure module, and the trusted secure communication of the data is realized by adopting the trusted communication cryptographic algorithm standard conforming to the international standard;
(3) The high expansibility is realized, and a plurality of SRIO nodes can be expanded to carry out interconnection communication through the external SRIO Switch chip, so that higher system-level performance is obtained;
(4) The invention can work under different operating systems, and can adjust the default configuration of the system through the configuration module according to specific SRIO network structure and data transmission requirements, thereby improving the data transmission efficiency.
Drawings
Fig. 1 is a schematic structural diagram of a high-throughput trusted data communication system based on PCIE to SRIO.
Fig. 2 is a schematic diagram of an initialization operation flow of a high-throughput trusted data communication system based on PCIE to SRIO.
Detailed Description
The invention provides a high-throughput trusted data communication system and method based on PCIE-SRIO, which are further described in detail below with reference to the accompanying drawings and the specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The invention provides a high-throughput trusted data communication system based on PCIE-to-SRIO, which has a principle structure shown in figure 1 and comprises a PCIE processing module, a protocol conversion module, a trusted security module, an SRIO processing module, a clock module, a reset module, a configuration module and a debugging module; one side of the PCIE processing module is connected with the PCIE bus, the other side of the PCIE processing module is connected with one side of the protocol conversion module, the other side of the protocol conversion module is connected with one side of the trusted security module, the other side of the trusted security module is connected with one side of the SRIO processing module, and the other side of the SRIO processing module is connected with the SRIO bus. The PCIE processing module is used for sending and receiving PCIE messages, and realizing data communication with upstream equipment through a PCIE bus; the protocol conversion module performs data conversion on PCIE protocol and SRIO protocol; the trusted security module encrypts and decrypts the communication data of the SRIO packet and ensures the security and the credibility of the data; the SRIO processing module is used for sending and receiving SRIO protocol data and realizing communication through SRIO bus connection with the opposite terminal equipment; the clock module provides a normal working clock of the whole system; the reset module provides reset of each internal logic; the configuration module is used for configuring the operation mode of the whole system; the debugging module is used for providing function debugging of each module in the whole system.
With continued reference to fig. 1, in this embodiment of the present invention, the PCIE processing module includes a PCIE physical interface module and a PCIE logical processing module. The PCIE physical interface module is used for connecting upstream equipment of a PCIE bus, supporting PCIE2.1 protocol, supporting x4/x2/x1 links, and enabling the highest data flux to reach 20Gbps; the PCIE logic processing module is configured to process TPL packets sent and received by the upstream device, and implement functions of classification filtering, buffer queuing and priority arbitration of TLP packets.
The protocol conversion module is used for converting data packets of PCIE protocol and SRIO protocol, and comprises a Message engine, a Mapping engine, a DMa engine and an inter engine. The Message engine module is used for realizing conversion between PCIE packets and SRIO Message packets; the Mapping engine is used for realizing conventional packet conversion between PCIE and SRIO; the DMa engine is used for realizing a DMA function and improving the conversion efficiency of data; the inter engine is configured to implement conversion of an Interrupt request of an SRIO to the PCIE processing module.
The trusted security module encrypts and decrypts the data content of the SRIO message, adopts a trusted communication cryptographic algorithm standard conforming to the international standard, and meets the characteristics of confusion and diffusion of the encryption algorithm.
The SRIO processing module comprises an SRIO physical interface module and an SRIO logic processing module. The SRIO physical interface module is used for connecting the physical connection of the SRIO equipment at the opposite end, supporting the SRIO2.2 protocol, supporting the x4/x2/x1 link, and enabling the highest data flux to reach 25Gbps; the SRIO logic processing module is used for realizing a plurality of data communication functions such as doorbell, message, DMA, nread/Nwrite of an SRIO protocol.
The clock module comprises two groups of clock differential inputs, one group is used by the PCIE processing module, and the other group is used by the SRIO processing module.
The reset module is used for resetting all logic in the whole system and is effective at low level.
The debugging module supports JTAG boundary scanning, and an external JTAG emulator can access all configuration spaces of the whole system through the debugging module and support a breakpoint debugging function.
The configuration module supports an I2C bus protocol, realizes the function of loading configuration information from the EEPROM, and comprises the following steps: the method comprises a starting mode, an SRIO working mode, a data communication bit width and the complexity of an encryption and decryption algorithm.
Based on the high-throughput trusted data communication system based on PCIE-SRIO, the invention also provides an initialization operation flow method thereof, the flow of which is shown in figure 2, and the initialization operation flow method comprises the following steps:
step S1: after the system is normally powered on, firstly, the configuration module loads configuration information from the EEPROM through an I2C bus protocol, and the loaded configuration information comprises: the system operates the corresponding modes according to the configuration information, such as a starting mode, an SRIO working mode, a data bit width, the complexity of an encryption and decryption algorithm and the like.
Step S2: the PCIE processing module completes the function configuration of the PCIE processing module by receiving and sending the main control TLP from the PCIE, including functions such as PCIE device enumeration, BAR address space allocation, bus allocation, etc.
Step S3: the protocol conversion module realizes PCIE and SRIO data packet conversion, and sends a TLP (protocol packet transfer protocol) of the SRIO processing module to the PCIE processing module to be subjected to protocol conversion, and the TLP is converted into a Message data packet, a conventional data packet (doorbell, maintenance Message), nread/Nwrite and an Interrupt Message respectively through a Message engine, a Mapping engine, a DMa engine and an Interrupt engine according to different data types in the TLP; for the PCIE processing module, receiving a data packet of the SRIO processing module, converting the SRIO data packets of the Message data packet, the conventional data packet (doorbell, maintenance Message), the Nread/Nwrite and the interrupt Message into TLPs with different data types, and sending the TLPs to the upstream PCIE master controller through the PCIE processing module, so as to implement protocol conversion between PCIE and SRIO.
Step S4: and the trusted security module encrypts and decrypts the data content of the SRIO message by adopting a trusted communication cryptographic algorithm standard conforming to the international standard, so as to realize the trusted security of the data.
Step S5: the SRIO processing module processes the encrypted SRIO data packet and sends the encrypted SRIO data packet to the opposite-end SRIO equipment; meanwhile, data sent by the SRIO equipment at the opposite end are processed and uploaded to a trusted security module for decryption, so that doorbell, message, DMA, nread/Nwrite multiple data communication functions of the SRIO are finally completed.
According to the invention, through PCIE and SRIO high-speed buses, the high-performance LVDS technology is adopted, and effective transmission of 20Gbps can be realized on 4 pairs of differential lines; meanwhile, the novel trusted security module adopts a trusted communication cryptographic algorithm standard conforming to the international standard, meets the confusion and diffusion characteristics of an encryption algorithm, has the characteristics of routing, exchange, fault tolerance and error correction, trusted security, convenient use and the like, and realizes high-flux trusted security communication based on hardware.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (9)
1. The high-throughput trusted data communication system based on PCIE-SRIO is characterized by comprising a PCIE processing module, a protocol conversion module, a trusted security module and an SRIO processing module;
one side of the PCIE processing module is connected with a PCIE bus, the other side of the PCIE processing module is connected with one side of the protocol conversion module, the other side of the protocol conversion module is connected with one side of the trusted security module, the other side of the trusted security module is connected with one side of the SRIO processing module, and the other side of the SRIO processing module is connected with an SRIO bus;
the PCIE processing module is used for sending and receiving PCIE messages and carrying out data communication with upstream equipment through a PCIE bus;
the protocol conversion module performs data conversion on PCIE protocol and SRIO protocol;
the trusted security module encrypts and decrypts the communication data of the SRIO packet to ensure the security and the credibility of the data;
the SRIO processing module is used for sending and receiving SRIO protocol data and is connected with the opposite terminal equipment through an SRIO bus for communication;
the high-throughput trusted data communication system based on PCIE-SRIO also comprises a clock module, a reset module, a configuration module and a debugging module; the clock module provides a normal working clock of the whole system; the reset module provides reset of each internal logic; the configuration module is used for configuring the operation mode of the whole system; the debugging module is used for providing function debugging of each module in the whole system.
2. The PCIE-to-SRIO based high-throughput trusted data communication system of claim 1 wherein said PCIE processing module comprises a PCIE physical interface module and a PCIE logical processing module; the PCIE physical interface module is used for connecting upstream equipment of a PCIE bus, supporting PCIE2.1 protocol, supporting x4/x2/x1 links, and enabling the highest data flux to reach 20Gbps; the PCIE logic processing module is configured to process TPL packets sent and received by the upstream device, and implement functions of classification filtering, buffer queuing and priority arbitration of TLP packets.
3. The PCIE to SRIO based high throughput trusted data communication system of claim 1 wherein said protocol conversion module comprises a Message engine, a Mapping engine, a DMa engine and an inter engine; the Message engine module is used for realizing conversion between PCIE packets and SRIO Message packets; the Mapping engine is used for realizing conventional packet conversion between PCIE and SRIO; the DMa engine is used for realizing a DMA function and improving the conversion efficiency of data; the inter engine is configured to implement conversion of an Interrupt request of an SRIO to the PCIE processing module.
4. The PCIE to SRIO based high throughput trusted data communication system of claim 1 wherein said trusted security module comprises data encryption and data decryption employing trusted communications cryptography algorithm standards conforming to international standards, satisfying the confusion and diffusion characteristics of encryption algorithms.
5. The PCIE to SRIO based high throughput trusted data communication system of claim 1 wherein said SRIO processing module comprises an SRIO physical interface module and an SRIO logical processing module; the SRIO physical interface module is used for connecting the physical connection of the SRIO equipment at the opposite end, supporting the SRIO2.2 protocol, supporting the x4/x2/x1 link, and enabling the highest data flux to reach 25Gbps; the SRIO logic processing module is used for realizing doorbell, message, DMA, nread/Nwrite various data communication functions of the SRIO protocol.
6. The PCIE to SRIO based high throughput trusted data communication system of claim 1 wherein said clock module comprises two sets of clock differential inputs, one set for use by said PCIE processing module and the other set for use by said SRIO processing module.
7. The PCIE to SRIO based high throughput trusted data communication system of claim 1 wherein said debug module supports JTAG boundary scan, an external JTAG emulator accessing all configuration space of the overall system through said debug module and supporting breakpoint debug functionality.
8. The PCIE to SRIO based high throughput trusted data communication system of claim 1 wherein said configuration module supports an I2C bus protocol implementing a function of loading configuration information from EEPROM, the loaded configuration information comprising: the method comprises a starting mode, an SRIO working mode, a data communication bit width and the complexity of an encryption and decryption algorithm.
9. The initialization operation flow method based on PCIE-SRIO is applied to the high-throughput trusted data communication system based on PCIE-SRIO as claimed in any one of claims 1 to 9, and is characterized by comprising the following steps:
step S1: after the system is normally powered on, firstly, a configuration module loads configuration information from the EEPROM through an I2C bus protocol, and the system operates a corresponding mode according to the configuration information;
step S2: the PCIE processing module completes the function configuration of the PCIE processing module by receiving and sending a main control TLP (protocol message) from the PCIE, wherein the function configuration comprises PCIE equipment enumeration, BAR (Bus address space allocation) and Bus allocation functions;
step S3: the protocol conversion module realizes PCIE and SRIO data packet conversion, performs protocol conversion on a TLP (protocol packet transfer protocol) sent by the PCIE processing module to the SRIO processing module, and converts the TLP into a Message data packet, a conventional data packet, nread/Nwrite and an Interrupt Message through a Message engine, a Mapping engine, a DMa engine and an inter engine according to different data types in the TLP; for the PCIE processing module to receive the data packet of the SRIO processing module, converting the SRIO data packets of the Message data packet, the conventional data packet, the Nread/Nwrite and the interrupt Message into TLPs with different data types, and sending the TLPs to an upstream PCIE main controller through the PCIE processing module to realize protocol conversion of PCIE and SRIO;
step S4: the trusted security module encrypts and decrypts the data content of the SRIO message by adopting a trusted communication cryptographic algorithm standard conforming to the international standard, so as to realize the trusted security of the data;
step S5: the SRIO processing module processes the encrypted SRIO data packet and sends the encrypted SRIO data packet to the opposite-end SRIO equipment; meanwhile, data sent by the SRIO equipment at the opposite end are processed, and are uploaded to a trusted security module for decryption processing, so that doorbell, message, DMA, nread/Nwrite multiple data communication functions of the SRIO are completed.
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2222130A1 (en) * | 2007-11-21 | 2010-08-25 | ZTE Corporation | Base band unit, radio frequency unit and distributed bs system based on srio protocol |
CN107203484A (en) * | 2017-06-27 | 2017-09-26 | 北京计算机技术及应用研究所 | A kind of PCIe based on FPGA and SRIO bus bridge systems |
CN115396527A (en) * | 2022-10-27 | 2022-11-25 | 成都智明达电子股份有限公司 | PCIE and SRIO protocol conversion system and method based on FPGA |
CN115834804A (en) * | 2022-11-28 | 2023-03-21 | 中国航空无线电电子研究所 | Video transmission system for converting multi-path SRIO into multi-path ARINC818 |
-
2023
- 2023-09-19 CN CN202311206451.6A patent/CN116939052A/en active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2222130A1 (en) * | 2007-11-21 | 2010-08-25 | ZTE Corporation | Base band unit, radio frequency unit and distributed bs system based on srio protocol |
CN107203484A (en) * | 2017-06-27 | 2017-09-26 | 北京计算机技术及应用研究所 | A kind of PCIe based on FPGA and SRIO bus bridge systems |
CN115396527A (en) * | 2022-10-27 | 2022-11-25 | 成都智明达电子股份有限公司 | PCIE and SRIO protocol conversion system and method based on FPGA |
CN115834804A (en) * | 2022-11-28 | 2023-03-21 | 中国航空无线电电子研究所 | Video transmission system for converting multi-path SRIO into multi-path ARINC818 |
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