CN116938248A

CN116938248A - Analog-to-digital converter and method for improving bandwidth of analog-to-digital converter

Info

Publication number: CN116938248A
Application number: CN202210333217.9A
Authority: CN
Inventors: 扶仲毅; 李定
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-03-31
Filing date: 2022-03-31
Publication date: 2023-10-24
Also published as: WO2023185192A1

Abstract

The application provides an analog-digital converter, a method for improving the bandwidth of the analog-digital converter and electronic equipment, and relates to the technical field of signal processing. Wherein, a dynamic amplifier and a time-to-digital converter are newly added in the SAR ADC. The first input end of the dynamic amplifier is coupled with the capacitor array, the second input end of the dynamic amplifier is coupled with the comparator, and the output end of the dynamic amplifier is coupled with the time-to-digital converter. After the comparator enters a metastable state, the dynamic amplifier receives a control signal sent by the comparator, converts an input analog electric signal into a time sequence signal with time, and then converts the time sequence signal into a digital signal through the time-to-digital converter, so that higher resolution is obtained under the same time, namely the conversion speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

Description

Analog-to-digital converter and method for improving bandwidth of analog-to-digital converter

Technical Field

The present application relates to the field of signal processing technologies, and in particular, to an analog-to-digital converter, a method for improving bandwidth of the analog-to-digital converter, and an electronic device.

Background

An analog-to-digital converter (ADC) is a converter that converts an analog signal to a digital signal. Successive approximation register (successive approximation register, SAR) ADCs are medium to high resolution applications with sample rates below 5Msps (million samples per second). In each conversion process, all quantized values are traversed and converted into analog values, and input signals are compared with the analog values one by one, so that digital signals to be output are finally obtained. The SAR ADC has the characteristics of low power consumption, small size, and the like, and is widely used in various electronic devices. However, the single channel bandwidth of the existing SAR ADC, that is, half of the nyquist sampling rate, cannot meet the large bandwidth/multi-mode direct acquisition requirement of the existing wireless communication and optical communication, so how to improve the single channel bandwidth of the SAR ADC is a problem to be solved at present.

Disclosure of Invention

In order to solve the above-mentioned problems, in the embodiments of the present application, an analog-to-digital converter, a method for improving the bandwidth of the analog-to-digital converter, and an electronic device are provided, where after the analog-to-digital converter enters a metastable state, an SAR logic circuit stops working, and after a dynamic amplifier obtains a residual voltage, the dynamic amplifier converts the input residual voltage into a time sequence signal with time, and then the time information is converted into a digital signal by a time-to-digital converter to obtain LSB information, so that a higher resolution is obtained at the same time, that is, the conversion speed of the SAR ADC is improved, thereby improving the single channel bandwidth of the SAR ADC.

For this purpose, the following technical scheme is adopted in the embodiment of the application:

in a first aspect, an embodiment of the present application provides an analog-to-digital converter, including: the analog signal input end, the capacitor array, the comparator circuit, the dynamic amplifier and the time-to-digital converter; the capacitor array is coupled between the analog signal input terminal and the first output terminal of the comparator circuit; the input end of the comparator circuit is coupled with the analog signal input end, the first output end of the comparator circuit is coupled with the control end of the capacitor array, the second output end of the comparator circuit is coupled with the control end of the dynamic amplifier, the comparator circuit is used for generating a comparison signal according to the analog signal received by the analog signal input end and outputting the comparison signal to the capacitor array through the first output end, and is used for generating a first control signal according to the analog signal and outputting the first control signal to the dynamic amplifier through the second output end, the first control signal is used for enabling the dynamic amplifier to work, and the comparison signal is used for generating a first part of digital signal; the input end of the dynamic amplifier is coupled with the input end of the analog signal, and the output end of the dynamic amplifier is coupled with the input end of the time-to-digital converter; the output end of the time-to-digital converter is used for outputting a second part of digital signals.

In this embodiment, a dynamic amplifier and a time-to-digital converter are newly added to the SAR ADC. The first input end of the dynamic amplifier is coupled with the capacitor array, the second input end of the dynamic amplifier is coupled with the comparator, and the output end of the dynamic amplifier is coupled with the time-to-digital converter. After the comparator enters a metastable state, the dynamic amplifier receives a control signal sent by the comparator, converts an input analog electric signal into a time sequence signal with time, and then converts the time sequence signal into a digital signal through the time-to-digital converter, so that higher resolution is obtained under the same time, namely the conversion speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

In one embodiment, the method further comprises: the input end of the SAR logic circuit is coupled with the first output end of the comparator circuit, the first output end of the SAR logic circuit is coupled with the control end of the capacitor array, the second output end of the SAR logic circuit is used for outputting a second control signal, the second output end of the SAR logic circuit is used for outputting the first part of digital signals, and the second control signal is used for enabling the capacitor array to work.

In one embodiment, the comparator circuit is configured to generate the first control signal according to whether a difference between analog signals received at the analog signal input terminal is smaller than a set threshold value, and when the difference between analog signals is smaller than the set threshold value.

In one embodiment, the comparator circuit includes a clock signal input, a comparator, a delay circuit, and a flip-flop; the first input end of the comparator is coupled with the analog signal input end, the second input end of the comparator is coupled with the clock signal input end, the output end of the comparator is respectively coupled with the output end of the SAR logic circuit and the first input end of the trigger, and the comparator is used for generating the comparison signal according to the clock signal input by the clock signal input end and the analog signal received by the analog signal input end; the delay circuit is coupled between the clock signal input end and the second input end of the trigger; the input end of the trigger is coupled to the control end of the dynamic amplifier, and the input end of the trigger is used for outputting the first control signal.

In one embodiment, the comparator includes a first MOS transistor M1, a second MOS transistor M2, a first inverter, a second inverter, and/or a logic device, where a source of the first MOS transistor M1 and a source of the second MOS transistor M2 are respectively coupled to a first power input terminal, a drain of the first MOS transistor M1 and a drain of the second MOS transistor M2 are respectively grounded, and a gate of the first MOS transistor M1 and a gate of the second MOS transistor M2 are respectively coupled to the analog signal input terminal; the input end of the first inverter is coupled between the first power input end and the source electrode of the first MOS tube M1, the input end of the second inverter is coupled between the first power input end and the source electrode of the second MOS tube M2, the output end of the first inverter and the output end of the second inverter are coupled with the input end of the OR logic device, and the output end of the OR logic device is used for outputting the comparison signal.

In one embodiment, the comparator further includes a third MOS transistor M7, a fourth MOS transistor M8, a fifth MOS transistor M9, and a sixth MOS transistor M10; the source electrode of the third MOS tube M7 is coupled between the first power input end and the first inverter, and the source electrode of the fourth MOS tube M8 is coupled between the first power input end and the second inverter; the source electrode of the fifth MOS tube M9 is coupled with the drain electrode of the first MOS tube M1 and the drain electrode of the second MOS tube M2, and the drain electrode of the fifth MOS tube M9 is grounded; the sixth MOS transistor M10 is coupled between the source of the first MOS transistor M1 and the source of the second MOS transistor M2; the gate of the third MOS transistor M7, the gate of the fourth MOS transistor M8, the gate of the fifth MOS transistor M9, and the gate of the sixth MOS transistor M10 are respectively coupled to the clock signal input terminal.

In one embodiment, the delay circuit is configured to generate a second clock signal according to the clock signal received by the clock signal input terminal, where the second clock signal is a clock signal delayed by a set time from the clock signal received by the clock signal input terminal.

In one embodiment, the flip-flop is configured to generate the first control signal based on the comparison signal and the second clock signal.

In one embodiment, the dynamic amplifier comprises a first switch circuit, a second switch circuit, a first MOS tube, a second MOS tube and a current source; one end of the first switch circuit and one end of the first switch circuit are respectively coupled with a second power input end, the other end of the first switch circuit is coupled with the source electrode of the first MOS tube, and the other end of the second switch circuit is coupled with the source electrode of the second MOS tube; the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are respectively coupled with one end of the current source, and the other end of the current source is grounded; the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are respectively coupled with the analog signal input end.

In one embodiment, the dynamic amplifier further comprises a first capacitance and a second capacitance; one end of the first capacitor is coupled between the first switch circuit and the first MOS tube, and the other end of the first capacitor is grounded; one end of the second capacitor is coupled between the second switch circuit and the second MOS tube, and the other end of the second capacitor is grounded.

In one embodiment, the dynamic amplifier is configured to turn off the first switch circuit and the second switch circuit according to the first control signal sent by the comparator circuit.

In a second aspect, an embodiment of the present application provides a method for converting an analog signal into a digital signal, including: the comparator circuit generates a first control signal according to the first analog signal and outputs the first control signal to the dynamic amplifier; after receiving the first control signal, the dynamic amplifier converts the first analog signal into a second analog signal, wherein the second analog signal carries time information; and after the time-to-digital converter receives the second analog signal, the second analog signal is converted into a digital signal.

In one embodiment, the method further comprises: the comparator circuit receives a clock signal; the comparator circuit generates a first control signal according to a first analog signal and outputs the first control signal to the dynamic amplifier, and specifically comprises: the comparator circuit generates the first control signal based on the clock signal and the first analog signal.

In one embodiment, the method further comprises: the comparator circuit generates a comparison signal according to the first analog signal and the clock signal and outputs the comparison signal to the successive approximation register type SAR logic circuit; and after the SAR logic circuit receives the comparison signal, generating a digital signal according to the comparison signal.

In a third aspect, an embodiment of the present application provides an electronic device, including: an analog circuit for generating an analog signal; a clock circuit for generating a clock signal; at least one analog-to-digital converter as each possible implementation of the first aspect for receiving the analog signal and the clock signal, converting the analog signal into a digital signal; and the digital circuit is used for receiving the digital signal and processing the digital signal.

Drawings

The drawings that accompany the detailed description can be briefly described as follows.

FIG. 1 is a schematic diagram of a prior art SAR ADC;

fig. 2 is a schematic structural diagram of a SAR ADC according to an embodiment of the present application;

fig. 3 is a schematic diagram of a specific structure of a SAR ADC according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a comparator circuit according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a comparator according to an embodiment of the present application;

FIG. 6 is a simulation diagram showing the discharge time of the capacitor C and the voltage difference before and after the discharge;

FIG. 7 is a schematic diagram showing the performance comparison of the prior art SAR ADC and the SAR ADC protected by the present application;

fig. 8 is a flowchart of a method for improving bandwidth of a SAR ADC according to an embodiment of the application;

Fig. 9 is a schematic diagram of a frame of an electronic device according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

The term "and/or" herein is an association relationship describing an associated object, and means that there may be three relationships, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. The symbol "/" herein indicates that the associated object is or is a relationship, e.g., A/B indicates A or B.

The terms "first" and "second" and the like in the description and in the claims are used for distinguishing between different objects and not for describing a particular sequential order of objects. For example, the first response message and the second response message, etc. are used to distinguish between different response messages, and are not used to describe a particular order of response messages.

In embodiments of the application, words such as "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "e.g." in an embodiment should not be taken as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" means two or more, for example, the meaning of a plurality of processing units means two or more, or the like; the plurality of elements means two or more elements and the like.

Fig. 1 is a schematic structural diagram of a conventional SAR ADC. As shown in fig. 1, the SAR ADC mainly includes a capacitor array, a comparator, and SAR logic.

In the practical application process, the capacitor array is used for inputting the analog signal V _IN Sampling is carried out, and analog input voltage V is output after sampling is completed _IN And an analog output voltage V _OUT . Analog input voltage V _OUTN And an analog output voltage V _OUTP Respectively to the positive and negative inputs of the comparator. The comparator inputs an analog input voltage V _OUTN And an analog output voltage V _OUTP Comparing and generating a comparison signal V _comp . If the input voltage V is simulated _OUTN Greater than the analog output voltage V _OUTP The comparator outputs a comparison signal V _comp Is a logic high level or "1"; if the input voltage V is simulated _OUTN Less than the analog output voltage V _OUTP The comparator outputs a comparison signal V _comp At a logic low level or "0".

The clock signal clk is used as an enabling signal to control the output updating of the comparator and the SAR logic circuit. When the clock signal clk is in the most significant bit (most significant bit, MSB) stage, the comparator inputs an analog input voltage V _OUTN And an analog output voltage V _OUTP Compares and outputs a comparison signal V _comp . SAR logic circuit based on comparison signal V _comp After completing the setting once, the device moves to the next highest position and prepares for the next comparison. And so on, until the clock signal clk is at the least significant bit (least significant bit, LSB), the transition is completed. After the whole successive comparison process is finished, the SAR ADC finishes conversion from one analog quantity to a digital quantity, and outputs a digital code corresponding to the analog quantity.

In order to improve the single channel bandwidth of SAR ADC, the following solutions are proposed in the prior art, specifically:

1. multi-bit synchronous comparison techniques. In the SAR ADC, set 2 ^N And a comparator. SAR ADC in-process ratioIn the latter process, the comparison is performed by a plurality of comparators at the same time. In the scheme, the sampling rate of the SAR ADC reaches N bits/cycle, the SAR conversion times can be reduced, and the single-channel bandwidth of the SAR ADC is improved. However, set 2 in SAR ADC ^N Comparators are added with 2 ^N -1 comparator, such that the power consumption of the SAR ADC is relatively large.

2. loop-unrell technology. In the SAR ADC, N comparators are set. The SAR ADC uses one comparator for each bit in performing the comparison. After the comparator finishes one-time comparison, the current comparator is not reset, and the next comparator is directly started, so that the time for waiting for the reset of the comparator can be saved, and the single-channel bandwidth of the SAR ADC is improved. However, with the development of technology and the improvement of production process, the reset time of the comparator is shorter and shorter, so the effect of improving the single-channel bandwidth of the SAR ADC by adopting the scheme is not obvious.

3. Phase (phase) hopping techniques. In order to achieve N bit precision, a conventional SAR ADC needs to undergo N conversion phases. In order to improve the comparison time of the SAR ADC, the technology is called as a phase jump technology by judging other conditions to realize that a plurality of phases are skipped and directly obtain a final quantization result. Taking metastable state judgment technology as an example, after the comparator enters metastable state in a certain comparison, the SAR ADC can consider that the input residual voltage is converged to a small range, a quantization result is obtained, and the rest phase can be skipped. However, if the metastable state does not occur or the metastable state judgment is wrong, the comparison time of the SAR ADC cannot be increased, so that the single-channel bandwidth of the SAR ADC cannot be increased. The metastable state refers to a state that the voltages of two input ends of the comparator are very close, so that the comparator needs a long time to output a comparison signal.

In order to solve the problems existing in the existing SAR ADC, the embodiment of the application provides a novel SAR ADC. As shown in fig. 2, the SAR ADC includes a capacitive array 210, a comparator circuit 220, SAR logic 230, a dynamic amplifier 240, and a time-to-digital converter 250. The newly added dynamic amplifier 240 is connected to two input terminals of the comparator circuit 220 and is connected in parallel with the comparator circuit 220 . The comparator circuit 220 determines whether the clock signal clk is in the MSB stage, i.e., whether the SAR ADC is in the MSB stage. When the SAR ADC is in MSB stage, the comparator circuit 220 compares the residual voltages received at the two inputs and outputs a comparison signal V _comp . SAR logic circuit 230 is based on comparison signal V _comp After completing the setting once, the next highest order is shifted to, and a control signal is generated and sent to the capacitor array 210 to prepare for the next comparison. SAR logic 230 also compares signal V _comp And converting the analog signal into a digital signal and outputting a digital code corresponding to the analog quantity. Comparator circuit 220 determines that a metastable state has been entered when it detects that the difference between the residual voltages at the two inputs is relatively small. The comparator circuit 220 controls the SAR logic 230 to stop operating. The comparator circuit 220 sends a control signal to the dynamic amplifier 240 to cause the dynamic amplifier 240 to operate.

The dynamic amplifier 240 converts the input residual voltage into a time-series signal with time, and then inputs the signal to the time-to-digital converter 250. After the time-to-digital converter 250 receives the two timing signals, it measures the time interval between the two timing signals, and converts the time information corresponding to the time interval into a digital signal, obtains LSB information, and outputs the digital code corresponding to the analog quantity. In the SAR ADC designed by the application, after the comparator enters a metastable state, the SAR logic circuit stops working, the dynamic amplifier converts the input residual voltage into a time sequence signal with time after obtaining the residual voltage, and then the time sequence signal is converted into a digital signal through the time-to-digital converter to obtain LSB information, so that higher resolution is obtained under the same time, namely the conversion speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

Fig. 3 is a schematic diagram of a specific structure of a SAR ADC according to an embodiment of the present application. As shown in fig. 3, the SAR ADC includes a capacitive array 210, a comparator circuit 220, SAR logic 230, a dynamic amplifier 240, and a time-to-digital converter 250.

The capacitor array 210 samples and holds the analog signal to obtain two voltage signals, which are the first voltage signal V ₁ And a second voltage signal V ₂ Then the first voltage signal V ₁ And a second voltage signal V ₂ Respectively to two inputs of the comparator circuit 220.

As shown in fig. 3, the present application provides a capacitor array 210, which includes two input paths, and an input circuit inputs a voltage signal to an input terminal of a comparator circuit 220. Input path and negative reference voltage V _refn Circuit or positive reference voltage V _refp Four capacitors C are connected in parallel between the circuits. Each capacitor C and a negative reference voltage V _refn Circuit or positive reference voltage V _refp A switching circuit S is electrically connected between the circuits. The SAR logic circuit 230 outputs a comparison signal V according to the comparator circuit 220 _comp Generates a control signal and sends the control signal to the capacitor array 210 to control each switch circuit, select the input circuit and the negative reference voltage V _refn The circuit being electrically connected, or the input circuit being connected to a positive reference voltage V _refp The circuit is electrically connected.

The operation of the capacitor array 210 can be divided into three phases, namely a sampling phase, a holding phase and a charge redistribution phase. The specific implementation process is as follows:

1. and (3) a sampling stage. The capacitor array 210 may control the switching circuit S ₁₁ And a switch circuit S ₂₁ Closing, first voltage signal V ₁ And a second voltage signal V ₂ Directly to both inputs of the comparator circuit 220. In the input circuit 1, the SAR logic circuit 230 can control the switching circuit S ₁₂ -S ₁₅ Closing, input circuit 1 and negative reference voltage V _refn The circuit is electrically connected. Capacitor C ₁₁ -C ₁₄ After the circuits are communicated, the stored charge is Q ₁ ＝C _{1 total of} ×(V ₁ -V _refn ),C _{1 total of} ＝C ₁₁ +C ₁₂ +C ₁₃ +C ₁₄ . In the input circuit 2, the SAR logic 230 can control the switching circuit S ₂₂ -S ₂₅ Closing, input circuit 2 and positive reference voltage V _refp The circuit is electrically connected with the capacitor C ₂₁ -C ₂₄ After the circuits are communicated, the stored charge is Q ₂ ＝C _{2 total} ×(V ₂ -V _refp ),C _{2 total} ＝C ₂₁ +C ₂₂ +C ₂₃ +C ₂₄ 。

2. And (3) a holding stage. The capacitor array 210 may control the switching circuit S ₁₁ And a switch circuit S ₂₁ Closing, first voltage signal V ₁ And a second voltage signal V ₂ Directly to both inputs of the comparator circuit 220. In the input circuit 1, the SAR logic circuit 230 can control the switching circuit S ₁₂ -S ₁₅ Off, capacitor C ₁₁ -C ₁₄ The stored charge is Q ₁ ＝C _{1 total of} ×V ₁ ,C _{1 total of} ＝C ₁₁ +C ₁₂ +C ₁₃ +C ₁₄ . In the input circuit 2, the SAR logic 230 can control the switching circuit S ₂₂ -S ₂₅ Off, capacitor C ₂₁ -C ₂₄ The stored charge is Q ₂ ＝C _{1 total of} ×V ₂ ,C _{2 total} ＝C ₂₁ +C ₂₂ +C ₂₃ +C ₂₄ 。

3. And a charge redistribution stage. The capacitor array 210 can be operated according to the comparison signal V of the comparator circuit 220 after the sampling stage and the holding stage are completed _cmp ＝V ₁ -V ₂ The comparison signal is quantized. The method comprises the following steps: in the first comparison, if the comparison signal V _cmp1 >0, indicating a first voltage signal V ₁ Greater than the second voltage signal V ₂ SAR logic 230 sends a high level or "1" to each of the switching circuits. At this time, the SAR logic 230 may control the switching circuit S ₁₂ -S ₁₅ The input circuit 1 is disconnected from the reference voltage V _ref The circuit being broken, i.e. the capacitor C being supplied to the circuit 1 ₁₁ -C ₁₄ Ground GND; SAR logic 230 can control switching circuit S ₂₂ -S ₂₅ Closing, input circuit 2 and negative reference voltage V _refn The circuit being electrically connected, i.e. the capacitor C being on the input circuit 2 ₂₁ -C ₂₄ And the other end of the voltage V _refn The circuit is electrically connected. If the signal V is compared _cmp1 <0, indicating a first voltage signal V ₁ Less than the second voltage signal V ₂ SAR logic 230 sends a low level or "0" to the various switching circuits. At this time, the liquid crystal display device,SAR logic 230 can control switching circuit S ₁₂ -S ₁₅ Closing, input circuit 1 and positive reference voltage V _refp The circuit being electrically connected, i.e. the capacitor C being provided on the input circuit 1 ₁₁ -C ₁₄ And a positive reference voltage V _refp The circuit is electrically connected; SAR logic 230 can control switching circuit S ₂₂ -S ₂₅ The input circuit 2 is disconnected from the reference voltage V _ref The circuit being broken, i.e. the capacitor C being supplied to the circuit 1 ₂₁ -C ₂₄ Ground GND.

After the first comparison is completed, the charges are redistributed again, and the comparison signal V is output from the comparator circuit 220 _cmp2 Is the comparison signal V in the first comparison _cmp1 Up-or down-by 1/2 reference voltage V _ref I.e. increase or reference voltage V _ref Multiplying the capacitance value of the secondary participation quantization by the total capacitance proportion.

In the second comparison, if the comparison signal V _cmp2 >0, indicating a first voltage signal V ₁ Greater than the second voltage signal V ₂ SAR logic 230 sends a high level or "1" to each of the switching circuits. At this time, the SAR logic 230 may control the switching circuit S ₁₃ -S ₁₅ The input circuit 1 is disconnected from the reference voltage V _ref The circuit being broken, i.e. the capacitor C being supplied to the circuit 1 ₁₂ -C ₁₄ Ground GND; SAR logic 230 can control switching circuit S ₂₃ -S ₂₅ Closing, input circuit 2 and negative reference voltage V _refn The circuit being electrically connected, i.e. the capacitor C being on the input circuit 2 ₂₂ -C ₂₄ And the other end of the voltage V _refn The circuit is electrically connected. If the signal V is compared _cmp2 <0, indicating a first voltage signal V ₁ Less than the second voltage signal V ₂ SAR logic 230 sends a low level or "0" to the various switching circuits. At this time, the SAR logic 230 may control the switching circuit S ₁₃ -S ₁₅ Closing, input circuit 1 and positive reference voltage V _refp The circuit being electrically connected, i.e. the capacitor C being provided on the input circuit 1 ₁₂ -C ₁₄ And a positive reference voltage V _refp The circuit is electrically connected; SAR logic circuit230 can control the switching circuit S ₂₃ -S ₂₅ The input circuit 2 is disconnected from the reference voltage V _ref The circuit being broken, i.e. the capacitor C being supplied to the circuit 1 ₂₂ -C ₂₄ Ground GND.

After the second comparison is completed, the charges are redistributed again, and the comparison signal V is output from the comparator circuit 220 _cmp3 Is the comparison signal V in the second comparison _cmp2 Up-or down-by 1/4 of the reference voltage V _ref And analogizing, and finally finishing the quantization of the level signal.

After receiving the clock signal clk, the comparator circuit 220 can determine whether the comparator circuit 220 is in the MSB stage by determining the timing of the comparator circuit 220. The comparator circuit 220 determines that the clock signal clk is in the MSB stage and receives the received first voltage signal V ₁ And a second voltage signal V ₂ Compares and outputs a comparison signal V _comp 。

As shown in fig. 4, the present application provides a comparator circuit 220, the comparator circuit 220 comprising a comparator 221, a delay block 222 and a flip-flop 223. The input terminal 1 and the input terminal 2 of the comparator 221 are respectively electrically connected to two output terminals of the capacitor array 210, one input terminal 3 of the comparator 221 is electrically connected to an external clock circuit, and the output terminal 4 of the comparator 221 is electrically connected to the SAR logic circuit 230 and one input terminal 7 of the flip-flop 223. When the clock signal input from the external clock circuit is in MSB stage, the comparator 221 will generate a first voltage signal V for the first voltage ₁ And a second voltage signal V ₂ Compares and outputs a comparison signal V _comp 。

In general, when the first voltage signal V ₁ And a second voltage signal V ₂ The relation between them is V ₁ -V ₂ >0, comparison signal V output by comparator 221 _comp Is a logic high level or "1". When the first voltage signal V ₁ And a second voltage signal V ₂ The relation between them is V ₁ -V ₂ <0, comparison signal V output by comparator 221 _comp At a logic low level or "0". When the first voltage signal V ₁ And a second voltage signal V ₂ Is very close to, i.e. the first voltage signal V ₁ And a second voltage signal V ₂ The relation between them is V ₁ -V ₂ Approximately 0, the comparator 221 compares the first voltage signal V ₁ And a second voltage signal V ₂ The time required would be longer than otherwise. If the comparator 221 cannot give a determination result within a prescribed time, the comparator 221 enters a "metastable state". In addition, the comparator circuit 220 locks the first voltage signal V after entering the metastable state ₁ And a second voltage signal V ₂ A fixed high bit information is implemented to provide a stable electrical signal to the dynamic amplifier 240.

Illustratively, as shown in fig. 5, in the comparator 221, a source of the MOS transistor M1 and a source of the MOS transistor M2 are respectively connected to a power supply, a drain of the MOS transistor M1 and a drain of the MOS transistor M2 are respectively connected to a source of the MOS transistor M9, and a drain of the MOS transistor M9 is grounded; the gates of the transistors M1 and M2 are electrically connected to two output terminals of the capacitor array 210 for receiving the first voltage signal V ₁ And a second voltage signal V ₂ . The input end of the first inverter is coupled between the power supply and the source electrode of the MOS tube M1, and the input end of the second inverter is coupled between the power supply and the source electrode of the MOS tube M2. The output of the first inverter and the output of the second inverter are coupled to the input of an or logic device, or the output of the logic device is used to output the comparison signal. The source electrode of the MOS tube M7 is coupled between the power supply and the first inverter, and the source electrode of the MOS tube M8 is coupled between the power supply and the second inverter; the MOS tube M10 is coupled between the source electrode of the MOS tube M1 and the source electrode of the MOS tube M2; the grid electrode of the MOS tube M7, the grid electrode of the MOS tube M8, the grid electrode of the MOS tube M9 and the grid electrode of the MOS tube M10 are respectively connected with an external clock circuit. The first voltage signal V received by the comparator 221 ₁ And a second voltage signal V ₂ When the difference value is larger than the set threshold value, one of the electric signal Von and the electric signal Vop input into the OR logic device is high level or 1, or the comparison signal output by the logic device is high level or 1; the first voltage signal V received by the comparator 221 ₁ And a second voltage signal V ₂ The difference value is not greater than a set thresholdIn this case, that is, the two voltage signals are relatively close, the electric signal Von and the electric signal Vop inputted to the or logic device are both at low level or "0", or the comparison signal outputted from the logic device is at low level or "0".

The delay module 222 is generally composed of one or more inverters, and has an input terminal 5 electrically connected to an external clock circuit, and an output terminal 6 electrically connected to an input terminal 8 of the flip-flop 223, for delaying the clock signal clk by a set time, and then inputting the delayed clock signal clk to the flip-flop 223.

The flip-flop 223 is an electronic component that can store a circuit state. The circuit structure of the flip-flop 223 is typically composed of logic gates for handling interactions between the input, output signals and the clock frequency. In the present application, the input terminal 7 and the input terminal 8 of the trigger 223 receive the comparison signal V _comp And delaying the clock signal clk for a set time, comparing the signal V _comp Comparing the rising edge of the clock signal clk delayed by a set time to determine the comparison signal V outputted from the comparator 221 _comp Whether valid at the trigger time. When the trigger time outputs a signal valid value indicating that the comparator 221 does not enter a metastable state, the flip-flop 223 outputs a high level; when the trigger time output signal is inactive, indicating that comparator 221 enters a metastable state, flip-flop 223 outputs a low level. The signal output from the output 9 of the flip-flop 223, i.e. the control signal, is input to the dynamic amplifier 240.

When the comparator 221 is in a metastable state, the comparator 221 inputs the comparison signal V into the SAR logic 230 _comp SAR logic 230 may be disabled. The SAR logic 230 stops working after the comparator 221 enters a metastable state, which can reduce the phase number of conversion, equivalently understood as improving the conversion speed of the SAR logic 230. The flip-flop 223 sends a control signal to the dynamic amplifier 240 to cause the dynamic amplifier 240 to reset.

During the period when the comparator circuit 220 enters a metastable state, the SAR ADC 200 has no digital signal output. In order to improve the digital signal output of the SAR ADC 200, the SAR ADC 200 quantizes the input voltage of the comparator circuit 220 in the metastable state time period in the time domain, acquires LSB information, improves the sampling speed of the SAR ADC 200, and realizes improvement of the single channel bandwidth of the SAR ADC 200.

The SAR logic 230 is configured to receive a clock signal clk from an external clock circuit and a comparison signal V from the comparator 220 _comp A control signal is generated and input into the capacitor array 210 to control on or off of each switch circuit in the capacitor array 210, so as to control the capacitor array 210 to enter a sampling stage, a holding stage and a charge redistribution stage. In the present application, the SAR logic circuit 230 receives the comparison signal V input by the comparator 220 _comp The comparison signal V can also be then _comp And converting the analog signal into a digital signal, and outputting a digital code corresponding to the comparison signal to realize conversion of the analog signal into the digital signal. Since the SAR logic 230 employed in the present application is a conventional SAR logic, it will not be described in detail herein.

After receiving the control signal, the dynamic amplifier 240 receives the first voltage signal V output by the capacitor array 210 ₁ And a second voltage signal V ₂ First voltage signal V ₁ And a second voltage signal V ₂ After being converted into a time-series signal with time, the time-series signal is input to the time-to-digital converter 250.

As shown in fig. 3, the present application provides a dynamic amplifier 240 comprising two metal-oxide-semiconductor field-effect transistor (MOSFET) (Mos 1, mos 2), two capacitors (C _sp ，C _sm ) And two switch circuits (S _sp ，S _sm ). Switching circuit S _sp And a switch circuit S _sm Are connected in series. Switching circuit S _sp And the other end of (C) and the capacitor C _sp After the electrical connection, ground GND. Switching circuit S _sm And the other end of (C) and the capacitor C _sm After the electrical connection, ground GND. The gate of the transistor Mos1 is connected to the input circuit 1, and the source of the transistor Mos1 is electrically connected to the switching circuit S _sp And capacitor C _sp The drain of the transistor Mos1 is grounded GND. The gate of the transistor Mos2 is connected to the input circuit 2, and the source of the transistor Mos2 is electrically connected to the switching circuit S _sm And capacitor C _sm Between, transistor MoThe drain of s2 is connected to ground GND.

After receiving the control signal, the dynamic amplifier 240 controls the switching circuit S _sp And a switch circuit S _sm Open or close and let the first voltage signal V ₁ And a second voltage signal V ₂ Respectively introducing a capacitor C _sp And capacitor C _sm The gate of (c) allows the dynamic amplifier 240 to sequentially implement a reset phase, an amplification phase, and a sampling phase. The method comprises the following steps:

in the reset phase, the switching circuit S _sp And a switch circuit S _sm Closing the transistor Mos1 without applying the first voltage signal V ₁ The gate of the transistor Mos2 is not connected to the second voltage signal V ₂ . Capacitor C _sp And capacitor C _sm Both ends are reset to the set voltage level and respectively recorded as the set voltage V _sp And a set voltage V _sm 。

During the amplification phase, the dynamic amplifier 240 may yield the switching circuit S _sp And a switch circuit S _sm The transistor Mos1 is turned off and the first voltage signal V is turned on ₁ The grid electrode of the transistor Mos2 is connected with a second voltage signal V ₂ . The current source Is supplies current for the amplifying stage. The current source may be coupled to the capacitor C through the transistor Mos1 _sp The current source may be coupled to the capacitor C through the transistor Mos2 _sm . Capacitor C _sp And capacitor C _sm Discharging, setting voltage V _sp And a set voltage V _sm Is decreased. When the voltage V is set _sp And a set voltage V _sm When the common mode voltage of (2) reaches the set common mode voltage difference, the amplifying stage is ended.

After the amplification phase is over, a sampling phase is entered. Dynamic amplifier 240 acquires capacitance C _sp And capacitor C _sm The discharged voltages are respectively referred to as sampling voltages DeltaV _sp And sampling voltage DeltaV _sm . Dynamic amplifier 240 is based on capacitance C _sp And capacitor C _sm Voltage difference before and after discharge, capacitance C _sp And capacitor C _sm Time of discharge, determine capacitance C _sp Time of discharge and capacitance C _sp The change edge between the voltage differences before and after discharge also means the instant signal S _p A kind of electronic deviceCapacitor C _sm Time of discharge and capacitance C _sm The change edge between the voltage differences before and after discharge also means the instant signal S _m . Subsequently, the dynamic amplifier 240 outputs the timing signal S _p And timing signal S _m The transmit time-to-digital converter 250.

Fig. 6 is a simulation diagram between the discharge time of the capacitor C and the voltage difference before and after the discharge. As shown in fig. 6, when the dynamic amplifier 240 is turned to the switching circuit S _sp And a switch circuit S _sm When RST signal is sent, switch circuit S _sp And a switch circuit S _sm The dynamic amplifier 240 is in the reset phase, closed. When the dynamic amplifier 240 is turned to the switching circuit S _sp And a switch circuit S _sm When transmitting conv signal, switch circuit S _sp And a switch circuit S _sm The dynamic amplifier 240 is in the amplification stage, disconnected. At this time, the time of discharging the capacitor C and the voltage difference before and after discharging the capacitor C are in a linear relationship.

The time-to-digital converter 250 receives the timing signal S sent by the dynamic amplifier 240 _p And timing signal S _m After that, the timing signal S can be measured _p And timing signal S _m And then converting the time information corresponding to the time interval into a digital signal to obtain LSB information.

In the SAR ADC protected by the application, the dynamic amplifier and the time-to-digital converter are newly added, after the comparator enters a metastable state, the dynamic amplifier converts the input residual voltage into a time sequence signal with time, and then the time sequence signal is converted into a digital signal through the time-to-digital converter to obtain LSB information, so that higher resolution is obtained under the same time, namely the sampling speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

It should be noted that, in the SAR ADC protected by the present application, the structures of the capacitor array 210, the comparator circuit 220 and the dynamic amplifier 240 are not limited to one shown in fig. 3, and may be other structures, and the present application is only exemplified herein. The number of capacitor arrays 210, comparator circuits 220, dynamic amplifiers 240 and time-to-digital converters 250 in the present application is not limited to only one of fig. 3, but may be any number, and the present application is not limited thereto.

In one example, when the number of capacitor arrays 210, comparator circuit 220, dynamic amplifier 240, and time-to-digital converter 250 are all N, N is a positive integer greater than 2. Each of the capacitor array 210, the comparator circuit 220, the dynamic amplifier 240, and the time-to-digital converter 250 may be connected in a connection relationship as shown in fig. 3. The output end of each comparator circuit 220 is connected to the SAR logic circuit 230, and the SAR logic circuit 230 can be electrically connected to each capacitor array 210, so as to control each capacitor array 210.

In one example, the number of capacitor arrays 210 is one, and the number of comparator circuits 220, dynamic amplifiers 240, and time-to-digital converters 250 are all N, N being a positive integer greater than 2. The two inputs of each comparator circuit 220 are connected in parallel to the two outputs of the capacitor array 210, and the output of each comparator circuit 220 is connected to the SAR logic circuit 230. Each of the comparator circuit 220, the dynamic amplifier 240, and the time-to-digital converter 250 may be connected in a connection relationship as shown in fig. 3.

Fig. 7 is a schematic diagram showing performance comparison between two prior art SAR ADCs and the SAR ADC protected by the present application. Fig. 7 shows the resolution number and the conversion number of three SAR ADCs under the same precision condition. FIG. 7 (a) is a schematic diagram of an existing SAR ADC, wherein the comparator does not detect metastable state during the operation of the SAR ADC; FIG. 7 (b) is a prior art SAR ADC, wherein during operation, the comparator detects metastable state; fig. 7 (b) shows a protected SAR ADC of the present application, in which a comparator detects metastable states during operation, and a dynamic amplifier and a time-to-digital converter quantize the time.

Compared with the SAR ADC shown in the figure 7 (a), the SAR ADC protected by the application reduces the frequency of converting phase by the SAR logic circuit 230 and can improve the conversion speed; compared with the SAR ADC shown in the (b) of fig. 7, the SAR ADC can achieve higher resolution in the same time, and can improve the conversion speed.

The first table is the simulation results of each performance of three SAR ADCs. From the results presented in table one, it can be seen that the highest sampling rate of the SAR ADC protected by the present application is increased by nearly a factor of two at the same effective number of bits.

Table three SAR ADC performance simulation results

Fig. 8 is a flowchart of a method for improving a bandwidth of a SAR ADC according to an embodiment of the application. As shown in fig. 8, the implementation of the method specifically includes the following steps:

In step S801, the comparator circuit generates a control signal according to the first analog signal and outputs the control signal to the dynamic amplifier.

Before that, the capacitor array in the SAR ADC samples and holds the analog signal to obtain two voltage signals, which are a first output electrical signal and a second output electrical signal, and then inputs the first output electrical signal and the second output electrical signal to two input terminals of the comparator circuit, respectively. The specific implementation process may refer to fig. 3 and descriptions corresponding to fig. 3, and will not be described in detail herein.

The comparator circuit in the SAR ADC determines whether it is in the MSB stage according to the timing of the internal clock signal clk. The comparator circuit compares the received first output electric signal with the second output electric signal when determining that the comparator circuit is in the MSB stage, and outputs a comparison signal.

When the first output electric signal is larger than the second output electric signal, the comparison signal output by the comparator circuit is logic high level or '1'. When the first output electric signal is smaller than the second output electric signal, the comparison signal output by the comparator circuit is at a logic low level or '0'. When the first output electric signal is equal to or approximately equal to the second output electric signal, the comparator circuit compares the first output electric signal with the second output electric signal for a longer time. If the comparator circuit fails to give a determination within a prescribed time, the comparator enters a "metastable" state.

The comparator circuit locks the first output electrical signal and the second output electrical signal after entering the metastable state to provide a stable electrical signal for the dynamic amplifier. The comparator circuit sends a comparison signal to the SAR logic circuit to stop the SAR logic circuit, so that the frequency of converting phase of the SAR logic circuit can be reduced. The comparator circuit then sends a reset signal to the dynamic amplifier to unset the dynamic amplifier. The specific implementation process may refer to fig. 4-5 and descriptions corresponding to fig. 4-5, and will not be described in detail herein.

In step S802, the dynamic amplifier converts the first analog signal into the second analog signal after receiving the control signal.

This step is performed by a dynamic amplifier in the SAR ADC. After receiving the reset signal, the dynamic amplifier receives the first input electric signal and the second input electric signal output by the capacitor array, converts the first input electric signal and the second input electric signal into time sequence signals with time, and inputs the time sequence signals into the time-to-digital converter. The specific implementation process may refer to fig. 3 and descriptions corresponding to fig. 3, and will not be described in detail herein.

In step S803, the time-to-digital converter receives the second analog signal and then converts the second analog signal into a digital signal.

This step is performed by a time-to-digital converter in the SAR ADC. After receiving the time sequence signals sent by the dynamic amplifier, the time-to-digital converter can measure the time intervals between the time sequence signals, and then converts the time information corresponding to the time intervals into digital signals to obtain LSB information.

In the method, after the comparator enters a metastable state, the dynamic amplifier is enabled to convert the first input electric signal and the second input electric signal into time sequence signals with time, then the time information is converted into digital signals through the time-to-digital converter, LSB information is obtained, higher resolution is obtained under the same time, namely the sampling speed of the SAR ADC is improved, and the single-channel bandwidth of the SAR ADC is improved.

Fig. 9 is a schematic diagram of a frame of an electronic device according to an embodiment of the present application. As shown in fig. 9, the electronic device 900 includes an analog circuit 910, a clock circuit 920, a digital circuit 930, and at least one SAR ADC 200 described in fig. 2-8 and the corresponding protection schemes described above.

Analog circuitry 910 is used to generate analog signals that provide input electrical signals to capacitive array 210 in SAR ADC 200. Analog circuitry 910 may be, among other things, an analog sensor, as well as a component or device that includes an analog sensor.

The clock circuit 920 is configured to generate a clock signal to provide a clock signal clk to the comparator circuit 220 and SAR logic in the SAR ADC 200. The clock circuit 920 may be an oscillator, etc., and components including an oscillator.

The digital circuit 930 is used to process the digital signal output from the SAR ADC 200. The digital circuit 930 may be, among other things, a variety of processors, transceivers, memory, etc.

Since the electronic device 900 includes the SAR ADC 200 as described in fig. 2-8 and the corresponding protection schemes described above, the electronic device 900 has all or at least some of the advantages of the SAR ADC 200. The powered device may be, among other things, a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile location data unit, a global positioning system (global positioning system, GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (session initialization protocol, SIP) phone, a tablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (personal digital assistant, PDA), a display, a computer display, a television, a tuner, a radio, a satellite broadcast, a music player, a digital music player, a portable music player, a digital video player, a digital video disc (digital video disc, DVD) player, a portable digital video player, an automobile, a vehicle component, an avionics system, an unmanned aerial vehicle, and a multi-rotor aircraft.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The last explanation is: the above embodiments are only for illustrating the technical solution of the present application, but are not limited thereto; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions in the various embodiments of the application.

Claims

1. An analog-to-digital converter, comprising: the analog signal input end, the capacitor array, the comparator circuit, the dynamic amplifier and the time-to-digital converter;

the capacitor array is coupled between the analog signal input terminal and the first output terminal of the comparator circuit;

the input end of the comparator circuit is coupled with the analog signal input end, the first output end of the comparator circuit is coupled with the control end of the capacitor array, the second output end of the comparator circuit is coupled with the control end of the dynamic amplifier, the comparator circuit is used for generating a comparison signal according to the analog signal received by the analog signal input end and outputting the comparison signal to the capacitor array through the first output end, and is used for generating a first control signal according to the analog signal and outputting the first control signal to the dynamic amplifier through the second output end, the first control signal is used for enabling the dynamic amplifier to work, and the comparison signal is used for generating a first part of digital signal;

The input end of the dynamic amplifier is coupled with the input end of the analog signal, and the output end of the dynamic amplifier is coupled with the input end of the time-to-digital converter;

the output end of the time-to-digital converter is used for outputting a second part of digital signals.

2. The analog-to-digital converter of claim 1, further comprising: the input end of the SAR logic circuit is coupled with the first output end of the comparator circuit, the first output end of the SAR logic circuit is coupled with the control end of the capacitor array, the second output end of the SAR logic circuit is used for outputting a second control signal, the second output end of the SAR logic circuit is used for outputting the first part of digital signals, and the second control signal is used for enabling the capacitor array to work.

3. An analog to digital converter according to claim 1 or 2, wherein the comparator circuit is configured to generate the first control signal based on whether a difference between analog signals received at the analog signal input is less than a set threshold value, and when the difference between analog signals is less than the set threshold value.

4. An analog to digital converter according to any of claims 1 to 3, wherein the comparator circuit comprises a clock signal input, a comparator, a delay circuit and a flip-flop;

the first input end of the comparator is coupled with the analog signal input end, the second input end of the comparator is coupled with the clock signal input end, the output end of the comparator is respectively coupled with the output end of the SAR logic circuit and the first input end of the trigger, and the comparator is used for generating the comparison signal according to the clock signal input by the clock signal input end and the analog signal received by the analog signal input end;

the delay circuit is coupled between the clock signal input end and the second input end of the trigger;

the input end of the trigger is coupled to the control end of the dynamic amplifier, and the input end of the trigger is used for outputting the first control signal.

5. The analog-to-digital converter according to claim 4, wherein the comparator comprises a first MOS transistor M1, a second MOS transistor M2, a first inverter, a second inverter and or logic device,

the source electrode of the first MOS tube M1 and the source electrode of the second MOS tube M2 are respectively coupled with a first power input end, the drain electrode of the first MOS tube M1 and the drain electrode of the second MOS tube M2 are respectively grounded, and the grid electrode of the first MOS tube M1 and the grid electrode of the second MOS tube M2 are respectively coupled with the analog signal input end;

The input end of the first inverter is coupled between the first power input end and the source electrode of the first MOS tube M1, the input end of the second inverter is coupled between the first power input end and the source electrode of the second MOS tube M2, the output end of the first inverter and the output end of the second inverter are coupled with the input end of the OR logic device, and the output end of the OR logic device is used for outputting the comparison signal.

6. The analog-to-digital converter of claim 5, wherein the comparator further comprises a third MOS transistor M7, a fourth MOS transistor M8, a fifth MOS transistor M9, and a sixth MOS transistor M10;

the source electrode of the third MOS tube M7 is coupled between the first power input end and the first inverter, and the source electrode of the fourth MOS tube M8 is coupled between the first power input end and the second inverter;

the source electrode of the fifth MOS tube M9 is coupled with the drain electrode of the first MOS tube M1 and the drain electrode of the second MOS tube M2, and the drain electrode of the fifth MOS tube M9 is grounded; the sixth MOS transistor M10 is coupled between the source of the first MOS transistor M1 and the source of the second MOS transistor M2;

the gate of the third MOS transistor M7, the gate of the fourth MOS transistor M8, the gate of the fifth MOS transistor M9, and the gate of the sixth MOS transistor M10 are respectively coupled to the clock signal input terminal.

7. An analog-to-digital converter according to any of claims 4-6, wherein the delay circuit is configured to generate a second clock signal according to the clock signal received at the clock signal input terminal, the second clock signal being a clock signal delayed by a set time from the clock signal received at the clock signal input terminal.

8. The analog-to-digital converter of any of claims 4-7, wherein the flip-flop is configured to generate the first control signal based on the comparison signal and the second clock signal.

9. The analog-to-digital converter of any of claims 1-8, wherein the dynamic amplifier comprises a first switching circuit, a second switching circuit, a first MOS transistor, a second MOS transistor, and a current source;

one end of the first switch circuit and one end of the first switch circuit are respectively coupled with a second power input end, the other end of the first switch circuit is coupled with the source electrode of the first MOS tube, and the other end of the second switch circuit is coupled with the source electrode of the second MOS tube;

the drain electrode of the first MOS tube and the drain electrode of the second MOS tube are respectively coupled with one end of the current source, and the other end of the current source is grounded; the grid electrode of the first MOS tube and the grid electrode of the second MOS tube are respectively coupled with the analog signal input end.

10. The analog-to-digital converter of claim 9, wherein the dynamic amplifier further comprises a first capacitor and a second capacitor;

one end of the first capacitor is coupled between the first switch circuit and the first MOS tube, and the other end of the first capacitor is grounded; one end of the second capacitor is coupled between the second switch circuit and the second MOS tube, and the other end of the second capacitor is grounded.

11. An analog-to-digital converter according to claim 9 or 10, wherein the dynamic amplifier is configured to cause the first switching circuit and the second switching circuit to be turned off in accordance with the first control signal transmitted from the comparator circuit.

12. A method for converting an analog signal to a digital signal, comprising:

the comparator circuit generates a first control signal according to the first analog signal and outputs the first control signal to the dynamic amplifier;

after receiving the first control signal, the dynamic amplifier converts the first analog signal into a second analog signal, wherein the second analog signal carries time information;

and after the time-to-digital converter receives the second analog signal, the second analog signal is converted into a digital signal.

13. The method according to claim 12, wherein the method further comprises:

the comparator circuit receives a clock signal;

the comparator circuit generates a first control signal according to a first analog signal and outputs the first control signal to the dynamic amplifier, and specifically comprises:

the comparator circuit generates the first control signal based on the clock signal and the first analog signal.

14. The method of claim 13, wherein the method further comprises:

the comparator circuit generates a comparison signal according to the first analog signal and the clock signal and outputs the comparison signal to the successive approximation register type SAR logic circuit;

and after the SAR logic circuit receives the comparison signal, generating a digital signal according to the comparison signal.

15. An electronic device, comprising:

an analog circuit for generating an analog signal;

a clock circuit for generating a clock signal;

at least one analog-to-digital converter according to claims 1-11 for receiving said analog signal and said clock signal, converting said analog signal into a digital signal;

and the digital circuit is used for receiving the digital signal and processing the digital signal.