CN116936711A - Vertical light emitting diode, preparation method thereof and LED lamp panel - Google Patents
Vertical light emitting diode, preparation method thereof and LED lamp panel Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 76
- 238000006243 chemical reaction Methods 0.000 claims abstract description 56
- 229920002120 photoresistant polymer Polymers 0.000 claims description 108
- 239000010408 film Substances 0.000 claims description 88
- 238000005530 etching Methods 0.000 claims description 59
- 238000000034 method Methods 0.000 claims description 33
- 238000001704 evaporation Methods 0.000 claims description 22
- 238000007747 plating Methods 0.000 claims description 20
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 19
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- 238000000576 coating method Methods 0.000 claims description 13
- 238000004519 manufacturing process Methods 0.000 claims description 12
- 239000010409 thin film Substances 0.000 claims description 12
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- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 5
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Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
- H01L33/46—Reflective coating, e.g. dielectric Bragg reflector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0025—Processes relating to coatings
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The application provides a vertical light-emitting diode, a preparation method thereof and an LED lamp panel, wherein the vertical light-emitting diode comprises a conductive layer, and an Ag metal reflector, a light angle conversion layer, an epitaxial layer and a conductive metal layer which are sequentially deposited on the conductive layer; the conductive layer comprises a chip bonding pad, and a conductive substrate, an Au metal film layer, an Au metal film and an Ni metal film which are sequentially deposited on the chip bonding pad, wherein the cross section of the light angle conversion layer is of an inverted trapezoid structure, and the light angle conversion layer is an intrinsic GaN layer.
Description
Technical Field
The application belongs to the technical field of light emitting diodes, and particularly relates to a vertical light emitting diode, a preparation method thereof and an LED lamp panel.
Background
The vertical light-emitting diode chip has high efficiency, energy conservation, high reliability and high light efficiency, is widely applied to the fields of illumination and display, and can vertically transmit current due to the fact that the positive electrode and the negative electrode are distributed on two sides of the epitaxial layer, so that the high temperature resistance of the vertical light-emitting diode and the limiting current used by the vertical light-emitting diode are greatly improved.
However, the light with a large angle inside the conventional vertical light emitting diode cannot be released due to total reflection in the vertical light emitting diode, so that the light emitting efficiency of the vertical light emitting diode is reduced.
Disclosure of Invention
In order to solve the technical problems, the application provides a vertical light emitting diode, a preparation method thereof and an LED, which are used for solving the technical problems in the prior art.
In a first aspect, an embodiment of the present application provides a vertical light emitting diode, including a conductive layer, and an Ag metal mirror, a light angle conversion layer, an epitaxial layer, and a conductive metal layer sequentially deposited on the conductive layer;
the conductive layer comprises a chip bonding pad, and a conductive substrate, an Au metal film layer, an Au metal film and a Ni metal film which are sequentially deposited on the chip bonding pad, wherein the section of the light angle conversion layer is of an inverted trapezoid structure, and the light angle conversion layer is an intrinsic GaN layer.
Compared with the prior art, the application has the beneficial effects that: according to the application, the Ag metal reflector and the light angle conversion layer arranged in the inverted trapezoid are arranged, so that light rays with large angles in the vertical light-emitting diode are converted into light rays with small angles through reflection of the Ag metal reflector, and the light rays with large angles are prevented from being totally reflected in the vertical light-emitting diode and not being released, thereby improving the light-emitting efficiency of the vertical light-emitting diode.
Preferably, the thickness of the Ag metal mirror is 1200A-1500A, the thickness of the Au metal film is 10000A-20000A, and the thickness of the Ni metal film is 5000A-8000A.
Preferably, the epitaxial layer comprises a P-type GaN layer, an active light emitting layer, an N-type GaN layer and an AlN buffer layer which are sequentially deposited on the light angle conversion layer.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a vertical light emitting diode, including the following steps:
s1, providing a Si substrate, depositing an epitaxial layer on the Si substrate, and preparing SiO on the epitaxial layer 2 A thin film to obtain a sacrificial layer;
s2, coating photoresist on the surface of the sacrificial layer, exposing and developing the photoresist to expose part of the sacrificial layer, and corroding the exposed sacrificial layer by using corrosive liquid to form a trapezoid sacrificial layer opening on the sacrificial layer;
s3, preparing an intrinsic GaN layer on the epitaxial layer in the sacrificial layer opening, and corroding to remove the residual sacrificial layer to obtain a light angle conversion layer with a trapezoid cross section;
s4, coating a first positive photoresist on the light angle conversion layer and an epitaxial layer which is not covered by the light angle conversion layer, then exposing, coating a first negative photoresist on the first positive photoresist, then exposing, coating a second positive photoresist on the first negative photoresist, then exposing, and then uniformly developing to form a first photoresist opening on the first positive photoresist, a second photoresist opening on the first negative photoresist and a third photoresist opening on the second positive photoresist;
wherein the size of the first photoresist opening is larger than the size of the second photoresist opening, and the size of the second photoresist opening is equal to the size of the third photoresist opening;
s5, evaporating an Ag metal film on the epitaxial layer and the light angle conversion layer in the first photoresist opening by utilizing an electron beam evaporation technology, and then removing the first positive photoresist, the first negative photoresist and the second positive photoresist to obtain an Ag metal reflector;
s6, sequentially depositing a Ni metal film and an Au metal film on the Ag metal reflecting mirror;
s7, providing a conductive substrate, evaporating an Au metal film layer on the conductive substrate, turning over the Si substrate, and performing hot-press bonding on the Au metal film layer and the Au metal film;
and S8, removing the Si substrate, evaporating one side of the conductive substrate, which is far away from the Au metal film layer, to form a chip bonding pad, coating photoresist on the surface of the epitaxial layer, exposing, developing and removing part of the epitaxial layer to expose part of the epitaxial layer, and evaporating the exposed epitaxial layer to form a conductive metal layer so as to obtain the vertical light-emitting diode.
Preferably, the preparation of SiO on the epitaxial layer 2 The step of forming a sacrificial layer from the film comprises:
introducing a first N into a reaction cavity of a PECVD device 2 Then controlling the power of the radio frequency to be 30W-60W for 30S-60S to generate plasma and clean the reaction cavity by the plasma, and closing the radio frequency, wherein the first N 2 The flow rate of the water is 200sccm-300sccm;
then vacuuming the reaction cavity and simultaneously introducing a second N 2 Maintaining the cavity pressure at 120Pa-180Pa, where the second N 2 The flow rate of the water is 1500sccm-2000sccm;
then simultaneously introducing SiH 4 And N 2 O, then switching on the power of the radio frequency to 90W-120W for a preset time to obtain SiO 2 Film, N 2 O and SiH 4 The flow ratio is 5:1-20:1, N in the preset time 2 O and SiH 4 The flow rate ratio is gradually increased so that the prepared SiO 2 The film is gradually dense along the direction away from the epitaxial layer;
then, the radio frequency power is reduced to 30W-60W, and O is introduced 2 By ionising oxygen atoms with SiO 2 Dangling bond reaction on the surface of the film to clean SiO 2 The film, and thus the sacrificial layer, is obtained.
Preferably, the step of etching the exposed sacrificial layer with an etching solution to form a trapezoid sacrificial layer opening on the sacrificial layer includes:
etching the exposed sacrificial layer by using a first etching solution to form a vertical opening which is vertically arranged, then etching the side wall of the vertical opening by using a second etching solution to form an inverted trapezoid sacrificial layer opening, and gradually reducing the volume ratio of the hydrogen fluoride solution to the ammonium fluoride solution in the second etching solution along the direction away from the epitaxial layer so as to gradually reduce the etching rate, wherein an included angle between the sacrificial layer opening and the side wall of the epitaxial layer is 30-60 degrees.
Preferably, when the Ag metal film is evaporated, the plating pot of the electron beam evaporation machine revolves around the center of the machine, and simultaneously the plating pot rotates along the center of the plating pot, and when the evaporation thickness of the Ag metal film is increased by a preset thickness, the rotation and revolution directions of the plating pot change once, and simultaneously, after the evaporation of the Ag metal film is completed, the Si substrate is heated through a hot plate, so that the first positive photoresist, the first negative photoresist and the second positive photoresist are softened and wrap the Ag metal film.
Preferably, the step of removing the Si substrate includes:
the first etching is carried out on the Si substrate by using a first solution, the thickness of the first etching is 60% of the thickness of the Si substrate, the etching rate of the first solution on the Si substrate is 10 mu m/min-15 mu m/min, then the second etching is carried out on the Si substrate after the first etching by using a second solution, the thickness of the second etching is 30% of the thickness of the Si substrate, the etching rate of the second solution on the Si substrate is 10 mu m/min-15 mu m/min, then the third etching is carried out on the Si substrate after the second etching by using a third solution, the thickness of the third etching is 10% of the thickness of the Si substrate, and the etching rate of the third solution on the Si substrate is 1 mu m/min-3 mu m/min.
Preferably, in the step S1, an AlN buffer layer, an N-type GaN layer, an active light emitting layer, and a P-type GaN layer are sequentially deposited on the Si substrate to form an epitaxial layer.
The embodiment of the application also provides a technical scheme, which is characterized by comprising a PCB and a plurality of fluorescent powder dams arranged on the PCB, wherein a P-type bonding pad, an N-type bonding pad and the vertical light emitting diode are arranged in the fluorescent powder dams, the vertical light emitting diode is arranged on the P-type bonding pad through conductive adhesive, a conductive metal layer in the vertical light emitting diode is connected with the N-type bonding pad through Au wires, fluorescent powder is filled in the fluorescent powder dams, and transparent adhesive is arranged on the surfaces of the fluorescent powder and the PCB.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments or the description of the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a vertical light emitting diode according to a first embodiment of the present application;
fig. 2 is a flowchart of a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 3 is a schematic diagram of a semi-finished product generated in step S1 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 4 is a schematic diagram of a semi-finished product generated in step S2 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 5 is a schematic diagram of a semi-finished product generated in step S3 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 6 is a schematic diagram of a semi-finished product generated in step S4 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 7 is a schematic diagram of a semi-finished product generated in step S5 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 8 is a schematic diagram of a semi-finished product generated in step S6 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 9 is a schematic diagram of a semi-finished product generated in step S7 in a method for manufacturing a vertical light emitting diode according to a second embodiment of the present application;
fig. 10 is a block diagram of an LED lamp panel according to another embodiment of the present application;
fig. 11 is a sectional view a-a in fig. 10.
Reference numerals illustrate:
the application will be further described with reference to the drawings.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and intended to illustrate embodiments of the application and should not be construed as limiting the application.
In the description of the embodiments of the present application, it should be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like indicate orientations or positional relationships based on the orientation or positional relationships shown in the drawings, merely to facilitate description of the embodiments of the present application and simplify description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the embodiments of the present application, the meaning of "plurality" is two or more, unless explicitly defined otherwise.
Example 1
As shown in fig. 1, a first embodiment of the present application provides a vertical light emitting diode, which includes a conductive layer, and an Ag metal reflector 6, a light angle conversion layer 4, an epitaxial layer, and a conductive metal layer 12 sequentially deposited on the conductive layer;
the conductive layer comprises a chip bonding pad 11, and a conductive substrate 9, an Au metal film layer 10, an Au metal film 8 and a Ni metal film 7 which are sequentially deposited on the chip bonding pad 11, wherein the section of the light angle conversion layer 4 is in an inverted trapezoid structure, and the light angle conversion layer 4 is an intrinsic GaN layer;
the conductive substrate 9 is a P-type doped or N-type doped Si sheet, the Au metal film 8 is used for bonding Au metal on the subsequent conductive substrate 9, the Ni metal film 7 is used for protecting Ag metal from being corroded and oxidized by external environment, and the conductive metal layer 12 is made of metal Cr/Al/Ti/Au.
Specifically, in this embodiment, the cross section of the light angle conversion layer 4 is in an inverted trapezoid structure, that is, along the direction from the Ag metal mirror 6 to the epitaxial layer, the width of the light angle conversion layer 4 gradually increases, meanwhile, the light angle conversion layer 4 is specifically an intrinsic GaN layer, and since the refractive index of the intrinsic GaN layer is close to that of the P-type GaN layer 24 in the epitaxial layer, the light angle conversion layer can avoid that part of light emitted by the active light emitting layer 23 is totally reflected at the contact surface of the P-type GaN layer 24 and the light angle conversion layer 4, so as to cause light efficiency loss;
meanwhile, in the application, by arranging the Ag metal reflector 6 and the light angle conversion layer 4 arranged in an inverted trapezoid, the light rays with large angles in the vertical light-emitting diode are converted into the light rays with small angles through the reflection of the Ag metal reflector 6, so that the light rays with large angles are prevented from being totally reflected in the vertical light-emitting diode and not being released, and the luminous efficiency of the vertical light-emitting diode is improved.
In this embodiment, the thickness of the Ag metal mirror 6 is 1200 a-1500 a, the thickness of the Au metal film 8 is 10000 a-20000 a, and the thickness of the Ni metal film 7 is 5000 a-8000 a;
the thickness of the Ag metal reflector 6 is not lower than 1200 a, in order to ensure that the reflectivity of the Ag metal reflector 6 is greater than that of the Ag metal, and the thickness of the Ag metal reflector 6 is not higher than 1500 a, which is to further save the cost.
In this embodiment, the epitaxial layer includes a P-type GaN layer 24, an active light emitting layer 23, an N-type GaN layer 22, and an AlN buffer layer 21 sequentially deposited on the light-angle conversion layer 4.
As shown in fig. 10 and 11, it should be noted that in other embodiments of the present application, an LED lamp panel is further provided, which is characterized by comprising a PCB board 100 and a plurality of phosphor weirs 101 disposed on the PCB board 100, wherein a P-type bonding pad 102, an N-type bonding pad 103 and a vertical light emitting diode as described in the above embodiments are disposed in the phosphor weirs 101, the vertical light emitting diode is disposed on the P-type bonding pad 102 through a conductive adhesive 104, a conductive metal layer 12 in the vertical light emitting diode is connected with the N-type bonding pad 103 through an Au wire 105, phosphor 106 is filled in the phosphor weirs 101, and transparent adhesive 107 is disposed on the surfaces of the phosphor 106 and the PCB board 100;
specifically, a P-type bonding pad 102 is disposed at the bottom of the phosphor dam 101, the chip bonding pad 11 in the vertical light emitting diode is adhered and fixed on the P-type bonding pad 102 by a conductive adhesive 104, and the conductive metal layer 12 is connected with the N-type bonding pad 103 by an Au wire 105 to form conductive connection, and meanwhile, the transparent adhesive 107 is disposed to protect the phosphor 106 and the vertical light emitting diode on the PCB 100.
The preparation method of the LED lamp panel is worth explaining as follows:
firstly, providing a PCB 100, wherein the PCB 100 at least comprises a fluorescent powder dam 101, a P-type bonding pad 102 and an N-type bonding pad 103, then bonding a chip bonding pad 11 of the vertical light emitting diode and the P-type bonding pad 102 together by using a conductive adhesive 104 to form electric connection, wherein the conductive adhesive 104 can be Ag, snAg, snAgCu, and then connecting and conducting a conductive metal layer 12 of the chip bonding pad 11 and the N-type bonding pad 103 by using an Au wire 105 in a wire bonding process;
then, placing fluorescent powder 106 on the surface of the vertical light-emitting diode and in the fluorescent powder surrounding dam 101, and then rotating the PCB 100 by using a roller to uniformly fill the fluorescent powder 106 in the fluorescent powder surrounding dam 101, wherein the fluorescent powder 106 can emit red light and green light after being excited by blue light emitted by the vertical light-emitting diode, and can be combined with the blue light emitted by the vertical light-emitting diode into white light;
and then transparent adhesive 107 is coated on the fluorescent powder 106 and the surface of the PCB 100 to protect the vertical light emitting diode and the fluorescent powder 106, so as to obtain the LED lamp panel.
Example two
As shown in fig. 2, a second embodiment of the present application provides a method for manufacturing a vertical light emitting diode, which includes the following steps:
as shown in FIG. 3, S1, providing a Si substrate 1, depositing an epitaxial layer on the Si substrate 1, and preparing SiO on the epitaxial layer 2 A thin film to obtain a sacrificial layer 3;
wherein an AlN buffer layer 21, an N-type GaN layer 22, an active light emitting layer 23 and a P-type GaN layer 24 are sequentially deposited on the Si substrate 1 to form an epitaxial layer;
in step S1, the thickness of the sacrifice layer 3 is 2 to 3 times the thickness of the light angle conversion layer 4 prepared in the subsequent step.
In the step S1, siO is prepared on the epitaxial layer 2 The step of forming a sacrificial layer from the film comprises:
introducing a first N into a reaction cavity of a PECVD device 2 Then controlling the power of the radio frequency to be 30W-60W for 30S-60S to generate plasma and clean the reaction cavity by the plasma, and closing the radio frequency, wherein the first N 2 The flow rate of the water is 200sccm-300sccm;
then vacuuming the reaction cavity and simultaneously introducing a second N 2 Maintaining the cavity pressure at 120Pa-180Pa, where the second N 2 The flow rate of the water is 1500sccm-2000sccm;
wherein the second N is introduced 2 Maintaining the chamber pressure at 120Pa-180Pa for creating a low vacuum of N 2 Atmosphere, avoiding the influence of impurity gas in the reaction cavity on subsequent SiO 2 Film forming effect;
then simultaneously introducing SiH 4 And N 2 O, then turn on the RF power90W-120W for a preset time to obtain SiO 2 Film, N 2 O and SiH 4 The flow ratio is 5:1-20:1, N in a preset time 2 O and SiH 4 The flow rate ratio is gradually increased so that the prepared SiO 2 The film is gradually compact along the epitaxial direction;
wherein, the radio frequency power is switched on to 90W-120W for a preset time, and the preset time can be according to the SiO prepared as required 2 The thickness of the film is set, and the epitaxial direction specifically refers to the direction back to the epitaxial layer;
then, the radio frequency power is reduced to 30W-60W, and O is introduced 2 By ionising oxygen atoms with SiO 2 Dangling bond reaction on the surface of the film to clean SiO 2 A film, thereby obtaining a sacrificial layer;
wherein by ionizing oxygen atoms with SiO 2 Dangling bond reaction on the surface of the film, thereby achieving the purpose of cleaning SiO 2 The purpose of the film is to avoid SiO in the subsequent process of preparing the intrinsic GaN layer 2 The dangling bonds on the surface of the thin film affect the crystal quality of the intrinsic GaN layer.
As shown in fig. 4, S2, coating a photoresist on the surface of the sacrificial layer 3, exposing and developing the photoresist to expose a part of the sacrificial layer 3, and corroding the exposed sacrificial layer 3 with a corrosive liquid to form an inverted trapezoid sacrificial layer opening on the sacrificial layer 3;
wherein in the step S2, the step of etching the exposed sacrificial layer with an etching solution to form a trapezoid-shaped sacrificial layer opening on the sacrificial layer includes:
etching the exposed sacrificial layer by using a first etching solution to form a vertical opening which is vertically arranged, then etching the side wall of the vertical opening by using a second etching solution to form an inverted trapezoid sacrificial layer opening, and gradually reducing the volume ratio of the hydrogen fluoride solution to the ammonium fluoride solution in the second etching solution along the direction away from the epitaxial layer so as to gradually reduce the etching rate, wherein an included angle between the sacrificial layer opening and the side wall of the epitaxial layer is 30-60 degrees;
specifically, photoresist is coated on the surface of the sacrificial layer 3, and then exposure and development are carried outShadow-removing part of the photoresist to expose part of the sacrificial layer 3, and then etching the exposed SiO with a first BOE solution 2 The film is formed with vertical openings and then etched with a second BOE solution to form SiO 2 The vertical opening side wall of the film forms a ladder shape to form a sacrificial layer opening, then the photoresist is removed, the volume ratio of the hydrogen fluoride solution and the ammonium fluoride solution in the second BOE solution is controlled by the through hole to control the angle of the acute angle between the sacrificial layer opening and the epitaxial layer side wall, the larger the volume ratio of the hydrogen fluoride solution and the ammonium fluoride solution in the second BOE solution is, the smaller the angle of the acute angle between the sacrificial layer opening and the epitaxial layer side wall is, because the SiO of the sacrificial layer 3 is prepared 2 N in the film Process 2 O and SiH 4 The flow ratio is gradually increased so that SiO 2 The film is gradually dense along the direction away from the epitaxial layer, so the second BOE solution corrodes SiO 2 The sidewalls of the vertical openings of the film being in a direction SiO away from the epitaxial layer 2 The etching rate of the side wall of the vertical opening of the film is gradually reduced, so that the opening of the sacrificial layer can be trapezoid, and the intrinsic GaN layer prepared in the opening of the sacrificial layer can be trapezoid after the subsequent preparation.
S3, as shown in FIG. 5, preparing an intrinsic GaN layer on the epitaxial layer in the opening of the sacrificial layer, and corroding to remove the residual sacrificial layer 3 to obtain a light angle conversion layer 4 with a trapezoid cross section;
specifically, the step S3 specifically includes: an intrinsic GaN layer is prepared as the light angle conversion layer 4 on the P-type GaN layer 24 in the opening of the sacrificial layer by MOCVD process because the intrinsic GaN layer cannot be formed on SiO 2 The intrinsic GaN layer is not formed on the remaining sacrificial layer 3 in the process of preparing the intrinsic GaN layer above the P-type GaN layer 24 in the opening of the sacrificial layer, and the refractive index of the intrinsic GaN layer is similar to that of the P-type GaN layer 24, so that the total reflection of part of light emitted by the active light emitting layer 23 on the contact surface of the P-type GaN layer 24 and the light angle conversion layer 4 can be avoided, and the light efficiency loss is caused;
in the first embodiment, the cross section of the light angle conversion layer 4 is an inverted trapezoid, but in this step, the light angle conversion layer 4 is an inverted trapezoid, and since the Si substrate 1 needs to be inverted during the subsequent bonding process, the light angle conversion layer 4 of the trapezoid may be the light angle conversion layer 4 of the inverted trapezoid mentioned in the first embodiment.
As shown in fig. 6, S4, a first positive photoresist 51 is coated and then exposed on the light angle conversion layer 4 and the epitaxial layer not covered by the light angle conversion layer 4, a first negative photoresist 52 is coated and then exposed on the first positive photoresist 51, a second positive photoresist 53 is coated and then exposed on the first negative photoresist 52, and then unified development is performed to form a first photoresist opening on the first positive photoresist 51, a second photoresist opening on the first negative photoresist 52, and a third photoresist opening on the second positive photoresist 53;
wherein the size of the first photoresist opening is larger than the size of the second photoresist opening, and the size of the second photoresist opening is equal to the size of the third photoresist opening;
the viscosity of the first positive photoresist 51 is between 30CPS and 50CPS, the thickness is 2 to 10 times of the thickness of the Ag metal reflecting mirror 6 which is prepared later, so that the Ag metal reflecting mirror 6 can be prepared later into the hollowed-out area of the first positive photoresist 51 below the first negative photoresist 52, the first exposure energy is between 200mj/cm and 230mj/cm, and the first exposure time is between 0.4S and 0.6S;
the thickness of the first negative photoresist 52 is 5-10 times of that of the first positive photoresist 51, the viscosity of the first negative photoresist 52 is 200CPS-240CPS, the second exposure energy is 300mj/cm, the second exposure time is 0.6S-0.8S;
the thickness of the second positive photoresist 53 is 1.5-3 times that of the first negative photoresist 52, the viscosity of the second positive photoresist 53 is 150CPS-200CPS, the third exposure energy is 250 mj/cm-300 mj/cm, the third exposure time is 0.8S-1.0S, and the wavelength of light used for the third exposure is larger than that of light used for the second exposure, so that the first negative photoresist 52 is prevented from being damaged when the third exposure is performed, and the first negative photoresist 52 is prevented from being developed cleanly.
As shown in fig. 7, S5, an Ag metal film is vapor deposited on the epitaxial layer and the light angle conversion layer 4 in the first photoresist opening by using an electron beam vapor deposition technology, and then the first positive photoresist 51, the first negative photoresist 52 and the second positive photoresist 53 are removed to obtain an Ag metal reflector 6;
in the step S5, when the Ag metal thin film is evaporated, the plating pot of the electron beam evaporation machine revolves around the center of the machine and rotates along the center of the plating pot, and when the evaporation thickness of the Ag metal thin film increases by a preset thickness, the rotation and revolution directions of the plating pot change once, and after the evaporation of the Ag metal thin film is completed, the Si substrate 1 is heated by a hot plate, so that the first positive photoresist 51, the first negative photoresist 52 and the second positive photoresist 53 soften and wrap the Ag metal thin film;
specifically, the plating pot revolves around the center of the machine table in the process of electron beam evaporation, the plating pot rotates around the center of the plating pot, the revolution direction is consistent with the rotation direction, and the preset thickness is 300 a, so that when the evaporation thickness of the Ag metal film is increased by 300 a, the revolution and rotation directions of the plating pot are changed once, the initial rotation direction is not limited, the plating pot can be understood to rotate and revolve clockwise just before beginning, when the thickness of the Ag metal film is plated to 300 a, the plating pot is converted into rotate and revolve anticlockwise, when the thickness of the Ag metal film is plated to 600 a, the plating pot is converted into rotate and revolve clockwise, and the process is repeated until the process is finished, the evaporation is repeated until the process is finished, the thickness uniformity of the Ag metal film on a wafer can be reduced, the thickness uniformity of the Ag metal film on the wafer is ensured to be less than 5%, the included angle between the plating pot and the horizontal plane of the Ag metal target is ensured to be 30-60 DEG, and the Ag metal can be evaporated into the hollowed-out area of the first photoresist 51 below the first negative photoresist 52 in the evaporation process;
after Ag metal evaporation is finished, the wafer is taken down from the plating pot, the Si substrate 1 is heated through a hot plate, so that the first positive photoresist 51, the first negative photoresist 52 and the second positive photoresist 53 are softened and wrap the Ag metal film, the openings of the first positive photoresist 51, the first negative photoresist 52 and the second positive photoresist 53 collapse to completely wrap the edge of the Ag metal film, and the Ag metal film is prevented from falling off during subsequent blue film stripping;
then, the Ag metal remaining on the surface of the second positive photoresist 53 is removed by a blue film stripping process, and then the remaining first positive photoresist 51, first negative photoresist 52 and second positive photoresist 53 are removed by a photoresist remover, thus completing the preparation of the Ag metal reflecting mirror 6.
As shown in fig. 8, S6, a Ni metal film 7 and an Au metal film 8 are sequentially deposited on the Ag metal mirror 6;
specifically, step S6 specifically includes: the Ni metal film 7 and the Au metal film 8 are sequentially evaporated on the surfaces of the Ag metal reflecting mirror 6 and the P-type GaN layer 24 which is not covered by the Ag metal reflecting mirror 6 by utilizing an electron beam evaporation process, the thickness of the Ni metal film 7 is 5000-8000A, the Ni metal film is used for protecting Ag metal from being corroded and oxidized by the external environment, the Au metal film 8 is 10000-20000A, and the Au metal film 8 is used for bonding an Au metal film layer 10 on a subsequent conductive substrate 9.
As shown in fig. 9, S7, a conductive substrate 9 is provided, an Au metal film layer 10 is evaporated on the conductive substrate 9, the Si substrate 1 is turned over, and the Au metal film layer 10 and the Au metal film 8 are thermally bonded.
S8, removing the Si substrate 1, evaporating and forming a chip bonding pad 11 on one side of the conductive substrate 9 away from the Au metal film layer 10, coating photoresist on the surface of the epitaxial layer, exposing, developing and removing part of the epitaxial layer to expose the epitaxial layer part, and evaporating and forming a conductive metal layer 12 on the exposed epitaxial layer to obtain the vertical light-emitting diode;
wherein, in the step S8, the step of removing the Si substrate includes:
the method comprises the steps of carrying out first etching on a Si substrate by using a first solution, wherein the thickness of the first etching is 60% of the thickness of the Si substrate, the etching rate of the first solution on the Si substrate is 10 mu m/min-15 mu m/min, then carrying out second etching on the Si substrate after the first etching by using a second solution, the thickness of the second etching is 30% of the thickness of the Si substrate, the etching rate of the second solution on the Si substrate is 10 mu m/min-15 mu m/min, then carrying out third etching on the Si substrate after the second etching by using a third solution, the thickness of the third etching is 10% of the thickness of the Si substrate, and the etching rate of the third solution on the Si substrate is 1 mu m/min-3 mu m/min;
the first solution, the second solution and the third solution are all mixed solutions of nitric acid, hydrofluoric acid and water, and the concentrations and the volume ratios of the nitric acid, the hydrofluoric acid and the water are only different, wherein the larger the concentration of the hydrofluoric acid is, the larger the volume ratio is, the higher the corrosion rate of the Si substrate 1 is, as can be seen from the above, the corrosion rate is gradually reduced in the process of corroding the Si substrate 1, and the thickness of the Si substrate 1 is gradually reduced, because if the Si substrate 1 is corroded by the solution with the large corrosion rate, the Si substrate 1 can be removed too quickly, the stress in an epitaxial layer can not be released slowly, the dark crack of the epitaxial layer is easily caused, the chip yield is finally reduced, and if the Si substrate 1 is removed by the solution with the small corrosion rate is too long in operation time, the machine yield is reduced;
after the Si substrate 1 is removed, removing a blue film on one side of the conductive substrate 9 away from the Au metal film layer 10, and then evaporating an Au metal layer on one side of the conductive substrate 9 away from the Au metal film layer 10 by utilizing an electron beam evaporation process to serve as a chip bonding pad 11 for connecting the conductive substrate 9 and a subsequent packaging bracket;
then, coating photoresist on the surface of the AlN buffer layer 21, exposing and developing to remove part of the photoresist, exposing the AlN buffer layer 21 below, removing the exposed AlN buffer layer 21 and the N-type GaN layer 22 below by using an inductive coupling plasma etching process to form an epitaxial layer concave part, sequentially evaporating metal Cr/Al/Ti/Au on the surface of the rest of the photoresist and in the epitaxial layer concave part by using an electron beam evaporation process, removing metal on the photoresist by using a blue film stripping process, removing the photoresist by using a photoresist removing solution, and preparing the metal Cr/Al/Ti/Au in the epitaxial layer concave part as a conductive metal layer 12 which is used for forming electric connection with a packaging bracket by using a wire bonding process.
In summary, in the application, by arranging the Ag metal reflector 6 and the light angle conversion layer 4 arranged in an inverted trapezoid, the light rays with large angles in the vertical light emitting diode are converted into the light rays with small angles through the reflection of the Ag metal reflector 6, so that the light rays with large angles are prevented from being totally reflected in the vertical light emitting diode and not released, thereby improving the light emitting efficiency of the vertical light emitting diode.
The foregoing description of the preferred embodiments of the application is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the application.
Claims (10)
1. The vertical light-emitting diode is characterized by comprising a conductive layer, and an Ag metal reflector, a light angle conversion layer, an epitaxial layer and a conductive metal layer which are sequentially deposited on the conductive layer;
the conductive layer comprises a chip bonding pad, and a conductive substrate, an Au metal film layer, an Au metal film and a Ni metal film which are sequentially deposited on the chip bonding pad, wherein the section of the light angle conversion layer is of an inverted trapezoid structure, and the light angle conversion layer is an intrinsic GaN layer.
2. The vertical light emitting diode of claim 1, wherein the Ag metal mirror has a thickness in the range of 1200 a-1500 a, the Au metal film has a thickness in the range of 10000 a-20000 a, and the Ni metal film has a thickness in the range of 5000 a-8000 a.
3. The led of any of claims 1-2, wherein the epitaxial layer comprises a P-type GaN layer, an active light emitting layer, an N-type GaN layer, an AlN buffer layer sequentially deposited on the light angle conversion layer.
4. The preparation method of the vertical light-emitting diode is characterized by comprising the following steps of:
s1, providing a Si substrate, depositing an epitaxial layer on the Si substrate, and preparing SiO on the epitaxial layer 2 A thin film to obtain a sacrificial layer;
s2, coating photoresist on the surface of the sacrificial layer, exposing and developing the photoresist to expose part of the sacrificial layer, and corroding the exposed sacrificial layer by using corrosive liquid to form a trapezoid sacrificial layer opening on the sacrificial layer;
s3, preparing an intrinsic GaN layer on the epitaxial layer in the sacrificial layer opening, and corroding to remove the residual sacrificial layer to obtain a light angle conversion layer with a trapezoid cross section;
s4, coating a first positive photoresist on the light angle conversion layer and an epitaxial layer which is not covered by the light angle conversion layer, then exposing, coating a first negative photoresist on the first positive photoresist, then exposing, coating a second positive photoresist on the first negative photoresist, then exposing, and then uniformly developing to form a first photoresist opening on the first positive photoresist, a second photoresist opening on the first negative photoresist and a third photoresist opening on the second positive photoresist;
wherein the size of the first photoresist opening is larger than the size of the second photoresist opening, and the size of the second photoresist opening is equal to the size of the third photoresist opening;
s5, evaporating an Ag metal film on the epitaxial layer and the light angle conversion layer in the first photoresist opening by utilizing an electron beam evaporation technology, and then removing the first positive photoresist, the first negative photoresist and the second positive photoresist to obtain an Ag metal reflector;
s6, sequentially depositing a Ni metal film and an Au metal film on the Ag metal reflecting mirror;
s7, providing a conductive substrate, evaporating an Au metal film layer on the conductive substrate, turning over the Si substrate, and performing hot-press bonding on the Au metal film layer and the Au metal film;
and S8, removing the Si substrate, evaporating one side of the conductive substrate, which is far away from the Au metal film layer, to form a chip bonding pad, coating photoresist on the surface of the epitaxial layer, exposing, developing and removing part of the epitaxial layer to expose part of the epitaxial layer, and evaporating the exposed epitaxial layer to form a conductive metal layer so as to obtain the vertical light-emitting diode.
5. The method of claim 4, wherein the preparing SiO on the epitaxial layer 2 The step of forming a sacrificial layer from the film comprises:
introducing a first N into a reaction cavity of a PECVD device 2 Then controlling the power of the radio frequency to be 30W-60W for 30S-60S to generate plasma and clean the reaction cavity by the plasma, and closing the radio frequency, wherein the first N 2 The flow rate of the water is 200sccm-300sccm;
then vacuuming the reaction cavity and simultaneously introducing a second N 2 Maintaining the cavity pressure at 120Pa-180Pa, where the second N 2 The flow rate of the water is 1500sccm-2000sccm;
then simultaneously introducing SiH 4 And N 2 O, then switching on the power of the radio frequency to 90W-120W for a preset time to obtain SiO 2 Film, N 2 O and SiH 4 The flow ratio is 5:1-20:1, N in the preset time 2 O and SiH 4 The flow rate ratio is gradually increased so that the prepared SiO 2 The film is gradually dense along the direction away from the epitaxial layer;
then, the radio frequency power is reduced to 30W-60W, and O is introduced 2 By ionising oxygen atoms with SiO 2 Dangling bond reaction on the surface of the film to clean SiO 2 The film, and thus the sacrificial layer, is obtained.
6. The method of manufacturing a vertical light emitting diode according to claim 4, wherein the etching the exposed sacrificial layer with the etching solution to form a trapezoid-shaped sacrificial layer opening on the sacrificial layer comprises:
etching the exposed sacrificial layer by using a first etching solution to form a vertical opening which is vertically arranged, then etching the side wall of the vertical opening by using a second etching solution to form an inverted trapezoid sacrificial layer opening, and gradually reducing the volume ratio of the hydrogen fluoride solution to the ammonium fluoride solution in the second etching solution along the direction away from the epitaxial layer so as to gradually reduce the etching rate, wherein an included angle between the sacrificial layer opening and the side wall of the epitaxial layer is 30-60 degrees.
7. The method according to claim 4, wherein the plating pot of the electron beam evaporation machine rotates along the center of the plating pot while the plating pot revolves around the center of the machine during the evaporation of the Ag metal thin film, and the rotation and revolution directions of the plating pot change once every time the evaporation thickness of the Ag metal thin film increases by a preset thickness, and the Si substrate is heated by a hot plate after the evaporation of the Ag metal thin film is completed, so that the first positive photoresist, the first negative photoresist and the second positive photoresist soften and encapsulate the Ag metal thin film.
8. The method of manufacturing a vertical light emitting diode according to claim 4, wherein the removing the Si substrate comprises:
the first etching is carried out on the Si substrate by using a first solution, the thickness of the first etching is 60% of the thickness of the Si substrate, the etching rate of the first solution on the Si substrate is 10 mu m/min-15 mu m/min, then the second etching is carried out on the Si substrate after the first etching by using a second solution, the thickness of the second etching is 30% of the thickness of the Si substrate, the etching rate of the second solution on the Si substrate is 10 mu m/min-15 mu m/min, then the third etching is carried out on the Si substrate after the second etching by using a third solution, the thickness of the third etching is 10% of the thickness of the Si substrate, and the etching rate of the third solution on the Si substrate is 1 mu m/min-3 mu m/min.
9. The method according to any one of claims 4 to 8, wherein in the step S1, an AlN buffer layer, an N-type GaN layer, an active light emitting layer, and a P-type GaN layer are sequentially deposited on the Si substrate to form an epitaxial layer.
10. The LED lamp panel is characterized by comprising a PCB and a plurality of fluorescent powder dams arranged on the PCB, wherein a P-type bonding pad, an N-type bonding pad and the vertical light emitting diode according to any one of claims 1-3 are arranged in the fluorescent powder dams, the vertical light emitting diode is arranged on the P-type bonding pad through conductive adhesive, a conductive metal layer in the vertical light emitting diode is connected with the N-type bonding pad through an Au wire, fluorescent powder is filled in the fluorescent powder dams, and transparent adhesive is arranged on the surfaces of the fluorescent powder and the PCB.
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