CN116935911A - One-time programmable memory based on MRAM - Google Patents

One-time programmable memory based on MRAM Download PDF

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Publication number
CN116935911A
CN116935911A CN202210332881.1A CN202210332881A CN116935911A CN 116935911 A CN116935911 A CN 116935911A CN 202210332881 A CN202210332881 A CN 202210332881A CN 116935911 A CN116935911 A CN 116935911A
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metal
mram
memory
equivalent resistance
magnetic tunnel
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王跃锦
何世坤
于志猛
郑泽杰
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Hikstor Technology Co Ltd
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Hikstor Technology Co Ltd
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Priority to CN202210332881.1A priority Critical patent/CN116935911A/en
Publication of CN116935911A publication Critical patent/CN116935911A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The application discloses an MRAM-based one-time programmable memory, which relates to the field of semiconductor manufacturing, and comprises a memory cell, a reference cell and a comparison circuit, wherein the memory cell comprises a first magnetic tunnel junction, and the equivalent resistance of a first metal column in the memory cell is far smaller than that when the first magnetic tunnel junction is in a parallel state, so that the equivalent resistance of the memory cell is mainly determined by the state of the first magnetic tunnel junction.

Description

One-time programmable memory based on MRAM
Technical Field
The present application relates to the field of semiconductor manufacturing, and in particular, to an MRAM-based one-time programmable memory.
Background
One-time programmable memory is a non-volatile memory that is allowed to be programmed only once and cannot be modified once it has been programmed, and thus is often used to store data that is reliable and needs to be read repeatedly, including configuration information of a memory chip, such as trim information, a failure address, a device ID, a manufacturing ID, and the like. The one-time programmable memory comprises a memory unit and a reference unit, wherein the equivalent resistance of the memory unit corresponding to the stored data is different from the equivalent resistance of the memory unit corresponding to the stored data is 1 when the stored data is 0; and judging whether the data stored in the one-time programmable memory is 0 or 1 based on the equivalent resistance of the memory cell and the equivalent resistance of the reference cell when the data is read.
MRAM (Magnetic Random Access Memor, magnetic random access memory) is a non-volatile magnetic spin random access memory that uses the magnetoresistive effect of a magnetic tunnel junction to store and read data. The equivalent resistances of the magnetic tunnel junction in the short circuit state, the parallel state and the antiparallel state are different from each other, so that the equivalent resistance of the magnetic tunnel junction is changed by changing the state of the magnetic tunnel junction when data is stored, and then the data information stored in the MRAM is read based on the equivalent resistance of the magnetic tunnel junction and a preset reading resistance.
The one-time programmable memory and the MRAM are all very commonly used memories, but because the production processes of the two are different, the one-time programmable memory and the MRAM are required to be respectively produced through different production lines, so that the production cost is high, and the production process is complex.
Disclosure of Invention
The application aims to provide an MRAM-based one-time programmable memory, which can utilize the same production process to produce the MRAM and the MRAM-based one-time programmable memory, thereby reducing the production cost and simplifying the production process.
In order to solve the technical problems, the application provides an MRAM-based one-time programmable memory, which comprises a memory cell, a reference cell and a comparison circuit, wherein the memory cell comprises a first top metal line, a first bottom metal line, N first top through holes, N first bottom through holes and N memory subunits, and N is a positive integer;
the memory subunit includes a first metal pillar and a first magnetic tunnel junction;
the first ends of the N first metal posts are respectively connected with the first ends of the N magnetic tunnel junctions in a one-to-one correspondence manner, the second ends of the N first metal posts are respectively connected with the first ends of the N first bottom through holes, the second ends of the N magnetic tunnel junctions are respectively connected with the first ends of the N first top through holes, the second ends of the N first bottom through holes are respectively connected with the first bottom metal wires, and the second ends of the N first top through holes are respectively connected with the first top metal wires;
the first input end of the comparison circuit is connected with the storage unit, and the second input end of the comparison circuit is connected with the reference unit and is used for outputting high level or low level based on the equivalent resistance of the storage unit and the equivalent resistance of the reference unit.
Preferably, the equivalent resistance of the first metal pillar is much smaller than the equivalent resistance of the first magnetic tunnel junction in the parallel state.
Preferably, the memory subunit further includes a first bottom electrode disposed between the first metal pillar and the first bottom via.
Preferably, the material of the first metal pillar is tungsten or titanium or tantalum.
Preferably, the reference unit includes a second top metal line, a second top via, a second bottom metal line, a connection layer, a second bottom via, and M second metal columns, where the equivalent resistance of the second metal columns is far greater than that of the connection layer, and M is a positive integer not less than 2;
the connecting layer is used for connecting M second metal columns in series, the first ends of the M second metal columns after being connected in series are connected with the second top through holes, the second ends of the M second metal columns after being connected in series are connected with the second bottom through holes, the second bottom through holes are connected with the second bottom metal wires, and the second top through holes are connected with the second top metal wires.
Preferably, a second bottom electrode is further included;
the second bottom electrode is arranged between the second ends of the M second metal columns connected in series and the second bottom through holes.
Preferably, the connection layer is a second magnetic tunnel junction and/or a metallic connection layer.
Preferably, the second metal pillar is made of tungsten or titanium or tantalum.
Preferably, the circuit further comprises a gating circuit and a reading circuit;
the reading circuit is used for reading the level output by the comparison circuit connected with the storage unit selected by the gating circuit.
Preferably, the equivalent resistance of the reference cell is one half of the sum of the equivalent resistance of each magnetic tunnel junction in the memory cell in the short-circuited state and the equivalent resistance of each magnetic tunnel junction in the parallel state.
The application provides an MRAM-based one-time programmable memory, which comprises a memory cell, a reference cell and a comparison circuit, wherein the memory cell comprises a first magnetic tunnel junction, and the equivalent resistance of a first metal column in the memory cell is far smaller than that when the first magnetic tunnel junction is in a parallel state, so that the equivalent resistance of the memory cell is mainly determined by the state of the first magnetic tunnel junction.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of an MRAM-based one-time programmable memory according to the present application;
FIG. 2 is a schematic diagram of a reference cell in an MRAM-based one-time programmable memory according to the present application;
FIG. 3 is a schematic diagram of a reference cell in another MRAM-based one-time programmable memory according to the present application;
FIG. 4 is a schematic diagram of a reference cell in another MRAM-based one-time programmable memory according to the present application;
FIG. 5 is a schematic diagram of a reference cell in another MRAM-based one-time programmable memory according to the present application;
FIG. 6 is a schematic diagram of a reference cell in another MRAM-based one-time programmable memory according to the present application;
FIG. 7 is a graph showing the equivalent resistance of a reference cell in an MRAM-based one-time programmable memory according to the present application.
Detailed Description
The core of the application is to provide an MRAM-based one-time programmable memory, which can utilize the same production process to produce the MRAM and the MRAM-based one-time programmable memory, thereby reducing the production cost and simplifying the production process.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an MRAM-based otp memory according to the present application, the MRAM-based otp memory includes a memory cell 01, a reference cell 02 and a comparison circuit 03, the memory cell 01 includes a first top metal line 11, a first bottom metal line 12, N first top vias 13, N first bottom vias 14 and N memory sub-cells, N is a positive integer;
the memory subunit comprises a first metal pillar 15 and a first magnetic tunnel junction 16;
the first ends of the N first metal columns 15 are respectively connected with the first ends of the N magnetic tunnel junctions in a one-to-one correspondence manner, the second ends of the N first metal columns 15 are respectively connected with the first ends of the N first bottom through holes 14, the second ends of the N magnetic tunnel junctions are respectively connected with the first ends of the N first top through holes 13, the second ends of the N first bottom through holes 14 are respectively connected with the first bottom metal wires 12, and the second ends of the N first top through holes 13 are respectively connected with the first top metal wires 11;
the first input terminal of the comparison circuit 03 is connected to the memory cell 01, and the second input terminal is connected to the reference cell 02, and outputs a high level or a low level based on the equivalent resistance of the memory cell 01 and the equivalent resistance of the reference cell 02.
Both OTP memory and MRAM are currently in common use, and in standard logic CMOS processes, OTP memory has three types of memory elements: floating gate transistors, fuses, and antifuses. Such as: polysilicon fuses (poly fuses) are typically programmed in a bit-by-bit order, with slower programming speed, high current, high power consumption, large select transistors and programming circuit area for driving the high current, and further cell size expansion due to the high temperature during programming, which also requires isolation regions around the fuses. However, because the principles of the one-time programmable memories and the MRAM for storing data are different, the internal structures of the two are different, and the production processes are different, the memory manufacturers need to produce the one-time programmable memories and the MRAM respectively through different production lines, so that the production cost is relatively high and the production cost is relatively complex.
To solve the above technical problem, the present application uses the magnetic tunnel junction as a part of the memory cell 01 in the MRAM based otp memory based on the principle that the equivalent resistances of the magnetic tunnel junction in the short-circuit state, the parallel state, and the antiparallel state are different from each other.
Specifically, the MRAM-based otp memory of the present application includes a memory cell 01, a reference cell 02, and a comparison circuit 03, where the comparison circuit 03 outputs a high level or a low level based on an equivalent resistance of the memory cell 01 and an equivalent resistance of the reference cell 02. The equivalent resistance of the memory cell 01 is different when the stored data is different, but the equivalent resistance of the reference cell 02 is not changed according to the stored data. The memory cell 01 achieves the purpose of different equivalent resistances when the stored data are different based on the magnetoresistive effect of the first magnetic tunnel junction 16. For example, when the MRAM-based otp memory stores "0" into the memory cell 01, the first magnetic tunnel junction 16 in the memory cell 01 is controlled to be in a short-circuited state, and when the "1" is stored in the memory cell 01, the first magnetic tunnel junction 16 in the memory cell 01 needs to be controlled to be in a parallel state, and in any case, the states of the first magnetic tunnel junction 16 in the memory cell 01 are different when the memory cell 01 stores different logic states. When reading the data accessed in the memory cell 01, the comparison circuit 03 outputs a high level or a low level based on the equivalent resistance of the memory cell 01 and the equivalent resistance of the reference cell 02. The output of the comparison circuit 03 represents the magnitude relation between the equivalent resistance of the memory cell 01 and the equivalent resistance of the reference cell 02, for example, the comparison circuit 03 outputs a low level when the equivalent resistance of the memory cell 01 is smaller than the equivalent resistance of the reference cell 02.
For example, the equivalent resistance of the reference cell 02 is between the equivalent resistance when the memory cell 01 is in the short-circuited state and the equivalent resistance when the memory cell 01 is in the parallel state; when the logic state '0' is stored, the memory cell 01 enters a short circuit state by applying breakdown voltage, and the memory cell 01 is controlled to enter a parallel state when the logic state '1' is stored; the comparison circuit 03 outputs a low level when the equivalent resistance of the memory cell 01 is smaller than that of the reference cell 02, and otherwise outputs a high level. When the data stored in the memory cell 01 in the otp memory cell is read, for example, the output level of the comparison circuit 03 is read, for example, the comparison circuit 03 outputs a low level, it can be determined that the equivalent resistance of the memory cell 01 is smaller than the equivalent resistance of the reference cell 02 at this time, that is, the memory cell 01 is in a short-circuit state and the corresponding logic state of the memory cell 01 is "0". The comparison circuit may be a comparator, which is not particularly limited in the present application.
Specifically, referring to fig. 1, fig. 1 is a schematic structural diagram of an MRAM-based otp memory according to the present application, IN1 is an equivalent resistance of a memory cell 01, IN2 is an equivalent resistance of a reference cell 02, and IOUT is an output level of a comparison circuit 03. The memory cell 01 comprises a first top metal line 11, a first bottom metal line 12, N first top vias 13, N first bottom vias 14, and N memory sub-cells, wherein the memory sub-cells comprise a first metal pillar 15 and a first magnetic tunnel junction 16.
The memory sub-unit is connected to the first top metal line 11 through the first top via 13, to the first bottom metal line 12 through the first bottom via 14, and finally to the first input of the comparison circuit 03 through the first top metal line 11 and the first bottom metal line 12 for comparing the output level of the circuit 03.
In summary, the present application provides an MRAM-based one-time programmable memory, which includes a memory cell 01, a reference cell 02 and a comparison circuit 03, wherein the memory cell 01 includes a first magnetic tunnel junction 16, and the equivalent resistance of the first metal pillar 15 in the memory cell 01 is far smaller than that when the first magnetic tunnel junction 16 is in a parallel state, so that the equivalent resistance of the memory cell 01 is mainly determined by the state of the first magnetic tunnel junction 16.
Based on the above embodiments:
as a preferred embodiment, the equivalent resistance of the first metal pillar is much smaller than when the first magnetic tunnel junction is in the parallel state.
Considering that in some extreme cases, if the equivalent resistance of the first metal pillar 15 is too large or even close to the equivalent resistance of the first magnetic tunnel junction 16 in the parallel state, even if the first magnetic tunnel junction 16 in the memory cell 01 is in the short-circuited state, the equivalent resistance of the memory cell 01 is disturbed by the equivalent resistance of the first metal pillar 15, which results in the output of the comparison circuit 03 being abnormal and thus in the one-time programmable memory cell being abnormal, it is required that the equivalent resistance of the first metal pillar 15 is much smaller than the equivalent resistance when the first magnetic tunnel junction 16 is in the parallel state in order to avoid the above-mentioned problems.
In summary, in the present embodiment, the equivalent resistance of the first metal pillar 15 is far smaller than that of the parallel state of the first magnetic tunnel junction 16, so that the reliability of the MRAM-based otp memory is further ensured.
As a preferred embodiment, the memory subunit further comprises a first bottom electrode 17 arranged between the first metal pillar 15 and the first bottom via 14.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an MRAM-based otp memory according to the present application, in this embodiment, a first bottom electrode 17 is further disposed between a first metal pillar 15 and a first bottom via 14, so as to block diffusion between the first metal pillar 15 and the first bottom via 14, thereby ensuring the memory performance of the MRAM-based otp memory.
As a preferred embodiment, the first metal pillar 15 is made of tungsten or titanium or tantalum.
In this embodiment, considering that the characteristics of tungsten, titanium and tantalum are different, for example, tungsten has stable chemical properties, titanium has high strength, tantalum has high melting point, high density and acid resistance, so the material of the first metal pillar 15 can be selected according to practical application requirements, which is not particularly limited in the present application.
As a preferred embodiment, the reference cell 02 includes a second top metal line 21, a second top via 22, a second bottom metal line 23, a connection layer 25, a second bottom via 24, and M second metal pillars 26, where the equivalent resistance of the second metal pillars 26 is much greater than that of the connection layer 25, and M is a positive integer not less than 2;
the connection layer 25 is used for connecting M second metal pillars 26 in series, a first end of the M second metal pillars 26 connected in series is connected to the second top via 22, a second end of the M second metal pillars 26 connected in series is connected to the second bottom via 24, the second bottom via 24 is connected to the second bottom metal line 23, and the second top via 22 is connected to the second top metal line 21.
In this embodiment, since the equivalent resistance of the reference cell 02 does not need to be changed according to the logic state, a material with stable resistance can be used as a part of the reference cell 02. Specifically, after the M second metal pillars 26 are connected in series through the connection layer 25, one end is connected to the second top via 22, the other end is connected to the second bottom via 24, then the second top via 22 is connected to the second top metal line 21, and the second bottom via 24 is connected to the second bottom metal line 23 so as to be connected to the comparison circuit 03, so that the purpose of providing a stable reference resistance for the reference cell 02 is achieved through the above parts together.
The equivalent resistance of the reference cell 02 may be a value between the equivalent resistance when the memory cell 01 is in the short-circuited state and the equivalent resistance when the memory cell 01 is in the parallel state, and the present application is not limited thereto.
As a preferred embodiment, a second bottom electrode 27 is also included;
the second bottom electrode 27 is disposed between the second ends of the M second metal posts 26 connected in series and the second bottom via 24.
In this embodiment, a second bottom electrode 27 is further disposed between the second metal pillar 26 and the second bottom via 24, so as to block diffusion between the second metal pillar 26 and the second bottom via 24, thereby ensuring the storage performance of the otp memory cell and the otp memory.
As a preferred embodiment, the connection layer 25 is a second magnetic tunnel junction and/or a metallic connection layer.
In this embodiment, the connection layer 25 of the M second metal pillars 26 connected in series may be a second magnetic tunnel junction, or a metal connection layer, or a combination of the second magnetic tunnel junction and the metal connection layer, which is not particularly limited in the present application.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a reference cell in an MRAM-based otp memory according to the present application, in which a connection layer 25 is formed by a second magnetic tunnel junction and a metal connection layer, the reference cell 02 is produced by using the same material as that required for producing the memory cell 01, the upper connection layer 25 in fig. 2 is the second magnetic tunnel junction, the lower connection layer 25 in fig. 2 is a second bottom electrode 27, a second bottom via 24 and a second bottom metal line 23, and all of the materials are metal materials, and M second metal pillars 26 are connected in series through the connection layer 25.
Referring to fig. 3, fig. 3 is a schematic diagram of a reference cell structure in another MRAM-based otp memory according to the present application, in which the upper connection layer 25 in fig. 3 is a top electrode, and the lower connection layer 25 in fig. 3 is a metal connection layer made of the same material as the second bottom electrode 27, the second bottom via 24 and the second bottom metal line 23.
Referring to fig. 4, fig. 4 is a schematic structural diagram of a reference cell in another MRAM-based otp memory according to the present application, the connection layer 25 is formed by a second magnetic tunnel junction and a metal connection layer, the material of the connection layer 25 above in fig. 4 is the same as that of the second top metal line 21, the second top via 22 and the second magnetic tunnel junction, and the material of the connection layer 25 below in fig. 4 is the same as that of the second bottom electrode 27, the second bottom via 24 and the second bottom metal line 23.
Referring to fig. 5, fig. 5 is a schematic structural diagram of a reference cell in another MRAM-based otp memory according to the present application, the connection layer 25 is a metal connection layer, the material of the connection layer 25 above in fig. 5 is the same as the material of the second top metal line 21 and the second top via 22, and the material of the connection layer 25 below in fig. 5 is the same as the material of the second bottom electrode 27, the second bottom via 24 and the second bottom metal line 23.
Referring to fig. 6, fig. 6 is a schematic structural diagram of a reference cell in another MRAM-based otp memory according to the present application, the connection layer 25 is a metal connection layer, the material of the upper connection layer 25 in fig. 6 is the same as that of the top electrode, the second top metal line 21 and the second top via 22, and the material of the lower connection layer 25 in fig. 6 is the same as that of the second bottom electrode 27, the second bottom via 24 and the second bottom metal line 23.
In summary, the reference cell 02 may be manufactured based on the same material as the memory cell 01 in a variety of ways, and may be selected according to the actual manufacturing situation, which is not particularly limited in the present application. The reference cell 02 is finally connected to a second input of the comparison circuit 03 via a second top metal line 21 and a second bottom metal line 23.
As a preferred embodiment, the second metal pillar 26 is made of tungsten or titanium or tantalum.
In this embodiment, considering that the characteristics of tungsten, titanium and tantalum are different, for example, tungsten has stable chemical properties, titanium has high strength, tantalum has high melting point, high density and acid resistance, so the material of the first metal pillar 15 can be selected according to practical application requirements, which is not particularly limited in the present application.
As a preferred embodiment, the device further comprises a gating circuit and a reading circuit;
the reading circuit is used for reading the level output by the one-time programmable memory cell selected by the gating circuit.
The reading circuit is used for reading the level of the output of the comparison circuit connected with the memory cell selected by the gating circuit.
In order to accurately read data stored in memory cells in an MRAM-based one-time programmable memory, a gating circuit is provided in the present application for selecting a target memory cell, and then a reading circuit reads the level output from a comparison circuit 03 connected to the memory cell selected by the gating circuit.
As a preferred embodiment, the equivalent resistance of the reference cell 02 is one half of the sum of the equivalent resistance of each magnetic tunnel junction in the memory cell 01 in the shorted state and the equivalent resistance of each magnetic tunnel junction in the parallel state.
The selection of the reference cell 02 with the appropriate equivalent resistance has a great influence on the accurate reading of the information stored in the MRAM-based otp memory, please refer to fig. 7, fig. 7 is a graph of the equivalent resistance of the reference cell in the MRAM-based otp memory provided by the present application, the ideal equivalent resistance of the reference cell 02 in the otp memory is (rshort+rp)/2, where Rshort is the equivalent resistance when each magnetic tunnel junction in the memory cell 01 is in a short-circuited state, rp is the equivalent resistance when each magnetic tunnel junction is in a parallel state, rap is the equivalent resistance when each magnetic tunnel junction is in an antiparallel state, and Rref is the equivalent resistance of the reference cell 02. Further, referring to fig. 7, it can be found that the equivalent resistance of the reference cell 02 actually produced also fluctuates to some extent, as long as the fluctuation in the resistance value of the equivalent resistance is controlled within a certain range.
In addition, in practical cases, the equivalent resistance of the magnetic tunnel junction in a short-circuited state after breakdown is very small, so that the equivalent resistance of the reference cell 02 can also be set to Rp/2.
It should be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The one-time programmable memory based on the MRAM is characterized by comprising a memory cell, a reference cell and a comparison circuit, wherein the memory cell comprises a first top metal line, a first bottom metal line, N first top through holes, N first bottom through holes and N memory subunits, and N is a positive integer;
the memory subunit includes a first metal pillar and a first magnetic tunnel junction;
the first ends of the N first metal posts are respectively connected with the first ends of the N magnetic tunnel junctions in a one-to-one correspondence manner, the second ends of the N first metal posts are respectively connected with the first ends of the N first bottom through holes, the second ends of the N magnetic tunnel junctions are respectively connected with the first ends of the N first top through holes, the second ends of the N first bottom through holes are respectively connected with the first bottom metal wires, and the second ends of the N first top through holes are respectively connected with the first top metal wires;
the first input end of the comparison circuit is connected with the storage unit, and the second input end of the comparison circuit is connected with the reference unit.
2. The MRAM-based one-time programmable memory of claim 1, wherein an equivalent resistance of the first metal pillar is substantially less than an equivalent resistance of the first magnetic tunnel junction in a parallel state.
3. The MRAM-based one-time programmable memory of claim 2, wherein the memory subunit further comprises a first bottom electrode disposed between the first metal pillar and the first bottom via.
4. The MRAM-based one-time programmable memory of claim 2, wherein the first metal pillar is tungsten or titanium or tantalum.
5. The MRAM-based one-time programmable memory of claim 1, wherein the reference cell comprises a second top metal line, a second top via, a second bottom metal line, a connection layer, a second bottom via, and M second metal pillars, and an equivalent resistance of the second metal pillars is much greater than an equivalent resistance of the connection layer, M is a positive integer not less than 2;
the connecting layer is used for connecting M second metal columns in series, the first ends of the M second metal columns after being connected in series are connected with the second top through holes, the second ends of the M second metal columns after being connected in series are connected with the second bottom through holes, the second bottom through holes are connected with the second bottom metal wires, and the second top through holes are connected with the second top metal wires.
6. The MRAM-based one-time programmable memory of claim 5, further comprising a second bottom electrode;
the second bottom electrode is arranged between the second ends of the M second metal columns connected in series and the second bottom through holes.
7. The MRAM-based one-time programmable memory of claim 5, wherein the connection layer is a second magnetic tunnel junction and/or a metal connection layer.
8. The MRAM-based one-time programmable memory of claim 5, wherein the second metal pillar is tungsten or titanium or tantalum.
9. The MRAM-based one-time programmable memory of claim 1, further comprising a gating circuit and a reading circuit;
the reading circuit is used for reading the level output by the comparison circuit connected with the storage unit selected by the gating circuit.
10. The MRAM-based one-time programmable memory of any of claims 1 to 9, wherein an equivalent resistance of the reference cell is a sum of an equivalent resistance when each of the magnetic tunnel junctions in the memory cell is in a shorted state and an equivalent resistance when each of the magnetic tunnel junctions is in a parallel state.
CN202210332881.1A 2022-03-31 2022-03-31 One-time programmable memory based on MRAM Pending CN116935911A (en)

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CN116935911A true CN116935911A (en) 2023-10-24

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