CN112103306B - Three-dimensional phase change memory and control method thereof - Google Patents
Three-dimensional phase change memory and control method thereof Download PDFInfo
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- CN112103306B CN112103306B CN202011258822.1A CN202011258822A CN112103306B CN 112103306 B CN112103306 B CN 112103306B CN 202011258822 A CN202011258822 A CN 202011258822A CN 112103306 B CN112103306 B CN 112103306B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- G—PHYSICS
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- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
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Abstract
The embodiment of the application discloses a three-dimensional phase change memory and a control method thereof, wherein the three-dimensional phase change memory comprises: a phase change memory array region including a fuse sub-region and a memory sub-region adjacent to each other; the fuse sub-region is provided with a first phase change memory array; the first phase change memory array includes a first phase change memory cell storing fuse data that cannot be changed by a subsequent write operation; the memory sub-region is provided with a second phase change memory array, and phase change memory cells in the second phase change memory array are used for storing memory data which can be changed by a subsequent writing operation.
Description
Technical Field
The embodiment of the application relates to the field of semiconductor manufacturing, in particular to a three-dimensional phase change memory and a control method thereof.
Background
A conventional fuse is formed of polysilicon, and functions as a fuse by applying a control pulse to the polysilicon fuse to cut a fuse wire of the polysilicon fuse. Because the melting temperature of polysilicon is high, a polysilicon fuse requires a high control pulse, and the size of a switching device corresponding to the polysilicon fuse also needs to be relatively large. Larger fuses may consume excessive power and occupy excessive area.
Disclosure of Invention
In view of the above, embodiments of the present application provide a three-dimensional phase change memory and a control method thereof to solve at least one problem in the prior art.
In order to achieve the above purpose, the technical solution of the embodiment of the present application is implemented as follows:
in a first aspect, an embodiment of the present application provides a three-dimensional phase change memory, including:
a phase change memory array region including a fuse sub-region and a memory sub-region adjacent to each other;
the fuse sub-region is provided with a first phase change memory array; the first phase change memory array includes a first phase change memory cell storing fuse data that cannot be changed by a subsequent write operation;
the memory sub-region is provided with a second phase change memory array, and phase change memory cells in the second phase change memory array are used for storing memory data which can be changed by a subsequent writing operation.
In an alternative embodiment, the phase change memory cells in the first phase change memory cell and the second phase change memory cell are identical in structure.
In an alternative embodiment, the phase change material of the phase change memory cells in the first phase change memory array is the same as the phase change material of the phase change memory cells in the second phase change memory array;
wherein the phase change material is a chalcogenide compound.
In an alternative embodiment, the first phase change memory array further includes a second phase change memory cell independent of the first phase change memory cell;
the fusing data comprises a first address and a first control pulse configuration, the first address is used for indicating the position of the second phase change memory unit, and the first control pulse configuration is used for representing a first control pulse for enabling the second phase change memory unit to be fused.
In an alternative embodiment, the fuse data further includes a second address and a second control pulse configuration, the second address data is used for indicating the position of the second phase change memory array, and the second control pulse configuration is used for representing a second control pulse for enabling the phase change memory cells in the second phase change memory array to generate crystalline state transition;
wherein the amplitude of the first control pulse is greater than the amplitude of the second control pulse.
In an alternative embodiment, the second phase change memory cell is capable of an irreversible state transition under the influence of the first control pulse.
In an alternative embodiment, the states of the second phase change memory cell include a blown reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state.
In an alternative embodiment, the phase change memory cells in the second phase change memory array are capable of reversible state transitions under the influence of the second control pulse.
In an alternative embodiment, the states of the phase change memory cells in the second phase change memory array include an amorphous reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state.
In an alternative embodiment, the fuse data includes repair data and trim data.
In a second aspect, an embodiment of the present application provides a control method of a three-dimensional phase change memory, where the three-dimensional phase change memory includes a phase change memory array region, where the phase change memory array region includes a fuse sub-region and a memory sub-region that are adjacent to each other; the method comprises the following steps:
determining a first phase change memory array selected to be located in the fuse sub-region;
storing, by a first control pulse, blown data that cannot be changed by a subsequent write operation in the first phase change memory array;
wherein the first control pulse is larger than a second control pulse for storing memory data that can be changed by a subsequent write operation in a second phase change memory array located in the memory sub-region.
In an alternative embodiment, the phase change memory cells in the first phase change memory array and the phase change memory cells in the second phase change memory array have the same structure.
In an alternative embodiment, the phase change material of the phase change memory cells in the first phase change memory array is the same as the phase change material of the phase change memory cells in the second phase change memory array;
wherein the phase change material is a chalcogenide compound.
In an alternative embodiment, the storing, by the first control pulse, the fuse data that cannot be changed by a subsequent write operation in the first phase change memory array includes:
and controlling the phase change memory cells of the first phase change memory array to irreversibly change from the low resistance state to the high resistance state through the first control pulse so as to store the fusing data which cannot be changed by a subsequent writing operation in the phase change memory cells of the first phase change memory array.
In an alternative embodiment, the high resistance state corresponds to a blown reset state of a phase change memory cell of the first phase change memory array;
the low resistance state corresponds to a crystalline setting state of the phase change memory cells of the first phase change memory array.
In an optional embodiment, the method further comprises:
determining a second control pulse of the second phase change memory array according to the fusing data stored in the first phase change memory array;
storing storage data, which can be changed by a subsequent write operation, in the second phase change memory array by a second control pulse.
In an alternative embodiment, the storing the storage data that can be changed by the subsequent write operation in the second phase change memory array by the second control pulse includes:
and controlling the phase change memory cells of the second phase change memory array to reversibly change from the low resistance state to the high resistance state by the second control pulse so as to store the memory data which can be changed by a subsequent write operation in the phase change memory cells of the second phase change memory array.
In an alternative embodiment, the high resistive state corresponds to an amorphous reset state of a phase change memory cell of the second phase change memory array;
the low resistance state corresponds to a crystalline set state of the phase change memory cells of the second phase change memory array.
In an alternative embodiment, the fuse data includes trim data and repair data.
In an alternative embodiment, the phase change memory array includes a first phase change memory cell and a second phase change memory cell independent of each other;
the storing, by a first control pulse, the blown data that cannot be changed by a subsequent write operation in the first phase change memory array includes:
storing the fuse data in the first phase change memory cell by the first control pulse;
determining a first control pulse of the second phase change memory cell according to the fusing data stored in the first phase change memory cell;
storing repair data in the second phase change memory cell by the first control pulse.
The embodiment of the application discloses a three-dimensional phase change memory and a control method thereof, wherein the three-dimensional phase change memory comprises: a phase change memory array region including a fuse sub-region and a memory sub-region adjacent to each other; the fuse sub-region is provided with a first phase change memory array; the first phase change memory array includes a first phase change memory cell storing fuse data that cannot be changed by a subsequent write operation; the memory sub-region is provided with a second phase change memory array, and phase change memory cells in the second phase change memory array are used for storing memory data which can be changed by a subsequent writing operation. In the embodiment of the application, the fuse data is stored by using the phase change memory cell in the phase change memory array, and the melting temperature of the phase change material is relatively low, so that the fuse data is stored by using the phase change memory cell only by using a small control pulse.
Drawings
FIG. 1 is a schematic diagram of a structure of an integrated circuit device including a polysilicon fuse;
fig. 2 is a schematic structural diagram of a three-dimensional phase change memory according to an embodiment of the present disclosure;
fig. 3 is a schematic flow chart illustrating an implementation of a control method of a three-dimensional phase change memory according to an embodiment of the present disclosure;
FIG. 4a is a schematic structural diagram illustrating an unblown phase change memory cell according to an embodiment of the present invention;
FIG. 4b is a schematic structural diagram of a phase change memory cell according to an embodiment of the present disclosure after being fused;
FIG. 5a is an electron microscope view of an unblown phase change memory cell according to an embodiment of the present disclosure;
fig. 5b is an electron microscope image of the phase change memory cell provided in the embodiment of the present application after being fused.
Detailed Description
Exemplary embodiments disclosed in the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application; that is, not all features of an actual embodiment are described herein, and well-known functions and structures are not described in detail.
In the drawings, the size of layers, regions, elements, and relative sizes may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "adjacent to … …," "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on … …," "directly adjacent to … …," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. And the discussion of a second element, component, region, layer or section does not imply that a first element, component, region, layer or section is necessarily present in the application.
Spatial relationship terms such as "under … …", "under … …", "below", "under … …", "above … …", "above", and the like, may be used herein for ease of description to describe the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below … …" and "below … …" can encompass both an orientation of up and down. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings.
Fig. 1 is a schematic structural diagram of an integrated circuit device including a polysilicon fuse, and as shown in fig. 1, the polysilicon fuse 110 in the integrated circuit device is disposed independently of a memory array 120, and the polysilicon fuse 110 requires a higher driving current and needs to be designed with a larger device size due to the higher melting point of polysilicon. Thus, miniaturization and power consumption of the integrated circuit device are not facilitated.
Therefore, the following technical scheme of the embodiment of the application is provided.
Fig. 2 is a schematic structural diagram of a three-dimensional phase change memory provided in an embodiment of the present application, and it should be noted that fig. 2 illustrates, by taking a first phase change memory array as an example, a phase change memory array, as shown in fig. 2, the three-dimensional phase change memory includes: a phase change memory array region 200 including a fuse sub region and a memory sub region adjacent to each other; the fuse sub-region is provided with a first phase change memory array 210; the first phase change memory array 210 includes first phase change memory cells storing fuse data that cannot be changed by a subsequent write operation; the memory sub-region is provided with a second phase change memory array 220, and the phase change memory cells in the second phase change memory array 220 are used for storing memory data which can be changed by a subsequent writing operation.
In the embodiment of the present application, the first phase change memory array 210 and the second phase change memory array 220 are both phase change memory arrays located in the phase change memory array region 200. The structure of the phase change memory cells in the first phase change memory array 210 is the same as the structure of the phase change memory cells in the second phase change memory array 220. The phase change memory cells in the first phase change memory array 210 and the phase change memory cells in the second phase change memory array 220 each include a stacked phase change memory layer, a selector layer, and a plurality of electrode layers, respectively. The phase change material of the phase change memory cells in the first phase change memory array 210 is the same as the phase change material of the phase change memory cells in the second phase change memory array 220; wherein the phase change material is a chalcogenide compound. In other words, the first phase change memory array 210 and the second phase change memory array 220 are identical phase change memory arrays, so that in the process of forming the three-dimensional phase change memory, the manufacturing process of the fuse is not required to be additionally introduced, and the manufacturing of the memory array and the fuse array can be completed at the same time only by the manufacturing process of the phase change memory array. In addition, since the first phase change memory array 210 and the second phase change memory array 220 have the same structure, the fuse data is stored by using the phase change memory cell in the embodiment of the present application, and thus, it is not necessary to provide other fuses for storing the fuse data, and therefore, the size of the three-dimensional phase change memory can be reduced to a certain extent, and the manufacturing process is simplified.
In an embodiment of the application, the fuse data includes repair data and trimming data. The trim data is information required for performing three-dimensional phase change memory operations (e.g., program operation, erase operation, and read operation). For example, the trim data may include parameters such as a programming pulse configuration (e.g., voltage and/or current pulses), an erase pulse configuration (e.g., voltage and/or current pulses), a read pulse configuration (e.g., voltage and/or current pulses), a programming pulse width, an erase pulse width, a read pulse width, a number of programming pulses in a programming operation, a number of read pulses in a reading operation, and/or an allowable programming operation rate of the three-dimensional phase change memory. Different defective phase change memory cells may exist in the memory due to manufacturing process variations or user-specific operations. To accommodate the defect, the three-dimensional phase change memory may identify the defective phase change memory cell (e.g., during a test operation). And after identifying any defective phase change memory cells, the address corresponding to the defective phase change memory cells may be determined. If a read/write request is received, the address may be saved and used to indicate that the corresponding phase change memory cell is defective. The saved addresses of defective phase change memory cells are referred to as repair data.
In some embodiments, to compensate for physical differences in different three-dimensional phase change memories of the same design, information needed to perform three-dimensional phase change memory operations, which may also be referred to as trim data, may be adjusted based on internal characteristics of the different three-dimensional phase change memories, such as adjusting output voltages/currents of drivers within the three-dimensional phase change memories to increase or decrease magnitudes of voltages/currents applied to phase change memory cells within the three-dimensional phase change memories. Then these trim data may also be stored in the first phase change memory cell at this time.
In the embodiment of the present application, a portion of the first phase change memory array 210 stores trim data, and another portion of the first phase change memory array 210 stores repair data. It should be noted that, in the embodiment of the present application, the first phase change memory array 210 may be one phase change memory array, or may be multiple phase change memory arrays.
In the embodiment of the present application, the first phase change memory array 210 further includes a second phase change memory cell; the fusing data comprises a first address and a first control pulse configuration, the first address is used for indicating the position of the second phase change memory unit, and the first control pulse configuration is used for representing a first control pulse for enabling the second phase change memory unit to be fused. Here, the first control pulse is a program pulse of the second phase change memory cell. The first control pulse is configured to characterize an amplitude and a width of the first control pulse that causes the second phase change memory cell to fuse.
In an embodiment of the application, the second phase change memory cell is capable of performing an irreversible state transition under the influence of the first control pulse. In other words, the second phase change memory cell is irreversibly blown.
In an embodiment of the present application, the states of the second phase change memory cell include a blown reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state. The second phase change memory cell is capable of transitioning from a crystalline set state (low resistance state) to a blown reset state (high resistance state) under the influence of the first control pulse, the state transition being irreversible.
In the embodiment of the present application, the fuse data further includes a second address and a second control pulse configuration, the second address data is used for indicating a position of the second phase change memory array 220, and the second control pulse configuration is used for characterizing a second control pulse for causing a crystalline state transition of the phase change memory cells in the second phase change memory array 220; wherein the amplitude of the first control pulse is greater than the amplitude of the second control pulse. Here, the second control pulse includes a program pulse and an erase pulse of the phase change memory cells in the second phase change memory array 220. The second control pulse is configured to characterize an amplitude and a width of the second control pulse that causes a crystalline state transition to occur in the phase change memory cells in the second phase change memory array 220. In practical application, the width of the first control pulse is larger than that of the second control pulse.
In some embodiments, the first control pulse has an amplitude and width that are both greater than the amplitude and width of the erase pulse for the phase change memory cells in the second phase change memory array 220. In other words, the first control pulse may cause the phase change material to be heated to a temperature above the melting point.
In the embodiment of the present application, the phase change memory cells in the second phase change memory array 220 can perform reversible state transition under the action of the second control pulse.
In the embodiment of the present application, the states of the phase change memory cells in the second phase change memory array 220 include an amorphous reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state. The second phase change memory array 220 is capable of transitioning from a crystalline set state (low resistance state) to an amorphous reset state (high resistance state) under a second control pulse, and the state transition is reversible. In practical applications, the second phase change memory array 220 can be changed from the amorphous reset state to the crystalline set state under the action of the programming pulse, specifically: when the phase change material in the phase change memory cells in the second phase change memory array 220 is heated to a temperature between the crystallization temperature and the melting point of the phase change material by the programming pulse, the phase change material is transformed into a crystalline state; the second phase change memory array 220 can be changed from a crystalline setting state to an amorphous resetting state under the action of an erase pulse, specifically: the phase change material in the phase change memory cells in second phase change memory array 220 is heated to a temperature slightly above the melting point by the erase pulse and immediately quenched again, the phase change material transitions to the amorphous state.
It should be noted that, in the embodiment of the present application, a first control pulse is applied to the first phase change memory array 210, and both the amplitude and the width of the first control pulse are greater than those of the second control pulse, so that the phase change materials in the first phase change memory cell and the second phase change memory cell are melted to generate an irreversible permanent void (void), thereby causing irreversible fusing of the first phase change memory cell and the second phase change memory cell. Thus, this control method enables the first phase change memory array 210 to function as a one-time-programmable fuse (one-time-programmable fuse), so that the first phase change memory array 210 in the embodiment of the present application can be used as a fuse array. The reason why the permanent voids (void) are formed is as follows: the phase-change material is heated to a temperature higher than the melting point under the action of a first control pulse, and after the first control pulse lasts for a certain time, the phase-change material is changed into a molten state, and in the molten state, anions and cations in the phase-change material move towards the positive electrode and the negative electrode respectively, so that the phase-change material is subjected to material loss, and a spatial void (void) is formed in the phase-change memory cell in the process.
In the embodiment of the present application, the fuse data is stored in the first phase change memory array 210, that is, in the embodiment of the present application, the first phase change memory array 210 is used as a fuse array, and the fuse of the fuse array is controlled by a first control pulse larger than a second control pulse, so that the fuse data stored in the first phase change memory array 210 cannot be changed by a subsequent write operation. In addition, since the first phase change memory array 210 is irreversibly fused under the first control pulse, the fused data stored in the first phase change memory array 210 is not affected by the packaging temperature and loses data in the subsequent high-temperature packaging process. When the phase change memory array is used for realizing the fuse function, in order to increase the confidence of the fuse, bit width expansion can be performed on a fuse signal, a single-bit (bit) fuse signal is expanded into a multi-bit (for example, 4bit, 16bit or 32 bit) fuse signal, for example, two or more phase change memory units are used to form a fuse bit unit (fuse bit), and then the confidence is increased through redundancy check, parity check or other modes.
In some embodiments, the fuse data further comprises a third control pulse configuration and a fourth control pulse configuration; wherein the third control pulse is configured to represent a third control pulse for reading the fuse data stored in the second phase change memory cell; the fourth control pulse is configured to represent a fourth control pulse for reading storage data stored in a phase change memory cell in the second phase change memory array 220. In practice, the third control pulse and the fourth control pulse may be the same.
The embodiment of the application discloses a three-dimensional phase change memory, including: a phase change memory array region including a fuse sub-region and a memory sub-region; the first phase change memory array is positioned in the fusing subarea; a second phase change memory array located in the memory sub-region; the first phase change memory array comprises a first phase change memory cell and a second phase change memory cell, wherein the first phase change memory cell stores fusing data which cannot be changed by a subsequent writing operation; the second phase change memory array is for storing memory data that can be changed by a subsequent write operation. In the embodiment of the application, the fuse data is stored by using the phase change memory cell in the phase change memory array, and the melting temperature of the phase change material is relatively low, so that the fuse data is stored by using the phase change memory cell only by using a small control pulse.
Fig. 3 is a schematic view illustrating an implementation flow of a control method of a three-dimensional phase change memory provided in an embodiment of the present application, where the three-dimensional phase change memory includes a phase change memory array region, and the phase change memory array region includes a fuse sub-region and a memory sub-region that are adjacent to each other; the method mainly comprises the following steps:
In an embodiment of the present application, the three-dimensional phase change memory includes a phase change memory array region, the phase change memory array region includes a fuse sub-region and a memory sub-region, and a first phase change memory array located in the fuse sub-region is selected to store fuse data that cannot be changed by a subsequent write operation, i.e., to serve as a fuse. Therefore, when the fusing data needs to be stored in the first phase change memory array, the first phase change memory array in the phase change memory array area needs to be determined. It should be noted that, in the embodiment of the present application, the first phase change memory array may be one phase change memory array, or may be multiple phase change memory arrays.
In the embodiment of the application, the phase change memory cells of the first phase change memory array are controlled to irreversibly convert from the low resistance state to the high resistance state through the first control pulse so as to store the fusing data which cannot be changed by the subsequent writing operation in the phase change memory cells of the first phase change memory array; wherein the first control pulse is greater than a second control pulse of the second phase change memory array. Here, the first control pulse is a program pulse of the first phase change memory array.
In an embodiment of the present application, the states of the phase change memory cells of the first phase change memory array include a blown reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state. The phase change memory cells of the first phase change memory array are irreversibly converted from a crystalline set state (low resistance state) to a blown reset state (high resistance state) by a first control pulse.
Fig. 4a is a schematic structural diagram of a phase change memory cell provided in an embodiment of the present disclosure that is not blown, and fig. 4b is a schematic structural diagram of a phase change memory cell provided in an embodiment of the present disclosure that is blown, and referring to fig. 4a and fig. 4b, after applying a first control pulse to a first phase change memory array in the embodiment of the present disclosure, a phase change material in a phase change memory cell 410 in the first phase change memory array is melted to generate an irreversible permanent void (void), so that the phase change memory cell 410 is blown irreversibly. In this way, this control method enables the first phase change memory array to function as a one-time programmable fuse, so that the first phase change memory array in the embodiment of the present application can be used as a fuse array.
Fig. 5a is an electron microscope image of a phase change memory cell provided in the present embodiment without being fused, and fig. 5b is an electron microscope image of a phase change memory cell provided in the present embodiment after being fused, and with reference to fig. 5a and fig. 5b, after applying a first control pulse to a first phase change memory array in the present embodiment, a phase change material in a phase change memory cell 510 in the first phase change memory array is melted to generate an irreversible permanent void (void), so that the phase change memory cell 510 is irreversibly fused.
In the embodiment of the application, the phase change memory array is used as a fuse to store fusing data, and the fusing of the phase change memory unit of the first phase change memory array is controlled through a first control pulse larger than a second control pulse, so that the fusing data stored in the phase change memory unit of the first phase change memory array cannot be changed by subsequent writing operation. And just because the phase change memory cell of the first phase change memory array can be irreversibly fused under the first control pulse, the fused data stored in the first phase change memory array can not lose data under the influence of the packaging temperature in the subsequent high-temperature packaging process.
In the embodiment of the application, a second control pulse of the second phase change memory array is determined according to the fusing data stored in the first phase change memory array; storing storage data, which can be changed by a subsequent write operation, in the second phase change memory array by a second control pulse. Specifically, the method comprises the following steps: and controlling the phase change memory cells of the second phase change memory array to reversibly change from the low resistance state to the high resistance state by the second control pulse so as to store the memory data which can be changed by a subsequent write operation in the phase change memory cells of the second phase change memory array. The high resistance state corresponds to an amorphous reset state of a phase change memory cell of the second phase change memory array; the low resistance state corresponds to a crystalline set state of the phase change memory cells of the second phase change memory array.
In an embodiment of the present application, the second control pulse of the phase change memory cell in the second phase change memory array includes a program pulse and an erase pulse of the phase change memory cell of the second phase change memory array.
In some embodiments, the first control pulse has an amplitude and a width that are both greater than an amplitude and a width of an erase pulse for a phase change memory cell in the second phase change memory array. In other words, the first control pulse may cause the phase change material to be heated to a temperature above the melting point.
In an embodiment of the application, the fuse data includes trimming data and repair data. The first phase change memory array comprises a first phase change memory cell and a second phase change memory cell which are independent of each other; the storing, by a first control pulse, the blown data that cannot be changed by a subsequent write operation in the first phase change memory array includes: storing the fuse data in the first phase change memory cell by the first control pulse; determining a first control pulse of the second phase change memory cell according to the fusing data stored in the first phase change memory cell; storing repair data in the second phase change memory cell by the first control pulse. In practical application, the first phase change memory cell may be a phase change memory cell used for storing fusing data before leaving a factory, and the second phase change memory cell may be a phase change memory cell used for storing fusing data after leaving the factory. When the second phase change memory cell is needed, the first control pulse of the second phase change memory cell may be determined according to the fuse data stored in the first phase change memory cell, so that the repair data is stored in the second phase change memory cell by the first control pulse.
In an embodiment of the present application, a portion of the first phase change memory array stores trim data and another portion of the first phase change memory array stores repair data. It should be noted that, in the embodiment of the present application, the first phase change memory array may be one phase change memory array, or may be multiple phase change memory arrays.
In the embodiment of the present application, when a read pulse is applied to the phase change memory cells of the first phase change memory array, the phase change memory cells of the first phase change memory array may perform a threshold switching operation through a transition of an on state (low resistance state) or an off state (high resistance state). That is, the read pulse is below the threshold voltage, the phase change memory cells of the first phase change memory array will be 'off' and conduct little or no current. The read pulse is above the threshold voltage, the phase change memory cells of the first phase change memory array are turned 'on' and conduct current and/or current above the threshold current. However, since the high resistance state of the phase change memory cell of the first phase change memory array corresponds to the fuse reset state of the phase change memory cell of the first phase change memory array, that is, after the phase change memory cell of the first phase change memory array is switched to the high resistance state, the phase change memory cell cannot be switched to the low resistance state, and only the high resistance state can be permanently maintained. After applying a read pulse higher than a threshold voltage to the phase change memory cells of the first phase change memory array, if the phase change memory cells of the first phase change memory array are subjected to threshold switching, it is indicated that the phase change memory cells of the first phase change memory array are not fused; if the phase change memory cell of the first phase change memory array is not subjected to threshold switching, it indicates that the phase change memory cell of the first phase change memory array is fused.
In the embodiment of the application, the phase change material of the phase change memory cell in the first phase change memory array is the same as the phase change material of the phase change memory cell in the second phase change memory array; wherein the phase change material is a chalcogenide compound. It should be noted that the first phase change memory array and the second phase change memory array have the same structure, and the phase change material of the phase change memory cell in the first phase change memory array is the same as the phase change material of the phase change memory cell in the second phase change memory array. In other words, the first phase change memory array and the second phase change memory array are identical memory arrays, so that in the process of forming the three-dimensional phase change memory, the manufacturing process of the fuse is not required to be additionally introduced, and the manufacturing of the memory array and the fuse array can be completed at the same time only by the manufacturing process of the phase change memory array. In addition, due to the fact that the first phase change memory array and the second phase change memory array have the same structure, one or more phase change memory arrays can be directly selected from the phase change memory arrays to serve as fuse arrays to store fusing data which cannot be changed by subsequent writing operation. Therefore, a fuse array is not required to be formed, the size of the device is reduced to a certain extent, and the manufacturing process of the device is simplified.
The embodiment of the application discloses a control method of a three-dimensional phase change memory, wherein the three-dimensional phase change memory comprises a phase change memory array region, and the phase change memory array region comprises a fusing sub-region and a memory sub-region which are adjacent to each other; the method comprises the following steps: selecting a first phase change memory array located in the fuse sub-region; storing, by a first control pulse, blown data that cannot be changed by a subsequent write operation in the first phase change memory array; wherein the first control pulse is larger than a second control pulse for storing memory data that can be changed by a subsequent write operation in a second phase change memory array located in the memory sub-region. The fuse data is stored by using the phase change memory cell in the phase change memory array in the embodiment of the application, namely, the phase change memory array is used as the fuse array in the embodiment of the application, because the melting temperature of the phase change material is relatively low, therefore, only a small control pulse is needed for storing the fuse data by using the phase change memory cell, and the phase change memory array is used as the fuse array in the embodiment of the application, compared with a polysilicon fuse, the size of a device can be reduced, and further, the fuse data is stored by using the phase change memory cell in the embodiment of the application, so that other fuses are not needed to be arranged for storing the fuse data, therefore, the size of the three-dimensional phase change memory can be reduced to a certain extent, and the.
It should be appreciated that reference throughout this specification to "some embodiments" or "an embodiment" means that a particular feature, structure or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the appearances of the phrases "in some embodiments" or "in embodiments of the present application" in various places throughout this specification are not necessarily all referring to the same embodiments. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in the various embodiments of the present application, the sequence numbers of the above-mentioned processes do not mean the execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are merely for description and do not represent the merits of the embodiments.
The methods disclosed in the several method embodiments provided in the present application may be combined arbitrarily without conflict to obtain new method embodiments.
The features disclosed in the several apparatus embodiments provided in the present application may be combined in any combination to arrive at new apparatus embodiments without conflict.
The features disclosed in the several method or article of manufacture embodiments provided herein may be combined in any combination to yield new method or article of manufacture embodiments without conflict.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (18)
1. A three-dimensional phase change memory, comprising:
a phase change memory array region including a fuse sub-region and a memory sub-region adjacent to each other;
the fuse sub region is provided with a first phase change memory array, and the first phase change memory array comprises first phase change memory cells which store fuse data which cannot be changed by subsequent write-in operation;
the first phase change memory array further comprises a second phase change memory cell independent of the first phase change memory cell;
the fusing data comprises a first address and a first control pulse configuration, the first address is used for indicating the position of the second phase change memory unit, and the first control pulse configuration is used for representing a first control pulse for fusing the second phase change memory unit;
the memory sub-region is provided with a second phase change memory array, and phase change memory cells in the second phase change memory array are used for storing memory data which can be changed by a subsequent writing operation.
2. The three-dimensional phase change memory according to claim 1,
the phase change memory cells in the first phase change memory cell and the second phase change memory cell are identical in structure.
3. The three-dimensional phase change memory according to claim 1,
the phase change materials of the first phase change memory unit and the phase change memory unit in the second phase change memory array are the same;
wherein the phase change material is a chalcogenide compound.
4. The three-dimensional phase change memory according to claim 1,
the fuse data further comprises a second address and a second control pulse configuration, the second address data is used for indicating the position of the second phase change memory array, and the second control pulse configuration is used for representing a second control pulse for enabling the phase change memory cells in the second phase change memory array to generate crystalline state transition;
wherein the amplitude of the first control pulse is greater than the amplitude of the second control pulse.
5. The three-dimensional phase change memory according to claim 1,
the second phase change memory cell is capable of an irreversible state transition under the influence of the first control pulse.
6. The three-dimensional phase change memory according to claim 5,
the states of the second phase change memory cell include a blown reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state.
7. The three-dimensional phase change memory according to claim 1,
the phase change memory cells in the second phase change memory array are capable of reversible state transitions under the influence of a second control pulse.
8. The three-dimensional phase change memory according to claim 7,
the states of the phase change memory cells in the second phase change memory array include an amorphous reset state corresponding to a high resistance state and a crystalline set state corresponding to a low resistance state.
9. The three-dimensional phase change memory according to claim 1,
the fuse data includes repair data and trim data.
10. The control method of the three-dimensional phase change memory is characterized in that the three-dimensional phase change memory comprises a phase change memory array region, wherein the phase change memory array region comprises a fusing subarea and a memory subarea which are adjacent to each other; the method comprises the following steps:
selecting a first phase change memory array located in the fuse sub-region;
the first phase change memory array comprises a first phase change memory cell and a second phase change memory cell which are independent of each other;
storing, by a first control pulse, blown data that cannot be changed by a subsequent write operation in the first phase change memory cell;
determining a first control pulse of the second phase change memory cell according to the fusing data stored in the first phase change memory cell;
storing repair data in the second phase change memory cell by the first control pulse;
wherein the first control pulse is larger than a second control pulse for storing memory data that can be changed by a subsequent write operation in a second phase change memory array located in the memory sub-region.
11. The method of controlling a three-dimensional phase change memory according to claim 10,
the phase change memory cells in the first phase change memory array and the phase change memory cells in the second phase change memory array have the same structure.
12. The method of controlling a three-dimensional phase change memory according to claim 10,
the phase change materials of the phase change memory cells in the first phase change memory array and the phase change memory cells in the second phase change memory array are the same;
wherein the phase change material is a chalcogenide compound.
13. The method for controlling the three-dimensional phase-change memory according to claim 10, wherein the storing of the fuse data, which cannot be changed by the subsequent write operation, in the first phase-change memory array by the first control pulse comprises:
and controlling the phase change memory cells of the first phase change memory array to irreversibly change from the low resistance state to the high resistance state through the first control pulse so as to store the fusing data which cannot be changed by a subsequent writing operation in the phase change memory cells of the first phase change memory array.
14. The method of controlling a three-dimensional phase change memory according to claim 13,
the high resistance state corresponds to a fuse reset state of a phase change memory cell of the first phase change memory array;
the low resistance state corresponds to a crystalline setting state of the phase change memory cells of the first phase change memory array.
15. The method of controlling a three-dimensional phase change memory according to claim 10, further comprising:
determining a second control pulse of the second phase change memory array according to the fusing data stored in the first phase change memory array;
storing storage data, which can be changed by a subsequent write operation, in the second phase change memory array by a second control pulse.
16. The method for controlling a three-dimensional phase change memory according to claim 15, wherein the storing the storage data that can be changed by the subsequent write operation in the second phase change memory array by the second control pulse comprises:
and controlling the phase change memory cells of the second phase change memory array to reversibly change from the low resistance state to the high resistance state by the second control pulse so as to store the memory data which can be changed by a subsequent write operation in the phase change memory cells of the second phase change memory array.
17. The method of controlling a three-dimensional phase change memory according to claim 16,
the high resistance state corresponds to an amorphous reset state of a phase change memory cell of the second phase change memory array;
the low resistance state corresponds to a crystalline set state of the phase change memory cells of the second phase change memory array.
18. The method of controlling a three-dimensional phase change memory according to claim 10,
the fuse data includes trim data and repair data.
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