CN116931411A - Time-to-digital conversion device and time interval measurement method - Google Patents

Abstract

The application provides a time-to-digital conversion device and a time interval measurement method, and relates to the technical field of time accurate measurement. According to the application, the coarse time measuring unit counts the number of rising edges of clock signals after rising edges of the start measuring signals come, the fine time measuring unit calibrates the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal, and the fine time measuring unit measures the target time length between the rising edges of the stop measuring signal and the rising edges of the target clock signals according to the calibrated delay time of the single delay module when the delay chain unit transmits the stop measuring signal, and then the time interval between the rising edges of the start/stop measuring signal is calculated by the time interval output unit, so that the delay time calibration cost is reduced, the delay time calibration accuracy is improved, and meanwhile, the time measurement accuracy and the time measurement efficiency are effectively ensured.

Description

Time-to-digital conversion device and time interval measurement method

Technical Field

The application relates to the technical field of time accurate measurement, in particular to a time-to-digital conversion device and a time interval measurement method.

Background

With the continuous development of science and technology, many fields such as space science, medical diagnosis and imaging, nuclear physics, quantum communication, laser detection and the like need to measure speed or distance, and a Time-to-Digital Converter (TDC) is generally used to convert the speed or distance measurement into a Time measurement so as to represent a specific speed or distance by the measured Time. With the rapid development of FPGA (Field-Programmable Gate Array, field programmable gate array) technology and the continuous improvement of cost performance, the time-to-digital converter (TDC) designed by using the FPGA technology not only can achieve higher time resolution, but also has a great advantage in low cost and rapid development cycle, thereby having a profound application prospect.

However, it is noted that, due to the specificity of the internal structure of the FPGA, the delay time of the delay chain unit inside the FPGA may change with the change of the internal temperature and/or the internal voltage, which results in a measurement deviation of the final time measurement result of the corresponding time-to-digital converter.

Currently, the main stream in the industry generally includes an additional calibration circuit externally arranged on the FPGA-based time-to-digital converter, so as to calibrate the delay time of the time measurement result by the calibration circuit, thereby improving the time measurement accuracy of the time-to-digital converter. However, this time measurement calibration scheme requires a costly delay time calibration cost, and the corresponding delay time calibration accuracy and time measurement efficiency are not high.

Disclosure of Invention

Therefore, the present application is directed to a time-to-digital conversion device and a time interval measurement method, which can multiplex a fine time measurement unit to realize a real-time delay time calibration function of a delay chain unit and a fine time delay measurement function of a measured stop signal without an external calibration circuit, so that the delay time calibration cost is reduced, the delay time calibration accuracy is improved, and meanwhile, the time measurement accuracy and the time measurement efficiency are effectively ensured.

In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows:

in a first aspect, the present application provides a time-to-digital conversion device, the device including a delay chain unit, a coarse time measurement unit, a fine time measurement unit, a time interval output unit, and a signal switching unit;

the time delay chain unit is externally connected with a clock signal, the coarse time measuring unit is electrically connected with the time delay chain unit, the coarse time measuring unit is externally connected with a start measuring signal, and the coarse time measuring unit is used for counting the number of rising edges of the clock signal after the rising edges of the start measuring signal come;

the signal switching unit is externally connected with a delay calibration signal and a stop measurement signal, and is electrically connected with the delay chain unit, wherein the signal switching unit is used for switching the delay calibration signal or the stop measurement signal to be input into the delay chain unit for transmission;

The fine time measurement unit is electrically connected with the delay chain unit, and is used for calibrating the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal, and measuring the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal according to the calibrated delay time of the single delay module when the delay chain unit transmits the stop measurement signal, wherein the rising edge of the target clock signal is the first clock signal rising edge after the rising edge of the stop measurement signal arrives;

the time interval output unit is electrically connected with the fine time measurement unit and the coarse time measurement unit at the same time, and is used for calculating the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the number of the rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit.

In an alternative embodiment, the delay chain unit comprises a trigger array, an encoder and a plurality of delay modules;

The delay modules are mutually cascaded and are used for carrying out delay transmission on the input signals of the delay chain units;

the trigger array comprises a plurality of triggers, each trigger is correspondingly connected with one delay module and is used for latching the signal output of each delay module when the rising edge of a clock signal arrives, so as to obtain the signal transmission condition of the input signal in the delay chain unit when the rising edge of the clock signal arrives;

the encoder is electrically connected with the trigger array and is used for performing code conversion on signal transmission conditions in the delay chain unit when the rising edge of the clock signal arrives, so as to obtain binary code data which can be identified by the fine time measuring unit and the coarse time measuring unit.

In an alternative embodiment, the sum of the respective delay times of all delay modules of the delay chain unit is greater than a single clock period of the clock signal, and all delay modules of the delay chain unit are all an advanced fast carry logic structure inside the FPGA chip.

In an alternative embodiment, in the case that the delay chain unit transmits the delay calibration signal, the fine time measurement unit acquires a target delay module position from the delay chain unit, wherein the target delay module position captures rising edges of the delay calibration signal when rising edges of two adjacent clock signals arrive;

The fine time measuring unit calculates the number of traversing delay modules required by the delay chain unit to transmit the delay calibration signal in a single clock period according to the positions of the target delay modules corresponding to the rising edges of the two adjacent clock signals;

and the fine time measuring unit performs division operation on the clock period and the number of the traversing delay modules so as to calibrate the delay time of a single delay module in the delay chain unit.

In an alternative embodiment, the apparatus further comprises a clock calibration generation unit;

the clock calibration generating unit is electrically connected with the delay chain unit and is used for generating clock signals and transmitting the generated clock signals to the delay chain unit;

the clock calibration generating unit is further electrically connected with the signal switching unit, and is used for performing phase adjustment processing on the generated clock signal to obtain a corresponding delay calibration signal, and transmitting the obtained delay calibration signal to the signal switching unit.

In an alternative embodiment, the apparatus further comprises a measurement signal generating unit;

the measuring signal generating unit is electrically connected with the coarse time measuring unit and is used for generating a starting measuring signal and transmitting the generated starting measuring signal to the coarse time measuring unit;

The measuring signal generating unit is also electrically connected with the signal switching unit and is used for generating a stop measuring signal and transmitting the generated stop measuring signal to the signal switching unit.

In a second aspect, the present application provides a time interval measurement method, which is applied to the time-to-digital conversion device in any one of the foregoing embodiments, and the method includes:

controlling the coarse time measuring unit to count the rising edge of the clock signal after the rising edge of the received start measuring signal comes;

the control signal switching unit inputs an external stop measurement signal into the delay chain unit for transmission, so that the fine time measurement unit measures a target time length between a rising edge of the stop measurement signal and a rising edge of a target clock signal based on the delay time of a single delay module in the delay chain unit which is calibrated currently, wherein the rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives;

and controlling the time interval output unit to calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the target time length measured by the fine time measurement unit and the number of the rising edges of the clock signal counted by the coarse time measurement unit between the rising edges of the start measurement signal and the rising edges of the stop measurement signal.

In an alternative embodiment, the step of calculating the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edge of the start measurement signal and the rising edge of the stop measurement signal includes:

calculating a time difference value between a single clock period of the clock signal and the target time length to obtain a first time length to be superimposed;

according to a single clock period of the clock signal, calculating the time length corresponding to the number of rising edges of the clock signal counted by the coarse time measuring unit to obtain a second time length to be superimposed;

and performing addition operation on the first time length to be superimposed and the second time length to be superimposed to obtain a time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

In an alternative embodiment, the method further comprises:

controlling the signal switching unit to input an external delay calibration signal into the delay chain unit for transmission;

And controlling the fine time measuring unit to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit.

In an alternative embodiment, the step of calibrating the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit includes:

acquiring the target delay module position of the delay chain unit, which captures the rising edge of the delay calibration signal when the rising edges of two adjacent clock signals come;

according to the positions of the target delay modules corresponding to the rising edges of the two adjacent clock signals, calculating the number of traversal delay modules required by the delay chain unit to transmit the delay calibration signal in a single clock period;

and performing division operation on the clock period and the number of the traversing delay modules to calibrate the delay time of a single delay module in the delay chain unit.

In this case, the beneficial effects of the embodiments of the present application may include the following:

according to the application, the coarse time measuring unit is electrically connected with the delay chain unit externally connected with the clock signal, so that the coarse time measuring unit counts the number of rising edges of the clock signal after the rising edge of the self-externally connected starting measuring signal arrives, the signal switching unit switches the external delay calibration signal or stops the measuring signal to be input into the delay chain unit for transmission, and the fine time measuring unit calculates the time interval between the rising edge of the starting measuring signal and the rising edge of the stopping measuring signal according to the transmission condition of the delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal, and the fine time measuring unit measures the target time length between the rising edge of the stopping measuring signal and the rising edge of the target clock signal according to the calibrated delay time of the single delay module when the delay chain unit transmits the stopping measuring signal, and then the time interval output unit calculates the time interval between the rising edge of the starting measuring signal and the rising edge of the stopping measuring signal according to the number of the rising edge of the clock signal and the target time length measured by the time interval output unit, so that the delay time measuring unit can realize the accurate calibration function when the delay calibration unit is stopped according to the calibrated delay time of the single delay time module, and the time conversion function is realized, and the time calibration efficiency is reduced, and the time accuracy is guaranteed.

In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a time-to-digital conversion device according to an embodiment of the present application;

fig. 2 is a schematic diagram of the composition of a delay chain unit according to an embodiment of the present application;

FIG. 3 is a second schematic diagram of a time-to-digital conversion device according to an embodiment of the present application;

fig. 4 is a schematic flow chart of a time interval measurement method according to an embodiment of the present application;

fig. 5 is a flow chart illustrating the sub-steps included in step S230 in fig. 4;

FIG. 6 is a second flowchart of a time interval measurement method according to an embodiment of the present application;

Fig. 7 is a flow chart illustrating the sub-steps included in step S250 in fig. 6.

Icon: 10-time-to-digital conversion means; 11-a signal switching unit; 12-a delay chain unit; 13-a coarse time measurement unit; 14-a fine time measurement unit; 15-a time interval output unit; a 16-clock calibration generation unit; 17-a measurement signal generation unit.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the present application, it should be understood that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The embodiments described below and features of the embodiments may be combined with each other without conflict.

Referring to fig. 1, fig. 1 is a schematic diagram of a time-to-digital conversion device 10 according to an embodiment of the application. In the embodiment of the application, the delay time calibration cost of the time-to-digital conversion device 10 is low, the overall delay time calibration accuracy is high, and the time interval measurement function with high accuracy and high efficiency can be realized for the measured signal. The time-to-digital conversion device 10 may include a signal switching unit 11, a delay chain unit 12, a coarse time measurement unit 13, a fine time measurement unit 14, and a time output unit 15.

In this embodiment, the delay chain unit 12 may be externally connected to a clock signal, and the coarse time measuring unit 13 is externally connected to a start measuring signal. Wherein the coarse time measuring unit 13 is configured to start counting the number of rising edges of the clock signal received by the delay chain unit 12 after the rising edges of the measurement signal come to realize a coarse time counting function for the measured signal. Wherein the start measurement signal rising edge is used to instruct the time-to-digital conversion device 10 to make a start point in time of the time interval measurement.

In this embodiment, the signal switching unit 11 is externally connected with a delay calibration signal and a stop measurement signal, and meanwhile, the signal switching unit 11 is electrically connected with the delay chain unit 12, so as to switch the delay calibration signal or stop the measurement signal from being input into the delay chain unit 12 for transmission.

If the signal switching unit 11 switches the delay calibration signal to be input into the delay chain unit 12 for transmission, the delay chain unit 12 performs delay value measurement on the transmitted delay calibration signal, so as to obtain the transmission condition of the delay calibration signal under the action of the clock signal.

If the signal switching unit 11 switches the stop measurement signal to be input into the delay chain unit 12 for transmission, the delay chain unit 12 performs delay value measurement on the transmitted stop measurement signal, so as to obtain the transmission condition of the stop measurement signal under the action of the clock signal. At this time, the delay chain unit 12 informs the coarse time measuring unit 13 of stopping counting when the rising edge of the stop measurement signal arrives, so as to ensure that the number of rising edges of the clock signal correspondingly counted by the coarse time measuring unit 13 belongs to the number of clock cycles elapsed in a period from the start of the rising edge of the measurement signal to the stop of the rising edge of the measurement signal, wherein the signal rising edge of the stop measurement signal is used for indicating a stop time point of time interval measurement performed by the time-to-digital conversion device 10.

In this embodiment, the fine time measurement unit 14 is electrically connected to the delay chain unit 12, and is configured to calibrate the delay time of a single delay module in the delay chain unit 12 in real time according to the transmission condition of the delay calibration signal at the delay chain unit 12 when the delay chain unit 12 transmits the delay calibration signal, so as to implement the function of calibrating the delay time of the delay chain unit 12 in real time. The foregoing delay calibration signal is used to instruct the fine time measurement unit 14 to calibrate in real time the actual delay time of the single delay module in the delay chain unit 12 under the current operating environment.

In this embodiment, the fine time measurement unit 14 is further configured to measure, when the delay chain unit 12 transmits the stop measurement signal, a target time length between a rising edge of the signal of the stop measurement signal and a rising edge of the target clock signal according to the delay time of the single delay module that is calibrated currently, so as to implement a fine time delay measurement function for the measured stop signal. The rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives.

In this embodiment, the time interval output unit 15 is electrically connected to the fine time measurement unit 14 and the coarse time measurement unit 13 at the same time, and is configured to directly calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the target time length measured by the fine time measurement unit 14 and the number of rising edges of the clock signal counted by the coarse time measurement unit 13 between the rising edges of the start measurement signal and the rising edges of the stop measurement signal.

The time interval output unit 15 may calculate a time difference between a single clock cycle of the clock signal and the target time length to obtain a first time interval to be superimposed, and then multiply the clock cycle by the number of rising edges of the clock signal counted by the coarse time measurement unit 13 to obtain a second time interval to be superimposed, and further perform an addition operation on the first time interval to be superimposed and the second time interval to obtain a time interval between a rising edge of the start measurement signal and a rising edge of the stop measurement signal.

Therefore, the present application can be composed by the specific device of the time-to-digital conversion device 10, and the multiplexing fine time measurement unit 14 can realize the real-time calibration function of the delay time of the delay chain unit 12 and the fine time delay measurement function of the measured stop signal without an external calibration circuit, and can obtain the time interval corresponding to the measured signal by measuring the coarse time and the fine time of the measured signal (including the start measurement signal and the stop measurement signal), thereby reducing the delay time calibration cost of the time-to-digital conversion device 10, improving the delay time calibration accuracy of the time-to-digital conversion device 10, and simultaneously effectively ensuring the time measurement accuracy and the time measurement efficiency of the time-to-digital conversion device 10.

Optionally, referring to fig. 2, fig. 2 is a schematic diagram illustrating the composition of the delay chain unit 12 according to an embodiment of the present application. In an embodiment of the present application, the delay chain unit 12 may include a trigger array, an encoder, and a plurality of delay modules.

In this embodiment, the delay chain unit 12 includes a plurality of delay modules that are cascaded, where the input end of the first cascaded delay module of the plurality of delay modules is externally connected with a corresponding input signal (i.e., the delay calibration signal or the stop measurement signal), and the input ends of other cascaded delay modules are connected with the output end of the previous cascaded delay module, so that delay transmission measurement is performed on the input signal corresponding to the delay chain unit 12 through the plurality of delay modules.

In this embodiment, the trigger array included in the delay chain unit 12 may be composed of a plurality of triggers, and each trigger is correspondingly connected to one delay module, so as to latch the signal output of each delay module in the delay chain unit 12 when the rising edge of the clock signal arrives, so as to obtain the signal transmission condition of the input signal in the delay chain unit 12 when the rising edge of the clock signal arrives. The flip-flop related to the flip-flop array may be a D flip-flop, so that a clock input end of the D flip-flop is externally connected with a clock signal, and a signal input end of the D flip-flop is connected with an output end of a corresponding delay module.

In this embodiment, the encoder included in the delay chain unit 12 is electrically connected to each trigger in the trigger array, and is used for performing code conversion on the signal transmission condition in the delay chain unit 12 when the clock signal rising edge arrives, so as to obtain binary code data that can be identified by both the fine time measurement unit 14 and the coarse time measurement unit 13.

The signal transmission condition of the input signal in the delay chain unit 12 when the rising edge of the clock signal arrives may indicate to which delay module the rising edge of the signal corresponding to the input signal is transmitted when the rising edge of the corresponding clock signal arrives, and the module position of the delay module (which may be described by the module serial number of the delay module) may be regarded as the target delay module position where the rising edge of the input signal is captured at the rising edge of the corresponding clock signal.

It will be appreciated that in the case where the input signal is a stop measurement signal, the encoder will inform the coarse time measurement unit 13 of stopping counting when the stop measurement signal rising edge arrives by transmitting specific binary code data to the coarse time measurement unit 13, thereby ensuring that the number of clock signal rising edges actually counted by the coarse time measurement unit 13 belongs to the number of clock cycles elapsed in the period from the start of the measurement signal rising edge to the stop of the measurement signal rising edge.

In the embodiment of the present application, to ensure that the fine time measurement unit 14 can implement the delay time real-time calibration function and the fine time delay measurement function through the delay chain unit 12, the total delay time (i.e., the sum of the respective delay times of all delay modules of the delay chain unit 12) involved in the delay chain unit 12 needs to be maintained in a state greater than a single clock cycle of the clock signal, so as to ensure that the time length of the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal exceeding the integral multiple of the clock cycle can be measured by the fine time measurement unit 14.

Meanwhile, through diligent research, the applicant finds that the conventional FPGA-based time-to-digital converter constructs a delay chain unit by taking a plurality of CARRY logic structures included in each of a plurality of CARRY-in-advance logic structures (for example, CARRY4 or CARRY 8) inside an FPGA chip as one delay module, so that a delay interval (i.e., T) between two adjacent delay modules belonging to the same CARRY-in-advance logic structure in the corresponding time-to-digital converter is obviously different from a delay interval (i.e., T) between two adjacent delay modules belonging to different CARRY-in-advance logic structures (i.e., T > T), which results in uneven distribution of delay times of the delay modules in the conventional delay chain unit, and further in obvious errors in a final time measurement result.

Therefore, each advanced fast-carry logic structure in the FPGA chip is directly used as one delay module of the delay chain unit 12, so that the characteristic that the wiring length in the single advanced fast-carry logic structure is basically the same is utilized, the delay time of each advanced fast-carry logic structure when being used as the delay module is ensured to be basically consistent, the delay time of each delay module in the delay chain unit 12 is ensured to be in a uniform distribution state, and the result accuracy of a final time measurement result is improved.

In this case, to ensure that the fine time measurement unit 14 can implement the real-time delay calibration function of the delay chain unit 12, the delay calibration signal may be switched and input into the delay chain unit 12 by the control signal switching unit 11, and the fine time measurement unit 14 correspondingly acquires the target delay module positions of the rising edges of the delay calibration signal when the rising edges of two adjacent clock signals arrive, and then calculates the number of delay modules between the two target delay module positions based on the target delay module positions corresponding to the rising edges of the two adjacent clock signals, so as to obtain the number of traversing delay modules required by the delay chain unit 12 for transmitting the delay calibration signal in a single clock period under the current operating environment, and then directly calibrate the delay time of the single delay module in the delay chain unit 12 under the current operating environment by dividing the single clock period by the number of traversing delay modules, thereby ensuring that the calibrated delay time is substantially matched with the current operating environment, and ensuring the accuracy of the final time measurement result.

Optionally, referring to fig. 3, fig. 3 is a second schematic diagram of a time-to-digital conversion device 10 according to an embodiment of the application. In an embodiment of the present application, the time-to-digital conversion apparatus 10 shown in fig. 3 may further include a clock calibration generating unit 16, as compared to the time-to-digital conversion apparatus 10 shown in fig. 1.

In this embodiment, the clock calibration generating unit 16 may be electrically connected to the delay chain unit 12, and is configured to generate a clock signal and transmit the generated clock signal to the delay chain unit 12, so as to ensure that the delay chain unit 12, the fine time measuring unit 14 and the coarse time measuring unit 13 can normally implement the time measuring function.

In this embodiment, the clock calibration generating unit 16 may be further electrically connected to the signal switching unit 11, and is configured to perform phase adjustment processing on the generated clock signal to obtain a corresponding delay calibration signal, and transmit the obtained delay calibration signal to the signal switching unit 11, so that the signal switching unit 11 can output the delay calibration signal to the delay chain unit 12 when the delay time needs to be calibrated.

In one implementation of this embodiment, the clock calibration generating unit 16 may step-adjust the signal phase of the delay calibration signal according to a specific frequency (for example, at intervals of 15 picoseconds), until the rising edge of the signal of the adjusted delay calibration signal after being input to the delay chain unit 12 can be captured by the rising edges of two adjacent clock signals, so as to ensure that the corresponding fine time measuring unit 14 normally implements the delay time real-time calibration function for the delay chain unit 12.

Alternatively, in the embodiment of the present application, the above-described time-to-digital conversion apparatus 10 may further include a measurement signal generation unit 17.

In this embodiment, the measurement signal generating unit 17 is electrically connected to the coarse time measuring unit 13, and is configured to generate a start measurement signal when time measurement for the measured signal needs to be started, and transmit the generated start measurement signal to the coarse time measuring unit 13, so as to instruct the coarse time measuring unit 13 to start counting the rising edge of the clock signal through the rising edge of the start measurement signal.

The measurement signal generating unit 17 is further electrically connected to the signal switching unit 11, and is configured to generate a stop measurement signal when time measurement on the measured signal needs to be stopped, and transmit the generated stop measurement signal to the signal switching unit 11, so that the signal switching unit 11 can output the stop measurement signal to the delay chain unit 12 when time measurement needs to be stopped, so as to instruct the coarse time measuring unit 13 to stop counting rising edges of the clock signal through rising edges of the stop measurement signal, and instruct the fine time measuring unit 14 to operate a fine time delay measurement function of the measured stop signal.

In order to ensure that the time-to-digital conversion device 10 can implement the time interval measurement function for the measured signal (including the start measurement signal and the stop measurement signal), the embodiment of the application provides a time interval measurement method applied to the time-to-digital conversion device 10 to achieve the above objective. The time interval measurement method provided by the application is described in detail below.

Referring to fig. 4, fig. 4 is a flowchart of a time interval measurement method according to an embodiment of the application. In the embodiment of the present application, the time interval measurement method is applied to the time-to-digital conversion device 10, and the time interval measurement method may include steps S210 to S230.

In step S210, the coarse time measurement unit is controlled to count the rising edge of the clock signal after the rising edge of the received start measurement signal arrives.

In this embodiment, when the electronic device in which the time-to-digital conversion device 10 is located needs to perform time interval measurement, the time-to-digital conversion device 10 can drive the start measurement signal to generate a signal rising edge, so that the coarse time measurement unit 13 included in the time-to-digital conversion device 10 performs clock signal rising edge counting after the received start measurement signal rising edge arrives.

It will be appreciated that the time-to-digital conversion device 10 described above may be applied to a laser scanning process of a laser radar, in which the laser radar drives the start measurement signal to generate a signal rising edge each time the laser beam is emitted, so that the coarse time measurement unit 13 included in the time-to-digital conversion device 10 counts the rising edges of the clock signal after the received rising edges of the start measurement signal arrive.

Step S220, the control signal switching unit inputs an external stop measurement signal into the delay chain unit for transmission, so that the fine time measurement unit measures the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of the single delay module in the delay chain unit which is calibrated currently.

In this embodiment, when the electronic device in which the time-to-digital conversion device 10 is located needs to measure at a stop time interval, the signal switching unit 11 included in the time-to-digital conversion device 10 may be driven to switch the stop measurement signal to be input into the delay chain unit 12 for transmission, and drive the stop measurement signal to generate a signal rising edge, so that the fine time measurement unit 14 included in the time-to-digital conversion device 10 directly measures the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of the single delay module in the delay chain unit 12 that has been calibrated, and the delay chain unit 12 drives the coarse time measurement unit 13 to suspend counting the rising edge of the clock signal after the rising edge of the stop measurement signal arrives. Wherein the target clock signal rising edge is the first clock signal rising edge after the arrival of the stop measurement signal rising edge.

The fine time measurement unit 14 may obtain the target delay module position of the delay chain unit 12 capturing the rising edge of the stop measurement signal at the rising edge of the target clock signal, then determine the number of delay modules between the first cascaded delay module in the delay chain unit 12 and the target delay module position, and then multiply the delay time of the single delay module that is currently standardized with the determined number of delay modules to obtain the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal.

It will be appreciated that when the time-to-digital conversion device 10 is applied to a laser radar, the laser radar may be driven to switch the signal switching unit 11 included in the time-to-digital conversion device 10 to switch the stop measurement signal to be input into the delay chain unit 12 for transmission when the laser radar emits the laser beam, and drive the stop measurement signal to generate a signal rising edge when the laser radar receives the reflected laser beam, so that the fine time measurement unit 14 included in the time-to-digital conversion device 10 directly measures the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of the single delay module in the delay chain unit 12, and the coarse time measurement unit 13 is driven by the delay chain unit 12 to stop counting the rising edge of the clock signal after the rising edge of the stop measurement signal arrives.

In step S230, the control interval output unit calculates the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edges of the start measurement signal and the rising edges of the stop measurement signal.

In this embodiment, when the fine time measuring unit 14 measures the target time length and the coarse time measuring unit 13 counts the number of rising clock signal edges between the rising clock signal edges and the rising clock signal edges, the time-to-digital converting apparatus 10 includes the time interval output unit 15 that obtains the time interval between the rising clock signal edges and the rising clock signal edges by performing data processing on the target time length and the number of rising clock signal edges.

It will be appreciated that when the time-to-digital conversion device 10 is applied to the laser scanning process of the laser radar, the time interval between the laser emission time point and the laser receiving time point can be calculated through the cooperation of the steps S210 to S230.

Optionally, referring to fig. 5, fig. 5 is a flowchart illustrating the sub-steps included in step S230 in fig. 4. In the embodiment of the present application, the step S230 may include sub-steps S231 to S233 to accurately measure the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

In sub-step S231, a time difference between a single clock cycle of the clock signal and the target time length is calculated, resulting in a first time length to be superimposed.

Wherein the first length of time to be superimposed may be derived from a single clock cycle of the clock signal minus the target length of time.

In sub-step S232, according to the single clock cycle of the clock signal, a time length corresponding to the number of rising edges of the clock signal counted by the coarse time measurement unit is calculated, so as to obtain a second time length to be superimposed.

The second time length to be superimposed may be obtained by multiplying a single clock cycle of the clock signal by the number of rising edges of the clock signal counted by the coarse time measuring unit 13.

In the sub-step S233, the first length of time to be superimposed and the second length of time to be superimposed are added to obtain a time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

Thus, the present application can precisely measure the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal by performing the above-described sub-steps S231 to S233.

The present application can implement the time interval measurement function for the measured signal (including the start measurement signal and the stop measurement signal) by executing the above steps S210 to S230.

Optionally, referring to fig. 6, fig. 6 is a second flowchart of a time interval measurement method according to an embodiment of the application. In the embodiment of the present application, compared to the time interval measurement method shown in fig. 4, the time interval measurement method shown in fig. 6 may further include step S240 and step S250 to ensure that the time-to-digital conversion device 10 can multiplex the fine time measurement unit 14 to implement the delay time real-time calibration function for the delay chain unit 12.

In step S240, the control signal switching unit inputs the external delay calibration signal to the delay chain unit for transmission.

In this embodiment, when the electronic device in which the time-to-digital conversion device 10 is located needs to perform delay time calibration, the signal switching unit 11 can be driven to switch the delay calibration signal to be input into the delay chain unit 12 for transmission, so that the delay chain unit 12 can correspondingly capture the signal rising edge of the delay calibration signal when the rising edges of two adjacent clock signals come.

It will be appreciated that when the time-to-digital conversion device 10 is applied to a laser radar, the signal switching unit 11 may be driven to switch the delay calibration signal to be input to the delay chain unit 12 for transmission during the laser charging idle period of the laser radar, so as to perform the delay time calibration operation during the laser charging idle period.

Step S250, the fine time measuring unit is controlled to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit.

In this embodiment, the fine time measurement unit 14 may calibrate the delay time of a single delay module of the delay chain unit 12 in real time in the current operating environment according to the signal transmission condition of the delay calibration signal captured in the delay chain unit 12 when the delay chain unit 12 transmits the delay calibration signal.

Optionally, referring to fig. 7, fig. 7 is a flowchart illustrating the sub-steps included in step S250 in fig. 6. In an embodiment of the present application, the step S250 may include sub-steps S251 to S253 to calibrate the delay time of the single delay module of the delay chain unit 12 in real time in the current operating environment.

In sub-step S251, the target delay module position of the delay chain unit capturing the rising edge of the delay calibration signal when the rising edges of the two adjacent clock signals arrive is obtained.

In sub-step S252, the number of traversal delay modules required by the delay chain unit to transmit the delay calibration signal in a single clock cycle is calculated according to the positions of the target delay modules corresponding to the rising edges of the two adjacent clock signals.

The number of traversing delay modules is the number of delay modules between the two target delay module positions.

In sub-step S253, a division operation is performed on the clock cycle and the number of traversing delay modules to calibrate the delay time of a single delay module in the delay chain unit.

Thus, the present application can calibrate the delay time of a single delay module of the delay chain unit 12 in real time in the current operating environment by performing the above-described sub-steps S251 to S253.

The present application can ensure that the time-to-digital conversion device 10 can multiplex the fine time measurement unit 14 to implement the real-time calibration function of the delay time for the delay chain unit 12 by executing the above step S240 and step S250.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, of the flowcharts and block diagrams in the figures that illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods and computer program products according to embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part. The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solution of the present application, or the part contributing to the prior art or the part of the technical solution, may be embodied in the form of a software product stored in a readable storage medium, comprising several instructions for causing a main control chip in the above-mentioned lidar system to perform all or part of the steps of the method of the various embodiments of the present application. And the aforementioned readable storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In summary, in the time-to-digital conversion device and the time interval measurement method provided by the embodiments of the present application, the coarse time measurement unit is electrically connected with the delay chain unit externally connected with the clock signal, so that the coarse time measurement unit counts the number of rising edges of the clock signal after the rising edge of the signal to be measured comes, and the signal switching unit switches the external delay calibration signal or stops the signal to be measured and inputs the signal to the delay chain unit for transmission, when the delay calibration signal is transmitted by the fine time measurement unit, the delay time of the single delay module in the delay chain unit is calibrated in real time according to the transmission condition of the delay calibration signal at the delay chain unit, and when the delay measurement signal is transmitted by the fine time measurement unit, the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal is measured according to the calibrated delay time of the single delay time module, and then the time interval output unit calculates the rising edge of the signal to be measured according to the number of rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit, thereby realizing the accurate calibration of the time delay time between the rising edge and the signal at the delay chain unit, and the time of the delay calibration circuit is not required to be calibrated, and the time of the delay calibration circuit is accurately measured, and the time of the time calibration device is reduced.

The above description is merely illustrative of various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the scope of the present application, and the application is intended to be covered by the scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims (10)

1. The time-to-digital conversion device is characterized by comprising a delay chain unit, a coarse time measuring unit, a fine time measuring unit, a time interval output unit and a signal switching unit;

the time delay chain unit is externally connected with a clock signal, the coarse time measuring unit is electrically connected with the time delay chain unit, the coarse time measuring unit is externally connected with a start measuring signal, and the coarse time measuring unit is used for counting the number of rising edges of the clock signal after the rising edges of the start measuring signal come;

the signal switching unit is externally connected with a delay calibration signal and a stop measurement signal, and is electrically connected with the delay chain unit, wherein the signal switching unit is used for switching the delay calibration signal or the stop measurement signal to be input into the delay chain unit for transmission;

The fine time measurement unit is electrically connected with the delay chain unit, and is used for calibrating the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal, and measuring the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal according to the calibrated delay time of the single delay module when the delay chain unit transmits the stop measurement signal, wherein the rising edge of the target clock signal is the first clock signal rising edge after the rising edge of the stop measurement signal arrives;

the time interval output unit is electrically connected with the fine time measurement unit and the coarse time measurement unit at the same time, and is used for calculating the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the number of the rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit.

2. The apparatus of claim 1, wherein the delay chain unit comprises a trigger array, an encoder, and a plurality of delay modules;

The delay modules are mutually cascaded and are used for carrying out delay transmission on the input signals of the delay chain units;

the trigger array comprises a plurality of triggers, each trigger is correspondingly connected with one delay module and is used for latching the signal output of each delay module when the rising edge of a clock signal arrives, so as to obtain the signal transmission condition of the input signal in the delay chain unit when the rising edge of the clock signal arrives;

the encoder is electrically connected with the trigger array and is used for performing code conversion on signal transmission conditions in the delay chain unit when the rising edge of the clock signal arrives, so as to obtain binary code data which can be identified by the fine time measuring unit and the coarse time measuring unit.

3. The apparatus of claim 2, wherein the sum of the respective delay times of all delay blocks of the delay chain unit is greater than a single clock cycle of the clock signal, and wherein all delay blocks of the delay chain unit are of an advanced fast carry logic structure within the FPGA chip.

4. The apparatus of claim 1, wherein the fine time measurement unit obtains, from the delay chain unit, a target delay module position at which the rising edges of the delay calibration signal are captured when the rising edges of two adjacent clock signals arrive, in a case where the delay chain unit transmits the delay calibration signal;

The fine time measuring unit calculates the number of traversing delay modules required by the delay chain unit to transmit the delay calibration signal in a single clock period according to the positions of the target delay modules corresponding to the rising edges of the two adjacent clock signals;

and the fine time measuring unit performs division operation on the clock period and the number of the traversing delay modules so as to calibrate the delay time of a single delay module in the delay chain unit.

5. The apparatus according to any one of claims 1-4, further comprising a clock calibration generation unit;

the clock calibration generating unit is electrically connected with the delay chain unit and is used for generating clock signals and transmitting the generated clock signals to the delay chain unit;

the clock calibration generating unit is further electrically connected with the signal switching unit, and is used for performing phase adjustment processing on the generated clock signal to obtain a corresponding delay calibration signal, and transmitting the obtained delay calibration signal to the signal switching unit.

6. The apparatus according to claim 5, further comprising a measurement signal generation unit;

The measuring signal generating unit is electrically connected with the coarse time measuring unit and is used for generating a starting measuring signal and transmitting the generated starting measuring signal to the coarse time measuring unit;

the measuring signal generating unit is also electrically connected with the signal switching unit and is used for generating a stop measuring signal and transmitting the generated stop measuring signal to the signal switching unit.

7. A time interval measurement method, applied to the time-to-digital conversion device of any one of claims 1 to 6, comprising:

controlling the coarse time measuring unit to count the rising edge of the clock signal after the rising edge of the received start measuring signal comes;

the control signal switching unit inputs an external stop measurement signal into the delay chain unit for transmission, so that the fine time measurement unit measures a target time length between a rising edge of the stop measurement signal and a rising edge of a target clock signal based on the delay time of a single delay module in the delay chain unit which is calibrated currently, wherein the rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives;

And controlling the time interval output unit to calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal according to the target time length measured by the fine time measurement unit and the number of the rising edges of the clock signal counted by the coarse time measurement unit between the rising edges of the start measurement signal and the rising edges of the stop measurement signal.

8. The method according to claim 7, wherein the step of calculating the time interval between the start measurement signal rising edge and the stop measurement signal rising edge from the target time length measured by the fine time measurement unit and the number of clock signal rising edges counted by the coarse time measurement unit between the start measurement signal rising edge and the stop measurement signal rising edge includes:

calculating a time difference value between a single clock period of the clock signal and the target time length to obtain a first time length to be superimposed;

according to a single clock period of the clock signal, calculating the time length corresponding to the number of rising edges of the clock signal counted by the coarse time measuring unit to obtain a second time length to be superimposed;

And performing addition operation on the first time length to be superimposed and the second time length to be superimposed to obtain a time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

9. The method according to claim 7 or 8, characterized in that the method further comprises:

controlling the signal switching unit to input an external delay calibration signal into the delay chain unit for transmission;

and controlling the fine time measuring unit to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission condition of the delay calibration signal at the delay chain unit.

10. The method of claim 9, wherein said step of calibrating the delay time of individual delay modules in said delay chain unit in real time based on the transmission condition of said delay calibration signal at said delay chain unit comprises:

acquiring the target delay module position of the delay chain unit, which captures the rising edge of the delay calibration signal when the rising edges of two adjacent clock signals come;

according to the positions of the target delay modules corresponding to the rising edges of the two adjacent clock signals, calculating the number of traversal delay modules required by the delay chain unit to transmit the delay calibration signal in a single clock period;

And performing division operation on the clock period and the number of the traversing delay modules to calibrate the delay time of a single delay module in the delay chain unit.