CN116916526A - Multilayer ceramic circuit board structure and preparation method thereof - Google Patents
Multilayer ceramic circuit board structure and preparation method thereof Download PDFInfo
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- CN116916526A CN116916526A CN202310879924.2A CN202310879924A CN116916526A CN 116916526 A CN116916526 A CN 116916526A CN 202310879924 A CN202310879924 A CN 202310879924A CN 116916526 A CN116916526 A CN 116916526A
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- 239000000919 ceramic Substances 0.000 title claims abstract description 81
- 238000002360 preparation method Methods 0.000 title abstract description 16
- 238000002955 isolation Methods 0.000 claims abstract description 71
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 238000000034 method Methods 0.000 claims abstract description 46
- 230000008569 process Effects 0.000 claims abstract description 39
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052802 copper Inorganic materials 0.000 claims abstract description 23
- 239000010949 copper Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 20
- 239000003292 glue Substances 0.000 claims abstract description 15
- 238000004528 spin coating Methods 0.000 claims abstract description 15
- 238000009713 electroplating Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 13
- 238000000059 patterning Methods 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 238000001723 curing Methods 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 230000010354 integration Effects 0.000 claims abstract description 7
- 238000005553 drilling Methods 0.000 claims abstract description 6
- 238000011161 development Methods 0.000 claims abstract description 4
- 230000000149 penetrating effect Effects 0.000 claims abstract description 4
- 238000001259 photo etching Methods 0.000 claims abstract description 4
- 238000009413 insulation Methods 0.000 claims abstract 2
- 238000005516 engineering process Methods 0.000 claims description 13
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 8
- 229920001721 polyimide Polymers 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 6
- 238000000227 grinding Methods 0.000 claims description 6
- 229920002120 photoresistant polymer Polymers 0.000 claims description 6
- 239000010936 titanium Substances 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- 238000005459 micromachining Methods 0.000 claims description 5
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000013461 design Methods 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- 238000004381 surface treatment Methods 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 claims description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims description 2
- 239000011347 resin Substances 0.000 claims description 2
- 229920005989 resin Polymers 0.000 claims description 2
- 230000017525 heat dissipation Effects 0.000 abstract description 6
- 238000004806 packaging method and process Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 102
- 239000011229 interlayer Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical group O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000002086 nanomaterial Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000005202 decontamination Methods 0.000 description 1
- 230000003588 decontaminative effect Effects 0.000 description 1
- 238000005238 degreasing Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 238000013007 heat curing Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
- H05K1/0256—Electrical insulation details, e.g. around high voltage areas
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
- H05K1/116—Lands, clearance holes or other lay-out details concerning the surrounding of a via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
- H05K3/424—Plated through-holes or plated via connections characterised by electroplating method by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Inorganic Chemistry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application discloses a multilayer ceramic circuit board structure and a preparation method thereof. The upper surface and the lower surface of the ceramic substrate are provided with a patterning circuit, communication holes penetrating through the upper surface and the lower surface are formed in the patterning circuit, and metal copper columns are filled in the communication holes. And coating heat-resistant insulating glue on the surface of the ceramic substrate by a spin coating process, heating and curing to form an isolation layer, and manufacturing a graphical circuit on the surface of the isolation layer. The isolating layer contains communicating holes and is filled with metal copper columns, so that the ceramic substrate and the isolating layer are electrically interconnected, and a multilayer circuit is obtained. The application prepares the multilayer ceramic circuit board with strong practicability and simple process by utilizing the insulation and heat dissipation properties of the ceramic substrate through processes such as spin coating, laser drilling, photoetching development, pattern electroplating and the like, and improves the packaging integration level.
Description
Technical Field
The application belongs to the technical field of electronic packaging, and particularly relates to a structure of a multilayer ceramic circuit board and a preparation method thereof.
Background
The electronic information industry, one of the pillar industries developed in the current society, greatly changes people's lifestyle. Under the guidance of moore's law, the functions of various electronic products are developed towards high operation speed, high performance and high integration level. The feature sizes of integrated circuit components and devices that play a central role are continuously reduced, and the gate delays are correspondingly reduced, but the time delay problem caused by the interconnection between modules is increasingly remarkable. In the process of packaging chips and micro-nano structures on a substrate, the chip and micro-nano structures are limited by the size of the substrate on one hand and the connection requirement of wires on the other hand, and the length of the interconnection wires is generally selected to be greatly increased to meet the functional requirement. Therefore, the circuit structure and the semiconductor component arrangement strategy are designed in a multilayer stacking mode, the traditional two-dimensional layout can be expanded to a three-dimensional layout, the degree of freedom of circuit design is greatly increased, parasitic capacitance is reduced, the overall signal exchange performance of the circuit is improved, and related application requirements are met.
At present, there are two main types of multi-layer circuit integrated structures: an embedded rewiring layer (RDL) and a Through Silicon Via (TSV) bond interconnect. The rewiring technology is widely applied to manufacturing of Printed Circuit Boards (PCBs), and the purpose of improving the density of devices on the surface of the PCB is achieved by arranging element connecting wires in multiple layers. The process has high maturity and low cost, but the rewiring layer can not be used for arranging the circuit because of being capable of placing independent components, so that the density of the components is greatly limited to be further improved. The three-dimensional integrated circuit is manufactured by using a silicon through hole bonding technology, is an integrated circuit process structure which is rapidly developed at present, and realizes the electrical and mechanical interconnection between different circuit layers by etching through holes on a silicon wafer and filling the through holes, thereby achieving the complete and reliable three-dimensional layout effect of the circuit. However, the process has the advantages of higher difficulty, higher cost and no feasibility due to a circuit structure with lower corresponding precision requirements; on the other hand, the three-dimensional structure performance is improved, the heat productivity is greatly improved, and the silicon substrate is stacked, so that the troublesome heat dissipation problem exists.
In view of the above problems, the present application proposes to use a ceramic substrate as a substrate of a multilayer circuit structure, thereby improving the overall heat dissipation performance of the device. And the two sides of the ceramic substrate are subjected to electroplating patterning, and interconnection is formed through the vertical through holes, so that the structure is simple. The isolation layer is formed by coating high-heat-conductivity insulating glue by using a spin coating process, so that the reliability and the heat conductivity of the device are improved; the isolation layer interconnection through hole is prepared by utilizing the through hole technology, and then the interconnection channel is formed after electroplating and deposition, so that the interlayer interconnection cost is reduced, and the overall manufacturing speed of the device is improved. The patterned circuit is prepared by a semiconductor micromachining technology, and the laminated circuit is formed by the vertical through holes, so that the original multilayer circuit manufacturing process is simplified.
Disclosure of Invention
Aiming at the requirements of high performance and multifunctional monolithic integration, the application provides a structure of a multilayer ceramic circuit board and a preparation process thereof, which solve the problems of low yield and the like caused by insufficient heat dissipation capacity and complex process of the existing multilayer circuit board, are compatible with the existing integrated circuit process, and realize rapid and mass production.
In order to achieve the aim of the application, the technical scheme of the application is as follows:
a multilayer ceramic circuit board is formed by combining a layer of ceramic substrate, a plurality of layers of isolation layers, vertical through holes and a patterned circuit; the upper and lower surfaces of the ceramic substrate are plated with a patterning circuit, vertical through holes penetrating through the upper and lower surfaces are arranged in the patterning circuit, and metal copper columns are filled in the through holes; the surface of the ceramic substrate is coated with heat-resistant insulating glue through a spin coating process, an isolation layer is formed after heating and curing, and a graphical circuit is manufactured on the surface of the isolation layer; the isolating layer contains vertical through holes and is filled with metal copper columns, so that the ceramic substrate and the isolating layer are electrically interconnected, and a multilayer circuit is manufactured.
In the multilayer ceramic substrate and the preparation method thereof, the ceramic substrate is a direct-plated ceramic substrate (DPC) and can be one or more of aluminum oxide, aluminum nitride and silicon nitride. The upper surface of the ceramic substrate is provided with a circuit layer which is interconnected with the isolation layer, and the lower surface of the ceramic substrate is provided with a circuit layer which is connected with an external circuit.
Further, the DPC substrate surface circuit layer is prepared by a semiconductor micro-processing technology, the thickness is 10-300 mu m, and the diameter of the vertical through hole is 60-120 mu m.
In the multilayer ceramic substrate and the preparation method thereof, the surface of the ceramic substrate is coated with heat-resistant insulating glue through a spin coating process, an isolation layer is formed after heating and curing, and a graphical circuit is manufactured on the surface of the isolation layer. The isolation layer contains vertical through holes and is filled with metal copper columns.
Further, the heat-resistant insulating adhesive is one of Polyimide (PI), liquid crystal resin (LCP) and ABF, and is formed into a film by low-speed spin coating, and then is heated and cured at the curing temperature of 100-300 ℃ for 1-3 hours, and the thickness of the cured film is 50-150 mu m.
Further, the vertical through holes of the isolation layer are prepared by adopting a laser drilling or photoetching/developing/etching process, and the diameter of the vertical through holes is 100-300 mu m.
Further, the vertical through holes in the isolation layer are filled by adopting an electroplating process, and electroplated copper is carried out by using the upper layer of bonding pad as a seed layer until the through holes are filled.
In the multilayer ceramic circuit board and the preparation method thereof, the isolation layer is thinned by using a grinding process after the vertical through holes are filled, so that the surface quality and the flatness of the isolation layer are controlled, and the thickness of the thinned circuit layer is 10-300 mu m.
Further, the preparation method of the multilayer ceramic circuit board specifically comprises the following steps:
1) Coating heat-resistant insulating glue on the surface of the DPC ceramic substrate as an isolation layer;
2) Preparing a vertical through hole in the isolation layer by adopting a laser drilling or photoetching/developing/etching process;
3) Deoiling, decontaminating and drying the surface of the isolation layer;
4) Depositing a metal titanium layer and a copper layer on the surface of the isolation layer by a sputtering process to serve as seed layers, wherein the thickness of the titanium layer is 100-200nm, and the thickness of the copper layer is 300-1000nm;
5) Coating photoresist on the surface of the metal layer, preparing a patterned circuit through exposure, development, etching and electroplating processes, and grinding and flattening;
6) Removing the residual photoresist and the redundant seed layer;
7) And (3) surface treatment, namely, preventing the oxidation of the circuit layer and finishing the preparation.
In the multilayer ceramic circuit board and the preparation method thereof, the DPC ceramic substrate and the isolation layer circuit are both prepared by the semiconductor micro-processing technology, the pattern is easy to design and process, and the number of circuit layers is increased by repeatedly coating new isolation layers on the isolation layers and preparing the patterned circuit, so that the integration level of the ceramic circuit board is increased.
In summary, compared with the existing manufacturing method, the application has the following advantages:
1) The DPC ceramic substrate is used as a multilayer circuit substrate, and has the advantages of high heat conductivity, mature process technology and the like. The heat dissipation strength of the device can be improved by utilizing the high heat conduction capability of the ceramic material; on the other hand, the DPC substrate has higher pattern precision and can be matched with the isolation layer circuit precision.
2) The application uses spin coating technology to coat the isolation layer insulating glue. The whole ceramic substrate can be fully paved by the heat-resistant insulating adhesive by utilizing the spin coating process, so that the surface is uniform and flat, and the preparation of a subsequent isolation layer graphical circuit is facilitated.
3) The application fills the vertical through holes in an electroplating mode, skillfully utilizes the formed interconnection pads under the through holes as electroplating seed layers, and realizes the positioning growth of interconnection metals.
4) The application uses the semiconductor micro-processing technology to prepare the patterned circuit on the isolation layer, has high precision and good quality, and increases the integration level of the multilayer circuit board.
5) The application provides a ceramic substrate which is used as a substrate with a multilayer circuit structure, and the overall heat dissipation performance of the device is improved. And the two sides of the ceramic substrate are subjected to electroplating patterning, and interconnection is formed through the vertical through holes, so that the structure is simple. The isolation layer is formed by coating high-heat-conductivity insulating glue by using a spin coating process, so that the reliability and the heat conductivity of the device are improved; the isolation layer interconnection through hole is prepared by utilizing the through hole technology, and then the interconnection channel is formed after electroplating and deposition, so that the interlayer interconnection cost is reduced, and the overall manufacturing speed of the device is improved. The patterned circuit is prepared by a semiconductor micromachining technology, and the laminated circuit is formed by the vertical through holes, so that the original multilayer circuit manufacturing process is simplified.
Drawings
Fig. 1 is a cross-sectional view of a multilayer ceramic circuit board according to an embodiment of the present application.
Fig. 2 is a flowchart of a process for manufacturing the multilayer ceramic circuit board shown in fig. 1.
Fig. 3 is a cross-sectional view of a portion of the multilayer ceramic circuit board shown in fig. 1, which is separated from the through-hole.
The same reference numerals are used to denote the same structures throughout the figures, wherein: 1. 4, 7, 10-graphic circuit layers; 3. 6-insulating adhesive isolation layers; 2. 5, 9-conducting copper columns; 8-a ceramic substrate; 11-metal sputtered layer.
Detailed Description
The present application will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present application more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. In addition, the technical features of the embodiments of the present application described below may be combined with each other as long as they do not collide with each other.
Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
The terms "comprising," "including," "having," "containing," or any other variation thereof, as used herein, are intended to cover a non-exclusive inclusion. For example, a composition, step, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but may include other elements not expressly listed or inherent to such composition, step, method, article, or apparatus.
The phrase "consisting of …" excludes any unspecified element, step or component. If used in a claim, such phrase will cause the claim to be closed, such that it does not include materials other than those described, except for conventional impurities associated therewith. When the phrase "consisting of …" appears in a clause of the claim body, rather than immediately following the subject, it is limited to only the elements described in that clause; other elements are not excluded from the stated claims as a whole.
When an equivalent, concentration, or other value or parameter is expressed as a range, preferred range, or a range bounded by a list of upper preferable values and lower preferable values, this is to be understood as specifically disclosing all ranges formed from any pair of any upper range limit or preferred value and any lower range limit or preferred value, regardless of whether ranges are separately disclosed. For example, when ranges of "1 to 5" are disclosed, the described ranges should be construed to include ranges of "1 to 4", "1 to 3", "1 to 2 and 4 to 5", "1 to 3 and 5", and the like. When a numerical range is described herein, unless otherwise indicated, the range is intended to include its endpoints and all integers and fractions within the range.
In some examples, the approximating language may correspond to the precision of an instrument for measuring the value. In the description and claims of the application, the range limitations may be combined and/or interchanged. These ranges include all subranges subsumed therebetween, if not otherwise stated.
The indefinite articles "a" and "an" preceding an element or component of the application are not limited to the requirement (i.e. the number of occurrences) of the element or component. Thus, the use of "a" or "an" should be interpreted as including one or at least one, and the singular reference of an element or component includes the plural reference unless the amount clearly dictates otherwise.
The description of the terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., herein describe means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms are not necessarily for the same embodiment or example. The technical features of the respective embodiments of the present application may be combined with each other as long as they do not collide with each other.
The materials and equipment used in the present application are commercially available or are those commonly used in the art, and the methods described in the examples are those commonly used in the art unless otherwise specified.
The present application will be further described with reference to the process flow of fig. 2 in combination with the multilayer ceramic circuit board structure of fig. 1 and the isolation layer via structure of fig. 3.
The multilayer ceramic circuit board is formed by overlapping a ceramic substrate 8 and isolation layers 3 and 6, and the like, wherein the upper surface and the lower surface of the ceramic substrate 8 are plated with patterned circuits 7 and 10, vertical through holes penetrating through the upper surface and the lower surface are arranged in the patterned circuits, and metal copper columns 9 are filled in the vertical through holes. The surface of the ceramic substrate 8 is coated with heat-resistant insulating glue by a spin coating process, an isolation layer 6 is formed after heating and curing, and a patterned circuit 4 is manufactured on the surface of the isolation layer. The isolating layer contains through holes and is filled with metal copper columns 5, so that electric interconnection between the ceramic substrate and the isolating layer is realized, then the steps are repeated, insulating glue is coated on the isolating layer 6 in a spin mode, the isolating layer 3 is obtained through heating and solidification, the through holes are formed in the isolating layer, the copper columns 2 are filled, and the patterned circuit 1 is formed on the surface of the isolating layer, so that the multilayer circuit board is obtained.
In the multilayer ceramic circuit board structure and the preparation method of the application, the ceramic substrate is a direct-plating ceramic substrate (DPC), the material is preferably aluminum nitride, and the thermal expansion coefficient is 4.4 multiplied by 10 -6 Heat conductivity is 180W/(m.k), and substrate thickness is 500 μm; the upper surface of the ceramic substrate is provided with a circuit layer 7 which is interconnected with the isolation layer, the lower surface of the ceramic substrate is provided with a circuit layer 10 which is connected with an external circuit, and copper columns 9 which are communicated with the upper surface and the lower surface of the ceramic substrate are prepared by a semiconductor micromachining technology. The circuit layer thickness in this embodiment is 80 μm and the vertical via diameter is 100 μm.
In the multilayer ceramic circuit board structure and the preparation method thereof of the application, theThe surface of the ceramic substrate is coated with heat-resistant insulating glue through a spin coating process. In this embodiment, the insulating paste is PI (polyimide), the viscosity is 5000cp, and the thermal expansion coefficient is 3.5X10 -5 and/C. Forming an isolation layer 6 after PI heating and solidifying, and manufacturing a graphical circuit 4 on the surface of the isolation layer; the isolation layer contains a through hole and is filled with a metal copper column 5. In this example, the PI heat curing temperature was 70 ℃, 110 ℃, 150 ℃, 200 ℃ and 250 ℃ in this order, and each temperature was heated for 30 minutes, to obtain an isolation layer thickness of 80. Mu.m. In the embodiment, the isolation layer through holes are prepared by using a laser drilling mode, the laser is a carbon dioxide laser with the wavelength of 10.6 mu m, the isolation layer can be selectively ablated only, and the through holes are formed and then electroplated and filled, so that interlayer electrical connection is realized. The diameter of the through hole in this example was 300. Mu.m.
The method of preparing the isolation layer and realizing the interlayer interconnection is further described with reference to the process flow of fig. 2 and the cross-sectional view of the portion of the multilayer ceramic circuit board in fig. 3 where the isolation layer is through-hole.
In this embodiment, a laser is used to punch the isolation layer coated on the ceramic substrate, the DPC ceramic substrate patterned circuit layer 7 is used as a seed layer, and an electroplating process is used to electroplate the through hole in the isolation layer, so as to obtain the conductive copper pillar 5. And (3) thinning the circuit layer by using a grinding process after the through holes are filled, controlling the surface quality and the flatness of the isolation layer, and enabling the thickness of the circuit layer to be 50 mu m after thinning.
Further, the step of preparing the patterned circuit 4 on the surface of the isolation layer 6 in this embodiment includes:
1) The surface of the isolation layer 6 is treated by degreasing, decontamination and drying;
2) Sputtering a metal seed layer 11 on the surface of the isolation layer 6 by magnetron sputtering, and sputtering a layer of metal titanium and a layer of metal copper successively, wherein the thickness of the titanium layer is 100nm, and the thickness of the copper layer is 400nm;
3) Pasting a dry film or coating photoresist on the surface of the seed layer 11, preparing a patterned circuit 4 through exposure, development, etching and electroplating processes, and grinding to be flat to obtain a circuit layer with the thickness of 80 mu m;
4) Removing the residual photoresist and the redundant seed layer;
5) And (3) surface treatment, namely, preventing the oxidation of the circuit layer and finishing the preparation.
In the multilayer ceramic circuit board structure and the preparation method thereof, the isolation layer is formed by spin coating insulating glue on the surface of the substrate, interlayer electric interconnection is formed by laser drilling and electroplating filling, and a patterned circuit is prepared on the isolation layer, so that each layer of circuit has independent functions and can be mutually communicated and interconnected. The DPC ceramic substrate and the isolation layer patterning circuit are both manufactured through semiconductor micromachining, the patterns are easy to design and process, the number of lamination layers is increased through repeatedly coating a new isolation layer on the isolation layer and preparing the patterning circuit, and a multilayer circuit with more layers is manufactured, so that the integration level of the multilayer circuit board is improved.
The above embodiments are provided to illustrate the technical concept and features of the present application and are intended to enable those skilled in the art to understand the present application and implement the same, and are not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A multilayer ceramic circuit board, characterized in that: the device consists of a ceramic substrate, a plurality of layers of isolation layers, vertical through holes and a patterning circuit; the upper and lower surfaces of the ceramic substrate are plated with a patterning circuit, vertical through holes penetrating through the upper and lower surfaces are contained in the patterning circuit, and metal copper columns are filled in the vertical through holes; the surface of the ceramic substrate is coated with heat-resistant insulating glue through a spin coating process, an isolation layer is formed by heating and curing, and a graphical circuit is manufactured on the surface of the isolation layer; the isolating layer contains vertical through holes and is filled with metal copper columns, so that the ceramic substrate and the isolating layer are electrically interconnected, and the multilayer ceramic circuit board is obtained.
2. A multilayer ceramic circuit board according to claim 1, wherein: the ceramic substrate is a direct-electroplating ceramic substrate (DPC) and is made of aluminum oxide or aluminum nitride; the upper surface of the ceramic substrate is provided with a circuit layer which is interconnected with the isolation layer, the lower surface of the ceramic substrate is provided with a circuit layer which is connected with an external circuit, and the thickness of the ceramic substrate is 100-1000 mu m.
3. A multilayer ceramic circuit board according to claim 2, wherein: the DPC substrate surface circuit layer is prepared by a semiconductor micro-processing technology, the thickness is 10-300 mu m, and the diameter of the vertical through hole is 60-120 mu m.
4. A multilayer ceramic circuit board according to claim 1, wherein: the surface of the ceramic substrate is coated with heat-resistant insulating glue through a spin coating process, an isolation layer is formed after heating and curing, and a graphical circuit is manufactured on the surface of the isolation layer; the isolation layer contains vertical through holes and is electroplated and filled with metal copper columns.
5. The multilayer ceramic circuit board of claim 4, wherein: the heat-resistant insulating adhesive is one of Polyimide (PI), liquid crystal resin (LCP) and ABF.
6. A multilayer ceramic circuit board according to any one of claims 4-5, wherein: the isolation layer is formed by spin coating thermal insulation glue at a low speed, and then heating and curing, wherein the curing temperature is 100-300 ℃, the curing time is 1-3 hours, and the thickness after curing is 50-150 mu m.
7. A method for producing a multilayer ceramic circuit board according to any one of claims 1 to 6, comprising:
1) Coating heat-resistant insulating glue on the surface of the DPC ceramic substrate as an isolation layer;
2) Preparing a vertical through hole in the isolation layer by adopting a laser drilling or photoetching/developing/etching process;
3) Deoiling, decontaminating and drying the surface of the isolation layer;
4) Depositing a metal titanium layer and a copper layer on the surface of the isolation layer by a sputtering process to serve as seed layers, wherein the thickness of the titanium layer is 100-200nm, and the thickness of the copper layer is 300-1000nm;
5) Coating photoresist on the surface of the metal layer, preparing a patterned circuit through exposure, development, etching and electroplating processes, and grinding and flattening;
6) Removing the residual photoresist and the redundant seed layer;
7) And (3) carrying out surface treatment to prevent the oxidation of the circuit layer and obtain the multilayer ceramic circuit board.
8. The method for manufacturing a multilayer ceramic circuit board according to claim 7, wherein: and the diameter of the vertical through hole in the isolation layer is 100-300 mu m, and the vertical through hole is filled by adopting an electrolytic copper plating process until the through hole is filled.
9. The method for manufacturing a multilayer ceramic circuit board according to claim 7, wherein: and after the vertical through holes are filled, thinning the isolation layer by using a grinding process to control the surface quality and the flatness of the isolation layer, wherein the thickness of the thinned circuit layer is 10-300 mu m.
10. A method of producing a multilayer ceramic circuit board according to any one of claims 7 to 9, characterized in that: the DPC ceramic substrate and the isolation layer patterning circuit are both manufactured through semiconductor micromachining, the patterns are easy to design and process, and the number of circuit layers is increased by repeatedly coating the isolation layer on the isolation layer and preparing the patterning circuit, so that the integration level of the circuit board is increased.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310879924.2A CN116916526A (en) | 2023-07-18 | 2023-07-18 | Multilayer ceramic circuit board structure and preparation method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310879924.2A CN116916526A (en) | 2023-07-18 | 2023-07-18 | Multilayer ceramic circuit board structure and preparation method thereof |
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| CN116916526A true CN116916526A (en) | 2023-10-20 |
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| CN202310879924.2A Pending CN116916526A (en) | 2023-07-18 | 2023-07-18 | Multilayer ceramic circuit board structure and preparation method thereof |
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| Country | Link |
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| CN (1) | CN116916526A (en) |
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- 2023-07-18 CN CN202310879924.2A patent/CN116916526A/en active Pending
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