CN114188300A - Thin film and thick film hybrid integrated ceramic substrate and preparation method thereof - Google Patents
Thin film and thick film hybrid integrated ceramic substrate and preparation method thereof Download PDFInfo
- Publication number
- CN114188300A CN114188300A CN202111467922.XA CN202111467922A CN114188300A CN 114188300 A CN114188300 A CN 114188300A CN 202111467922 A CN202111467922 A CN 202111467922A CN 114188300 A CN114188300 A CN 114188300A
- Authority
- CN
- China
- Prior art keywords
- ceramic substrate
- thin film
- layer
- film
- thick
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000919 ceramic Substances 0.000 title claims abstract description 116
- 239000000758 substrate Substances 0.000 title claims abstract description 114
- 239000010409 thin film Substances 0.000 title claims abstract description 88
- 239000010408 film Substances 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000000034 method Methods 0.000 claims abstract description 56
- 230000008569 process Effects 0.000 claims abstract description 48
- 229910052751 metal Inorganic materials 0.000 claims abstract description 39
- 239000002184 metal Substances 0.000 claims abstract description 39
- 238000009713 electroplating Methods 0.000 claims abstract description 13
- 229910001128 Sn alloy Inorganic materials 0.000 claims abstract description 12
- JVPLOXQKFGYFMN-UHFFFAOYSA-N gold tin Chemical compound [Sn].[Au] JVPLOXQKFGYFMN-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 102
- 230000004888 barrier function Effects 0.000 claims description 16
- 238000004519 manufacturing process Methods 0.000 claims description 14
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052802 copper Inorganic materials 0.000 claims description 12
- 239000010949 copper Substances 0.000 claims description 12
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical group [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 238000001259 photo etching Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000004544 sputter deposition Methods 0.000 claims description 5
- 239000002335 surface treatment layer Substances 0.000 claims description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical group [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 4
- 230000005540 biological transmission Effects 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 239000010936 titanium Substances 0.000 claims description 4
- 230000001680 brushing effect Effects 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 125000004122 cyclic group Chemical group 0.000 claims description 3
- 238000005553 drilling Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000005429 filling process Methods 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 229920002120 photoresistant polymer Polymers 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 230000003746 surface roughness Effects 0.000 claims description 3
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 claims description 2
- 239000011229 interlayer Substances 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000005498 polishing Methods 0.000 claims description 2
- 239000004642 Polyimide Substances 0.000 claims 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims 2
- 229920001721 polyimide Polymers 0.000 claims 2
- 229910015363 Au—Sn Inorganic materials 0.000 claims 1
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 238000000151 deposition Methods 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 238000005459 micromachining Methods 0.000 claims 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 claims 1
- 239000011148 porous material Substances 0.000 claims 1
- 238000004381 surface treatment Methods 0.000 claims 1
- 230000010354 integration Effects 0.000 abstract description 13
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 230000006872 improvement Effects 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
- H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
- H05K1/0219—Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Ceramic Engineering (AREA)
- Electromagnetism (AREA)
- Geometry (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Optics & Photonics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The invention discloses a thin film/thick film hybrid integrated ceramic substrate, which specifically comprises a thin film ceramic substrate prepared by a semiconductor thin film process and a thick film ceramic substrate prepared by a pattern electroplating process, wherein the thin film ceramic substrate and the thick film ceramic substrate share the same ceramic substrate and are electrically connected through a surface metal layer. The thin film ceramic substrate contains a thin film multilayer wiring, a metal through hole and a gold-tin alloy layer and is used as a digital/control circuit of a resistor, an inductor, a capacitor and the like; the thick film ceramic substrate comprises a thick metal layer and a metal through hole and is used for packaging a power device. The invention also discloses a preparation method of the thin film/thick film hybrid integrated ceramic substrate. According to the invention, the thin film and pattern electroplating process is implemented on the same ceramic substrate, so that the mixed integration of the thin film/thick film ceramic substrate is realized, and the integration level and the reliability of the device are improved.
Description
Technical Field
The invention belongs to the related field of electronic packaging technology, and particularly relates to a ceramic substrate and a preparation method thereof.
Background
The ceramic material has the advantages of high thermal conductivity, good heat resistance, high insulation, high strength, small thermal expansion coefficient, corrosion resistance, radiation resistance and the like, is very suitable for manufacturing a packaging heat dissipation substrate, and is widely applied to electronic component packaging. The ceramic substrate (ceramic circuit board) is composed of a ceramic substrate and a metal circuit layer (distributed on the surface and in a through hole), and can be divided into a thin film ceramic substrate and a thick film ceramic substrate according to the thickness of the circuit layer. The thin film ceramic substrate is prepared by a semiconductor thin film process, has the advantages of high wiring density (small line width/line distance), high pattern precision, high integration level and the like, and is only suitable for small-current occasions (such as passive devices) due to the small thickness of a circuit layer. On the contrary, the thick film ceramic substrate can be used in the heavy current and high power load occasions due to the larger thickness of the circuit layer, but the existing thick film ceramic substrate (such as a thick film printed ceramic substrate, a direct bonding ceramic substrate and the like) has the problems of low pattern precision, high temperature process and the like.
With the continuous development of semiconductor technology, electronic components are gradually developed in the directions of high power, miniaturization, integration, multifunction and the like, and higher requirements are also put on the performance of ceramic substrates for packaging, including thin film and thick film hybrid integration, high pattern precision, miniaturization and the like. However, the ceramic substrate prepared based on the thin film and thick film processes has large differences in film thickness, line width/line distance, wiring accuracy and the like, so that power devices and passive devices in a system need to be integrated after being packaged on different types of ceramic substrates, and module signal electromagnetic shielding, transmission efficiency, integration density improvement and packaging size reduction are limited. More importantly, the existing thin film and thick film ceramic substrate preparation processes are incompatible (low-temperature and high-temperature processes) and are difficult to mix and integrate, and the integration and interconnection of the thin film and the thick film ceramic substrate must adopt a wire bonding mode, so that the reliability of the device is influenced. Therefore, it is necessary to develop a novel ceramic substrate, and perform a thin film and pattern plating process on the same ceramic substrate to realize hybrid integration of thin film/thick film ceramic substrates, thereby improving device integration and reliability.
Disclosure of Invention
Aiming at the defects or improvement requirements of the prior art, the invention provides a thin film/thick film hybrid integrated ceramic substrate and a preparation method thereof, and the thin film circuit and the thick film circuit are integrated on the same ceramic substrate. The advantages of good heat conduction/heat resistance, high graphic precision, vertical interconnection, compatibility with thin film technology and the like of the electroplated ceramic substrate (DPC) are exerted, and the function/volume ratio and the reliability of the system module are effectively improved.
Correspondingly, the invention provides a thin film/thick film hybrid integrated ceramic substrate, which comprises a thin film ceramic substrate prepared by a semiconductor thin film process and a thick film ceramic substrate prepared by a pattern electroplating process, wherein the thin film ceramic substrate and the thick film ceramic substrate share the same ceramic substrate and are electrically connected through a surface metal layer, the thin film ceramic substrate comprises a thin film multilayer wiring layer, a metal through hole and a gold-tin alloy layer, and the thick film ceramic substrate comprises a thick metal layer and a metal through hole.
More preferably, the thin film multilayer wiring structure of the thin film ceramic substrate is in the form of a wiring layer/a dielectric film/a wiring layer, the number of wiring layers is more than 2, the thickness of the thin film is 0.1 to 1 μm, preferably 0.2 μm, the dielectric film is used as interlayer insulation, and the material is PI or BCB.
Preferably, the thick metal layer of the thick film ceramic substrate comprises a seed layer, a circuit layer and a surface treatment layer, wherein the seed layer is titanium or chromium nickel, the circuit layer is copper, the surface treatment layer is nickel gold, and the total thickness is 30-300 μm, preferably 60-100 μm.
Preferably, the metal through holes of the ceramic substrate are used as heat flow transmission channels, electromagnetic shields and upper and lower layer electrical interconnections, the aperture of the metal through hole of the thin film region is 60-100 μm, the aperture of the metal through hole of the thick film region is 120-180 μm, and the material is copper.
Correspondingly, the invention also provides a preparation method of the thin film/thick film hybrid integrated ceramic substrate, which comprises the following steps:
(a) preparing a plurality of metal through holes on the ceramic substrate by adopting a laser drilling and electroplating hole filling process;
(b) manufacturing a patterned seed layer on a ceramic substrate by a sputtering coating process, and manufacturing a barrier layer 1 on the ceramic substrate by adopting photoetching and developing processes;
(c) preparing a thin film multilayer wiring on an unblocked area on a ceramic substrate by adopting a semiconductor processing technology;
(d) removing the barrier layer 1 by adopting a wet etching process, and manufacturing a barrier layer 2 on the thin film multilayer wiring by adopting photoetching and developing processes;
(e) preparing a circuit layer on the unblocked area on the ceramic substrate through an electroplating process;
(f) improving the flatness of the circuit layer by utilizing a surface grinding process, and manufacturing a nickel layer on the surface of the circuit layer by utilizing a chemical nickel-gold process;
(g) removing the barrier layer 2 by adopting a wet etching process, and preparing a gold-tin alloy layer on the thin film multilayer wiring by adopting an electroplating or sputtering process;
(h) and (3) obtaining the thin film thick film hybrid integrated ceramic substrate through a film removing/etching process.
More preferably, in steps (b) and (d), the barrier layer 1 is used for protecting a thick film ceramic substrate region, and the barrier layer 2 is used for protecting a thin film ceramic substrate region, and both are made on a ceramic substrate by spin-on photoresist or dry film pasting.
As a further preferred, in the step (c), the thin film multilayer wiring is to prepare a first wiring layer, spin-coat a dielectric film layer, prepare a second wiring layer, and perform a cyclic operation according to the number of wiring layers.
As a further preference, in step (f), the surface grinding process is numerical control grinding, ceramic brushing or chemical mechanical polishing, and the surface roughness is less than 0.3 μm.
Further preferably, in step (g), the gold-tin alloy layer of the thin film ceramic substrate is used for a high quality patch, and has a square or circular shape and a thickness of 1 to 7 μm, preferably 3 to 5 μm.
In general, compared with various existing packaging substrates, the technical scheme of the invention prepares the thin film/thick film hybrid integrated ceramic substrate by adopting the technology of semiconductor thin film process and pattern electroplating, solves the problem of hybrid integration of power devices and passive devices, and thus remarkably improves the integration level and reliability of electronic systems.
Drawings
FIG. 1 is a schematic diagram of a thin film/thick film hybrid integrated ceramic substrate constructed in accordance with the present invention.
FIG. 2 is a process flow diagram of a method for manufacturing a thin film/thick film hybrid integrated ceramic substrate constructed in accordance with a preferred embodiment.
The reference numbers of the figures illustrate the following:
the structure comprises a ceramic substrate 1, a surface metal layer 2, a thin film multilayer wiring 3, a metal through hole 4, a gold-tin alloy layer 5, a thick metal layer 6 and a metal through hole 7.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.
In view of the above defects or improvement requirements of the conventional ceramic substrate, the main objective of the present invention is to provide a thin film/thick film hybrid integrated ceramic substrate and a method for manufacturing the same, so as to solve the difficult problem of thin film/thick film hybrid integration of the ceramic substrate, and to significantly improve the integration level and reliability of the electronic system.
Specific examples are given below to more clearly explain the process flow, important mechanisms and key process conditions of the present invention in detail.
Examples
Referring to fig. 1, the embodiment provides a thin film/thick film hybrid integrated ceramic substrate, which includes a thin film ceramic substrate prepared by a semiconductor thin film process and a thick film ceramic substrate prepared by a pattern plating process, both share the same ceramic substrate 1, and are electrically connected through a surface metal layer 2; the thin film ceramic substrate comprises a thin film multilayer wiring 3, a metal through hole 4 and a gold-tin alloy layer 5, wherein the thin film multilayer wiring 3 is a wiring layer/a dielectric film/a wiring layer, the number of wiring layers is 3, the thickness of the thin film is 0.2 mu m, the dielectric film is made of PI insulating materials, the gold-tin alloy layer 5 is positioned on the wiring layer, the shape of the gold-tin alloy layer is square, the thickness of the gold-tin alloy layer is 3 mu m, the metal through hole 4 is used for upper and lower layer electrical interconnection and electromagnetic shielding, the material is copper, and the aperture is 80 mu m; the thick film ceramic substrate comprises a thick metal layer 6 and a metal through hole 7, wherein the thick metal layer 6 comprises a seed layer, a circuit layer and a nickel-gold layer, the seed layer is titanium, the circuit layer is copper, the surface treatment layer is nickel-gold, the total thickness is 100 mu m, the metal through hole 7 is used as an upper layer and a lower layer of electric interconnection and heat flow transmission channels, the material is copper, and the aperture is 150 mu m.
Referring to fig. 2, the embodiment further provides a method for preparing a thin film/thick film hybrid integrated ceramic substrate, which may exemplarily comprise the following steps:
step 1, preparing a plurality of defect-free copper metal through holes on a ceramic substrate 1 by adopting laser drilling and electrolytic copper filling processes, wherein the aperture of a metal through hole 4 of a thin film ceramic substrate is 80 microns, and the aperture of a metal through hole 7 of the thin film ceramic substrate is 150 microns;
step 2, manufacturing a graphical seed layer (titanium/copper with the thickness of 0.2 mu m) on the ceramic substrate 1 through a sputtering coating process, spin-coating photoresist on the ceramic substrate 1, and manufacturing a barrier layer 1 by adopting photoetching and developing processes for protecting a thick-film ceramic substrate area;
(c) preparing a thin film multilayer wiring 3 on an unblocked area on a ceramic substrate 1 by adopting a semiconductor processing technology, firstly preparing a first wiring layer, then spin-coating a dielectric film layer, then preparing a second wiring layer, and performing cyclic operation according to the number of wiring layers to prepare 3 layers of thin film wiring;
(d) removing the barrier layer 1 by adopting a wet etching process, pasting a dry film on the ceramic substrate 1, and then manufacturing a barrier layer 2 by adopting photoetching and developing processes for protecting a thin film ceramic substrate area;
(e) preparing a thick copper circuit layer on the unblocked area on the ceramic substrate 1 by a copper electroplating process;
(f) improving the flatness of the circuit layer by using a ceramic brushing and grinding process, wherein the surface roughness is less than 0.3 mu m, and manufacturing a nickel-gold layer on the surface of the circuit layer by using a chemical nickel-gold process to obtain a thick metal layer 6 of the thick-film ceramic substrate, wherein the thickness is 100 mu m;
(g) removing the barrier layer 2 by adopting a wet etching process, and preparing a square gold-tin alloy layer 5 with the thickness of 2 microns on the thin film multilayer wiring 3 by adopting an electroplating process;
(h) and removing the redundant colloid material through a film removing/etching process so as to obtain the thin film thick film hybrid integrated ceramic substrate.
It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the present invention, and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A thin film/thick film hybrid integrated ceramic substrate is characterized by comprising a thin film ceramic substrate prepared by a semiconductor thin film process and a thick film ceramic substrate prepared by a pattern electroplating process, wherein the thin film ceramic substrate and the thick film ceramic substrate share the same ceramic substrate and are electrically connected through a surface metal layer; the thin film ceramic substrate contains a thin film multilayer wiring, a metal via and a gold-tin alloy layer, and the thick film ceramic substrate contains a thick metal layer and a metal via.
2. The thin film/thick film hybrid integrated ceramic substrate according to claim 1, wherein the thin film ceramic substrate has a thin film multilayer wiring structure in the form of a wiring layer/dielectric film/wiring layer, the number of wiring layers is greater than 2, the thin film thickness is 0.1 to 1 μm, the dielectric film is used as interlayer insulation, and the material is Polyimide (PI) or benzocyclobutene (BCB).
3. The thin film/thick film hybrid integrated ceramic substrate of claim 1, wherein the thick metal layer of the thick film ceramic substrate comprises a seed layer, a circuit layer and a surface treatment layer, the seed layer is titanium or chromium nickel, the circuit layer is copper, the surface treatment layer is nickel gold or nickel palladium gold, and the total thickness is 30-300 μm.
4. The thin film/thick film hybrid integrated ceramic substrate as claimed in claim 1, wherein the metal via holes of the ceramic substrate are used as heat flow transmission channels, electromagnetic shield and upper and lower layer electrical interconnection, and are made of copper with a pore size of 50-200 μm.
5. The thin film/thick film hybrid integrated ceramic substrate as claimed in any one of claims 1 to 4, wherein the aperture of the metal through hole in the thin film region is 60-100 μm, and the aperture of the metal through hole in the thick film region is 120-180 μm.
6. A method for preparing a thin/thick film hybrid integrated ceramic substrate according to any one of claims 1 to 5, comprising the steps of:
(a) preparing a plurality of metal through holes on the ceramic substrate by adopting a laser drilling and electroplating hole filling process;
(b) depositing a metal seed layer on the ceramic substrate by a sputtering coating process, and manufacturing a barrier layer 1 on the ceramic substrate by adopting photoetching and developing processes;
(c) preparing a thin film multilayer wiring on an unblocked area on a ceramic substrate by adopting a semiconductor micromachining process;
(d) removing the barrier layer 1 by adopting a wet etching process, and manufacturing a barrier layer 2 on the thin film multilayer wiring by adopting photoetching and developing processes;
(e) preparing a circuit layer on the unblocked area on the ceramic substrate through an electroplating process;
(f) improving the flatness of the circuit layer by using a surface grinding process, and manufacturing a nickel layer on the surface of the circuit layer by using a surface treatment process;
(g) removing the barrier layer 2 by adopting a wet etching process, and preparing a gold-tin alloy layer on the thin film multilayer wiring by adopting an electroplating or sputtering process;
(h) and (3) obtaining the thin film/thick film hybrid integrated ceramic substrate through a film removing/etching process.
7. The method for preparing a thin film/thick film hybrid integrated ceramic substrate according to claim 6, wherein the barrier layer 1 is used for protecting the thick film ceramic substrate region, and the barrier layer 2 is used for protecting the thin film ceramic substrate region, and both are fabricated on the ceramic substrate by spin-on photoresist or dry film pasting.
8. The method for preparing a thin film/thick film hybrid integrated ceramic substrate according to claim 6, wherein the thin film multilayer wiring is prepared by preparing a first wiring layer, spin-coating a dielectric film layer, and then preparing a second wiring layer, and performing a cyclic operation according to the number of wiring layers.
9. The method for preparing a thin film/thick film hybrid integrated ceramic substrate according to claim 6, wherein the surface grinding process is numerical control grinding, ceramic brushing or chemical mechanical polishing, and the surface roughness is less than 0.3 μm.
10. The method for preparing a thin film/thick film hybrid integrated ceramic substrate according to any one of claims 6 to 9, wherein the Au-Sn alloy layer of the thin film ceramic substrate is used for high quality mounting, is positioned on the wiring layer, is square or circular in shape, and has a thickness of 1 to 7 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111467922.XA CN114188300A (en) | 2021-12-03 | 2021-12-03 | Thin film and thick film hybrid integrated ceramic substrate and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111467922.XA CN114188300A (en) | 2021-12-03 | 2021-12-03 | Thin film and thick film hybrid integrated ceramic substrate and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114188300A true CN114188300A (en) | 2022-03-15 |
Family
ID=80542175
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111467922.XA Pending CN114188300A (en) | 2021-12-03 | 2021-12-03 | Thin film and thick film hybrid integrated ceramic substrate and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114188300A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115551195A (en) * | 2022-11-28 | 2022-12-30 | 四川斯艾普电子科技有限公司 | SRD comb spectrum generator based on thick-film multilayer circuit and preparation method thereof |
| CN115551239A (en) * | 2022-11-25 | 2022-12-30 | 四川斯艾普电子科技有限公司 | Thick-film circuit substrate grounding method and thick-film circuit |
| CN115603691A (en) * | 2022-12-15 | 2023-01-13 | 四川斯艾普电子科技有限公司（Cn） | Multilayer thick-film integrated numerical control attenuator and implementation method thereof |
| CN115866936A (en) * | 2023-03-01 | 2023-03-28 | 四川斯艾普电子科技有限公司 | Method for realizing multilayer circuit board by adopting thick-film process |
| CN116031172A (en) * | 2023-01-09 | 2023-04-28 | 上海泽丰半导体科技有限公司 | Manufacturing method of large-size ceramic substrate and large-size ceramic substrate |
-
2021
- 2021-12-03 CN CN202111467922.XA patent/CN114188300A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115551239A (en) * | 2022-11-25 | 2022-12-30 | 四川斯艾普电子科技有限公司 | Thick-film circuit substrate grounding method and thick-film circuit |
| CN115551239B (en) * | 2022-11-25 | 2023-03-14 | 四川斯艾普电子科技有限公司 | Thick-film circuit substrate grounding method and thick-film circuit |
| CN115551195A (en) * | 2022-11-28 | 2022-12-30 | 四川斯艾普电子科技有限公司 | SRD comb spectrum generator based on thick-film multilayer circuit and preparation method thereof |
| CN115551195B (en) * | 2022-11-28 | 2023-03-14 | 四川斯艾普电子科技有限公司 | Thick-film multilayer circuit based SRD comb spectrum generator and preparation method thereof |
| CN115603691A (en) * | 2022-12-15 | 2023-01-13 | 四川斯艾普电子科技有限公司（Cn） | Multilayer thick-film integrated numerical control attenuator and implementation method thereof |
| CN115603691B (en) * | 2022-12-15 | 2023-02-17 | 四川斯艾普电子科技有限公司 | Multilayer thick-film integrated numerical control attenuator and implementation method thereof |
| CN116031172A (en) * | 2023-01-09 | 2023-04-28 | 上海泽丰半导体科技有限公司 | Manufacturing method of large-size ceramic substrate and large-size ceramic substrate |
| CN116031172B (en) * | 2023-01-09 | 2024-02-13 | 上海泽丰半导体科技有限公司 | Manufacturing method of large-size ceramic substrate and large-size ceramic substrate |
| CN115866936A (en) * | 2023-03-01 | 2023-03-28 | 四川斯艾普电子科技有限公司 | Method for realizing multilayer circuit board by adopting thick-film process |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN114188300A (en) | Thin film and thick film hybrid integrated ceramic substrate and preparation method thereof | |
| US6400573B1 (en) | Multi-chip integrated circuit module | |
| US5601678A (en) | Method for providing electrical interconnections between adjacent circuit board layers of a multi-layer circuit board | |
| US5306670A (en) | Multi-chip integrated circuit module and method for fabrication thereof | |
| US8492870B2 (en) | Semiconductor package with interconnect layers | |
| US5765279A (en) | Methods of manufacturing power supply distribution structures for multichip modules | |
| US5262351A (en) | Process for manufacturing a multilayer integrated circuit interconnection | |
| JP3112059B2 (en) | Thin film multilayer wiring board and method of manufacturing the same | |
| US9048242B2 (en) | Semiconductor device manufacturing method, semiconductor device, and wiring board | |
| EP0332559A2 (en) | Method of manufacturing a substrate for carrying and electrically interconnecting electronic devices | |
| JPH10214920A (en) | Improved type polytetrafluoroethylene thin film chip carrier | |
| EP0425607A1 (en) | High-density, multi-level interconnects, flex circuits, and tape for tab | |
| KR101470885B1 (en) | Multilayer electronic structure with integral metal core | |
| CN105307382A (en) | Printed circuit board and method of manufacturing the same | |
| JP2006210911A (en) | Capacitor material used in circuit board, circuit board utilizing said capacitor material, method of manufacturing circuit board, and information processing system utilizing circuit board | |
| WO1993012539A1 (en) | Thermal transfer posts for high density multichip substrates and formation method | |
| TW201506969A (en) | Thin film capacitor embedded in polymer dielectric | |
| JP2000512083A (en) | Multilayer circuit having via matrix interlayer connection and method of manufacturing the same | |
| JPH04234198A (en) | Multilayer circuit device and manufacture | |
| US5568682A (en) | Orthogonal grid circuit interconnect method | |
| CN101683003B (en) | Manufacturing method of the thin film ceramic multi layer substrate | |
| JP2003031945A (en) | Wiring board, manufacturing method therefor and electric circuit assembly | |
| JP7069711B2 (en) | A wiring board and a semiconductor device having a wiring board | |
| EP0510049A1 (en) | A method for manufacturing of mineature impedance matched interconnection patterns | |
| CN113990763A (en) | Chip packaging structure based on electroforming technology and packaging method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |