CN116913960A - Single particle resistant P-GaN transistor with buried layer structure and preparation method thereof - Google Patents

Single particle resistant P-GaN transistor with buried layer structure and preparation method thereof Download PDF

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Publication number
CN116913960A
CN116913960A CN202310843353.7A CN202310843353A CN116913960A CN 116913960 A CN116913960 A CN 116913960A CN 202310843353 A CN202310843353 A CN 202310843353A CN 116913960 A CN116913960 A CN 116913960A
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layer
nitride
buried
doped buried
doped
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赵胜雷
张嘎
张进成
张怡忱
游淑珍
于龙洋
张苇杭
郝跃
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT

Abstract

The embodiment of the application relates to the technical field of semiconductor devices, in particular to an anti-single particle P-GaN transistor with a buried layer structure and a preparation method thereof, wherein the transistor comprises the following components: the semiconductor device comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a nitride layer and a passivation layer, wherein at least one doped buried layer is positioned in the buffer layer, and a grid electrode is positioned on the nitride layer; the source electrode and the drain electrode respectively form ohmic contact with the barrier layer; the nitride layer is positioned between the source electrode and the drain electrode, and the passivation layer is positioned between the source electrode and the nitride layer and between the nitride layer and the drain electrode; the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer; the bottom of the gate forms an ohmic or schottky contact with the nitride layer. The embodiment of the application can solve the problem of electric field concentration of the traditional P-type nitride gate HEMT device, and can absorb electrons and holes generated after single particle incidence more quickly, thereby improving the breakdown voltage and burning voltage of the device.

Description

Single particle resistant P-GaN transistor with buried layer structure and preparation method thereof
Technical Field
The embodiment of the application relates to the technical field of semiconductor devices, in particular to an anti-single particle P-GaN transistor with a buried layer structure and a preparation method thereof.
Background
Gallium nitride (GaN) is a representation of third generation semiconductor materials, has a wider forbidden band width and higher critical breakdown field strength than silicon or gallium arsenide, and its high electron mobility transistor (High Electron Mobility Transistor, HEMT) exhibits excellent high voltage resistance and is popular in the field of single particle irradiation resistance.
The depletion type GaN-based HEMT device can cause higher switching loss under the condition of no external bias voltage, and meanwhile, additional negative bias voltage is required to maintain a non-working state (off state) so as to increase circuit power consumption, and the current application is greatly limited. In contrast, the enhanced P-type nitride gate HEMT device has a channel turned off without an external bias voltage, and has no power consumption in a state, and is widely adopted by people and is accepted in industry.
When the conventional P-type nitride gate HEMT is voltage-resistant, an electric field is concentrated at one side of the edge of the gate electrode, which is close to the drain electrode, and a very high electric field peak value is formed at the electric field, so that the voltage-resistant capability of the device is reduced. And a large number of electron hole pairs can be generated after the high-energy single particle enters the P-type nitride gate HEMT device, and the higher the electric field intensity is, the worse the single particle characteristic is, so that the performance of the device is degraded or burnt.
Disclosure of Invention
The embodiment of the application provides an anti-single particle P-GaN transistor with a buried layer structure and a preparation method thereof, solves the problem of electric field concentration of a traditional P-type nitride gate HEMT device, can absorb electrons and holes generated after single particle incidence more quickly, and improves breakdown voltage and burning voltage of the device.
In order to solve the above technical problems, an embodiment of the present application provides an anti-single particle P-GaN transistor with a buried layer structure, including: the semiconductor device comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a nitride layer, a passivation layer, at least one doped buried layer and a grid electrode, wherein the nucleation layer, the buffer layer, the channel layer, the barrier layer, the source electrode and the drain electrode are sequentially stacked on the substrate; the source electrode and the drain electrode respectively form ohmic contact with the barrier layer; the nitride layer is positioned between the source electrode and the drain electrode, and the passivation layer is positioned between the source electrode and the nitride layer and between the nitride layer and the drain electrode; the doped buried layer is connected with the source electrode or the drain electrode, the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer; the bottom of the gate forms an ohmic or schottky contact with the nitride layer.
In some exemplary embodiments, the material of the doped buried layer includes one of P-type gallium nitride, P-type aluminum gallium nitride, N-type aluminum nitride, or N-type aluminum gallium nitride.
In some exemplary embodiments, the anti-single particle P-GaN transistor with the buried layer structure includes two doped buried layers, the two doped buried layers are respectively located at two ends of the buffer layer, and the two doped buried layers are respectively connected with the source electrode and the drain electrode.
In some exemplary embodiments, the single-particle-resistant P-GaN transistor with the buried layer structure includes a plurality of doped buried layers spaced apart in a buffer layer; the two doped buried layers are respectively connected with the source electrode and the drain electrode, and the rest of the doped buried layers are distributed between the two doped buried layers at intervals.
In some exemplary embodiments, the material of the nitride layer includes one of P-type gallium nitride, P-type aluminum nitride, or P-type aluminum gallium nitride.
In some exemplary embodiments, the height of the buried doped layer is 1% to 100% of the height of the buffer layer along the direction in which the gate electrode points toward the nitride layer.
In some exemplary embodiments, the doped buried layer has a length of 100nm to 10 μm in a direction in which the source electrode points toward the drain electrode.
In some exemplary embodiments, the spacing between adjacent doped buried layers is 100nm to 10 μm.
In some exemplary embodiments, the single-particle-resistant P-GaN transistor with buried layer structure further includes: an insertion layer for improving carrier mobility, the insertion layer being located between the barrier layer and the channel layer.
On the other hand, the embodiment of the application also provides a preparation method of the single-particle-resistant P-GaN transistor with the buried layer structure, which comprises the following steps: firstly, providing a substrate, and forming a nucleation layer and a buffer layer which are stacked in sequence on the substrate; then, forming a doped buried layer in the buffer layer; the doped buried layer comprises one or more; the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer; sequentially forming a channel layer and a barrier layer on one side of the doped buried layer far away from the bottom surface of the buffer layer; forming a nitride material layer on one side of the barrier layer far away from the channel layer to obtain an epitaxial wafer; etching the nitride material layer to form a nitride layer; manufacturing a mask on the barrier layer to form an ohmic window so as to form a source electrode and a drain electrode; forming a mask on the barrier layer and the nitride layer to form a gate window so as to form a gate; forming a passivation material layer over the barrier layer, the source electrode, the drain electrode, and the gate electrode; and opening holes on the passivation material layers above the source electrode, the drain electrode and the grid electrode, and leading out electrodes to obtain the transistor.
The technical scheme provided by the embodiment of the application has at least the following advantages:
aiming at the problem that the performance of a traditional P-type nitride gate HEMT device is degraded or burnt due to the concentration of an electric field of the HEMT device, the embodiment of the application provides a single-particle-resistant P-GaN transistor with a buried layer structure and a preparation method thereof, and the transistor comprises the following steps: the semiconductor device comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a nitride layer, a passivation layer and at least one doped buried layer, wherein the nucleation layer, the buffer layer, the channel layer, the barrier layer, the source electrode, the drain electrode, the nitride layer and the passivation layer are sequentially stacked on the substrate; the source electrode and the drain electrode respectively form ohmic contact with the barrier layer; the nitride layer is positioned between the source electrode and the drain electrode, and the passivation layer is positioned between the source electrode and the nitride layer and between the nitride layer and the drain electrode; the doped buried layer is connected with the source electrode or the drain electrode, the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer; the bottom of the gate forms an ohmic or schottky contact with the nitride layer.
In order to improve the single particle burning voltage of the P-type nitride gate HEMT device, one or more doped buried layers are designed in a buffer layer of the transistor device, and the doped buried layers are distributed in the buffer layer and are connected with a source electrode or a drain electrode so as to deplete electrons introduced by unintended doping and reduce leakage current of the device; meanwhile, the electric field distribution of the device in voltage withstanding can be modulated, and the peak electric field is reduced so as to relieve the single particle effect; and electrons can be absorbed to the drain electrode more quickly, and the doped buried layer is favorable for absorbing holes in the buffer layer under the grid electrode, so that potential barriers between the source and the channel are improved, an electron channel under the grid electrode is restrained, and the risk of single particle burning is reduced. The P-type nitride gate HEMT provided by the application not only can keep the enhanced characteristic, but also can improve the single-particle resistance of the device, thereby improving the single-particle breakdown voltage and the burning voltage of the device.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise.
FIG. 1 is a schematic diagram of a conventional P-type nitride gate HEMT structure;
fig. 2 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with a buried layer structure according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with a buried layer structure according to another embodiment of the present application;
fig. 4 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with a buried layer structure according to another embodiment of the present application;
fig. 5 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with a buried layer structure according to another embodiment of the present application;
fig. 6 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with a buried layer structure according to another embodiment of the present application;
fig. 7 is a schematic flow chart of a method for manufacturing a single-particle-resistant P-GaN transistor with a buried layer structure according to an embodiment of the present application;
fig. 8 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with buried layer structure according to an embodiment of the present application in the process of manufacturing;
fig. 9 is a schematic structural diagram of a single-particle-resistant P-GaN transistor with buried layer structure according to another embodiment of the present application;
fig. 10 is a simulation diagram of a P-type nitride gate high electron mobility transistor of conventional structure;
FIG. 11 is a schematic diagram of a single-particle-resistant P-GaN transistor with buried layer structure according to an embodiment of the present application;
fig. 12 is a graph comparing simulation results of a P-type nitride gate hemt with a conventional structure according to an embodiment of the present application and a single-particle-resistant P-GaN transistor with a buried layer structure according to the present application.
Detailed Description
As known from the background art, the current conventional P-type nitride gate HEMT device has the problem of electric field concentration, so that the breakdown voltage of the device is easily achieved, resulting in lower reliability of the device.
With the continuous development of space satellite, space exploration and other aerospace technologies, the requirements on a power supply system which is high-temperature resistant, high-power, miniaturized and suitable for extreme radiation environments are increasingly obvious, and a gallium nitride-based power device is one of the core representatives of a wide-forbidden-band semiconductor technology, and compared with a traditional silicon device, the gallium nitride-based power device has the advantages of high breakdown voltage, small on-resistance, high-temperature resistance, radiation resistance and the like, and can meet the application requirements of a new generation of spacecraft power supply system. Various energetic particles are contained in the space, and the space system is threatened by the energetic particles at any time in such an environment.
The conventional P-type nitride gate HEMT is based on an AlGaN/GaN heterostructure, and referring to fig. 1, the conventional structure of the high electron mobility transistor includes a substrate 100, a nucleation layer 101, a buffer layer 102, a channel layer 103, a barrier layer 104, a source electrode 105, a drain electrode 106, and a nitride layer 108, the nitride layer 108 is located between the source electrode 105 and the drain electrode 106, passivation layers 107 are provided on both sides of the nitride layer 108, a gate electrode 109 is provided over the nitride layer 108, the passivation layers 107 fill the region between the source electrode 105 and the nitride layer 108, and the passivation layers 107 also fill the region between the nitride layer 108 and the drain electrode 106.
Under normal operation of a conventional P-type nitride enhanced HEMT device, the electric field of the device is concentrated on the side of the edge of the gate 109 near the drain 106. When the drain 106 voltage increases, the electric field here is strongest and reaches the breakdown field of the GaN material first (typically 3.3 MV/cm), resulting in a broken down state of the HEMT device. Therefore, this limits the application of P-type nitride gate HEMT devices in high voltage operation modes.
In order to solve the above technical problems, an embodiment of the present application provides an anti-single particle P-GaN transistor with a buried layer structure, including: the semiconductor device comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a nitride layer, a passivation layer and at least one doped buried layer, wherein the nucleation layer, the buffer layer, the channel layer, the barrier layer, the source electrode, the drain electrode, the nitride layer and the passivation layer are sequentially stacked on the substrate; the source electrode and the drain electrode respectively form ohmic contact with the barrier layer; the nitride layer is positioned between the source electrode and the drain electrode, and the passivation layer is positioned between the source electrode and the nitride layer and between the nitride layer and the drain electrode; the doped buried layer is connected with the source electrode or the drain electrode, the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer; the bottom of the gate forms an ohmic or schottky contact with the nitride layer.
Embodiments of the present application will be described in detail below with reference to the attached drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the claimed technical solution of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.
Referring to fig. 2, an embodiment of the present application provides a single-particle-resistant P-GaN transistor having a buried layer structure, including: a substrate 100 and a nucleation layer 101, a buffer layer 102, a channel layer 103 and a barrier layer 104 stacked in this order on the substrate 100, a source 105 and a drain 106 on the barrier layer 104, a nitride layer 108 and a passivation layer 107 on the barrier layer 104, and at least one doped buried layer 110 within the buffer layer 102 and a gate 109 on the nitride layer 108; the source electrode 105 and the drain electrode 106 form ohmic contacts with the barrier layer 104, respectively; a nitride layer 108 is located between the source 105 and the drain 106, and a passivation layer 107 is located between the source 105 and the nitride layer 108, between the nitride layer 108 and the drain 106; the doped buried layer 110 is connected with the source 105 or the drain 106, and the top surface of the doped buried layer 110 is not higher than the top surface of the buffer layer 102, and the bottom surface of the doped buried layer 110 is not lower than the bottom surface of the buffer layer 102; the bottom of the gate 109 forms an ohmic or schottky contact with the nitride layer 108.
The single-particle-resistant P-GaN transistor with the buried layer structure provided by the embodiment of the application can be used for a power switch, a power conversion circuit and an irradiation environment of an aerospace system. The application provides a single-particle-resistant P-GaN transistor with a buried layer structure, aiming at the technical problems that the electric field intensity of a side, close to a drain electrode, of a grid electrode edge of a high-electron-mobility transistor is large, the electric field is concentrated on the side, close to the drain electrode, of the grid electrode edge, a very high electric field peak value is formed at the side, and the voltage endurance capacity of a device is reduced. In order to improve the single particle burning voltage of the P-type nitride gate HEMT device, one or more doped buried layers 110 are designed in the buffer layer 102 of the device and used for exhausting electrons which are led in by unintended doping, so that the leakage current of the device is reduced, the electric field distribution is modulated, and electrons and holes generated after single particle incidence can be absorbed more quickly, so that the breakdown voltage and burning voltage of the device are improved.
Note that the buried doped layer 110 may be formed in the buffer layer 102 by using ion implantation or etching regrowth technology.
Fig. 2 and 3 show schematic structural diagrams of a P-GaN transistor in the case of designing a buried doped layer in the buffer layer 102, respectively. As can be seen from fig. 2, the buried doped layer 110 is disposed on a side of the buffer layer 103 near the source 105, and the buried doped layer 110 is connected to the source 105. In fig. 3, the doped buried layer 110 is disposed on a side of the buffer layer 103 near the drain 106, and the doped buried layer 110 is connected to the drain 106.
In some embodiments, the anti-single particle P-GaN transistor with the buried layer structure includes two doped buried layers 110, the two doped buried layers 110 are respectively located at two ends of the buffer layer 103, and the two doped buried layers 110 are respectively connected with the source electrode 105 and the drain electrode 106.
Fig. 4 and 5 show schematic structural diagrams of a P-GaN transistor in the case of designing two buried doping layers in the buffer layer 102, wherein the two buried doping layers are denoted by 110a and 110b, respectively. As can be seen from fig. 4 and 5: the doped buried layer 110a is located at one end of the buffer layer 103 near the source 105, and the doped buried layer 110a is connected with the source 105; the doped buried layer 110b is located at an end of the buffer layer 103 near the drain electrode 106, and the doped buried layer 110b is connected to the drain electrode 106.
It should be noted that, the two doped buried layers 110a and 110b may be made of different materials to respectively manufacture the doped buried layer 110a and the doped buried layer 110b, or may be doped with different ion concentrations to realize different doping. The electric field distribution of the device in voltage withstanding is modulated by the two doped buried layers 110a and 110b with different doping, and the peak electric field is reduced to relieve the single event effect. It is understood that the lengths, widths, and heights of the two buried doped layers 110a, 110b may be equal or unequal; that is, the lengths, widths, and heights of the two buried doped layers 110a, 110b are adjustable.
In some embodiments, the anti-single particle P-GaN transistor with the buried layer structure includes a plurality of doped buried layers 110 spaced apart in the buffer layer 103; wherein, two doped buried layers are respectively connected with the source electrode 105 and the drain electrode 106, and the rest doped buried layers are distributed between the two doped buried layers at intervals.
Fig. 6 shows a schematic structure of a P-GaN transistor in the case of designing three doped buried layers in the buffer layer 102, wherein the three doped buried layers are denoted by 110a, 110b, and 110c, the doped buried layers 110a and 110b are respectively disposed at two ends in the buffer layer 103, the doped buried layer 110c is disposed between the doped buried layer 110a and the doped buried layer 110b, and the doped buried layer 110a and 110b are respectively connected to the source 105 and the drain 106. As shown in fig. 2 to 6, one or more doped buried layers 110 in the buffer layer 102 may be designed, and the length, width and height of each doped buried layer 110 may be adjustable. The lengths of the plurality of buried doped layers 110 may be equal or unequal; likewise, the heights of the plurality of buried doped layers 110 may be equal or unequal. Here, the length of the doped buried layer 110 refers to the length of the doped buried layer 110 in the lateral direction along the direction in which the source 105 points to the drain 106; the height of the buried doped layer 110 refers to the height of the buried doped layer 110 in the longitudinal direction along the gate 109 toward the nitride layer 108.
In some embodiments, the height of the buried doped layer 110 is 1% to 100% of the height of the buffer layer 102 in the direction of the gate 109 toward the nitride layer 108. That is, the thickness of the buried doped layer 110 is 1% to 100% of the thickness of the buffer layer 102. For example, the height of the buried doped layer 110 may be 10%, 15%, 20%, 40%, 60%, 80%, 100% of the height of the buffer layer 102. Preferably, the height of the doped buried layer 110 is 10% -20% of the height of the buffer layer 102.
In the limit, the thickness of the buried doped layer 110 may be equal to the thickness of the buffer layer 102. Preferably, in general, the top surface of the doped buried layer 110 is flush with the top surface of the buffer layer 102, and the bottom surface of the doped buried layer 110 is higher than the bottom surface of the buffer layer 102, so as to achieve the purpose of relieving the electric field at the side of the edge of the device gate 109 near the drain 106.
In some embodiments, the doped buried layer 110 has a length of 100nm to 10 μm in the direction of the source 105 toward the drain 106. The height of the single buried doped layer 110 may or may not be equal to the height of the buffer layer 102. It should be noted that the number, length and height of the buried doped layers 110 may be adaptively adjusted according to practical design requirements.
In some embodiments, the spacing between adjacent doped buried layers 110 is 100 nm-10 μm.
It should be noted that, in the case of designing a plurality of doped buried layers 110, the length of each doped buried layer 110 and the spacing between adjacent doped buried layers 110 may be arbitrarily adjusted as needed. In the embodiment of the present application, n doped buried layers 110 may be disposed in the buffer layer 102, specifically, n=1 to 50.
As shown in fig. 4, two doped buried layers 110 may be designed in the buffer layer 102, where the two doped buried layers 110 are respectively located at two ends inside the buffer layer 102, one of the two doped buried layers 110 is located at a side close to the source 105, the other is located at a side close to the drain 106, and a space exists between the two doped buried layers 110. The top surfaces of the two doped buried layers 110 are not higher than the top surface of the buffer layer 102, and the heights of the two doped buried layers 110 may be equal or unequal. In the embodiment of the application, two doped buried layers 110 are designed in the buffer layer 102 to reduce the electric field at the side of the edge of the gate 109 close to the drain 106, so as to play a role in relieving the peak value of the electric field.
The doped buried layer 110 is connected to the source 105 or the drain 106. As shown in fig. 2 and 3, one end of the buried doped layer 110 located within the buffer layer 102 is flush with the left side edge of the buffer layer 102, and the other end is located inside the buffer layer 102. At this time, the buried doped layer 110 is connected to the source 105. When the doped buried layer 110 is two (110 a, 110 b), as shown in fig. 4 and 5, the doped buried layer 110a is connected to the source 105, the doped buried layer 110b is connected to the drain 106, and a space exists between the two doped buried layers 110. When the doped buried layer 110 is three (110 a, 110b, 110 c), as shown in fig. 6, the doped buried layer 110a is connected to the source 105, the doped buried layer 110b is connected to the drain 106, the doped buried layer 110c is located between the doped buried layer 110a and the doped buried layer 110b, and the doped buried layer 110c is spaced from the doped buried layer 110a and the doped buried layer 110b on both sides.
In some embodiments, the material of the doped buried layer 110 includes one of P-type gallium nitride (P-GaN), P-type aluminum nitride (P-AlN), P-type aluminum gallium nitride (P-AlGaN), N-type gallium nitride (N-GaN), N-type aluminum nitride (N-AlN), or N-type aluminum gallium nitride (N-AlGaN). Preferably, the material of the doped buried layer 110 is P-type GaN, and typically, the material of the doped buried layer 110 is Mg-doped P-type GaN.
In some embodiments, the material of nitride layer 108 includes one of P-type gallium nitride (P-GaN), P-type aluminum nitride (P-AlN), or P-type aluminum gallium nitride (P-AlGaN). Preferably, the material of the nitride layer 108 is P-type GaN, and typically, mg-doped P-type GaN material is used as the material of the nitride layer 108. The thickness of the nitride layer 108 is 10nm to 150nm in the thickness direction of the substrate 100.
In some embodiments, as shown in fig. 2 to 6, the anti-single particle P-GaN transistor with buried layer structure further includes: an interposed layer (at the position of the dotted line in fig. 2 to 6) is located between the barrier layer 104 and the channel layer 103. The intercalating layer is used to enhance carrier mobility and the material of the intercalating layer includes, but is not limited to AlN, inAlN, alGaN.
In some embodiments, the material of the substrate 100 includes one of sapphire, silicon carbide (SiC), silicon (Si), gallium nitride. The direction in which the lower surface of the substrate 100 is directed to the upper surface of the substrate 100 is the thickness direction, and the thickness of the substrate 100 is 100nm to 1000 μm. The thicknesses described in the following examples of the present application are all thicknesses of the respective film layers in the thickness direction.
In some embodiments, the material of nucleation layer 101 comprises one of gallium nitride, aluminum gallium nitride (AlGaN). Preferably, the material of nucleation layer 101 is aluminum nitride. The thickness of the nucleation layer 101 is 30nm to 500nm, respectively.
In some embodiments, the material of the buffer layer 102 includes one or more of gallium nitride, aluminum gallium nitride. The thickness of the buffer layer 102 is 0.5 μm to 5 μm.
In some embodiments, the material of the channel layer 103 includes one of gallium nitride, aluminum gallium nitride. Preferably, the material of the buffer layer 102 and the channel layer 103 is gallium nitride. The thickness of the channel layer 103 is 50nm to 500nm.
In some embodiments, the material of the barrier layer 104 is wurtzite structured AlGaN, and in particular, the material of the barrier layer 104 is Al x Ga (1-x) N. When the barrier layer 104 is Al x Ga (1-x) In the case of N, the component (value of x) of Al is 0.1 to 1.0. The thickness of the barrier layer 104 is 10nm to 50nm.
In some embodiments, the source 105 and drain 106 may employ a metal combination of Ti/Al/Ni/Au or Ti/Al/Pt/Au such that the source 105 and drain 106, respectively, form ohmic contacts with the barrier layer 104.
In some embodiments, the gate 109 employs a metal that may form an ohmic or schottky contact with the nitride layer 108.
In some embodiments, the passivation layer 107 may include a first passivation layer 107 and a second passivation layer 107; the first passivation layer 107 is located between the source electrode 105 and the nitride layer 108; the second passivation layer 107 is located between the nitride layer 108 and the drain electrode 106. Note that the height of the second passivation layer 107 may be equal to or different from the height of the first passivation layer 107. Typically, since the first passivation layer 107 and the second passivation layer 107 are fabricated at the same time, the height of the second passivation layer 107 is equal to the height of the first passivation layer 107.
In some exemplary embodiments, the material of the first passivation layer comprises silicon oxide (SiO 2 ) Alumina (Al) 2 O 3 ) Silicon nitride (Si) 3 N 4 ) One of the following; and/or the material of the second passivation layer comprises silicon oxide (SiO 2 ) Alumina (Al) 2 O 3 ) Silicon nitride (Si) 3 N 4 ) One of them. The material of the first passivation layer may be the same as or different from the material of the second passivation layer.
In particular, since the first passivation layer and the second passivation layer may be simultaneously fabricated, it is preferable that the first passivation layer and the second passivation layer are the same in material and the same in height. The heights of the first passivation layer and the second passivation layer are 20 nm-500 nm along the direction that the gate points to the nitride layer.
Referring to fig. 7, the embodiment of the application also provides a preparation method of the single-particle-resistant P-GaN transistor with the buried layer structure, which comprises the following steps:
step S1, providing a substrate, and forming a nucleation layer and a buffer layer which are stacked in sequence on the substrate.
S2, forming a doped buried layer in the buffer layer; the doped buried layer comprises one or more; the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer.
And S3, sequentially forming a channel layer and a barrier layer on one side of the doped buried layer far away from the bottom surface of the buffer layer.
And S4, forming a nitride material layer on one side of the barrier layer far away from the channel layer to obtain the epitaxial wafer.
And S5, etching the nitride material layer to form a nitride layer.
And S6, manufacturing a mask on the barrier layer to form ohmic windows so as to form a source electrode and a drain electrode.
And S7, manufacturing masks on the barrier layer and the nitride layer to form a gate window so as to form a gate.
And S8, forming a passivation material layer above the barrier layer, the source electrode, the drain electrode and the grid electrode.
And S9, opening holes in the passivation material layers above the source electrode, the drain electrode and the grid electrode, and leading out electrodes to obtain the transistor.
Specifically, in the preparation of a high electron mobility transistor, a substrate 100 is first provided, and a nucleation layer 101 and a buffer layer 102 are formed on the substrate 100 in this order. Before forming each stacked film layer on the substrate 100, firstly, pretreating and heat treating the substrate 100, soaking the substrate 100 in hydrofluoric acid (HF) solution for 1min, then sequentially placing acetone solution, absolute ethanol solution and deionized water for ultrasonic cleaning for 10min to eliminate hanging bonds on the surface of the substrate 100, and drying the cleaned and dried substrate 100 in hydrogen H 2 Performing heat treatment at 1050 ℃ for 10 minutes in the atmosphere reaction chamber to remove surface pollutants; the substrate 100 is then placed in a metal organic chemical vapor deposition (Metal Organic Chemical Vapor)Deposition, MOCVD) system, the process parameters of the MOCVD system are as follows: the pressure in the MOCVD process is 10 Torr-100 Torr, the flow rate of the Al source is 10 sccm-100 sccm, the flow rate of the ammonia gas is 3000 sccm-6000 sccm, the flow rate of the hydrogen gas is 1000 sccm-2000 sccm, and the temperature is 900 ℃. Preferably, the nucleation layer 101 having a height of about 30nm is deposited by MOCVD process by simultaneously introducing an Al source having a flow rate of 30sccm, hydrogen gas having a flow rate of 1000sccm, and ammonia gas having a flow rate of 3000sccm into the reaction chamber at a pressure of 10Torr and a temperature of 900 ℃. Preferably, the material of the nucleation layer 101 is AlN; the thickness of the substrate 100 is 100nm to 1000 μm, and the thickness of the nucleation layer 101 is 30nm to 500nm, respectively.
Sequentially depositing a buffer layer 102 on the nucleation layer 101 by adopting an MOCVD process; in the process of depositing the buffer layer 102, the pressure of a reaction chamber in the MOCVD process is 10 Torr-100 Torr, the flow rate of Ga source is 50 mu mol/min-100 mu mol/min, the flow rate of ammonia gas is 3000 sccm-6000 sccm, the flow rate of hydrogen gas is 1000 sccm-2000 sccm, and the temperature is 900 ℃. Preferably, the buffer layer 102 is formed by simultaneously introducing a Ga source at a flow rate of 50. Mu. Mol/min, hydrogen gas at a flow rate of 1000sccm, and ammonia gas at a flow rate of 3000sccm into a reaction chamber at a pressure of 10Torr and a temperature of 900 ℃. The thickness of the buffer layer 102 is 0.5 μm to 5 μm.
Next, a buried doped layer 110 is fabricated within the buffer layer 102 using ion implantation or etch regrowth techniques. The doped buried layer 110 may be fabricated in one or more; the material of the doped buried layer 110 is the same as that of the nitride layer 108, and the top surface of the doped buried layer 110 is not higher than the top surface of the buffer layer 102, and the bottom surface of the doped buried layer 110 is not lower than the bottom surface of the buffer layer 102.
On the buffer layer 102 and the doped buried layer 110, a channel layer 103 of 50nm is deposited sequentially by adopting an MOCVD process, and the MOCVD process parameters are as follows: introducing a Ga source with the flow rate of 50 mu mol/min, hydrogen with the flow rate of 1000sccm and ammonia with the flow rate of 3000sccm into the reaction chamber at the same time, wherein the pressure of the reaction chamber is 10Torr, the temperature is 900 ℃; preferably, the material of the channel layer 103 is GaN; the thickness of the channel layer 103 is 50nm to 500nm, respectively.
Depositing a barrier layer 104 on the channel layer 103 by adopting an MOCVD process continuously; preferably, the method comprises the steps of,the material of the barrier layer 104 is Al x Ga (1-x) N, wherein x has a value of 0.1 to 0.2. In the present example, the Al composition was 0.1 and the deposition thickness was 40nm. In the process of depositing the barrier layer 104, the pressure of a reaction chamber in the MOCVD process is 10 Torr-100 Torr, the flow rate of an Al source is 10 mu mol/min-30 mu mol/min, the flow rate of a Ga source is 30 mu mol/min-90 mu mol/min, the flow rate of ammonia gas is 3000 sccm-6000 sccm, the flow rate of hydrogen gas is 1000 sccm-2000 sccm, and the temperature is 900 ℃. Preferably, the MOCVD process parameters for depositing the barrier layer 104 are: the barrier layer 104 was formed by simultaneously introducing an Al source at a flow rate of 10. Mu. Mol/min, a Ga source at a flow rate of 30. Mu. Mol/min, hydrogen gas at a flow rate of 1000sccm, and ammonia gas at a flow rate of 3000sccm into the reaction chamber at a pressure of 10Torr and a temperature of 900 ℃. The thickness of the barrier layer 104 is 10nm to 50nm.
Depositing a nitride material layer with the thickness of 70nm on the P-GaN window by adopting an MOCVD process on the barrier layer 104 to obtain an epitaxial wafer; the MOCVD process parameters are as follows: the reaction chamber was simultaneously supplied with a Ga source at a flow rate of 50. Mu. Mol/min, hydrogen at a flow rate of 1000sccm, and ammonia at a flow rate of 3000sccm at a pressure of 10Torr and a temperature of 900 ℃.
The nitride material layer is etched to expose portions of barrier layer 104, forming nitride layer 108. Specifically, the nitride material layer is etched by patterning the nitride material layer, exposing the left and right surfaces of the barrier layer 104, forming the nitride layer 108. The material of the nitride layer 108 is P-type gallium nitride, P-type aluminum nitride or P-type aluminum gallium nitride.
A mask was fabricated on the barrier layer 104 to form an ohmic window, an E-Beam electron Beam evaporation apparatus was placed, source 105 and drain 106 were deposited using an electron Beam evaporation process at a rate of 0.1nm/s, ti/Al/Ni/Au metal was used as the source 105 and drain 106, and annealing was performed at 850 c for 30s.
Preferably, the source electrode 105 and the drain electrode 106 are made of Ti/Al/Ni/Au combined metal, wherein the thickness of the metal Ti is 20 nm-100 nm, the thickness of the metal Al is 100 nm-300 nm, the thickness of the metal Ni is 20 nm-200 nm, and the thickness of the metal Au is 20 nm-200 nm. In the embodiment of the application, the thickness of the metal Ti is 20nm, the thickness of the metal Al is 100nm, the thickness of the metal Ni is 20nm, and the thickness of the metal Au is 20nm.
A mask was fabricated on the nitride layer 108 and the barrier layer 104 to form a gate window, the windowed sample was placed in an electron beam evaporation reaction chamber, and metal Ni/Au was deposited as gate 109 in the gate window using a beam evaporation process using nickel and gold targets having a purity of 99.999%, wherein Ni had a thickness of 20nm and Au had a thickness of 50nm.
The sample wafer after the above steps is placed in a PECVD reaction chamber, and a passivation material layer 107' is deposited on top of the barrier layer 104, the source 105, the drain 106 and the gate 109 by a PECVD process, as shown in fig. 8. Fig. 8 shows a schematic structure of a P-GaN transistor in the case of designing four buried doping layers in the buffer layer 102, wherein the four buried doping layers are 110a, 110b, 110c, and 110d, respectively.
Specifically, a passivation material layer 107' having a thickness of 50nm to 400nm is deposited on the barrier layer 104, the source electrode 105, the drain electrode 106, and the gate electrode 109 using a plasma enhanced chemical vapor deposition (Plasma Enhanced chemical Vapour Deposition, PECVD) process. In the PECVD process for depositing the passivation material layer 107', the pressure of the reaction chamber is 0.5 Pa-30 Pa, the temperature of the reaction chamber is 200 ℃ to 350 ℃, and monosilane (SiH) with the concentration of 20sccm is simultaneously introduced into the reaction chamber 4 ) And 100sccm of nitrous oxide (N) 2 O) gas, or monosilane and ammonia gas. The material of the passivation material layer 107' includes SiO 2 、Al 2 O 3 、Si 3 N 4 One of them.
Finally, holes are formed in the passivation layer 107 above the source electrode 105, the drain electrode 106 and the gate electrode 109, and electrodes are led out, so that the transistor is obtained. The passivation layer 107 of the transistor shown in fig. 8 is etched to form the passivation layer 107, resulting in a high electron mobility transistor as shown in fig. 9.
In some embodiments, when the doped buried layer 110 is fabricated in the buffer layer 102 by using ion implantation or etching regrowth technology in step S2, the length and width of the doped buried layer 110, the number of doped buried layers 110, and the spacing between adjacent doped buried layers 110 may also be adaptively adjusted according to actual needs.
Comparing the P-GaN transistor with the conventional structure with the single-particle-resistant P-GaN transistor with the buried layer structure provided by the application, and performing effect verification on the single-particle-resistant P-GaN transistor with the buried layer structure provided by the application through simulation results, wherein the effect verification is shown in figures 10to 12; fig. 10 is a simulation diagram of a P-type nitride gate high electron mobility transistor with a conventional structure, fig. 11 is a simulation diagram of a P-type nitride gate high electron mobility transistor with a buried layer structure provided by the present application, and fig. 12 is a comparison diagram of simulation results of a P-GaN transistor with a conventional structure and an anti-single particle P-GaN transistor with a buried layer structure provided by the present application; wherein, the green curve in fig. 12 shows the breakdown voltage variation curve of the P-GaN transistor of the conventional structure; the red curve represents the breakdown voltage change curve of the single-particle-resistant P-GaN transistor with the buried layer structure; from the simulation result in fig. 12, it can be seen that the single-particle-resistant P-GaN transistor with the buried layer structure provided by the application significantly improves the breakdown voltage of the device, thereby improving the single-particle-resistant capability of the device and enhancing the reliability of the device.
By the technical scheme, the embodiment of the application aims at the problem that the performance of a traditional P-type nitride gate HEMT device is degraded or burnt due to the concentration of an electric field of the HEMT device, and provides the single-particle-resistant P-GaN transistor with the buried layer structure and the preparation method thereof, wherein the transistor comprises the following components: the semiconductor device comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a source electrode, a drain electrode, a nitride layer, a passivation layer, at least one doped buried layer and a grid electrode, wherein the nucleation layer, the buffer layer, the channel layer, the barrier layer, the source electrode and the drain electrode are sequentially stacked on the substrate; the source electrode and the drain electrode respectively form ohmic contact with the barrier layer; the nitride layer is positioned between the source electrode and the drain electrode, and the passivation layer is positioned between the source electrode and the nitride layer and between the nitride layer and the drain electrode; the doped buried layer is connected with the source electrode or the drain electrode, the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer; the bottom of the gate forms an ohmic or schottky contact with the nitride layer.
In order to improve the single particle burning voltage of the P-type nitride gate HEMT device, one or more doped buried layers are designed in a buffer layer of the transistor device, and the doped buried layers are distributed in the buffer layer and are connected with a source electrode or a drain electrode so as to deplete electrons introduced by unintended doping and reduce leakage current of the device; meanwhile, the electric field distribution of the device in the voltage withstanding process can be modulated, the peak electric field is reduced, and electrons and holes generated after single particle incidence can be absorbed more quickly, so that the single particle effect is relieved. The P-type nitride gate HEMT provided by the application not only can keep the enhanced characteristic, but also can improve the single-particle resistance of the device, thereby improving the single-particle breakdown voltage and the burning voltage of the device.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the application and that various changes in form and details may be made therein without departing from the spirit and scope of the application. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the application, and the scope of the application is therefore intended to be limited only by the appended claims.

Claims (10)

1. A single-particle resistant P-GaN transistor having a buried layer structure, comprising:
a substrate, and a nucleation layer, a buffer layer, a channel layer and a barrier layer sequentially stacked on the substrate;
a source electrode and a drain electrode on the barrier layer, and the source electrode and the drain electrode form ohmic contact with the barrier layer respectively;
a nitride layer and a passivation layer on the barrier layer, the nitride layer being between the source and the drain, the passivation layer being between the source and the nitride layer, between the nitride layer and the drain;
at least one doped buried layer in the buffer layer, the doped buried layer being connected to the source electrode or the drain electrode; the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer;
and the bottom of the grid electrode is in ohmic contact or Schottky contact with the nitride layer.
2. The single-particle-resistant P-GaN transistor with buried layer structure of claim 1, wherein said buried layer doped material comprises one of P-type gallium nitride, P-type aluminum gallium nitride, N-type aluminum nitride, or N-type aluminum gallium nitride.
3. The single-particle-resistant P-GaN transistor with buried layer structure according to claim 1, comprising two doped buried layers, which are respectively located at two ends of the buffer layer, and which are respectively connected to the source electrode and the drain electrode.
4. The single-particle-resistant P-GaN transistor with buried layer structure of claim 1, comprising a plurality of doped buried layers spaced apart within said buffer layer; the two doped buried layers are respectively connected with the source electrode and the drain electrode, and the rest of the doped buried layers are distributed between the two doped buried layers at intervals.
5. The single-particle-resistant P-GaN transistor with buried layer structure of claim 1, wherein said nitride layer material comprises one of P-type gallium nitride, P-type aluminum gallium nitride, N-type aluminum nitride, or N-type aluminum gallium nitride.
6. The single-particle-resistant P-GaN transistor with buried layer structure of claim 1, wherein the height of said doped buried layer is 1% -100% of the height of said buffer layer along the direction in which said gate electrode points to said nitride layer.
7. The single-particle-resistant P-GaN transistor with buried layer structure according to claim 1, characterized in that the length of said doped buried layer is 100 nm-10 μm along the direction in which said source electrode points to said drain electrode.
8. The single particle resistant P-GaN transistor with buried layer structure of claim 1, wherein a spacing between adjacent said doped buried layers is 100 nm-10 μm.
9. The single-particle-resistant P-GaN transistor with buried layer structure of claim 1, further comprising:
and the insertion layer is used for improving carrier mobility and is positioned between the barrier layer and the channel layer.
10. The preparation method of the single particle resistant P-GaN transistor with the buried layer structure is characterized by comprising the following steps:
providing a substrate, and forming a nucleation layer and a buffer layer which are stacked in sequence on the substrate;
forming a doped buried layer in the buffer layer; the doped buried layer comprises one or more; the top surface of the doped buried layer is not higher than the top surface of the buffer layer, and the bottom surface of the doped buried layer is not lower than the bottom surface of the buffer layer;
forming a channel layer and a barrier layer sequentially on one side of the doped buried layer far away from the bottom surface of the buffer layer;
forming a nitride material layer on one side of the barrier layer far away from the channel layer to obtain an epitaxial wafer;
etching the nitride material layer to form a nitride layer;
manufacturing a mask on the barrier layer to form an ohmic window so as to form a source electrode and a drain electrode;
forming a mask on the barrier layer and the nitride layer to form a gate window so as to form a gate;
forming a passivation material layer over the barrier layer, the source electrode, the drain electrode, and the gate electrode;
and opening holes on passivation material layers above the source electrode, the drain electrode and the grid electrode, and leading out electrodes to obtain the transistor.
CN202310843353.7A 2023-07-10 2023-07-10 Single particle resistant P-GaN transistor with buried layer structure and preparation method thereof Pending CN116913960A (en)

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