CN116913902A

CN116913902A - electronic device

Info

Publication number: CN116913902A
Application number: CN202310002856.1A
Authority: CN
Inventors: 曾嘉平
Original assignee: Innolux Display Corp
Current assignee: Innolux Corp
Priority date: 2022-04-13
Filing date: 2023-01-03
Publication date: 2023-10-20
Also published as: TW202341378A

Abstract

The invention provides an electronic device, which comprises a substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a bonding structure and a chip. The first conductive layer is disposed on the substrate. The first insulating layer is arranged on the first conductive layer and provided with a first through hole. The second conductive layer is disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the first via hole. The second insulating layer is arranged on the second conductive layer and provided with a second through hole. The bonding structure is arranged on the second insulating layer, and is electrically connected with the second conductive layer through the second through hole. The chip is arranged on the joint structure.

Description

Electronic device

Technical Field

The present disclosure relates to electronic devices, and particularly to an antenna device.

Background

In an electronic device, a conductive layer serving as a pad portion is provided to be applied to, for example, a back end of line (BEOL) bonding process; however, there are multiple insulating layers between the conductive layer and the external electronic component (e.g. chip), and the insulating layers do not include the same material, so when etching the insulating layers to form a through hole for electrically connecting the conductive layer and the external electronic component, the probability of defects generated in the through hole is easily increased due to the relatively large thickness and different material characteristics of the conductive layer, so that the reliability of the electronic device is reduced.

Disclosure of Invention

The present disclosure provides an electronic device, which can reduce the probability of generating defects in the formed through hole, so that the reliability of the electronic device is improved.

According to some embodiments of the present disclosure, an electronic device includes a substrate, a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a bonding structure, and a chip. The first conductive layer is disposed on the substrate. The first insulating layer is arranged on the first conductive layer and provided with a first through hole. The second conductive layer is disposed on the first insulating layer, wherein the second conductive layer is electrically connected to the first conductive layer through the first via hole. The second insulating layer is arranged on the second conductive layer and provided with a second through hole. The bonding structure is arranged on the second insulating layer, and is electrically connected with the second conductive layer through the second through hole. The chip is arranged on the joint structure.

In order to make the above features and advantages of the present disclosure more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Fig. 1 is a schematic partial cross-sectional view of an electronic device according to a first embodiment of the disclosure;

FIG. 2 is a schematic partial cross-sectional view of an electronic device according to a second embodiment of the disclosure;

FIG. 3 is a schematic partial cross-sectional view of an electronic device according to a third embodiment of the disclosure;

FIG. 4 is a schematic partial cross-sectional view of an electronic device according to a fourth embodiment of the disclosure;

FIG. 5 is a schematic partial cross-sectional view of an electronic device according to a fifth embodiment of the disclosure;

FIG. 6 is a schematic partial cross-sectional view of an electronic device according to a sixth embodiment of the disclosure;

fig. 7 is a schematic partial cross-sectional view of an electronic device according to a seventh embodiment of the disclosure.

Detailed Description

The present disclosure may be understood by referring to the following detailed description in conjunction with the accompanying drawings, it being noted that, in order to facilitate the understanding of the reader and the brevity of the drawings, the various drawings in the present disclosure depict only a portion of the electronic device and the specific elements of the drawings are not necessarily drawn to scale. Furthermore, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the present disclosure.

Certain terms are used throughout the description and following claims to refer to particular components. Those skilled in the art will appreciate that electronic device manufacturers may refer to a component by different names. It is not intended to distinguish between components that differ in function but not name. In the following description and claims, the terms "include," have, "and the like are open-ended terms, and thus should be interpreted to mean" include, but not limited to …. Thus, the terms "comprises," "comprising," "includes," and/or "including," when used in the description of the present disclosure, specify the presence of stated features, regions, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, and/or components.

Directional terms mentioned herein, such as: "upper", "lower", "front", "rear", "left", "right", etc., are merely directions with reference to the drawings. Thus, the directional terminology is used for purposes of illustration and is not intended to be limiting of the disclosure. In the drawings, the various figures illustrate the general features of methods, structures and/or materials used in certain embodiments. However, these drawings should not be construed as defining or limiting the scope or nature of what is covered by these embodiments. For example, the relative dimensions, thicknesses, and locations of various layers, regions, and/or structures may be reduced or exaggerated for clarity.

When a corresponding element (e.g., a film layer or region) is referred to as being "on" another element, it can be directly on the other element or other elements can be present therebetween. On the other hand, when an element is referred to as being "directly on" another element, there are no elements therebetween. In addition, when a member is referred to as being "on" another member, the two members have an up-and-down relationship in a top view, and the member may be above or below the other member, and the up-and-down relationship depends on the orientation of the device.

The terms "about," "substantially," or "approximately" are generally construed to be within 10% of a given value or range, or to be within 5%, 3%, 2%, 1%, or 0.5% of a given value or range.

The use of ordinal numbers such as "first," "second," and the like in the description and in the claims is used for modifying an element, and is not by itself intended to exclude the presence of any preceding ordinal number(s) or order(s) of a certain element or another element or order(s) of manufacture, and the use of such ordinal numbers merely serves to distinguish one element having a certain name from another element having a same name. The same words may not be used in the claims and the specification, whereby a first element in the description may be a second element in the claims.

It is to be understood that the following exemplary embodiments may be substituted, rearranged, and mixed for the features of several different embodiments without departing from the spirit of the disclosure to accomplish other embodiments. Features of the embodiments can be mixed and matched at will without departing from the spirit of the invention or conflicting.

The electrical connection or coupling described in this disclosure may refer to a direct connection or an indirect connection, in which case the terminals of the elements of the two circuits are directly connected or connected with each other by a conductor segment, and in which case the terminals of the elements of the two circuits have a switch, a diode, a capacitor, an inductor, other suitable elements, or a combination thereof, but is not limited thereto.

In the present disclosure, the thickness, length and width may be measured by an optical microscope, and the thickness may be measured by a cross-sectional image in an electron microscope, but is not limited thereto. In addition, any two values or directions used for comparison may have some error. If the first value is equal to the second value, it implies that there may be about a 10% error between the first value and the second value; if the first direction is perpendicular to the second direction, the angle between the first direction and the second direction may be between 80 degrees and 100 degrees; if the first direction is parallel to the second direction, the angle between the first direction and the second direction may be between 0 degrees and 10 degrees.

The electronic device of the present disclosure may include an antenna device, a display device, a sensing device, a light emitting device, or a stitching device, but is not limited thereto. The electronic device may comprise a bendable or flexible electronic device. The electronic device comprises, for example, a liquid crystal (liquid crystal) layer or a light emitting diode (Light Emitting Diode, LED). The electronic device may include an electronic component. The electronic devices may include passive devices and active devices such as, but not limited to, capacitors, resistors, inductors, variable capacitors, filters, diodes, transistors (transistors), inductors, microelectromechanical system devices (MEMS), liquid crystal chips (liquid crystal chip), etc. The diode may comprise a light emitting diode or a photodiode. The light emitting diode may include, for example, but not limited to, an organic light emitting diode (organic light emitting diode, OLED), a sub-millimeter light emitting diode (mini LED), a micro LED, a quantum dot LED, a fluorescent light (fluorescence), a phosphorescent light (phosphor), or other suitable materials, or combinations thereof. The sensor may include, for example, but not limited to, a capacitive sensor (capacitive sensors), an optical sensor (optical sensors), an electromagnetic sensor (electromagnetic sensors), a fingerprint sensor (fingerprint sensor, FPS), a touch sensor (touch sensor), an antenna (antenna), or a stylus (pen sensor), etc.

The following examples of exemplary embodiments of the present disclosure are illustrated in the accompanying drawings and description in which like reference numerals are used to designate like or similar parts throughout the figures and description.

Fig. 1 is a schematic cross-sectional view of an electronic device according to a first embodiment of the disclosure.

Referring to fig. 1, an electronic device 10a of the present embodiment includes a substrate SB, a conductive layer M0, an insulating layer IL1, a conductive layer M1, an insulating layer IL2, a bonding structure BS, and a CHIP. It should be noted that the electronic device 10a of the present embodiment may include an antenna device, a display apparatus, a sensing device, a light emitting device or a stitching device, but the disclosure is not limited thereto. In the present embodiment, the electronic device 10a is an antenna device. For example, the electronic device 10a may be applicable to the communication field, the radar/light-reaching field, the smart super surface (Reconfigurable Intelligent Surface; RIS) technology, or other suitable fields/technologies, but the disclosure is not limited thereto. In some embodiments, the electronic device 10a may be a flexible electronic device, but the disclosure is not limited thereto.

The material of the substrate SB may be, for example, glass, plastic, or a combination thereof. For example, the material of the substrate SB may include quartz, sapphire (sapphire), silicon (Si), germanium (Ge), silicon carbide (SiC), gallium nitride (GaN), silicon germanium (SiGe), polymethyl methacrylate (polymethyl methacrylate, PMMA), polycarbonate (PC), polyimide (PI), polyethylene terephthalate (polyethylene terephthalate, PET), or other suitable materials or combinations thereof, which are not limited to the disclosure.

The conductive layer M0 is provided on the substrate SB, for example. In some embodiments, the conductive layer M0 may serve as a pad portion of the electronic device 10 a. In detail, in the present embodiment, the conductive layer M0 is a pad portion for electrically connecting the CHIP with a driving device described later, for example, but the disclosure is not limited thereto. In some embodiments, the material of the conductive layer M0 may include a low-resistance material such as copper, titanium, silver, gold, aluminum, tin, nickel, or a combination thereof. However, the material of the conductive layer M0 may be, for example, other suitable materials or combinations of the above materials, which is not limited to the disclosure. In addition, the conductive layer M0 may include, for example, a single-layer structure or a multi-layer structure. For example, in some embodiments, the conductive layer M0 may include a single copper layer, but the disclosure is not limited thereto. In other embodiments, the conductive layer M0 may include a stacked structure stacked on each other. For example, the conductive layer M0 may be a multi-layer structure, which may be, for example, a titanium nitride layer, a copper layer and a titanium nitride layer stacked in this order, but the disclosure is not limited thereto.

The insulating layer IL1 is provided on the substrate SB, for example. In the present embodiment, the insulating layer IL1 is disposed on the conductive layer M0 and partially covers the conductive layer M0, i.e. the insulating layer IL1 has a VIA hole VIA11 and a VIA hole VIA12 exposing a portion of the conductive layer M0, but the disclosure is not limited thereto. The material of the insulating layer IL1 may be, for example, an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride or a stack layer of at least two of the above materials), an organic material (such as polyimide resin, epoxy resin or acryl resin), or a combination thereof, but the disclosure is not limited thereto.

The conductive layer M1 is disposed on the substrate SB, for example. In the present embodiment, the conductive layer M1 is disposed on the insulating layer IL1 and is electrically connected to the conductive layer M0 through the VIA hole VIA 11. In some embodiments, the conductive layer M1 may include a single layer structure, but the disclosure is not limited thereto. In some embodiments, the conductive layer M1 may be a multi-layer structure, but the disclosure is not limited thereto. In addition, the material of the conductive layer M1 and the material of the conductive layer M0 may be the same or similar, and will not be described herein.

The insulating layer IL2 is provided on the substrate SB, for example. In the present embodiment, the insulating layer IL2 is disposed on the conductive layer M1 and partially covers the conductive layer M1, i.e. the insulating layer IL2 has a VIA hole VIA21 exposing a portion of the conductive layer M1, but the disclosure is not limited thereto. In addition, the insulating layer IL2 further has a VIA hole VIA22, wherein the VIA hole VIA22 communicates with the VIA hole VIA12 of the insulating layer IL1 to expose a portion of the conductive layer M0 together. The material of the insulating layer IL2 may be, for example, an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride or a stack layer of at least two of the above materials), an organic material (such as polyimide resin, epoxy resin or acryl resin), or a combination thereof, but the disclosure is not limited thereto.

The bonding structure BS is disposed on the insulating layer IL2, for example. In this embodiment, the bonding structure BS may be electrically connected to the conductive layer M1 through the VIA hole VIA 21. In the embodiment, the bonding structure BS includes a solder BS1 and a bump BS2, wherein the solder BS1 is disposed on the bump BS2, and a portion of the bump BS2 is disposed in the VIA21 and electrically connected to the conductive layer M1, but the disclosure is not limited thereto. In other embodiments, the bonding structure BS may include solder balls, conductive pillars, and the like. The material of the bump BS2 may include, for example, a metal or an alloy. For example, the material of the bump BS2 may be an alloy of gold and nickel, which may be formed by electroless nickel immersion gold (electroless nickel immersion gold, ENIG), but the disclosure is not limited thereto.

The CHIP is disposed on the bonding structure BS, for example. In some embodiments, the CHIP may include a communication element. In detail, the CHIP may include, for example, a varactor (varactor), a variable capacitor, a radio frequency radiating element (radio frequency radiation element), a variable resistor, a phase shifter, an amplifier, an antenna, a biometric sensor, a graphene sensor, other suitable elements, or a combination thereof. For example, the CHIP of the present embodiment is a capacitance modulation element, which includes a varactor. The varactors may provide different capacitance values depending on the signal provided from the drive element as will be described later, i.e. the magnitude of the capacitance value of the varactors may be changed by changing the voltage across the varactors. Therefore, the electronic device 10a of the present embodiment can adjust the operating frequency band by adjusting the capacitance value of the varactor diode, but the disclosure is not limited thereto.

In this embodiment, the electronic device 10a may further include an insulating layer IL0.

The insulating layer IL0 is provided on the substrate SB, for example. In the present embodiment, the insulating layer IL0 is disposed between the substrate SB and the conductive layer M0. The material of the insulating layer IL0 may be selected to include a material having an appropriate thermal expansion coefficient or a material opposite to the stress generated when the conductive layer M0 is subjected to a heating process, so as to reduce the warpage phenomenon generated in the substrate SB; alternatively, the material of the insulating layer IL0 may be a material with good adhesion to the conductive layer M0, which is not limited in the disclosure. The material of the insulating layer IL0 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack layer of at least two of the above materials), but the disclosure is not limited thereto.

In this embodiment, the electronic device 10a may further include a conductive layer M0'.

The conductive layer M0' is disposed on the substrate SB, for example, and is the same layer as the conductive layer M0, for example. The conductive layer M0' may be separated from or connected to the conductive layer M0, for example, but the disclosure is not limited thereto. In some embodiments, the conductive layer M0' may surround the conductive layer M0 serving as the pad portion, but the disclosure is not limited thereto. The conductive layer M0' may be used as a ground plate, an electrostatic protection layer, an electromagnetic interference shielding layer, a heat dissipation layer, or other layers with other purposes of the electronic device 10a, but the disclosure is not limited thereto. In some embodiments, the conductive layer M0' may occupy more than 85% of the surface area of the substrate SB in the top view direction n of the substrate SB for shielding electromagnetic waves not to be received, but the disclosure is not limited thereto. The material and structure of the conductive layer M0' may be the same as or similar to those of the conductive layer M0, and will not be described herein. In addition, in the present embodiment, the insulating layer IL1 is also disposed on the conductive layer M0 'and partially covers the conductive layer M0'. That is, the insulating layer IL1 has a through hole VIA1 'exposing a portion of the conductive layer M0', but the disclosure is not limited thereto.

In this embodiment, the electronic device 10a may further include a driving element DC.

The driving element DC is disposed on the substrate SB, and is electrically connected to the CHIP. The driving devices DC may be disposed on the substrate SB, for example, in an array, a staggered arrangement (e.g., a pen-like arrangement), or other arrangements, which is not limited in this disclosure. In some embodiments, the driving element DC may include an active element, a passive element, or a combination thereof. In the present embodiment, the driving device DC is a thin film transistor, but the disclosure is not limited thereto. In detail, the driving element DC may include, for example, a gate G, a source S, a drain D, and a semiconductor layer SE, wherein the gate G and the conductive layer M1 are the same, and the semiconductor layer SE is disposed between the conductive layer (gate G) and the other conductive layer (source S and drain D) and electrically connected to the other conductive layer (source S and drain D). One of the gate G, the source S, and the drain D may be at least one conductive pattern of the conductive layer M1, the conductive layer M2, or the conductive layer M3, which will be described later, but the disclosure is not limited thereto. The material of the semiconductor layer SE may include, for example, low temperature polysilicon (low temperature polysilicon, LTPS), metal oxide (metal oxide), amorphous silicon (amorphous silicon, a-Si), or a combination thereof, but the disclosure is not limited thereto. For example, the material of the semiconductor layer SE may include, but is not limited to, amorphous silicon, polycrystalline silicon, germanium, compound semiconductors (e.g., gallium nitride, silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide), alloy semiconductors (e.g., siGe alloys, gaAsP alloys, alInAs alloys, alGaAs alloys, gaInAs alloys, gaInP alloys, gaInAsP alloys), or combinations of the foregoing. The material of the semiconductor layer SE may also include, but is not limited to, metal oxides such as Indium Gallium Zinc Oxide (IGZO), indium Zinc Oxide (IZO), indium gallium zinc oxide (IGZTO), or organic semiconductors including polycyclic aromatic compounds, or combinations thereof. In the present embodiment, the material of the semiconductor layer SE is amorphous silicon, but the disclosure is not limited thereto. The gate electrode G is at least partially overlapped with the semiconductor layer SE in the planar direction n of the substrate SB, for example. The source electrode S and the drain electrode D are separated from each other, for example, and cover at least a portion of the semiconductor layer SE and are electrically connected to the semiconductor layer SE. It should be noted that, although the driving device DC is shown in the present embodiment as any bottom gate type thin film transistor known to those skilled in the art, the disclosure is not limited thereto. In some embodiments, the conductive layer M0' may at least partially overlap the driving element DC in the top view direction n of the substrate SB. In the present embodiment, the conductive layer M0' overlaps the driving element DC in the top view direction n of the substrate SB, but the disclosure is not limited thereto.

In other embodiments, the driving element DC may be a circuit chip. For example, the driving device DC may include a substrate (not shown), a driving circuit (not shown) disposed on the substrate, or other suitable devices, which is not limited in this disclosure. The driving element DC may be disposed on the substrate SB in such a manner that a chip is disposed on the substrate, for example. In detail, the substrate of the driving element DC may be a flexible substrate, a glass substrate or other suitable substrate, and the driving element DC may be disposed on the substrate SB, for example, in a manner of a Chip On Panel (COP), but the disclosure is not limited thereto.

In the present embodiment, the electronic device 10a may further include a trace CL.

The trace CL is disposed on the insulating layer IL2, and is the same layer as the source S and the drain D. In the present embodiment, one end of the trace CL is electrically connected to the source S, and the other end of the trace CL can be electrically connected to the conductive layer M0 through the through hole VIA12 and the through hole VIA22 that are in communication with each other. Based on this, the driving element DC can be electrically connected to the conductive layer M0 as the pad portion, for example, through the trace CL, thereby being electrically connected to the CHIP.

In the present embodiment, the electronic device 10a may further include a scan line SL and a data line DL.

The scan lines SL and the data lines DL are disposed on the substrate SB, for example. In the present embodiment, the scan line SL and the data line DL are disposed on the conductive layer M0 (at least the insulating layer IL1 is disposed therebetween), wherein the scan line SL and the gate G are on the same layer, and the data line DL and the source S, the drain D and the trace CL are on the same layer. In some embodiments, the scan line SL is electrically connected to the gate G of the driving device DC, and the data line DL is electrically connected to the source S of the driving device DC for operating the driving device DC.

In this embodiment, the electronic device 10a may further include a storage capacitor CST.

The storage capacitor CST is disposed on the substrate SB and is electrically connected to the driving device DC. In detail, in the present embodiment, the storage capacitor CST is formed by the storage electrode SC1, the storage electrode SC2, and the insulating layer IL2 disposed between the storage electrode SC1 and the storage electrode SC2, wherein the storage electrode SC1 and the gate G and the scan line SL belong to the same layer, and the storage electrode SC2 and the source S, the drain D, the data line DL, and the trace CL belong to the same layer. The storage electrode SC1 may be electrically connected to the conductive layer M0 'through, for example, the VIA1' penetrating the insulating layer IL1, and the storage electrode SC2 may be electrically connected to the drain D, but the disclosure is not limited thereto. Based on this, the storage electrode SC1, the storage electrode SC2, and the insulating layer IL2 disposed between the storage electrode SC1 and the storage electrode SC2 can form the storage capacitor CST.

In this embodiment, the electronic device 10a may further include an insulating layer IL3.

The insulating layer IL3 is provided on the substrate SB, for example. In the present embodiment, the insulating layer IL3 is disposed on the conductive layer M1 and covers the conductive layer M1. In addition, in the present embodiment, the insulating layer IL3 has a VIA hole VIA31, wherein the VIA hole VIA31 is communicated with the VIA hole VIA21 of the insulating layer IL2 to expose a portion of the conductive layer M1 together, but the disclosure is not limited thereto. The material of the insulating layer IL3 may be, for example, an inorganic material (such as silicon oxide, silicon nitride, silicon oxynitride or a stack layer of at least two of the above materials), an organic material (such as polyimide resin, epoxy resin or acryl resin), or a combination thereof, but the disclosure is not limited thereto.

In this embodiment, the electronic device 10a may further include an insulating layer IL4.

The insulating layer IL4 is provided on the substrate SB, for example. In the present embodiment, the insulating layer IL4 is disposed on the insulating layer IL3. In addition, in the present embodiment, the insulating layer IL4 has a VIA hole VIA4, wherein the VIA hole VIA4 is communicated with the VIA hole VIA31 of the insulating layer IL3 and the VIA hole VIA21 of the insulating layer IL2 to expose a portion of the conductive layer M1 together, but the disclosure is not limited thereto. The material of the insulating layer IL4 may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack layer of at least two of the above materials), an organic material (e.g., polyimide resin, epoxy resin, or acryl resin), or a combination thereof, but the disclosure is not limited thereto.

Based on this, in the present embodiment, the through hole VIA21, the through hole VIA31, and the through hole VIA4 communicate with each other to constitute the through hole V1, and the CHIP passes through (1) the through hole V1; and (2) a conductive layer M1 disposed between the insulating layers IL1 and IL2 (the conductive layer M1 is connected to the conductive layer M0 through another VIA11 not communicating with the VIA V1), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layer M1 between the conductive layer M0 and the CHIP, the conductive layer M1 can be electrically connected to the conductive layer M0 and the CHIP respectively through different through holes for transfer, so that the CHIP can be prevented from being electrically connected to the conductive layer M0 of the pad portion through a single through hole, that is, the possibility of defects generated by the single through hole penetrating through a plurality of insulating layers can be avoided. By using the via holes and the conductive layers for transferring, the number of insulating layers penetrated by the via holes can be relatively reduced, thereby reducing the possibility of defects generated by the via holes V1 and improving the reliability of the electronic device 10a of the embodiment.

Fig. 2 is a schematic partial cross-sectional view of an electronic device according to a second embodiment of the disclosure, where the embodiment of fig. 2 may use the element numbers and part of the content of the embodiment of fig. 1, and the same or similar elements are denoted by the same or similar numbers, and descriptions of the same technical content are omitted.

Referring to fig. 2, the main differences between the electronic device 10b of the present embodiment and the aforementioned electronic device 10a are as follows: the electronic device 10b further includes a conductive layer M2. In the present embodiment, the CHIP is electrically connected to the conductive layer M2, and the conductive layer M2 is electrically connected to the conductive layer M1. The conductive layer M2 is the same layer as the source electrode S, the drain electrode D, the data line DL, the track CL, and the storage electrode SC2, for example.

In detail, the conductive layer M1 of the present embodiment is disposed between the insulating layer IL1 and the conductive layer M2, and the insulating layer IL2 of the present embodiment is disposed between the conductive layer M1 and the conductive layer M2, and further includes a VIA hole VIA23 but not a VIA hole VIA21, wherein the conductive layer M2 is electrically connected to the conductive layer M1 through the VIA hole VIA23, and the conductive layer M1 is electrically connected to the conductive layer M0 through the VIA hole VIA 11.

In this embodiment, the semiconductor layer SE is disposed between the conductive layer M2 (which is the same layer as the source electrode S and the drain electrode D) and the conductive layer M1 (which is the same layer as the gate electrode G). Alternatively, in the present embodiment, the semiconductor layer SE is disposed between the insulating layer IL2 and the conductive layer M2 (which is the same layer as the source S and the drain D).

Based on this, in the present embodiment, the through hole VIA31 and the through hole VIA4 communicate with each other to constitute the through hole V2, and the CHIP passes through (1) the through hole V2; (2) A conductive layer M1 disposed between the insulating layers IL1 and IL2 (the conductive layer M1 is connected to the conductive layer M0 through another VIA11 which is not in communication with the VIA V2); and (3) a conductive layer M2 disposed between the insulating layers IL2 and IL3 (the conductive layer M2 is connected to the conductive layer M1 through another VIA23 not communicating with the VIA V2), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layer M1 and the conductive layer M2 between the conductive layer M0 and the CHIP, the conductive layer M1 and/or the conductive layer M2 can be electrically connected to the conductive layer M0 and the CHIP respectively through different vias for transferring, so that the CHIP can be prevented from being electrically connected to the conductive layer M0 of the pad portion through a single via, that is, the possibility of defects generated by the single via penetrating through a plurality of insulating layers can be avoided. By using the via holes and the conductive layers for transferring, the number of insulating layers penetrated by the via holes can be relatively reduced, thereby reducing the probability of defects generated by the via holes and improving the reliability of the electronic device 10b of the embodiment.

Fig. 3 is a schematic partial cross-sectional view of an electronic device according to a third embodiment of the disclosure. It should be noted that, the embodiment of fig. 3 may use the element numbers and part of the content of the embodiment of fig. 2, where the same or similar numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted.

Referring to fig. 3, the main differences between the electronic device 10c of the present embodiment and the aforementioned electronic device 10b are as follows: the electronic device 10c further includes a conductive layer M3. In this embodiment, the CHIP is electrically connected to the conductive layer M3, the conductive layer M3 is electrically connected to the conductive layer M2, the conductive layer M2 is electrically connected to the conductive layer M1, and the conductive layer M1 is electrically connected to the conductive layer M0. In addition, the driving element DC is located between the conductive layers M0 and M3. In some embodiments, the driving element DC may partially overlap the conductive layer M0 and the conductive layer M3 in the top view direction n of the substrate SB, but the disclosure is not limited thereto. In other embodiments, the driving element DC may partially overlap the conductive layer M0 and the conductive layer M3 in a specific direction (having an angle of non-0 degrees or non-90 degrees with the top view direction n of the substrate SB), such that the driving element DC and the conductive layer M0 and/or the conductive layer M3 may be misaligned in the top view direction n of the substrate SB. It should be noted that the component between the conductive layer M0 and the conductive layer M3 may include other layers besides the driving element DC, for example, and the disclosure is not limited thereto.

In detail, the conductive layer M2 of the present embodiment is disposed between the insulating layer IL2 (or the insulating layer IL 1) and the conductive layer M3, and the insulating layer IL3 of the present embodiment is disposed between the conductive layer M2 and the conductive layer M3, and further includes the VIA hole VIA32 but not the VIA hole VIA31, wherein the conductive layer M3 is electrically connected to the conductive layer M2 through the VIA hole VIA 32.

Based on this, in the present embodiment, the CHIP passes through (1) the through hole V3 (through hole VIA 4); (2) A conductive layer M1 disposed between the insulating layers IL1 and IL2 (the conductive layer M1 is connected to the conductive layer M0 through another VIA11 which is not in communication with the VIA V3); and (3) a conductive layer M2 disposed between the insulating layers IL2 and IL3 (the conductive layer M2 is connected to the conductive layer M1 through another VIA23 which is not in communication with the VIA V3); and (4) a conductive layer M3 disposed between the insulating layers IL3 and IL4 (the conductive layer M3 is connected to the conductive layer M2 through another VIA32 not communicating with the VIA V3), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layer M1, the conductive layer M2 and the conductive layer M3 between the conductive layer M0 and the CHIP, the conductive layer M1, the conductive layer M2 and/or the conductive layer M3 can be electrically connected with the conductive layer M0 and the CHIP respectively through different through holes for switching, so that the CHIP can be prevented from being electrically connected with the conductive layer M0 of the pad portion through a single through hole, that is, the possibility that the single through hole penetrates through a plurality of insulating layers to generate defects can be avoided. By using the via holes and the conductive layers for transferring, the number of insulating layers penetrated by the via holes can be relatively reduced, thereby reducing the probability of defects generated by the via holes and improving the reliability of the electronic device 10c of the embodiment.

Fig. 4 is a schematic partial cross-sectional view of an electronic device according to a fourth embodiment of the disclosure. It should be noted that, the embodiment of fig. 4 may use the element numbers and part of the content of the embodiment of fig. 3, where the same or similar numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted.

Referring to fig. 4, the main differences between the electronic device 10d of the present embodiment and the aforementioned electronic device 10c are as follows: the electronic device 10d further includes a conductive layer M3', wherein the conductive layer M3' and the conductive layer M3 belong to the same layer, and the conductive layer M3' is disposed between the insulating layer IL4 and the scan line SL in the top view direction n of the substrate SB. In some embodiments, the conductive layer M3' may partially overlap the insulating layer IL4 and the scan line SL in the top view direction n of the substrate SB, but the disclosure is not limited thereto. In other embodiments, the conductive layer M3 'may partially overlap the insulating layer IL4 and the scan line SL in a specific direction (having an angle of non-0 degrees or non-90 degrees with respect to the top view direction n of the substrate SB), such that the conductive layer M3' and the insulating layer IL4 and/or the scan line SL are offset in the top view direction n of the substrate SB. It should be noted that the component between the insulating layer IL4 and the scan line SL may include other layers besides the conductive layer M3', which is not limited to this disclosure.

In the present embodiment, the scan line SL is electrically connected to the conductive layer M3 'through the VIA hole VIA3' penetrating the insulating layer IL2 and the insulating layer IL3, and the conductive layer M3 'is disposed farther from the conductive layer M0' than the scan line SL, so that the distance between the scan line SL and the conductive layer M0 'can be increased by electrically connecting the scan line SL and the conductive layer M3', thereby reducing the capacitive load generated by the scan line SL (the capacitive load is inversely proportional to the distance between the two conductive layers), and improving the signal transmission quality of the electronic device 10 d. Furthermore, by electrically connecting the scan line SL with the conductive layer M3', the cross-sectional area of the scan line SL can be increased, so that the impedance value generated by the scan line SL (the impedance value is inversely proportional to the cross-sectional area of the conductive layer) can be reduced, and the signal transmission quality of the electronic device 10d can be improved.

In general, by the design of electrically connecting the scan line SL with the conductive layer M3', the resistance-capacitance load (RC loading) of the electronic device 10d can be reduced, so as to improve the signal transmission quality of the electronic device 10 d.

It should be noted that, although not shown in the drawings, other embodiments of the disclosure can also electrically connect the data line DL with the conductive layer M3', which can also reduce the rc load of the electronic device 10 d.

Based on this, in the present embodiment, the CHIP passes (1) through-hole V4 (through-hole VIA 4); (2) A conductive layer M1 disposed between the insulating layers IL1 and IL2 (the conductive layer M1 is connected to the conductive layer M0 through another VIA11 which is not in communication with the VIA V4); and (3) a conductive layer M2 disposed between the insulating layers IL2 and IL3 (the conductive layer M2 is connected to the conductive layer M1 through another VIA23 which is not in communication with the VIA V4); and (4) a conductive layer M3 disposed between the insulating layers IL3 and IL4 (the conductive layer M3 is connected to the conductive layer M2 through another VIA32 not communicating with the VIA V4), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layer M1, the conductive layer M2 and the conductive layer M3 between the conductive layer M0 and the CHIP, the conductive layer M1, the conductive layer M2 and/or the conductive layer M3 can be electrically connected with the conductive layer M0 and the CHIP respectively through different through holes for switching, so that the CHIP can be prevented from being electrically connected with the conductive layer M0 of the pad portion through a single through hole, that is, the possibility that the single through hole penetrates through a plurality of insulating layers to generate defects can be avoided. By using the via holes and the conductive layers for transferring, the number of insulating layers penetrated by the via holes can be relatively reduced, thereby reducing the probability of defects generated by the via holes and improving the reliability of the electronic device 10d of the embodiment.

Fig. 5 is a schematic partial cross-sectional view of an electronic device according to a fifth embodiment of the disclosure. It should be noted that, the embodiment of fig. 5 may use the element numbers and part of the content of the embodiment of fig. 4, where the same or similar numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted.

Referring to fig. 5, the main differences between the electronic device 10e of the present embodiment and the aforementioned electronic device 10d are as follows: the conductive layer M0 of the electronic device 10e does not overlap the CHIP and/or the bonding structure BS in the top view direction n of the substrate SB, wherein the CHIP can be electrically connected to the driving element DC through the conductive layer M3 and the VIA 33. With this design, the influence of the topography difference due to the provision of the conductive layer M0 can be reduced.

Based on this, in the present embodiment, the CHIP passes through (1) the through hole V5 (through hole VIA 4); (2) A conductive layer M1 disposed between the insulating layers IL1 and IL2 (the conductive layer M1 is connected to the conductive layer M0 through another VIA11 which is not in communication with the VIA V5); and (3) a conductive layer M2 disposed between the insulating layers IL2 and IL3 (the conductive layer M2 is connected to the conductive layer M1 through another VIA23 which is not in communication with the VIA V5); and (4) a conductive layer M3 disposed between the insulating layers IL3 and IL4 (the conductive layer M3 is connected to the conductive layer M2 through another VIA32 not communicating with the VIA V5), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layer M1, the conductive layer M2 and the conductive layer M3 between the conductive layer M0 and the CHIP, the conductive layer M1, the conductive layer M2 and/or the conductive layer M3 can be electrically connected with the conductive layer M0 and the CHIP respectively through different through holes for switching, so that the CHIP can be prevented from being electrically connected with the conductive layer M0 of the pad portion through a single through hole, that is, the possibility that the single through hole penetrates through a plurality of insulating layers to generate defects can be avoided. By using the via holes and the conductive layers for transferring, the number of insulating layers penetrated by the via holes can be relatively reduced, thereby reducing the probability of defects generated by the via holes and improving the reliability of the electronic device 10e of the embodiment.

Fig. 6 is a schematic partial cross-sectional view of an electronic device according to a sixth embodiment of the disclosure. It should be noted that, the embodiment of fig. 6 may use the element numbers and part of the content of the embodiment of fig. 3, where the same or similar numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted.

Referring to fig. 6, the main differences between the electronic device 20a of the present embodiment and the aforementioned electronic device 10c are as follows: the electronic device 20a includes a driving element DC 'which is a top gate thin film transistor, wherein a material of the semiconductor layer SE in the driving element DC' includes low temperature polysilicon, and the semiconductor layer SE is disposed between the insulating layer IL1 and the conductive layer M2 (which is the same layer as the source S and the drain D). In addition, the driving element DC' is located between the conductive layer M0 and the conductive layer M3. In some embodiments, the driving element DC' may partially overlap the conductive layer M0 and the conductive layer M3 in the top view direction n of the substrate SB, but the disclosure is not limited thereto. In other embodiments, the driving element DC 'may partially overlap the conductive layer M0 and the conductive layer M3 in a specific direction (having an angle of non-0 degrees or non-90 degrees with respect to the top view direction n of the substrate SB), such that the driving element DC' may be misaligned with the conductive layer M0 and/or the conductive layer M3 in the top view direction n of the substrate SB. It should be noted that the component between the conductive layer M0 and the conductive layer M3 may include other layers besides the driving element DC', which is not limited to this disclosure.

In other embodiments, the driving element DC' may be a circuit chip. For example, the driving device DC' may include a substrate (not shown) and a driving circuit (not shown) or other suitable devices disposed on the substrate, which is not limited in this disclosure. The driving element DC' may be disposed on the substrate SB, for example, in such a manner that the chip is disposed on the substrate. In detail, the substrate of the driving element DC 'may be a flexible substrate, a glass substrate or other suitable substrates, and the driving element DC' may be disposed on the substrate SB, for example, in a manner of a Chip On Panel (COP), but the disclosure is not limited thereto.

Specifically, the insulating layer IL2 of the present embodiment includes an insulating layer IL2a and an insulating layer IL2b and is disposed on the semiconductor layer SE, wherein the insulating layer IL2b is disposed on the insulating layer IL2 a. The insulating layers IL2a and IL2b include, for example, a VIA hole VIA2a and VIA hole VIA2b, and the VIA hole VIA2a and VIA hole VIA2b are connected to each other to expose a portion of the semiconductor layer SE, and the source electrode S and the drain electrode D disposed on the insulating layer IL2b may be electrically connected to the semiconductor layer SE through the connected VIA hole VIA2a and VIA hole VIA2 b.

In this embodiment, the electronic device 20a may further include a light shielding layer BL.

The light shielding layer BL is provided on the substrate SB, for example. In the present embodiment, the light shielding layer BL is disposed on the insulating layer IL1 and located between the substrate SB and the channel region of the semiconductor layer SE, and the light shielding layer BL at least partially overlaps the channel region of the semiconductor layer SE in the top view direction n of the substrate SB, so that the channel region is less susceptible to degradation caused by irradiation of ambient light. In some embodiments, the material of the light shielding layer BL may include a material with a transmittance lower than 30%, but the disclosure is not limited thereto.

In this embodiment, the electronic device 20a may further include a buffer layer BF.

The buffer layer BF is disposed on the substrate SB, for example. In the embodiment, the buffer layer BF is disposed on the insulating layer IL1 and covers the light shielding layer BL, but the disclosure is not limited thereto. The material of the buffer layer BF may be, for example, an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, or a stack layer of at least two of the above materials), but the disclosure is not limited thereto.

In addition, the storage capacitor CST' of the present embodiment is disposed on the substrate SB, for example. In detail, in the present embodiment, the electronic device 20a may include the storage electrode SC1 'and the storage electrode SC2', wherein the storage electrode SC1 'and the light shielding layer BL belong to the same layer, and the storage electrode SC2' and the semiconductor layer SE belong to the same layer. The storage electrode SC1 'may be electrically connected to the scan line SL through a via VSL penetrating the buffer layer BF and the insulating layer IL2a, and the storage electrode SC2' may be electrically connected to the data line DL through a via VDL penetrating the buffer layer IL2a and the insulating layer IL2b, but the disclosure is not limited thereto. Based on this, the storage electrode SC1', the storage electrode SC2', and the buffer layer BF disposed between the storage electrode SC1' and the storage electrode SC2' may form the storage capacitor CST '.

In addition, in the present embodiment, the conductive layer M1 is electrically connected to the conductive layer M0 through the VIA hole VIA13 penetrating the insulating layer IL2a, the buffer layer BF, and the insulating layer IL 1.

Based on this, in the present embodiment, the CHIP passes (1) through-hole V6 (through-hole VIA 4); (2) A conductive layer M1 disposed between the insulating layers IL1 and IL2b (the conductive layer M1 is connected to the conductive layer M0 through another VIA13 which is not in communication with the VIA V6); and (3) a conductive layer M2 disposed between the insulating layers IL2 and IL3 (the conductive layer M2 is connected to the conductive layer M1 through another VIA23 which is not in communication with the VIA V6); and (4) a conductive layer M3 disposed between the insulating layers IL3 and IL4 (the conductive layer M3 is connected to the conductive layer M2 through another VIA32 not communicating with the VIA V6), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layers M1, M2 and M3 between the conductive layer M0 and the CHIP, the conductive layers M1, M2 and/or M3 can be electrically connected to the conductive layers M0 and the CHIP respectively through different through holes for switching, so that the number of insulating layers penetrated by the through holes V6 can be relatively reduced, thereby reducing the possibility of defects generated by the through holes V6, and improving the reliability of the electronic device 20a of the embodiment.

Fig. 7 is a schematic partial cross-sectional view of an electronic device according to a seventh embodiment of the disclosure. It should be noted that, the embodiment of fig. 7 may use the element numbers and part of the content of the embodiment of fig. 6, where the same or similar numbers are used to denote the same or similar elements, and descriptions of the same technical content are omitted.

Referring to fig. 7, the main differences between the electronic device 20b of the present embodiment and the aforementioned electronic device 20a are as follows: the electronic device 20b further includes a conductive layer M3', wherein the conductive layer M3' and the conductive layer M3 belong to the same layer.

In the present embodiment, the scan line SL can be electrically connected to the conductive layer M3 'through the VIA hole VIA3' penetrating the insulating layer IL2b and the insulating layer IL3, and therefore, since the conductive layer M3 'is disposed farther from the conductive layer M0' than the scan line SL, the distance between the scan line SL and the conductive layer M0 'can be increased by electrically connecting the scan line SL and the conductive layer M3', so that the capacitive load generated by the scan line SL (the capacitive load is inversely proportional to the distance between the two conductive layers) can be reduced, and the signal transmission quality of the electronic device 20b can be improved. Furthermore, by electrically connecting the scan line SL with the conductive layer M3', the cross-sectional area of the scan line SL can be increased, so that the impedance value generated by the scan line SL (the impedance value is inversely proportional to the cross-sectional area of the conductive layer) can be reduced, and the signal transmission quality of the electronic device 20b can be improved.

In general, by the design of electrically connecting the scan line SL with the conductive layer M3', the rc load of the electronic device 20b can be reduced, and the signal transmission quality of the electronic device 20b can be improved. In addition, the gate G is electrically connected to the conductive layer M3', which can also reduce the rc load of the electronic device 20 b.

It should be noted that, although not shown in the drawings, other embodiments of the disclosure can also electrically connect the data line DL with the conductive layer M3', which can also reduce the rc load of the electronic device 20 b.

Based on this, in the present embodiment, the CHIP passes through (1) the through hole V7 (through hole VIA 4); (2) A conductive layer M1 disposed between the insulating layers IL1 and IL2b (the conductive layer M1 is connected to the conductive layer M0 through another VIA13 which is not in communication with the VIA V7); and (3) a conductive layer M2 disposed between the insulating layers IL2 and IL3 (the conductive layer M2 is connected to the conductive layer M1 through another VIA23 which is not in communication with the VIA V7); and (4) a conductive layer M3 disposed between the insulating layers IL3 and IL4 (the conductive layer M3 is connected to the conductive layer M2 through another VIA32 not communicating with the VIA V7), and is electrically connected to the conductive layer M0 as a pad portion. By providing the conductive layers M1, M2 and M3 between the conductive layer M0 and the CHIP, the conductive layers M1, M2 and/or M3 can be electrically connected to the conductive layers M0 and the CHIP respectively through different through holes for switching, so that the number of insulating layers penetrated by the through holes V7 can be relatively reduced, thereby reducing the possibility of defects generated by the through holes V7, and improving the reliability of the electronic device 20b of the embodiment.

According to the above embodiments of the disclosure, at least one conductive layer is disposed between the pad portion and the chip, wherein the at least one conductive layer can be electrically connected to the pad portion and the chip through at least one different via hole respectively for transfer, so that the number of insulating layers penetrated by the at least one via hole can be relatively reduced, thereby reducing the probability of defects generated by the formed via hole, and improving the reliability of the electronic device of the disclosure.

In addition, other embodiments of the present disclosure can reduce the rc load of the electronic device of the present disclosure by electrically connecting the scan line with the conductive layer above the scan line, and the conductive layer is further away from the conductive layer, for example, as a ground plane, with respect to the scan line, so as to improve the signal transmission quality of the electronic device of the present disclosure.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, but not limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure. Features of the embodiments may be mixed and matched at will without departing from the spirit or conflict of the invention.

Claims

1. An electronic device, comprising:

a substrate;

a first conductive layer disposed on the substrate;

a first insulating layer disposed on the first conductive layer;

the second conductive layer is arranged on the first insulating layer, and the second conductive layer is electrically connected with the first conductive layer;

the second insulating layer is arranged on the second conductive layer and provided with a second through hole;

the bonding structure is arranged on the second insulating layer and is electrically connected with the second conductive layer through the second through hole; and

and the chip is arranged on the joint structure.

2. The electronic device of claim 1, wherein the first conductive layer is a multi-layer structure.

3. The electronic device of claim 2, wherein the first conductive layer comprises a copper layer.

4. The electronic device of claim 1, further comprising:

a third conductive layer disposed between the first insulating layer and the second conductive layer; and

a third insulating layer arranged between the third conductive layer and the second conductive layer and having a third through hole,

the first insulating layer is provided with a first through hole, the second conductive layer is electrically connected with the third conductive layer through the third through hole, and the third conductive layer is electrically connected with the first conductive layer through the first through hole.

5. The electronic device of claim 4, further comprising a semiconductor layer disposed between the second conductive layer and the third conductive layer.

6. The electronic device of claim 1, further comprising:

a third conductive layer disposed between the first insulating layer and the second conductive layer;

a fourth conductive layer disposed between the third insulating layer and the second conductive layer; and

a fourth insulating layer disposed between the fourth conductive layer and the second conductive layer and having a fourth via hole,

the first insulating layer is provided with a first through hole, the second conductive layer is electrically connected with the fourth conductive layer through the fourth through hole, the fourth conductive layer is electrically connected with the third conductive layer through the first through hole, and the third conductive layer is electrically connected with the first conductive layer through the first through hole.

7. The electronic device of claim 6, further comprising:

and a semiconductor layer disposed between the first insulating layer and the fourth conductive layer.

8. The electronic device of claim 1, further comprising:

the driving element is arranged on the substrate and comprises a grid electrode, a source electrode, a drain electrode and a semiconductor layer, wherein the driving element is electrically connected with the chip; and

a storage capacitor disposed on the substrate and electrically connected to the drain electrode of the driving device,

wherein the material of the semiconductor layer comprises amorphous silicon or low-temperature polysilicon.

9. The electronic device of claim 8, wherein the second conductive layer comprises a plurality of conductive patterns, wherein at least one of the gate, the source, and the drain is the plurality of conductive patterns, and the drive element is located between the first conductive layer and the second conductive layer.

10. The electronic device of claim 9, further comprising:

a fifth conductive layer disposed between the second insulating layer and the scan line in a top view direction of the substrate, wherein the scan line and the gate electrode belong to the same layer,

the fifth conductive layer is electrically connected with the scanning line.

11. The electronic device of claim 1, wherein the chip is a capacitance modulation element.

12. The electronic device of claim 1, further comprising:

and the driving element is a circuit chip.