CN116913770A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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Publication number
CN116913770A
CN116913770A CN202311162311.3A CN202311162311A CN116913770A CN 116913770 A CN116913770 A CN 116913770A CN 202311162311 A CN202311162311 A CN 202311162311A CN 116913770 A CN116913770 A CN 116913770A
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CN
China
Prior art keywords
oxide layer
semiconductor device
silicon oxide
manufacturing
etching
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311162311.3A
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Chinese (zh)
Inventor
朱红波
欧志文
刘单单
高向阳
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Yuexin Semiconductor Technology Co ltd
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Yuexin Semiconductor Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yuexin Semiconductor Technology Co ltd filed Critical Yuexin Semiconductor Technology Co ltd
Priority to CN202311162311.3A priority Critical patent/CN116913770A/en
Publication of CN116913770A publication Critical patent/CN116913770A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H01L21/0234—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity

Abstract

The application provides a manufacturing method of a semiconductor device, which comprises the following steps: providing a semiconductor substrate, forming a silicon oxide layer on the semiconductor substrate, wherein the silicon oxide layer is divided into a grid oxide region and a non-grid oxide region; forming and patterning a photoresist layer on the silicon oxide layer, wherein the patterned photoresist layer exposes a non-gate oxide region; and etching the non-gate oxide region by adopting a chemical dry etching method, wherein etching gas is ionized into plasma outside the reaction chamber in the chemical dry etching process. In the manufacturing method of the semiconductor device, the silicon oxide layer is etched by adopting a chemical dry etching method to form the gate oxide, so that plasma-induced damage can not be generated, the gate oxide can not be drilled and thinned, and the device performance is improved. In addition, the sacrificial oxide layer is reserved when the silicon oxide layer is etched, so that the working procedure can be reduced, and the cost can be reduced.

Description

Manufacturing method of semiconductor device
Technical Field
The application belongs to the technical field of semiconductors, and relates to a manufacturing method of a semiconductor device.
Background
In the integrated circuit manufacturing process, the oxide layer is selectively removed by a wet etching process in the etching process to form gate oxide, and due to the isotropy characteristic of wet etching, the gate oxide layer under the photoresist is inevitably thinned, and particularly, under the condition that the gate oxide layer is thicker, poor electrical property can be caused.
The technological process of the gate oxide comprises the following steps: and coating a layer of photoresist on the surface of the wafer, exposing the part to be etched through an exposure and development process, protecting a non-etching area by using the photoresist, removing the bare silicon dioxide layer by adopting a BOE solution (mixed solution of ammonium fluoride and hydrofluoric acid) or an HF solution through a wet etching process, taking the remained silicon dioxide layer as a gate oxide layer, and finally removing the photoresist and cleaning the wafer.
In practice, the process method has great defects that the hydrophilicity of the silicon dioxide film on the surface of the wafer causes the adhesiveness of the photoresist and the silicon dioxide film at the protection part to be not tight enough, and the BOE solution or the HF solution can be continuously circulated in the container during wet etching to ensure the uniformity of the solution temperature and concentration, so that the wafer can be subjected to a certain scouring force during soaking etching, and then a 'floating glue' phenomenon is generated, the silicon dioxide at the area to be protected is etched by the penetration of etching liquid along the gap between the photoresist and the silicon dioxide, the state of the longitudinal and transverse etching basically changes by 1:1 in the isotropic etching of the wet etching, and the side of the gate oxide layer is severely drawn due to the holding of the silicon dioxide under the etching of the photoresist, and the gate oxide is weakened and thinned to cause electrical failure, thereby causing the failure of the device.
Therefore, how to provide a method for manufacturing a semiconductor device, which is used for improving the undercut of gate oxide caused by photoresist floating in wet etching, and improving the performance of the device, is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a method for manufacturing a semiconductor device, which is used for solving the problem that in the prior art, the gate oxide is undercut due to photoresist "floating glue" in wet etching, and the performance of the device is affected.
To achieve the above and other related objects, the present application provides a method for manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate, and forming a silicon oxide layer on the semiconductor substrate, wherein the silicon oxide layer is divided into a grid oxide region and a non-grid oxide region;
forming a photoresist layer on the silicon oxide layer and patterning, wherein the patterned photoresist layer exposes the non-gate oxide region;
and etching the non-gate oxide region by adopting a chemical dry etching method, wherein etching gas is ionized into plasma outside the reaction chamber in the chemical dry etching process.
Alternatively, in the chemical dry etching process, a microwave source is used to ionize the etching gas into plasma, and then the plasma is introduced into the reaction chamber through the transfer tube.
Optionally, in the process of etching the non-gate oxide region, the silicon oxide layer with a preset thickness is reserved as the sacrificial oxide layer.
Optionally, removing the sacrificial oxide layer by a wet etching method to form the semiconductor device.
Optionally, the etching solution for removing the sacrificial oxide layer comprises a BOE solution or an HF solution.
Optionally, the semiconductor device comprises a dual gate device.
Optionally, the thickness of the silicon oxide layer is not less than 1000 a.
Optionally, after the oxide layer in the non-gate oxide region is etched, removing the photoresist layer by using a sulfuric acid-hydrogen peroxide mixed solution.
Optionally, the step of forming and patterning the photoresist layer on the silicon oxide layer includes:
and coating a photoresist layer on the upper surface of the silicon oxide layer, and removing the photoresist layer above the non-gate oxide region through an exposure process and a development process.
Optionally, the etching gas includes CF 4 And O 2 。
As described above, in the method for manufacturing the semiconductor device, the chemical dry etching method is adopted to etch the silicon oxide layer to form the gate oxide, so that plasma-induced damage is not generated, the gate oxide is not subjected to drilling and thinning, and the device performance is improved. In addition, the sacrificial oxide layer is reserved when the silicon oxide layer is etched, so that the working procedure can be reduced, and the cost can be reduced.
Drawings
Fig. 1 to 5 are schematic views illustrating a method for manufacturing a semiconductor device.
Fig. 6 is a flowchart showing a method of manufacturing a semiconductor device according to the present application.
Fig. 7 is a schematic diagram showing a method for forming a silicon oxide layer on a semiconductor substrate in the method for manufacturing a semiconductor device according to the present application.
Fig. 8 is a schematic diagram showing a photoresist layer formed on a silicon oxide layer in a method for fabricating a semiconductor device according to the present application.
Fig. 9 is a schematic diagram of a patterned photoresist layer in a method of fabricating a semiconductor device according to the present application.
Fig. 10 is a schematic diagram showing a chemical dry etching method for etching a silicon oxide layer in the method for manufacturing a semiconductor device according to the present application.
Fig. 11 is a schematic diagram showing chemical dry etching in the method for manufacturing a semiconductor device of the present application.
Fig. 12 is a schematic diagram showing photoresist removal in the method for manufacturing a semiconductor device according to the present application.
Fig. 13 is a schematic view showing removal of a sacrificial oxide layer in the method for manufacturing a semiconductor device according to the present application.
Description of element numbers: 10-a semiconductor substrate; a 20-silicon oxide layer, a 200-gate oxide region, a 201-non-gate oxide region, and a 202-gate oxide layer; 30-a photoresist layer; 40-sacrificial oxide layer; 50-etching gas; 60-quartz tube; 70-a microwave source; 80-a transfer tube; 90-reaction chamber; 100-a sample to be etched; S1-S3.
Detailed Description
As shown in fig. 1 to 5, a method for manufacturing a semiconductor device is shown, comprising the steps of: (1) As shown in fig. 1, a silicon oxide layer 20 is formed on the upper surface of a semiconductor substrate 10, a photoresist layer 30 is formed on the silicon oxide layer 20 and patterned, and the photoresist layer 30 is used for protecting a specific region of the silicon oxide layer 20; (2) As shown in fig. 2, the photoresist layer 30 is used as a mask, a wet etching process is used to etch the silicon oxide layer 20 to form the gate oxide layer 202, and as silicon dioxide is hydrophilic and photoresist is hydrophobic, the adhesion between the silicon oxide layer 20 and the photoresist layer 30 is not tight enough, and is flushed by wet etching liquid, the photoresist layer 30 generates a "floating photoresist", so that the area of the silicon oxide layer 20 protected by the photoresist layer 30 is etched to form an undercut, and the gate oxide layer 202 is thinned, thereby affecting the performance of the device; (3) as shown in fig. 3, removing the photoresist layer 30; (4) As shown in fig. 4, a sacrificial oxide layer 40 is formed on the upper surface of the semiconductor substrate 10; (5) As shown in fig. 5, the sacrificial oxide layer 40 is removed to form a semiconductor device. Since the photoresist layer 30 is washed to generate a "floating photoresist" phenomenon, the gate oxide layer 202 is undercut to be thinned, and thus the present application provides a new method for manufacturing a semiconductor device, so as to improve the problem of undercut of the gate oxide layer.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application.
Please refer to fig. 6 to 13. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The embodiment provides a method for manufacturing a semiconductor device, please refer to fig. 6, which shows a flow chart of the manufacturing method, comprising the following steps:
s1: providing a semiconductor substrate, and forming a silicon oxide layer on the semiconductor substrate, wherein the silicon oxide layer is divided into a grid oxide region and a non-grid oxide region;
s2: forming a photoresist layer on the silicon oxide layer and patterning, wherein the patterned photoresist layer exposes the non-gate oxide region;
s3: and etching the non-gate oxide region by adopting a chemical dry etching method, wherein etching gas is ionized into plasma outside the reaction chamber in the chemical dry etching process.
First, referring to fig. 7, step S1 is performed: a semiconductor substrate 10 is provided, a silicon oxide layer 20 is formed on the semiconductor substrate 10, and the silicon oxide layer 20 is divided into a gate oxide region 200 and a non-gate oxide region 201.
By way of example, the semiconductor substrate 10 may be any substrate known to those skilled in the art for carrying semiconductor integrated circuit components, and may be a die or a wafer processed by an epitaxial growth process; specifically, in this embodiment, the semiconductor substrate 10 is a silicon wafer.
As an example, the silicon oxide layer 20 is formed on the upper surface of the semiconductor substrate 10 using a deposition process or a thermal oxidation process; specifically, the silicon oxide layer 20 is formed by a deposition process in this embodiment.
As an example, the gate oxide layer of the present embodiment is a high voltage gate oxide (HV GOX) and the gate oxide layer is thicker, and the thickness of the silicon oxide layer 20 in the present embodiment is not less than 1000 a, for example, may be 1000 a, 1500 a, 2000 a, 2500 a, 3000 a, etc.
Next, referring to fig. 8 and 9, step S2 is performed: a photoresist layer 30 is formed on the silicon oxide layer 20 and patterned, and the patterned photoresist layer 30 exposes the non-gate oxide region 201.
As an example, as shown in fig. 8, the photoresist layer 30 is coated on the upper surface of the silicon oxide layer 20; specifically, the photoresist layer 30 is a positive photoresist.
As an example, as shown in fig. 9, the photoresist layer 30 above the non-gate oxide region 201 is dissolved away by an exposure process and a development process to expose the non-gate oxide region 201, and the gate oxide region 200 is protected by the photoresist layer 30.
Next, referring to fig. 10, step S3 is performed: and etching the non-gate oxide region 201 by adopting a chemical dry etching method, wherein etching gas is ionized into plasma outside the reaction chamber in the chemical dry etching process.
As an example, as shown in fig. 11, a schematic diagram of the chemical dry etching principle of the present embodiment is shown, in which an etching gas 50 is introduced into a quartz tube 60, the etching gas 50 is ionized into plasma in the quartz tube 60 under the action of a microwave source 70, and the plasma enters a reaction chamber 90 through a transmission tube 80 and chemically reacts with a sample 100 to be etched in the reaction chamber 90, so as to achieve the purpose of etching the sample 100 to be etched. Specifically, the etching gas 50 includes CF 4 And O 2 The microwave source 70 generates 2.45GHZ microwaves so that the etching gas 50 is converted into plasma, and the plasma enters the reaction chamber 90 to generate isotropic etching on the sample 100 to be etched.
As an example, the present embodiment employs chemical dry etching (Chemical Dry Etch, CDE), where plasma is generated before entering the reaction chamber 90, and the present embodiment does not cause plasma-induced damage and damage to the semiconductor substrate 10, as compared to the prior art where plasma is generated within the reaction chamber. In addition, compared with the wet etching adopted in the prior art, the high-voltage gate oxide layer 20 is thicker, the time required for wet etching is longer, the effect of scouring by etching liquid is stronger, so that the phenomenon of floating glue is more serious, the chemical dry etching adopted in the application does not generate floating glue on the photoresist layer 30, the gate oxide layer 202 is not drilled and etched to be thin, the process window of a semiconductor device is increased, and the device performance is improved.
As an example, in the process of etching the non-gate oxide region 201, the silicon oxide layer with the preset thickness in the non-gate oxide region 201 is reserved as the sacrificial oxide layer 40, and compared with the prior art that the silicon oxide layer in the non-gate oxide region is completely removed in wet etching, the embodiment can reduce the process flow and the cost.
As an example, as shown in fig. 12, after the etching of the non-gate oxide region 201 is completed, the photoresist layer 30 is removed by using a mixed solution of sulfuric acid and hydrogen peroxide (SPM solution); of course, in other examples, an ashing process may also be used to remove the photoresist layer 30.
As an example, the semiconductor substrate 10 is subjected to a process such as ion implantation and high-temperature diffusion with the sacrificial oxide layer 40 as a damaged layer, for example, P-type ions such as boron, indium, gallium, etc. are implanted, or N-type ions such as arsenic, antimony, phosphorus, etc. are implanted to form a source region or a drain region, according to the device fabrication requirements. Because of the existence of the sacrificial oxide layer 40, implantation damage acts on the sacrificial oxide layer 40, and damage to the semiconductor substrate 10 is not caused, so that the electrical performance and reliability of devices manufactured based on the semiconductor substrate 10 are improved.
As an example, as shown in fig. 13, the sacrificial oxide layer 40 is removed by a wet etching method, and the etching solution used in the wet etching may be a BOE solution or a hydrofluoric acid solution; specifically, in this embodiment, a hydrofluoric acid solution is used to remove the sacrificial oxide layer 40, where the sacrificial oxide layer 40 is silicon oxide, and the removal reaction of hydrofluoric acid on the silicon oxide generates soluble H 2 SiF 6 ，H 2 SiF 6 Is easy to dissolve in water to form a solution, and can well avoid generating particles; and the silicon oxide is hydrophilic, the sacrificial oxide layer 40 can be removed easily by wet etching, and the surface of the semiconductor substrate 10 can be cleaned.
In summary, in the method for manufacturing the semiconductor device, the chemical dry etching method is adopted to etch the silicon oxide layer to form the gate oxide, so that plasma-induced damage is not generated, the gate oxide is not subjected to drilling and thinning, and the device performance is improved. In addition, the sacrificial layer is reserved when the silicon oxide layer is etched, so that the working procedure can be reduced, and the cost can be reduced. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A method of fabricating a semiconductor device, comprising the steps of:
providing a semiconductor substrate, and forming a silicon oxide layer on the semiconductor substrate, wherein the silicon oxide layer is divided into a grid oxide region and a non-grid oxide region;
forming a photoresist layer on the silicon oxide layer and patterning, wherein the patterned photoresist layer exposes the non-gate oxide region;
and etching the non-gate oxide region by adopting a chemical dry etching method, wherein etching gas is ionized into plasma outside the reaction chamber in the chemical dry etching process.
2. The method for manufacturing a semiconductor device according to claim 1, wherein: in the chemical dry etching process, a microwave source is used to ionize etching gas into plasma, and then the plasma is introduced into the reaction chamber through a transmission pipe.
3. The method for manufacturing a semiconductor device according to claim 1, wherein: and in the process of etching the non-gate oxide region, reserving the silicon oxide layer with preset thickness as a sacrificial oxide layer.
4. A method of manufacturing a semiconductor device according to claim 3, wherein: and removing the sacrificial oxide layer by adopting a wet etching method to form the semiconductor device.
5. The method for manufacturing a semiconductor device according to claim 4, wherein: and the etching solution for removing the sacrificial oxide layer comprises a BOE solution or an HF solution.
6. The method for manufacturing a semiconductor device according to claim 4, wherein: the semiconductor device includes a dual gate device.
7. The method for manufacturing a semiconductor device according to claim 1, wherein: the thickness of the silicon oxide layer is not less than 1000A.
8. The method for manufacturing a semiconductor device according to claim 1, wherein: and after the silicon oxide layer in the non-gate oxide region is etched, removing the photoresist layer by adopting sulfuric acid-hydrogen peroxide mixed solution.
9. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming and patterning the photoresist layer on the silicon oxide layer comprises:
and coating a photoresist layer on the upper surface of the silicon oxide layer, and removing the photoresist layer above the non-gate oxide region through an exposure process and a development process.
10. The method for manufacturing a semiconductor device according to claim 1, wherein: the etching gas comprises CF 4 And O 2 。
CN202311162311.3A 2023-09-11 2023-09-11 Manufacturing method of semiconductor device Pending CN116913770A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106833A1 (en) * 2003-11-14 2005-05-19 Kabushiki Kaisha Toshiba Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same
KR100814372B1 (en) * 2007-01-24 2008-03-18 삼성전자주식회사 Method of manufacturing a semiconductor device
CN102103992A (en) * 2009-12-17 2011-06-22 中芯国际集成电路制造(上海)有限公司 Method for manufacturing gate oxide
CN108257860A (en) * 2018-01-19 2018-07-06 武汉新芯集成电路制造有限公司 A kind of production method of grid oxic horizon

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050106833A1 (en) * 2003-11-14 2005-05-19 Kabushiki Kaisha Toshiba Semiconductor device having metal silicide layer on source/drain region and gate electrode and method of manufacturing the same
KR100814372B1 (en) * 2007-01-24 2008-03-18 삼성전자주식회사 Method of manufacturing a semiconductor device
CN102103992A (en) * 2009-12-17 2011-06-22 中芯国际集成电路制造(上海)有限公司 Method for manufacturing gate oxide
CN108257860A (en) * 2018-01-19 2018-07-06 武汉新芯集成电路制造有限公司 A kind of production method of grid oxic horizon

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