CN116909796A - Satellite-borne DSP exception recovery method based on software trap - Google Patents
Satellite-borne DSP exception recovery method based on software trap Download PDFInfo
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- CN116909796A CN116909796A CN202310938179.4A CN202310938179A CN116909796A CN 116909796 A CN116909796 A CN 116909796A CN 202310938179 A CN202310938179 A CN 202310938179A CN 116909796 A CN116909796 A CN 116909796A
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- 238000011084 recovery Methods 0.000 title claims abstract description 34
- 238000000034 method Methods 0.000 title claims abstract description 33
- 230000002159 abnormal effect Effects 0.000 claims abstract description 48
- 230000015654 memory Effects 0.000 claims abstract description 47
- 230000005856 abnormality Effects 0.000 claims abstract description 16
- 230000006870 function Effects 0.000 claims abstract description 13
- 238000012544 monitoring process Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention relates to a satellite-borne DSP exception recovery method based on a software trap, which comprises the steps of constructing and initializing a satellite-borne DSP exception recovery system, wherein the exception recovery system comprises a DSP chip, an FPGA main control module and three external independent FLASH memories; filling unused memory areas into a DSP internal memory to form software exception instructions; storing an abnormal interrupt service table of the non-maskable interrupt NMI in a program area, and hanging an abnormal processing function to the non-maskable interrupt NMI; when software abnormality occurs, an abnormal interrupt service of the non-maskable interrupt NMI is entered, and an abnormal processing function is entered through branch jump; reading an abnormal event mark register in an abnormal processing function, judging the type of an abnormal event, storing the value of an internal memory or register of the DSP into an abnormal record structure body, and sending the result of the abnormal record structure body to the FPGA; the FPGA records the abnormal state information of the DSP in a local memory, resets the DSP, reloads the program and resumes normal operation. The invention realizes the abnormal recovery.
Description
Technical Field
The invention relates to the field of satellite-borne processors, in particular to a satellite-borne DSP exception recovery method based on a software trap.
Background
With the increase of the complexity of the space mission, the requirements on the flexibility and the processing capacity of the space-borne processor are also increasing, and the Digital Signal Processing (DSP) chip is beginning to be widely applied to the space field. Because of the specificity of the working environment of the satellite-borne processor, the requirement on the reliability of the system is very high. DSP software programs are generally stored in storage devices such as FLASH, but these storage devices are easily affected by high-energy particles to cause single-event upset, so that the problem that the programs cannot be loaded due to errors occurs.
The traditional solution is that a guide program and an application program of a DSP are generally stored in three independent FLASH, the FPGA is utilized to carry out three-out and two-out voting, then the correct guide program is sent to the DSP, and an application code is loaded into the DDR and jumps to run in the guide process; the method can effectively detect and correct the problem of program error caused by single event upset of the external memory, but can not process the problem of program execution error or run-out caused by single event upset effect in the RAM or the register of the internal memory of the DSP in the running process of DSP software, so that the state can not be reported and recovered, and the failure cause can not be traced back and analyzed.
Disclosure of Invention
The invention aims to provide a satellite-borne DSP exception recovery method based on a software trap, which solves the problem of program execution errors when single event upset occurs in a DSP internal memory or a register, realizes exception recovery and improves reliability and controllability.
In order to solve the technical problems, the technical scheme of the invention is as follows:
a satellite-borne DSP exception recovery method based on a software trap comprises the following steps:
step S100: constructing and initializing a satellite-borne DSP exception recovery system;
the abnormality recovery system comprises a DSP chip, an FPGA main control module and three external independent FLASH memories; the DSP chip and the three FLASH memories are connected to the FPGA main control module; the three FLASH memories respectively store a bootstrap program and an application program of the DSP;
initializing a DSP chip after the abnormal recovery system is powered on, and copying a guide program and an application program in the FLASH memory after the three-out-of-two voting into an internal memory or a register of the DSP by the FPGA main control module;
step S200: filling all unused memory areas except a program area and a data area into an internal memory of the DSP as software exception instructions;
step S300: constructing an abort service: setting an interrupt vector table address in a program area, storing an abnormal interrupt service table of the non-maskable interrupt NMI by the interrupt vector table address, and hanging an abnormal processing function to the non-maskable interrupt NMI; when software abnormality occurs, an abnormal interrupt service of the non-maskable interrupt NMI is entered, and an abnormal processing function is entered through branch jump;
step S400: reading an abnormal event mark register in an abnormal processing function, judging the type of an abnormal event, storing the value of an internal memory or register of the DSP into an abnormal record structure body if the abnormality can not be recovered by the abnormality, and sending an abnormal record structure body result, namely abnormal state information, to the FPGA;
step S500: the FPGA records the abnormal state information of the DSP in a local memory, resets the DSP, reloads the program and restores the normal running state.
Further, the anomaly recovery method further includes the steps of:
step S600: and reporting the execution result and the running state to the FPGA at each stage of the DSP running process, recording the running state of the DSP by the FPGA and performing corresponding processing, and sending the DSP state to the ground by the FPGA through a telemetry command to realize the monitoring of the DSP running process.
Further, the DSP internal memory includes SRAM and DDR internal to the DSP.
Further, the DSP and the FPGA are communicated through an EMIF interface.
Further, in the DSP internal memory, the 16-bit NOP no-operation instruction is filled in the non-32-bit aligned portion.
Further, in step S500, the method for reloading the program by the DSP includes: and the FPGA sends the bootstrap program and the application program after the three-out-of-two voting to the DSP.
Further, the three independent FLASH memories are all NOR FLASH.
The invention has the following beneficial effects:
1. the software trap refers to entering a specific program processing module through a certain instruction, and filling the software trap instruction in a memory blank area outside a code area and a data area, so that the controllability of the running state of the DSP can be realized, and the stability and the reliability of the system are improved; according to the invention, on the basis of the software trap, the space-borne DSP exception recovery is realized, except for the program code segments and data, the blank areas are filled with software exception instructions, the program runs to enter the blank areas, at the moment, software exception is triggered, the program enters an exception interrupt processing program, the exception state can be actively reported, the current DSP key register value is recorded, the analysis and positioning of fault reasons are facilitated, and the reliability and the controllability of the system are greatly improved;
2. and the state report is carried out on each stage of the DSP operation process, so that the normal operation of each module is ensured, when errors occur, the faults can be found and recovered in time, and the real-time performance of the fault recovery of the DSP is greatly improved.
Drawings
FIG. 1 is a flow chart of a software trap-based on-satellite DSP exception recovery method of the invention;
FIG. 2 is a diagram of an anomaly recovery system for a satellite-borne DSP constructed in accordance with the present invention;
FIG. 3 is a schematic diagram of filling a white region instruction in an embodiment of the present invention;
FIG. 4 is a schematic diagram of an exception service procedure according to an embodiment of the present invention;
fig. 5 is a flowchart of FPGA processing in step S500 according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, the present invention is a satellite-borne DSP exception recovery method based on a software trap, which includes:
step S100: constructing and initializing a satellite-borne DSP exception recovery system;
referring to fig. 2, the abnormality recovery system includes a DSP chip, an FPGA main control module, and three external independent FLASH memories; the DSP chip and the three FLASH memories are connected to the FPGA main control module; the three FLASH memories respectively store a bootstrap program and an application program of the DSP; the FPGA main control module is responsible for reset signal control, program loading, state monitoring and fault recovery of the DSP; the DSP and the FPGA are communicated through an EMIF interface; the three independent FLASH memories are respectively NOR FLASH;
after the abnormal recovery system is powered on, the DSP chip carries out EMIF interface initialization, and the FPGA main control module copies the bootstrap program and the application program in the FLASH memory after the two-out-of-three voting into the DSP internal memory or the register; the DSP internal memory comprises SRAM and DDR in the DSP.
Step S200: filling unused memory areas, namely blank memory areas, into software abnormal instructions except a program area and a data area in an internal memory of the DSP; in this embodiment, the unused memory area is fully filled with 0x10000003, and the operation code corresponds to a software exception (SWE) instruction, and executing the instruction triggers a software exception; in addition, the non-32-bit aligned portion is filled with 16-bit NOP no-op instructions to ensure proper instruction fetching, as shown in fig. 3.
Step S300: constructing an abort service: setting an interrupt vector table address of 0x800000 in a program area, wherein the interrupt vector table is arranged in the interrupt vector area, the 0x800000 address is the initial address of an on-chip memory L2SRAM, and the interrupt vector table address stores an abort service table of an unmasked interrupt NMI and enables abort; hanging an exception handling function to the non-maskable interrupt NMI; when a software exception occurs, an abort service of the non-maskable interrupt NMI is entered, and an exception handling function is entered through branch jump, as shown in FIG. 4;
step S400: reading an abnormal event mark register in an abnormal processing function, judging the type of an abnormal event, if the abnormal event can not be recovered by the abnormal processing function, storing the value of an internal memory or a register of the DSP into an abnormal recording structure body, namely an abnormal_record structure body, and sending the result of the abnormal recording structure body, namely abnormal state information, to the FPGA through an EMIF interface; wherein, the abnormal recording structure result inclusion information is shown in table 1:
table 1 abnormal State record information
Step S500: referring to fig. 5, the fpga records abnormal state information of the DSP in the local memory, then resets the DSP, reloads the program, and restores the normal operation state; the method for reloading the program by the DSP comprises the following steps: and the FPGA sends the bootstrap program and the application program after the three-out-of-two voting to the DSP.
In other embodiments, the software trap-based on-board DSP exception recovery method further includes the following steps based on the steps S100 to S500:
step S600: each stage of the DSP operation process reports the execution result and the operation state to the FPGA through the EMIF interface, the FPGA records the operation state of the DSP and carries out corresponding processing, and the FPGA sends the DSP state to the ground through a telemetry command to realize the monitoring of the DSP operation process.
The invention is not related in part to the same or implemented in part by the prior art.
The foregoing is a further detailed description of the invention in connection with specific embodiments, and it is not intended that the invention be limited to such description. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. A satellite-borne DSP exception recovery method based on a software trap is characterized in that: comprising
Step S100: constructing and initializing a satellite-borne DSP exception recovery system;
the abnormality recovery system comprises a DSP chip, an FPGA main control module and three external independent FLASH memories; the DSP chip and the three FLASH memories are connected to the FPGA main control module; the three FLASH memories respectively store a bootstrap program and an application program of the DSP;
initializing a DSP chip after the abnormal recovery system is powered on, and copying a guide program and an application program in the FLASH memory after the three-out-of-two voting into an internal memory or a register of the DSP by the FPGA main control module;
step S200: filling all unused memory areas except a program area and a data area into an internal memory of the DSP as software exception instructions;
step S300: constructing an abort service: setting an interrupt vector table address in a program area, storing an abnormal interrupt service table of the non-maskable interrupt NMI by the interrupt vector table address, and hanging an abnormal processing function to the non-maskable interrupt NMI; when software abnormality occurs, an abnormal interrupt service of the non-maskable interrupt NMI is entered, and an abnormal processing function is entered through branch jump;
step S400: reading an abnormal event mark register in an abnormal processing function, judging the type of an abnormal event, storing the value of an internal memory or register of the DSP into an abnormal record structure body if the abnormality can not be recovered by the abnormality, and sending an abnormal record structure body result, namely abnormal state information, to the FPGA;
step S500: the FPGA records the abnormal state information of the DSP in a local memory, resets the DSP, reloads the program and restores the normal running state.
2. The abnormality recovery method according to claim 1, characterized in that: the method also comprises the following steps:
step S600: and reporting the execution result and the running state to the FPGA at each stage of the DSP running process, recording the running state of the DSP by the FPGA and performing corresponding processing, and sending the DSP state to the ground by the FPGA through a telemetry command to realize the monitoring of the DSP running process.
3. The abnormality recovery method according to claim 1, characterized in that: the DSP internal memory comprises SRAM and DDR in the DSP.
4. The abnormality recovery method according to claim 1, characterized in that: and the DSP and the FPGA are communicated through an EMIF interface.
5. The abnormality recovery method according to claim 1, characterized in that: in the DSP internal memory, a 16-bit NOP no-operation instruction is filled in a non-32-bit aligned portion.
6. The abnormality recovery method according to claim 1, characterized in that: in step S500, the method for reloading the program by the DSP includes: and the FPGA sends the bootstrap program and the application program after the three-out-of-two voting to the DSP.
7. The abnormality recovery method according to claim 1, characterized in that: the three independent FLASH memories are all NOR FLASH.
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| CN202310938179.4A CN116909796A (en) | 2023-07-28 | 2023-07-28 | Satellite-borne DSP exception recovery method based on software trap |
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| CN202310938179.4A CN116909796A (en) | 2023-07-28 | 2023-07-28 | Satellite-borne DSP exception recovery method based on software trap |
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