CN116909123A - Self-monitoring method for motor controller of aviation dual-redundancy electromechanical actuating system - Google Patents
Self-monitoring method for motor controller of aviation dual-redundancy electromechanical actuating system Download PDFInfo
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Abstract
The invention relates to the technical field of self-monitoring, in particular to a self-monitoring method of a motor controller of an aviation dual-redundancy electromechanical actuating system, which comprises the following steps: judging whether the algorithm execution chip of each control channel fails according to the actual execution time of the program codes of the algorithm execution chips in the control channels, each clock cycle and the estimated value of the motor control parameters output by the controllers in the two algorithm execution chips, and judging whether the logic synthesis chip in the control channel fails according to the estimated value and the actual value of the control parameters of the motor and each clock cycle of the logic synthesis chip in the control channel according to the execution result of each logic synthesis chip when executing the same function. The method saves hardware resources and ensures the accuracy of the monitoring result.
Description
Technical Field
The invention relates to the technical field of self-monitoring, in particular to a self-monitoring method of a motor controller of an aviation dual-redundancy electromechanical actuating system.
Background
The dual redundancy of a motor controller for an aircraft electro-mechanical actuator is an important design principle because it improves the reliability, safety and maintainability of the controller. The dual redundancy design is adopted, namely, two independent systems are adopted to work in parallel in key components of the controller, and even if one subsystem fails, the other subsystem can still operate. Thus, adverse consequences such as reduced operability of the aircraft due to failure of critical components are avoided, and the safety of the aircraft is improved.
In order to decide whether the current control channel can continue to execute functions or not and ensure timely transfer of control rights among redundancy after faults, a state monitoring method is required to monitor the execution states of all functional modules in the current control channel respectively, so that maintenance cost is reduced, and product efficiency and quality are improved.
The digital signal processor (DSP, digital Signal Processor) has high-speed and high-precision digital signal processing capability, can implement complex operation and control algorithms, and is an algorithm execution chip. The field programmable gate array (FPGA, field Programmable Gate Array) has high programmability and parallel computing capability, can rapidly process a large amount of data and logic operation, is a logic integrated chip, and in the controller for the aeronautical electromechanical actuator, the DSP is responsible for processing functions related to a motor control algorithm to realize high-precision position, speed and torque control, and the FPGA is responsible for high-speed data acquisition, processing and pulse width modulation signal output, and can realize functions of real-time protection, fault detection and the like. The advantages of the DSP and the FPGA are fully exerted in the controller, and efficient, rapid and reliable motor control is realized.
In the dual redundancy controller, it is important to monitor the function execution states of the algorithm execution chip and the logic synthesis chip. Although an algorithm execution chip usually integrates a watchdog reset function, on one hand, the reset function is often disabled in a reliability key application, and on the other hand, a single timing reset function cannot monitor the execution state of each functional module in a program.
In the prior art, only the heartbeat signal of the working chip is monitored in the monitoring of the controller, and the monitoring of the execution state of the functional module in the working chip is not realized, so that the monitoring result is inaccurate.
Accordingly, there is a need to provide a method for self-monitoring an aircraft dual-redundancy electromechanical actuation system motor controller to address the above-described issues.
Disclosure of Invention
The invention provides a self-monitoring method of a motor controller of an aviation dual-redundancy electromechanical actuating system, which is characterized in that each chip is monitored through other chips in a control channel, and then a three-decision voting method is utilized to comprehensively judge whether faults exist, so that the problem that the monitoring result is inaccurate because only heartbeat signals of working chips are monitored and the execution state of functional modules in the working chips is not monitored in the existing controller monitoring is solved.
The invention discloses a self-monitoring method of a motor controller of an aviation dual-redundancy electromechanical actuating system, which adopts the following technical scheme: comprising the following steps:
acquiring the actual execution time of program codes in algorithm execution chips in each control channel and each clock period according to the logic integrated chips in each control channel;
acquiring estimated values of motor control parameters output by a controller in two algorithm execution chips according to the algorithm execution chip of each control channel;
judging whether the algorithm execution chip of each control channel is invalid or not according to the actual execution time of the program codes, the estimated value of the motor control parameters output by the controllers in the two algorithm execution chips and each clock period;
according to two chips in the same control channel, obtaining an estimated value and an actual value of a control parameter of the motor;
the method comprises the steps that a chip is executed according to an algorithm of one control channel, and each clock cycle of a logic integrated chip in the other control channel is obtained;
monitoring the execution result when the two logic integrated chips execute the same function according to the logic integrated chips in the two control channels;
judging whether the logic integrated chip in the corresponding control channel fails or not according to the execution result of each logic integrated chip in the two control channels when executing the same function, the estimated value and the actual value of the control parameter of the motor and each clock period of the logic integrated chip in the control channel;
Wherein, the two control channels are a main control channel and a hot backup control channel.
Preferably, the step of obtaining the actual execution time of the program code in the algorithm execution chip in each control channel and each clock cycle includes:
acquiring the actual execution time of program codes in algorithm execution chips in the corresponding control channels according to the logic comprehensive chips of each control channel;
the actual execution time of the program code is as follows: the actual execution time of the rotating speed loop program code and the actual execution time of the current loop program code in the algorithm execution chip;
acquiring each clock cycle in an algorithm execution chip in another control channel according to the logic synthesis chip in each control channel;
the clock cycles are the system clock cycle, the high-speed peripheral clock cycle and the low-speed peripheral clock cycle of the algorithm execution chip.
Preferably, the step of obtaining estimated values of motor control parameters output by the controller in the two algorithm execution chips includes:
generating an estimated value of a motor control parameter output by a controller in an algorithm execution chip in each control channel according to the algorithm execution chip in each control channel;
Wherein, the two motor control parameters are the rotating speed parameter and the current parameter of the motor.
Preferably, the step of monitoring the estimated and actual values of the rotational speed parameter and the current parameter of the motor according to two chips in the same control channel comprises:
acquiring an estimated value of a motor control parameter of the motor according to an algorithm execution chip of the same control channel;
acquiring an actual value of a motor control parameter of the motor according to a logic execution chip of the same control channel;
the motor control parameters are current parameters and rotation speed parameters of the motor.
Preferably, the step of judging whether the algorithm execution chip of each control channel is invalid includes:
judging whether the actual execution time of each program code in the algorithm execution chip in the control channel meets the set time condition;
judging whether each clock period in an algorithm execution chip in a control channel meets a set first period condition, wherein the first period condition is a period threshold corresponding to each clock period in the algorithm execution chip, and when one clock period in all clock periods in the algorithm execution chip is larger than the corresponding period threshold, meeting the preset first period condition;
Acquiring an estimated value difference value of motor control parameters output by a controller in an algorithm execution chip in the two control channels, and judging whether the estimated value difference value meets a set estimated value difference value condition;
and when at least two conditions among the three conditions of the time condition, the first period condition and the estimated value difference value condition are met, judging that the algorithm execution chip of the control channel fails.
Preferably, the step of judging whether the actual execution time of the program code in the algorithm execution chip in the control channel satisfies the set time condition includes:
the time conditions are as follows: the time required for the controller to execute each program code;
when the actual execution time of one of the program codes in the actual execution time of all the program codes is longer than the time required by the controller to execute the corresponding program code, the set time condition is satisfied.
Preferably, the step of judging whether the estimated value difference satisfies a set estimated value difference condition includes:
the estimation value difference condition is an estimation value difference threshold value corresponding to each estimation value difference;
and when one of the estimated value difference values is larger than the corresponding estimated value difference value threshold value, meeting the estimated value difference value condition.
Preferably, the step of judging whether the logic integrated chip in the corresponding control channel fails includes:
acquiring a first difference value between an estimated value and an actual value of a control parameter of the motor, and judging whether the first difference value meets a preset first difference value condition;
judging whether each clock cycle of the logic integrated chip in the control channel meets a preset second cycle condition, wherein the second cycle condition is a second cycle threshold corresponding to each clock cycle of the logic integrated chip, and when one clock cycle of all clock cycles of the logic integrated chip is larger than the second cycle threshold, the preset second cycle condition is met;
obtaining a result difference value of an execution result when the two logic integrated chips execute the same function, and judging whether the result difference value meets a preset result difference value condition;
and when at least two conditions among the first difference value condition, the second period condition and the result difference value condition are met, judging that the logic integrated chip in the corresponding control channel fails.
Preferably, the step of determining whether the result difference satisfies a preset result difference condition includes:
the result difference condition is a preset result difference threshold;
When the result difference value when executing the same function is larger than the result difference value threshold value, the preset result difference value condition is met;
the functions performed are: and acquiring the actual value of the control parameter of the motor.
Preferably, the step of determining whether the first difference value meets a preset first difference value condition includes:
the first difference condition is a first difference threshold corresponding to each first difference;
and when one of the first difference values is larger than the corresponding first difference value threshold value, the first difference value condition is met.
The beneficial effects of the invention are as follows:
when the algorithm execution chip is monitored, the actual execution time of the program codes corresponding to the algorithm execution chip, the estimated value of the motor control parameters output by the controller and each clock period are monitored through other three chips in the two control channels, and then, whether the algorithm execution chip fails or not is comprehensively judged by utilizing the three monitored results and the corresponding conditions and a three-decision voting method; when monitoring the logic integrated chip, monitoring each clock period corresponding to the logic integrated chip, an execution result when the two logic integrated chips execute the same function and an estimated value and an actual value of a control parameter of the motor through other three chips in the two control channels, and then comprehensively judging whether the logic integrated chip fails or not by utilizing a three-decision voting method based on the three monitoring results and corresponding conditions; therefore, the monitoring of faults is realized by utilizing the chips in the two control channels in the dual-redundancy controller, so that hardware resources are saved, whether the chips fail or not is comprehensively judged by utilizing a three-decision voting method, and the accuracy of monitoring results is ensured.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic general structural diagram of an embodiment of a self-monitoring method of an aviation dual-redundancy electromechanical actuation system motor controller according to the present invention.
Fig. 2 is a data flow chart of an embodiment 1 of a self-monitoring method of an aviation dual-redundancy electromechanical actuating system motor controller according to the present invention when judging whether an algorithm execution chip fails.
Fig. 3 is a three-decision voting chart for judging whether the algorithm execution chip fails or not in the embodiment 1 of the self-monitoring method of the motor controller of the aviation dual-redundancy electromechanical actuating system.
Fig. 4 is a data flow chart of the self-monitoring method of the motor controller of the aviation dual-redundancy electromechanical actuating system in embodiment 1 of the present invention when judging whether the logic integrated chip fails.
Fig. 5 is a three-decision voting chart for judging whether the logic integrated chip fails or not in the embodiment 1 of the self-monitoring method of the motor controller of the aviation dual-redundancy electromechanical actuating system.
Fig. 6 is a three-decision voting chart of the method for self-monitoring the motor controller of the aviation dual-redundancy electromechanical actuating system according to the embodiment 2 of the present invention when judging whether the algorithm execution chip a fails.
Fig. 7 is a three-decision voting chart for judging whether the logic integrated chip C fails in embodiment 2 of a self-monitoring method of an aviation dual redundancy electromechanical actuation system motor controller according to the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
The flow chart of the self-monitoring method of the motor controller of the aviation dual-redundancy electromechanical actuating system, as shown in figure 1, comprises the following steps:
S1, judging whether an algorithm execution chip of each control channel fails or not according to actual execution time of a program code of the algorithm execution chip in the control channel, each clock period and estimated values of motor control parameters output by a controller in the two algorithm execution chips;
specifically, according to the logic integrated chip in each control channel, the actual execution time of program codes in the algorithm execution chip in each control channel and each clock period are obtained; acquiring estimated values of motor control parameters output by a controller in two algorithm execution chips according to the algorithm execution chip of each control channel; and judging whether an algorithm execution chip of each control channel fails according to the actual execution time of the program codes, the estimated value of the motor control parameter output by the controller and each clock cycle.
The step 11 of obtaining the actual execution time of the program code in the algorithm execution chip in each control channel and each clock cycle includes: according to the logic integrated chip of each control channel, monitoring the actual execution time of program codes in the algorithm execution chip in the corresponding control channel; the actual execution time of the program code is as follows: the actual execution time of the rotating speed ring program codes and the actual execution time of the program codes of the current ring in the algorithm execution chip; and acquiring each clock cycle in the algorithm execution chip in the other control channel according to the logic synthesis chip in each control channel.
Step 12, according to the algorithm execution chip of each control channel, the step of obtaining the estimated value of the motor control parameter output by the controller in the two algorithm execution chips includes: generating an estimated value of a motor control parameter output by a controller in an algorithm execution chip in one control channel according to the algorithm execution chip in the control channel, and generating an estimated value of the motor control parameter output by the controller in the algorithm execution chip in the other control channel by the algorithm execution chip in the other control channel; wherein, the two motor control parameters are the rotating speed parameter and the current parameter of the motor.
The step 13 of judging whether the algorithm execution chip of each control channel fails or not includes: judging whether the actual execution time of the program codes in the algorithm execution chip in the control channel meets the set time condition; judging whether each clock period in an algorithm execution chip in a control channel meets a set first period condition, wherein the first period condition is a period threshold corresponding to each clock period in the algorithm execution chip, and when one clock period in all clock periods in the algorithm execution chip is larger than the corresponding period threshold, meeting the preset first period condition; acquiring an estimated value difference value of motor control parameters output by a controller in an algorithm execution chip in the two control channels, and judging whether the estimated value difference value meets a set estimated value difference value condition; and when at least two conditions among the three conditions of the time condition, the first period condition and the estimated value difference value condition are met, judging that the algorithm execution chip of the control channel fails.
Specifically, step 111 is taken to determine whether the algorithm execution chip a of the main control channel fails as an example:
in step 1111, as shown in fig. 2, the logic integrated chip C in the main control channel is used to monitor the execution time (i.e. the actual execution time in the embodiment) of the program code in the algorithm execution chip a in the main control channel, wherein the present invention mainly controls the motor, so the actual execution time of the program code in the algorithm execution chip a mainly includes: the first actual execution time of the rotational speed loop code and the second actual execution time of the current loop code.
In step 1112, as shown in fig. 2, the logic synthesis chip D in the hot standby control channel is used to monitor each clock cycle in the algorithm execution chip a in the main control channel, where each clock cycle in the algorithm execution chip a is: a system clock, a high speed peripheral clock, and a period of a low speed peripheral clock.
Step 1113, as shown in fig. 2, the algorithm execution chip a in the main control channel generates an estimated value (estimated value of rotation speed and current) of the motor control parameter output by the controller in the algorithm execution chip a, and generates an estimated value of the motor control parameter output by the controller in the algorithm execution chip B through the algorithm execution chip B in the hot standby control channel; wherein, the two motor control parameters are the rotating speed parameter and the current parameter of the motor.
Step 1114, the estimated value of the motor control parameter output by the controller obtained by the algorithm execution chip a is sent to the algorithm execution chip B, and the algorithm execution chip B obtains the estimated value difference value of the motor control parameter output by the controller in the algorithm execution chip in the two control channels, that is, the difference between the algorithm execution chip B and the estimated value (the estimated value of the rotation speed and the current) of the motor control parameter of the algorithm execution chip a obtains the estimated value difference value (the estimated value difference value of the rotation speed and the rotation speed, the estimated value difference value of the current and the current), and judges whether the estimated value difference value meets the set estimated value difference value condition; the estimation value difference condition is an estimation value difference threshold value corresponding to each estimation value difference; when one of the estimated value differences is greater than the corresponding estimated value difference threshold, the estimated value difference condition is satisfied, as shown in fig. 3, and the algorithm execution chip B sends the judgment result to the logic synthesis chip D.
According to the actual execution time of each program code of the algorithm execution chip a obtained by the logic synthesis chip C, the logic synthesis chip C determines whether the actual execution time of each program code in the algorithm execution chip a in the main control channel meets a set time condition, that is, the execution time of each program code in the controller is fixed, which is only related to the running speed of the controller itself, so the set time condition in this embodiment is the time required by the controller to execute the code, so when the actual execution time of one of the program codes in the actual execution time of all the program codes is greater than the time required by the controller to execute the corresponding program code, the set time condition is satisfied, as shown in fig. 3, and the logic synthesis chip C sends the determination result to the logic synthesis chip D;
(because the logic integrated chip D directly acquires each clock cycle in the algorithm execution chip A), when judging each clock cycle, the logic integrated chip D directly judges whether each clock cycle in the algorithm execution chip A in the main control channel meets a set first cycle condition, wherein the cycle condition is a cycle threshold corresponding to each clock cycle in the algorithm execution chip A, and when one clock cycle in all clock cycles in the algorithm execution chip A is greater than the corresponding cycle threshold, the preset first cycle condition is met; and when at least two conditions among the three conditions of the time condition, the first period condition and the estimated value difference value condition are met, judging that the algorithm execution chip A in the main control channel fails through the logic comprehensive chip D.
Specifically, step 112 is taken to take as an example whether the algorithm execution chip B of the hot standby control channel fails:
in step 1121, as shown in fig. 2, the actual execution time of the program code in the algorithm execution chip B in the hot standby control channel is obtained by using the logic synthesis chip D in the hot standby control channel, wherein the invention mainly controls the motor, so the program code in the algorithm execution chip B mainly includes: the first actual execution time of the rotational speed loop code and the second actual execution time of the current loop code.
In step 1122, as shown in fig. 2, each clock cycle in the algorithm execution chip B in the hot standby control channel is obtained by using the logic synthesis chip C in the main control channel, where each clock cycle in the algorithm execution chip B is: a system clock, a high speed peripheral clock, and a period of a low speed peripheral clock.
Step 1123, as shown in fig. 2, the algorithm execution chip a in the main control channel generates an estimated value (estimated value of rotation speed and current) of the motor control parameter output by the controller in the algorithm execution chip a, and generates an estimated value of the motor control parameter output by the controller in the algorithm execution chip B through the algorithm execution chip B in the hot standby control channel; wherein, the two motor control parameters are the rotating speed parameter and the current parameter of the motor.
Step 1124, sending the estimated value of the motor control parameter output by the controller obtained by the algorithm execution chip B to the algorithm execution chip a, and obtaining the estimated value difference value of the motor control parameter output by the controller in the algorithm execution chip in the two control channels by the algorithm execution chip a, that is, obtaining the estimated value difference value (the estimated value difference value of the rotation speed and the estimated value difference value of the current) by the difference between the estimated values (the estimated value difference value of the rotation speed and the estimated value difference value of the current) of the motor control parameter of the algorithm execution chip a and the algorithm execution chip B, and judging whether the estimated value difference value meets the set estimated value difference value condition; the estimation value difference condition is an estimation value difference threshold value corresponding to each estimation value difference; when one of the estimated value differences is greater than the corresponding estimated value difference threshold, the estimated value difference condition is satisfied, as shown in fig. 3, and the algorithm execution chip a sends the judgment result to the logic synthesis chip C.
According to the actual execution time of each program code of the algorithm execution chip B obtained by the logic synthesis chip D, the logic synthesis chip D determines whether the actual execution time of each program code in the algorithm execution chip B in the hot standby control channel meets a set time condition, that is, the execution time of each program code in the controller is fixed, which is only related to the running speed of the controller itself, so the set time condition in this embodiment is the time required by the controller to execute the code, so when the actual execution time of one of the program codes in the actual execution time of all the program codes is greater than the time required by the controller to execute the corresponding program code, the set time condition is satisfied, as shown in fig. 3, and the logic synthesis chip D sends the determination result to the logic synthesis chip C.
The logic integrated chip C directly acquires each clock cycle in the algorithm execution chip B, so that when judging each clock cycle, the logic integrated chip C judges whether each clock cycle in the algorithm execution chip B in the hot standby control channel meets a set first cycle condition, wherein the first cycle condition is a cycle threshold corresponding to each clock cycle in the algorithm execution chip B, and when one clock cycle in all clock cycles in the algorithm execution chip B is greater than the corresponding cycle threshold, the preset first cycle condition is met; and when at least two conditions among the three conditions of the time condition, the first period condition and the estimated value difference value condition are met, judging that the algorithm execution chip B in the hot standby control channel fails by the logic comprehensive chip C.
S2, judging whether the logic integrated chip in the control channel fails or not according to the execution result of each logic integrated chip when executing the same function, the estimated value and the actual value of the control parameter of the motor and each clock period of the logic integrated chip in the control channel;
specifically, according to two chips in the same control channel, an estimated value and an actual value of a control parameter of the motor are obtained; the method comprises the steps that a chip is executed according to an algorithm of one control channel, and each clock cycle of a logic integrated chip in the other control channel is obtained; monitoring the execution result when the two logic integrated chips execute the same function according to the logic integrated chips in the two control channels; and judging whether the logic integrated chip in the corresponding control channel fails according to the execution result of each logic integrated chip in the two control channels when the same function is executed, the estimated value and the actual value of the control parameter of the motor and each clock period of the logic integrated chip in the control channel.
Step 21, obtaining an estimated value and an actual value of a control parameter of the motor, including: acquiring an estimated value of a motor control parameter of the motor according to an algorithm execution chip of the same control channel; acquiring an actual value of a motor control parameter of the motor according to a logic execution chip of the same control channel; the motor control parameters are current parameters and rotation speed parameters of the motor.
Step 22, obtaining each clock cycle of the logic synthesis chip in another control channel, where each clock cycle in the logic synthesis chip is: a system clock, a high speed peripheral clock, and a period of a low speed peripheral clock.
The step 23 of monitoring the execution result when the two logic integrated chips execute the same function includes: wherein, the functions performed are: and acquiring the actual value of the motor control parameter.
Step 24, determining whether the logic integrated chip in the corresponding control channel fails, specifically includes: acquiring first difference values of an estimated value and an actual value of a control parameter of the motor, and judging whether the first difference values meet preset first difference value conditions, wherein the first difference value conditions are first difference value threshold values corresponding to each first difference value, and when one of the first difference values is larger than the corresponding first difference value threshold value, the first difference value conditions are met; judging whether each clock cycle of the logic integrated chip in the control channel meets a preset second cycle condition, wherein the second cycle condition is a second cycle threshold corresponding to each clock cycle of the logic integrated chip, and when one clock cycle of all clock cycles of the logic integrated chip is larger than the second cycle threshold, the preset second cycle condition is met; obtaining a result difference value of an execution result when the two logic integrated chips execute the same function, and judging whether the result difference value meets a preset result difference value condition, wherein the result difference value condition is a preset result difference value threshold; when the result difference value when executing the same function is larger than the result difference value threshold value, the preset result difference value condition is met; and when at least two conditions among the first difference value condition, the second period condition and the result difference value condition are met, judging that the logic integrated chip in the corresponding control channel fails.
Specifically, step 211 is taken to determine whether the logic integrated chip C of the main control channel fails as an example:
step 2111, as shown in fig. 4, of obtaining an estimated value and an actual value of a control parameter of the motor according to two chips in the main control channel, that is, an algorithm execution chip a in the main control channel generates the estimated value of the motor control parameter of the motor; the logic integrated chip C in the main control channel acquires the actual value of the motor control parameter of the motor.
In step 2112, as shown in fig. 4, the algorithm execution chip B in the hot standby control channel is used to monitor each clock cycle of the logic synthesis chip C in the main control channel.
Step 2113, as shown in fig. 4, obtains an execution result when the logic synthesis chip C in the main control channel executes the target function, and obtains an execution result when the logic synthesis chip D in the hot standby control channel executes the target function, where the target function is: and acquiring the actual value of the control parameter of the motor.
Step 2114, the logic integrated chip C in the main control channel sends the actual value of the motor control parameter of the acquired motor to the algorithm execution chip a, and the algorithm execution chip a acquires a first difference value between the estimated value of the motor control parameter and the actual value, that is, the algorithm execution chip a in the main control channel makes a difference between the estimated value of the motor control parameter of the motor and the actual value of the motor control parameter of the motor to obtain a first difference value, and judges whether the first difference value meets a preset first difference value condition, wherein the first difference value condition is a first difference value threshold value corresponding to each first difference value; when one of the first difference values is larger than the corresponding first difference value threshold value, the first difference value condition is met, and the judgment result is sent to the logic integrated chip D.
The algorithm executing chip B judges whether each clock period of the logic comprehensive chip C in the main control channel meets a preset second period condition, wherein the second period condition is a second period threshold corresponding to each clock period of the logic comprehensive chip C, when one clock period of all clock periods of the logic comprehensive chip C in the main control channel is larger than the second period threshold, the preset second period condition is met, and a judging result is sent to the logic comprehensive chip D.
The logic synthesis chip C sends the obtained actual value to the logic synthesis chip D, and the logic synthesis chip D obtains the result difference of the execution result when the two logic synthesis chips execute the same function, in this embodiment, since it is determined whether the logic synthesis chip C of the main control channel fails, the result difference is: subtracting the result of the target function executed by the logic integrated chip C of the main control channel from the result of the target function executed by the logic integrated chip D of the hot backup control channel, wherein the result difference condition is a preset result difference threshold; the logic integrated chip D judges that the result difference value is larger than a result difference value threshold value when the function of acquiring the actual value of the control parameter of the motor is executed, and then a preset result difference value condition is met; as shown in fig. 5, the result of the judgment of the algorithm execution chip a and the result of the judgment of the algorithm execution chip B are sent to the logic synthesis chip D, the logic synthesis chip D judges whether the three results meet the corresponding conditions, and when at least two conditions of the three conditions of the first difference condition, the second period condition and the result difference condition are met, the logic synthesis chip D judges that the logic synthesis chip C in the main control channel fails.
Specifically, step 212 is to determine whether the logical integrated chip D of the hot standby control channel fails as an example:
step 2121, obtaining an estimated value and an actual value of a control parameter of the motor according to two chips in the hot standby control channel, namely, as shown in fig. 4, an algorithm execution chip B in the hot standby control channel generates the estimated value of the motor control parameter of the motor; the logic integrated chip D in the hot standby control channel acquires the actual value of the motor control parameter of the motor.
In step 2122, as shown in fig. 4, the algorithm execution chip a in the main control channel is used to monitor each clock cycle of the logic synthesis chip D in the hot standby control channel.
In step 2123, as shown in fig. 4, an execution result of the target function performed by the logic synthesis chip D in the hot standby control channel is obtained, and an execution result of the target function performed by the logic synthesis chip C in the main control channel is obtained.
Step 2124, the logic integrated chip D in the hot standby control channel sends the actual value of the motor control parameter of the obtained motor to the algorithm execution chip B, and the algorithm execution chip B obtains a first difference value between the estimated value of the motor control parameter of the motor and the actual value, that is, the algorithm execution chip B in the main control channel obtains the first difference value by differentiating the estimated value of the motor control parameter of the motor and the actual value of the motor control parameter of the motor, and judges whether the first difference value meets a preset first difference value condition, wherein the first difference value condition is a first difference value threshold value corresponding to each first difference value; when one of the first difference values is larger than the corresponding first difference value threshold value, the first difference value condition is met;
The algorithm executing chip A judges whether each clock period of the logic integrated chip D in the hot standby control channel meets a preset second period condition, wherein the second period condition is a second period threshold corresponding to each clock period of the logic integrated chip D, and when one clock period of all clock periods of the logic integrated chip in the hot standby control channel is larger than the second period threshold, the preset second period condition is met;
the logic synthesis chip D sends the obtained actual value to the logic synthesis chip C, and the logic synthesis chip C obtains the result difference of the execution results when the two logic synthesis chips (the logic synthesis chips in the main control channel and the hot standby control channel) execute the same function, in this embodiment, because it is determined whether the logic synthesis chip D of the hot standby control channel fails, the result difference is: the result of the target function executed by the logic integrated chip C of the main control channel is subtracted from the result of the target function executed by the logic integrated chip D of the hot standby control channel, wherein the result difference condition is a preset result difference threshold; when the result difference value when executing the same function is larger than the result difference value threshold value, the preset result difference value condition is met;
As shown in fig. 5, the result of the judgment of the algorithm execution chip B and the result of the judgment of the algorithm execution chip a are sent to the logic synthesis chip C (the logic synthesis chip C itself has a judgment whether the preset result difference condition is satisfied), so that the logic synthesis chip C judges whether the three results satisfy the corresponding conditions, and when at least two conditions among the three conditions of the first difference condition, the second cycle condition and the result difference condition are satisfied, the logic synthesis chip C judges that the logic synthesis chip D in the hot standby control channel fails.
Example 2
Taking an example of judging whether the algorithm execution chip A of the main control channel fails:
as shown in fig. 2, the logic integrated chip C in the main control channel is used to monitor the execution time (i.e. the actual execution time in the embodiment) of the program code in the algorithm execution chip a in the main control channel, wherein the present invention mainly controls the motor, so the actual execution time of the program code in the algorithm execution chip a mainly includes: the first actual execution time of the rotating speed loop code and the second actual execution time of the current loop code; and monitoring each clock cycle in the algorithm execution chip A in the main control channel by utilizing the logic synthesis chip D in the hot standby control channel, wherein each clock cycle in the algorithm execution chip A is as follows: a period of a system clock, a high-speed peripheral clock, and a low-speed peripheral clock; an algorithm execution chip A in the main control channel generates an estimated value (estimated value of rotating speed and current) of a motor control parameter output by a controller in the algorithm execution chip A, and an algorithm execution chip B in the hot standby control channel generates an estimated value of the motor control parameter output by the controller in the algorithm execution chip B; wherein, the two motor control parameters are the rotating speed parameter and the current parameter of the motor.
As shown in fig. 6, the actual code execution time of the program code in the algorithm execution chip a obtained by the logic synthesis chip C is sent to the logic synthesis chip D, and then the logic synthesis chip D determines whether the actual code execution time meets the set time condition; the logic integrated chip D obtains an estimated value difference value by taking the difference between the estimated values of the motor control parameters (rotating speed and current) of the algorithm execution chip B and the algorithm execution chip A, and judges whether the estimated difference value meets a set estimated difference value condition; and judging whether each clock period of the algorithm chip A meets a first period condition by the logic integrated chip D, and finally carrying out three-decision voting by the logic integrated chip D, wherein at least two conditions among the three conditions of the time condition, the first period condition and the estimated value difference value condition are met, and judging that the algorithm execution chip A in the main control channel fails by the logic integrated chip D.
Taking the example of judging whether the logic integrated chip C of the main control channel fails:
according to two chips in the main control channel, obtaining an estimated value and an actual value of a control parameter of the motor, namely, an algorithm execution chip A in the main control channel generates the estimated value of the motor control parameter of the motor; a logic integrated chip C in the main control channel acquires an actual value of a motor control parameter of the motor; executing a chip B by utilizing an algorithm in a hot standby control channel, and monitoring each clock cycle of a logic integrated chip C in a main control channel; the method comprises the steps of obtaining an execution result when a logic integrated chip C in a main control channel executes a target function, and obtaining an execution result when a logic integrated chip D in a hot standby control channel executes the target function, wherein the target function is as follows: a function of acquiring an actual value of a control parameter of the motor;
As shown in fig. 7, the algorithm execution chip a sends all the generated estimated value of the motor control parameter (rotation speed and current), the execution result when the logic synthesis chip C executes the target function, and each clock cycle of the logic synthesis chip C acquired by the algorithm execution chip B to the logic synthesis chip D, the logic synthesis chip D makes a difference between the estimated value of the motor control parameter of the motor and the actual value of the motor control parameter of the motor acquired by the logic synthesis chip C to obtain a first difference value, and determines whether the first difference value meets a first difference value condition, and the logic synthesis chip D determines whether each clock cycle of the logic synthesis chip C meets a second cycle condition; subtracting the result of the target function executed by the logic integrated chip D from the result of the target function executed by the logic integrated chip C of the main control channel, namely subtracting the actual value of the motor control parameter acquired by the logic integrated chip D from the actual value of the motor control parameter acquired by the logic integrated chip C to obtain a result difference value, and judging whether the result difference value meets a result difference value condition; so far, when at least two conditions of the first difference condition, the second period condition and the result difference condition are met, the logic integrated chip D judges that the logic integrated chip C in the main control channel fails.
In summary, in the self-monitoring method for the motor controller of the aviation dual-redundancy electromechanical actuating system provided by the embodiment of the invention, when an algorithm execution chip is monitored, the actual execution time of a program code corresponding to the algorithm execution chip, an estimated value of a motor control parameter output by the controller and each clock period are monitored through other three chips in two control channels, and then, whether the algorithm execution chip fails or not is comprehensively judged by utilizing the monitored three monitoring results and corresponding conditions and a three-decision voting method; when monitoring the logic integrated chip, monitoring each clock period corresponding to the logic integrated chip, an execution result when the two logic integrated chips execute the same function and an estimated value and an actual value of a control parameter of the motor through other three chips in the two control channels, and then comprehensively judging whether the logic integrated chip fails or not by utilizing a three-decision voting method based on the three monitoring results and corresponding conditions; therefore, the monitoring of faults is realized by utilizing the chips in the two control channels in the dual-redundancy controller, so that hardware resources are saved, whether the chips fail or not is comprehensively judged by utilizing a three-decision voting method, and the accuracy of monitoring results is ensured.
The foregoing description is merely illustrative of the presently preferred embodiments of the invention, and it is therefore to be understood that the invention is not limited to the specific embodiments disclosed.
Claims (10)
1. A method for self-monitoring a motor controller of an aircraft dual-redundancy electromechanical actuation system, comprising:
acquiring the actual execution time of program codes in algorithm execution chips in each control channel and each clock period according to the logic integrated chips in each control channel;
acquiring estimated values of motor control parameters output by a controller in two algorithm execution chips according to the algorithm execution chip of each control channel;
judging whether the algorithm execution chip of each control channel is invalid or not according to the actual execution time of the program codes, the estimated value of the motor control parameters output by the controllers in the two algorithm execution chips and each clock period;
according to two chips in the same control channel, obtaining an estimated value and an actual value of a control parameter of the motor;
the method comprises the steps that a chip is executed according to an algorithm of one control channel, and each clock cycle of a logic integrated chip in the other control channel is obtained;
Monitoring the execution result when the two logic integrated chips execute the same function according to the logic integrated chips in the two control channels;
judging whether the logic integrated chip in the corresponding control channel fails or not according to the execution result of each logic integrated chip in the two control channels when executing the same function, the estimated value and the actual value of the control parameter of the motor and each clock period of the logic integrated chip in the control channel;
wherein, the two control channels are a main control channel and a hot backup control channel.
2. The method of claim 1, wherein the step of obtaining the actual execution time of the program code in the algorithm execution chip in each control channel and each clock cycle comprises:
acquiring the actual execution time of program codes in algorithm execution chips in the corresponding control channels according to the logic comprehensive chips of each control channel;
the actual execution time of the program code is as follows: the actual execution time of the rotating speed loop program code and the actual execution time of the current loop program code in the algorithm execution chip;
acquiring each clock cycle in an algorithm execution chip in another control channel according to the logic synthesis chip in each control channel;
The clock cycles are the system clock cycle, the high-speed peripheral clock cycle and the low-speed peripheral clock cycle of the algorithm execution chip.
3. The method for self-monitoring a motor controller of an aircraft dual-redundancy electromechanical actuation system according to claim 1, wherein the step of obtaining an estimate of motor control parameters output by the controller in the two algorithm execution chips comprises:
generating an estimated value of a motor control parameter output by a controller in an algorithm execution chip in each control channel according to the algorithm execution chip in each control channel;
wherein, the two motor control parameters are the rotating speed parameter and the current parameter of the motor.
4. The method for self-monitoring a motor controller of an aircraft dual-redundancy electromechanical actuating system according to claim 1, wherein the step of monitoring the estimated and actual values of the rotational speed parameter and the current parameter of the motor according to two chips in the same control channel comprises:
acquiring an estimated value of a motor control parameter of the motor according to an algorithm execution chip of the same control channel;
acquiring an actual value of a motor control parameter of the motor according to a logic execution chip of the same control channel;
The motor control parameters are current parameters and rotation speed parameters of the motor.
5. The method of claim 1, wherein the step of determining whether the algorithm execution chip of each control channel is disabled comprises:
judging whether the actual execution time of each program code in the algorithm execution chip in the control channel meets the set time condition;
judging whether each clock period in an algorithm execution chip in a control channel meets a set first period condition, wherein the first period condition is a period threshold corresponding to each clock period in the algorithm execution chip, and when one clock period in all clock periods in the algorithm execution chip is larger than the corresponding period threshold, meeting the preset first period condition;
acquiring an estimated value difference value of motor control parameters output by a controller in an algorithm execution chip in the two control channels, and judging whether the estimated value difference value meets a set estimated value difference value condition;
and when at least two conditions among the three conditions of the time condition, the first period condition and the estimated value difference value condition are met, judging that the algorithm execution chip of the control channel fails.
6. The method for self-monitoring an aircraft dual-redundancy electromechanical actuating system motor controller according to claim 5, wherein the step of determining whether the actual execution time of the program code in the algorithm execution chip in the control channel satisfies the set time condition comprises:
the time conditions are as follows: the time required for the controller to execute each program code;
when the actual execution time of one of the program codes in the actual execution time of all the program codes is longer than the time required by the controller to execute the corresponding program code, the set time condition is satisfied.
7. The method of claim 5, wherein the step of determining whether the estimated value difference satisfies a set estimated value difference condition comprises:
the estimation value difference condition is an estimation value difference threshold value corresponding to each estimation value difference;
and when one of the estimated value difference values is larger than the corresponding estimated value difference value threshold value, meeting the estimated value difference value condition.
8. The method for self-monitoring an aircraft dual-redundancy electromechanical actuation system motor controller according to claim 1, wherein the step of determining whether the logic integrated chip in the corresponding control channel fails comprises:
Acquiring a first difference value between an estimated value and an actual value of a control parameter of the motor, and judging whether the first difference value meets a preset first difference value condition;
judging whether each clock cycle of the logic integrated chip in the control channel meets a preset second cycle condition, wherein the second cycle condition is a second cycle threshold corresponding to each clock cycle of the logic integrated chip, and when one clock cycle of all clock cycles of the logic integrated chip is larger than the second cycle threshold, the preset second cycle condition is met;
obtaining a result difference value of an execution result when the two logic integrated chips execute the same function, and judging whether the result difference value meets a preset result difference value condition;
and when at least two conditions among the first difference value condition, the second period condition and the result difference value condition are met, judging that the logic integrated chip in the corresponding control channel fails.
9. The method of claim 8, wherein the step of determining whether the resulting difference satisfies a predetermined resulting difference condition comprises:
the result difference condition is a preset result difference threshold;
When the result difference value when executing the same function is larger than the result difference value threshold value, the preset result difference value condition is met;
the functions performed are: and acquiring the actual value of the control parameter of the motor.
10. The method of claim 8, wherein the step of determining whether the first difference satisfies a predetermined first difference condition comprises:
the first difference condition is a first difference threshold corresponding to each first difference;
and when one of the first difference values is larger than the corresponding first difference value threshold value, the first difference value condition is met.
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