CN116897509A

CN116897509A - Transmitter and signal processing method

Info

Publication number: CN116897509A
Application number: CN202280008686.1A
Authority: CN
Inventors: 屠国平
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-02-09
Filing date: 2022-02-09
Publication date: 2023-10-17
Also published as: WO2023150930A1

Abstract

The application discloses a transmitter and a signal processing method, which have smaller power loss and higher safety. At least one power amplifying circuit and a matching circuit; the matching circuit is coupled to the antenna; the power amplifying circuit comprises a plurality of switch capacitor circuits; the power supply circuit is coupled with the plurality of switch capacitance circuits; the power supply circuit is used for selectively providing a first level and a second level for the switch capacitor circuit, wherein the first level is smaller than the second level; the switched capacitor circuit comprises a first high-side switch, a first low-side switch and a capacitor, wherein the first high-side switch and the first low-side switch are coupled in series between the power supply circuit and the ground terminal, the capacitor is coupled with the first high-side switch and the first low-side switch, and the capacitor is coupled to the matching circuit; a first high-side switch for selectively receiving a first steady-state signal and a first digitally adjustable drive signal; a first low side switch for selectively receiving the second steady state signal and the second digitally adjustable drive signal.

Description

Transmitter and signal processing method

Technical Field

The present application relates to the field of electronic technology, and in particular, to a transmitter and a signal processing method.

Background

The switched capacitor digital power amplifier (switched capacitor digital power amplifier, SCDPA) is a power amplifier composed of a plurality of switched capacitor circuits. SCDPA is widely used in transmitters such as polar transmitters (polar transmitter, polar TX) because of the good linearity of the output voltage of switched capacitor circuits.

Switched capacitor circuits typically operate at one supply voltage, while switched capacitor circuits operate at a different supply voltage, resulting in greater power loss and lower safety, affecting transmitter operation.

Disclosure of Invention

The application provides a transmitter and a signal processing method, which have smaller loss on a power supply and higher safety.

In a first aspect, the present application provides a transmitter, which may have at least one power amplifying circuit and a matching circuit; the matching circuit is coupled to an antenna; the power amplifying circuit comprises a plurality of switch capacitor circuits; the plurality of switched-capacitor circuits are connected in parallel, the plurality of switched-capacitor circuits being coupled to a power supply circuit; the power supply circuit is used for selectively providing a first level and a second level for the switched capacitor circuit, wherein the first level is smaller than the second level; the switched capacitor circuit comprises a first high-side switch, a first low-side switch and a capacitor, wherein the first high-side switch and the first low-side switch are coupled in series between the power supply circuit and the ground terminal, and the capacitor is coupled between a connection point of the first high-side switch and the first low-side switch and the matching circuit. The first high-side switch can selectively receive a first steady-state signal and a first digital adjustable driving signal, so that the power supply circuit charges the capacitor through the first high-side switch; the first low side switch may selectively receive a second steady state signal and a second digitally adjustable drive signal to discharge the capacitor through the first low side switch.

In the embodiment of the application, the power supply circuit can have the capability of providing different levels, so that the transmitter can support outputting various transmitting powers. The driving signal of the first high-side switch is configurable, and can be a first steady-state signal or a first digital adjustable driving signal. The drive signal of the first low-side switch is also configurable, and may be a second steady state signal or a second digitally adjustable drive signal. For example, in the case where the power supply circuit provides the first level, the first high-side switch may receive the first digitally adjustable drive signal, which may cause the power supply circuit to charge a capacitor in the switching circuit through the first high-side switch. The first low side switch may receive a second digitally adjustable drive signal, which may discharge the capacitor through the first low side switch. At this time, the power supply circuit does not need to provide extra charges for the parasitic capacitance of the first high-side switch, so that power loss can be avoided, the charging and discharging speed of the power supply circuit to the capacitor is improved, and the emission efficiency is improved. For another example, in a case where the power supply circuit provides the second level, the first high-side switch may receive the first steady-state signal, and put the first high-side switch in the on state. The power supply circuit may charge the capacitor through the first high-side switch. Because the first high-side switch has on-resistance, the first high-side switch can play a role in voltage division, and the safety and the reliability of the switch capacitor circuit can be improved. The first low-side switch may receive a second steady-state signal, placing the first low-side switch in an on-state. The capacitor may be discharged through the first low side switch. The first low-side switch has on-resistance, so that the first low-side switch can play a role in voltage division, and the safety and reliability of the circuit of the switch capacitor can be improved. Therefore, the first high-side switch and the first low-side switch can be flexibly matched under different voltages, so that the switched capacitor circuit has low power loss, the safety of the switched capacitor circuit can be considered, and the transmitting power and the transmitting efficiency of the transmitter are improved.

In one possible design, the transmitter may include one or more configuration states. Different configuration states of the transmitter can realize different transmission modes of the transmitter. For example, the transmitter may include a first configuration state. The first configuration state of the transmitter may enable a low power transmit operating state of the transmitter. In a first configuration state, the power supply circuit may provide the first level, the first high-side switch may be configured to receive the first digitally-adjustable drive signal, and the first low-side switch may be configured to receive the second digitally-adjustable drive signal such that the power supply circuit does not charge parasitic capacitance of the first high-side switch and parasitic capacitance of the first low-side switch. Wherein the conduction period of the first high-side switch and the conduction period of the first low-side switch may not overlap or partially overlap.

In the embodiment of the application, the first high-side switch and the first low-side switch can directly receive the digital adjustable driving signal, and the charging speed of the power supply circuit to the capacitor and the discharging speed of the capacitor can be improved. And before the power supply circuit charges the capacitor and before the capacitor discharges, the power supply circuit is not required to provide additional charges for the parasitic capacitor of the first high-side switch, so that power loss is avoided, the charging and discharging speed of the power supply circuit to the capacitor is improved, and the emission efficiency is improved.

In one possible design, the transmitter may include a second configuration state. The second configuration state of the transmitter may enable a high power transmit operating state of the transmitter. In a second configuration state, the second level may be provided at the power supply circuit, the first high side switch may be configured to receive the first steady state signal, and the first low side switch may be configured to receive the second steady state signal, causing the first high side switch to divide and the first low side switch to divide. In the embodiment of the application, the first high-side switch and the second low-side switch can play a role in voltage division, so that the switch in the switched capacitor circuit can be protected, and the reliability and the safety of the switched capacitor circuit are improved.

In one possible design, the switched-capacitor circuit may further include a second high-side switch and a second low-side switch; the second high-side switch is coupled between the power supply circuit and the first high-side switch for selectively receiving a third steady-state signal and a third digitally adjustable drive signal; the second low-side switch is coupled between the first low-side switch and the ground for selectively receiving a fourth steady-state signal and a fourth digitally adjustable drive signal. In the embodiment of the application, the second high-side switch and the second low-side switch can have voltage division function, so that the first high-side switch and the second high-side switch are protected, and the reliability and the safety of the switched capacitor circuit are improved.

In one possible design, the switched-capacitor circuit further comprises a third high-side switch and a third low-side switch; the third high-side switch is connected in parallel with the second high-side switch, and the third low-side switch is connected in parallel with the second low-side switch. In the embodiment of the application, the conduction internal resistance of the third high-side switch is connected in parallel with the conduction internal resistance of the second high-side switch, so that the conduction internal resistances of the two switches are reduced, the output power loss of the power supply circuit can be reduced, and the output power and the efficiency of the switch capacitor circuit are improved. The conduction internal resistance of the third low-side switch is connected in parallel with the conduction internal resistance of the second low-side switch, so that the conduction internal resistances of the two switches are reduced, the output power loss of the power supply circuit can be reduced, and the output power and the efficiency of the switched capacitor circuit are improved.

In one possible design, in the first configuration state, the power supply circuit may provide the first level, the second high-side switch may receive the third steady-state signal, and the second low-side switch may receive the fourth steady-state signal, causing the second high-side switch to divide and the second low-side switch to divide.

In a possible design, in the second configuration state, the power supply circuit may provide the second level, the second high-side switch receives the third digitally-adjustable drive signal, and the second low-side switch receives the fourth digitally-adjustable drive signal; wherein the conduction period of the second high-side switch and the conduction period of the second low-side switch do not overlap or partially overlap.

In one possible design, the source of the first high-side switch is coupled to the power supply circuit, the drain of the first high-side switch is coupled to a first pole of the capacitor, and a second pole of the capacitor is coupled to the matching circuit. The source of the first low-side switch is coupled to the ground and the drain of the first low-side switch is coupled to a first pole of the capacitor. In an embodiment of the present application, the first high-side switch may be a metal oxide semiconductor transistor, and the first low-side switch may be a metal oxide semiconductor transistor.

In one possible design, if the switched capacitor circuit includes a second high-side switch and a second low-side switch, the source of the first high-side switch is coupled to the power supply circuit through the second high-side switch, and the source of the first low-side switch is coupled to the ground through the second low-side switch. In an embodiment of the present application, the second high-side switch may be a metal oxide semiconductor transistor, and the second low-side switch may be a metal oxide semiconductor transistor.

In one possible design, the impedance of the matching circuit is adapted to the voltage of the capacitive outputs of the plurality of switched-capacitor circuits such that the power of the signal output by the matching circuit to the antenna is the same as the desired transmit power.

In a second aspect, embodiments of the present application provide a switched capacitor circuit coupled to a power supply circuit for selectively providing the switched capacitor circuit with a first level and a second level, wherein the first level is less than the second level. The switched capacitor circuit comprises a first high-side switch, a first low-side switch and a capacitor, wherein the first high-side switch and the first low-side switch are coupled in series between the power supply circuit and the ground terminal, and the capacitor is coupled between a connection point of the first high-side switch and the first low-side switch and the matching circuit. The first high-side switch may be configured to selectively receive a first steady state signal and a first digitally adjustable drive signal to cause the power circuit to charge the capacitor through the first high-side switch. The first low-side switch coupling may be used to selectively receive a second steady state signal and a second digitally adjustable drive signal to discharge the capacitance through the first low-side switch.

In one possible design, the switched-capacitor circuit may include one or more configuration states. For example, the switched-capacitor circuit includes a first configuration state. In a first configuration state, the power supply circuit may be configured to provide the first level, the first high-side switch may be configured to receive the first digitally-adjustable drive signal, and the first low-side switch may be configured to receive the second digitally-adjustable drive signal such that the power supply circuit does not charge parasitic capacitance of the first high-side switch and parasitic capacitance of the first low-side switch; wherein the conduction period of the first high-side switch does not overlap or partially overlap with the conduction period of the first low-side switch.

In one possible design, the switched-capacitor circuit may include a second configuration state. In a second configuration state, the power supply circuit may be configured to provide the second level, the first high-side switch may be configured to receive the first steady-state signal, and the first low-side switch may be configured to receive the second steady-state signal, causing the first high-side switch to divide and the first low-side switch to divide.

In one possible design, the switched-capacitor circuit further comprises a second high-side switch and a second low-side switch; the second high-side switch is coupled between the power supply circuit and the first high-side switch for selectively receiving a third steady-state signal and a third digitally adjustable drive signal; the second low-side switch is coupled between the first low-side switch and the ground for selectively receiving a fourth steady-state signal and a fourth digitally adjustable drive signal.

In one possible design, the switched-capacitor circuit further comprises a third high-side switch and a third low-side switch; the third high-side switch is connected in parallel with the second high-side switch, and the third low-side switch is connected in parallel with the second low-side switch.

In one possible design, in the first configuration state, the power supply circuit is configured to provide the first level, the second high-side switch may be configured to receive the third steady-state signal, and the second low-side switch may be configured to receive the fourth steady-state signal, such that the second high-side switch is divided and the second low-side switch is divided.

In one possible design, in the second configuration state, the power supply circuit provides the second level, the second high-side switch may be configured to receive the third digitally-adjustable drive signal, and the second low-side switch may be configured to receive the fourth digitally-adjustable drive signal. Wherein the conduction period of the second high-side switch and the conduction period of the second low-side switch do not overlap or partially overlap.

In one possible design, the source of the first high-side switch is coupled to the power supply circuit, the drain of the first high-side switch is coupled to a first pole of the capacitor, and a second pole of the capacitor is coupled to the matching circuit; the source of the first low-side switch is coupled to the ground and the drain of the first low-side switch is coupled to a first pole of the capacitor.

In one possible design, if the switched capacitor circuit includes a second high-side switch and a second low-side switch, the source of the first high-side switch is coupled to the power supply circuit through the second high-side switch, and the source of the first low-side switch is coupled to the ground through the second low-side switch.

In a third aspect, embodiments of the present application provide a switched capacitor digital power amplifier, at least one power amplifying circuit, and a matching circuit; the matching circuit is coupled to an antenna; the power amplifying circuit comprises a plurality of switch capacitor circuits; the plurality of switched-capacitor circuits are connected in parallel, the plurality of switched-capacitor circuits being coupled to a power supply circuit; the power supply circuit is used for selectively providing a first level and a second level for the switched capacitor circuit, wherein the first level is smaller than the second level; wherein any one of the plurality of switched capacitor circuits may be a switched capacitor circuit as described in any one of the second aspect and any one of its possible designs.

In a fourth aspect, an embodiment of the present application provides a signal processing method, which may be used in a transmitter according to the first aspect and any one of the designs thereof, or in a switched capacitor digital power amplifier according to the third aspect and any one of the designs thereof. The signal processing method may include: selectively providing a first level and a second level to a switched capacitor circuit in a power amplification circuit, wherein the first level is less than the second level; the switch capacitor circuit comprises a first high-side switch, a first low-side switch and a capacitor, wherein the first high-side switch and the first low-side switch are coupled between the power supply circuit and the ground in series, and the capacitor is coupled between a connection point of the first high-side switch and the first low-side switch and the matching circuit; a first high-side switch of the switched-capacitor circuit selectively receives a first steady-state signal and a first digitally adjustable drive signal; the first low side switch of the switched capacitor circuit selectively receives a second steady state signal and a second digitally adjustable drive signal.

In one possible design, the switched-capacitor digital power amplifier may further include a matching circuit, the capacitance of the switched-capacitor circuit may be coupled to the matching circuit, and the matching circuit is coupled to the antenna.

In one possible design, the first high-side switch may receive the first digitally adjustable drive signal if the first level is provided to the switched-capacitor circuit; the first low side switch may receive the second digitally adjustable drive signal. In some examples, the first digitally adjustable drive signal and the second digitally adjustable drive signal may cause the conduction period of the first high side switch to not overlap or partially overlap with the conduction period of the first low side switch.

In one possible design, the first high-side switch may receive the first steady-state signal and the first low-side switch may receive the second steady-state signal if the second level is provided to the switched-capacitor circuit. In some examples, the first steady state signal may place the first high side switch in a conductive state and the second steady state signal may place the first low side switch in a conductive state.

In one possible design, the switched-capacitor circuit further comprises a second high-side switch and a second low-side switch; the second high-side switch may be coupled with a first high-side switch, e.g., a second high-side switch may be coupled between a supply circuit providing a level to a switched-capacitor circuit and the first high-side switch, and a second low-side switch may be coupled between the first low-side switch and the ground. The method may further include the second high-side switch selectively receiving a third steady-state signal and a third digitally adjustable drive signal; the second low side switch selectively receives a fourth steady state signal and a fourth digitally adjustable drive signal.

In some examples, if the first level is provided to the switched-capacitor circuit, the second high-side switch may receive a third steady-state signal and the second low-side switch may receive a fourth steady-state signal. In other examples, the second high-side switch may receive a third digitally tunable drive signal if the second level is provided to the switched-capacitor circuit; and the second low side switch may receive a fourth digitally adjustable drive signal.

In one possible design, the third digitally adjustable drive signal and the fourth digitally adjustable drive signal may cause the conduction period of the second high side switch to not overlap or partially overlap with the conduction period of the second low side switch.

In one possible design, the switched-capacitor circuit further comprises a third high-side switch and a third low-side switch; the third high-side switch is connected in parallel with the second high-side switch, and the third low-side switch is connected in parallel with the second low-side switch. The method may further comprise: the third high-side switch receives the first digitally tunable drive signal and the third low-side switch receives the second digitally tunable drive signal if the first level is provided to the switched-capacitor circuit.

In one possible design, the signal processing method may further include: if the second level is provided to the switched capacitor circuit, the third high-side switch is in an open state; and the third low side switch is in an open state.

In a fifth aspect, an embodiment of the present application further provides a signal processing method, which may be used in the second aspect and any one of the designs of the switched capacitor circuit. The signal processing method may include selectively providing a first level and a second level to the switched-capacitor circuit, wherein the first level is less than the second level; a first high-side switch of the switched-capacitor circuit selectively receives a first steady-state signal and a first digitally adjustable drive signal; the first low side switch of the switched capacitor circuit selectively receives a second steady state signal and a second digitally adjustable drive signal.

In one possible design, the capacitance of the switched-capacitor circuit may be coupled to a matching circuit, which is coupled to the antenna.

In one possible design, the first high-side switch receives the first digitally adjustable drive signal if the first level is provided to the switched-capacitor circuit; the first low side switch receives the second digitally adjustable drive signal. In some examples, the first digitally adjustable drive signal and the second digitally adjustable drive signal may cause the conduction period of the first high side switch to not overlap or partially overlap with the conduction period of the first low side switch.

In one possible design, the first high-side switch receives the first steady-state signal and the first low-side switch receives the second steady-state signal if the second level is provided to the switched-capacitor circuit. In some examples, the first steady state signal may place the first high side switch in a conductive state and the second steady state signal may place the first low side switch in a conductive state.

In one possible design, the third digitally adjustable drive signal and the fourth digitally adjustable drive signal may cause the conduction period of the second high side switch to completely overlap or partially overlap with the conduction period of the second low side switch.

In one possible design, the switched-capacitor circuit further comprises a third high-side switch and a third low-side switch; the third high-side switch is connected in parallel with the second high-side switch, and the third low-side switch is connected in parallel with the second low-side switch. The method further comprises the steps of: the third high side switch may receive the first digitally tunable drive signal and the third low side switch may receive the second digitally tunable drive signal if the first level is provided to the plurality of switched capacitor circuits.

In one possible design, the signal processing method may further include: if the second level is provided to the switched capacitor circuit, the third high side switch may be in an off state and the third low side switch may be in an off state.

The technical effects that can be achieved by the second aspect to the fifth aspect are described with reference to the technical effects that can be achieved by the corresponding designs in the first aspect, and the detailed description is not repeated here.

Drawings

FIG. 1 is a schematic diagram of a prior art transmitter;

FIG. 2 is a schematic diagram of another prior art transmitter;

FIG. 3 is a schematic diagram of a transmitter;

FIG. 4 is a schematic diagram of a switched capacitor circuit in a transmitter;

FIG. 5 is a schematic diagram of a digitally tunable drive signal;

FIG. 6 is a schematic diagram of a switched capacitor circuit;

FIG. 7 is a schematic diagram of the operation of the switched capacitor circuit at different levels;

FIG. 8 is a schematic diagram of another switched capacitor circuit;

FIG. 9 is a schematic diagram of a further switched capacitor circuit;

FIG. 10 is a schematic diagram of a specific construction of the circuit of the switched capacitor;

FIG. 11 is a schematic diagram of the operation of the switched capacitor circuit at different levels;

fig. 12 is a schematic diagram of a structure of a signal modulation unit corresponding to a switched capacitor circuit;

fig. 13 is a schematic diagram of a signal modulation unit corresponding to another switched capacitor circuit;

fig. 14 is a schematic flow chart of a signal processing method.

Detailed Description

As application scenarios increase, transmitters (TX) are required to have the ability to provide a variety of transmit powers. The higher the TX transmit power, the farther the transmission distance. Different powers of TX transmissions may satisfy different communication distances. As in super bluetooth systems, for example, the analog TX transmits 20dBm of power, communication between two devices up to a distance of 100 meters or more may be supported. In the bluetooth system, however, most of the two devices performing bluetooth communication have a distance within 10 meters, and the analog TX transmit power of 10dBm can satisfy the communication between the two devices having a distance within 10. If the analog TX transmits 20dBm power to support two devices within 10 meters of distance, resources and power consumption are wasted. The Power Amplifier (PA) transmit power in analog TX is thus backed off from a mode of 20dBm power to below 10 dBm. According to the characteristic of a monotonic curve of the transmission efficiency of the PA in the analog TX, the power backoff greatly decreases the transmission efficiency of the PA and decreases the battery utilization efficiency.

Polar TX based on digital circuit technology is well-developed with its high output power, efficiency and process portability. Currently, SCDPA is mostly adopted by polar TX. As shown in fig. 1, the SCDPA of the existing polar TX includes a first power amplifying branch and a second power amplifying branch. Each power amplifying branch circuit comprises a plurality of switch capacitor circuits. The first power amplifying branch is coupled to the matching network through a metal oxide semiconductor field effect (metal oxide semiconductor, MOS) switch 1 and the second power amplifying branch is coupled to the matching network through a MOS switch 2. The control circuit of the polar TX realizes the selection of the power amplification branch to amplify the power of the signal by controlling the conduction states of the MOS switch 1 and the MOS switch 2.

The first power amplifying branch is configured to output a high transmit power, and is provided with a first supply voltage, typically 1.8V, by a first power supply. Each switched capacitor circuit in the first power amplification branch is composed of a plurality of MOS switches and capacitors, such as the first SCDPA unit shown in fig. 1, where the plurality of MOS switches included in the first SCDPA unit include a plurality of P-channel metal oxide semiconductor field effect transistors (positive channel metal oxide semiconductor, PMOS) and a plurality of N-type metal oxide semiconductors (N metal oxide semiconductor, NMOS), respectively denoted PMOS1, PMOS2, NMOS1, NMOS2, and the capacitors included in the first SCDPA unit are denoted Cu1.PMOS1, PMOS2, NMOS1, NMOS2 are serially connected in sequence between the first power supply and ground, wherein PMOS2 and NMOS1 are coupled to a first pole of Cu1, respectively. The second pole of Cu1 is coupled to the MOS switch 1. When any one of the first switched capacitor circuits is used for outputting the level, in the first switched capacitor circuit, the PMOS1 is configured to receive the phase modulation signal, the NMOS2 is configured to receive the phase modulation signal, and the PMOS1 and the NMOS2 are not turned on at the same time. In the first SCDPA unit, the PMOS2 and the NMOS1 are in the conducting state for voltage division, damage caused by overhigh voltage division of the PMOS1 and the NMOS2 is avoided, and the reliability of the PMOS1 and the NMOS2 is ensured.

Similarly, each switched-capacitor circuit in the second power amplification branch is composed of a plurality of MOS switches and capacitors, as in the second switched-capacitor circuit shown in fig. 1, the plurality of MOS switches included in the second switched-capacitor circuit are PMOS3 and NMOS3, respectively, and the capacitor included in the second switched-capacitor circuit is denoted as Cu2.PMOS3 and NMOS3 are connected in series between the first power supply and ground. PMOS3 and NMOS3 are coupled to a first pole of Cu2, respectively, and a second pole of Cu2 is coupled to MOS switch 2.PMOS3 is configured to receive the phase modulated signal and NMOS3 is configured to receive the phase modulated signal, and PMOS3 and NMOS3 are not normally turned on at the same time.

Since the output power of the first power amplification branch is higher, the MOS switch 1 needs to be adapted to the output power of the first power amplification branch. The MOS switch 1 is typically a high voltage resistant MOS switch, which has a certain signal loss, typically about 1 to 2dB. While the output power of the second power amplification branch is lower, the MOS switch 2 is usually a MOS switch with a smaller voltage-resisting capability than the MOS switch 1, and the signal loss of the MOS switch 2 may be smaller than the signal loss of the MOS switch 1. The transmission efficiency of the first power amplifying branch may typically be up to 30%. The transmission efficiency of the second power amplifying branch may typically be up to 40%.

The more first switch capacitance circuits in the first power amplification branch, the stronger the voltage withstand capability of the MOS switch 1 matched to the output power of the first power amplification branch, the greater the signal loss of the MOS switch 1, resulting in lower emission efficiency. Similarly, if the more second switched capacitor circuits in the second power amplification branch, the stronger the voltage withstand capability of the MOS switch 2 matched to the output power of the second power amplification branch, the greater the signal loss of the MOS switch 2 will also result in lower emission efficiency.

The more voltage-withstand the cost of a MOS switch is greater. It can be seen that the more cost the DPA of the polar TX is, the lower the transmission efficiency is in the existing architecture of the polar TX supporting multiple power outputs. Thus, a polar TX supporting output of multiple transmit powers using one power amplification branch is proposed. As shown in fig. 2, the first power amplifying branch is connected to a power supply circuit. The power supply circuit may provide two levels to the first switched capacitor circuit. The pole TX operates in a high power mode, the power supply circuit provides the first switched capacitor circuit with a level of 1.8V, the pmos1 and NMOS2 receive the phase modulated signal, and the level of the phase modulated signal varies between 0.9-1.8V. The PMOS1 is driven by the phase modulation signal to charge the capacitor Cu1 by the power supply circuit. The NMOS1 discharges the capacitor Cu1 by the phase modulation signal. The level of the steady state signal received by PMOS2 is 0.9V. The level of the steady state signal received by NMOS2 is 0.9V.

The pole TX operates in a low power mode, the power supply circuit supplies the first switched capacitor circuit with a level of 0.9V, the pmos1 and NMOS2 receive the phase modulated signal, and the level of the phase modulated signal varies between 0-0.9V. The PMOS1 is driven by the phase modulation signal to charge the capacitor Cu1 by the power supply circuit. The NMOS1 discharges the capacitor Cu1 by the phase modulation signal. The level of the steady state signal received by PMOS2 is 0V. The level of the steady state signal received by NMOS2 is 0.9V.

It follows that providing the first switched capacitor circuit with two levels by the power supply circuit may enable the polar TX to support a plurality of transmit powers. However, in the low power mode, when the power supply circuit charges the capacitor, additional charges are required to be applied to the source parasitic capacitance of the PMOS2 and the source parasitic capacitance of the NMOS2 in each signal period, so that power consumption is increased, and output power is reduced and emission efficiency is reduced. If the loss of PMOS2 and NMOS2 is reduced to reduce the power consumption, the on-resistances of PMOS2 and NMOS2 become small, which easily causes the damage of PMOS1 and NMOS1, and the security or reliability is reduced. Therefore, when the first switch capacitor circuit works under different power supply voltages, the power supply loss is large, the safety is low, and the reliability and the emission efficiency of the transmitter are affected.

Therefore, the embodiment of the application provides a transmitter which can support various transmitting powers, has small power loss, high transmitting efficiency and high safety.

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings. The specific method of operation in the method embodiment may also be applied to the device embodiment or the system embodiment. In the description of the present application, "at least one" means one or more, wherein a plurality means two or more. In view of this, the term "plurality" may also be understood as "at least two" in embodiments of the present application. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/", unless otherwise specified, generally indicates that the associated object is an "or" relationship. In addition, it should be understood that in the description of the present application, the words "first," "second," and the like are used merely for distinguishing between the descriptions and not for indicating or implying any relative importance or order.

It should be noted that in embodiments of the present application, "coupled" may be understood as electrically connected, and that two electrical components may be coupled directly or indirectly to each other. For example, a may be coupled to B directly, or indirectly via one or more other electrical components, such as a may be coupled to B directly, or a may be coupled to C directly, or C may be coupled to B directly, where a and B are connected via C. In some cases, "coupled" may also be understood as connected. In summary, the connection between a and B may enable the transfer of electrical energy between a and B.

It should be noted that the switching transistors and switches in the embodiments of the present application may be one or more of various types of switching transistors such as a relay, a metal oxide semiconductor (metal oxide semiconductor, MOS) transistor, a bipolar junction transistor (bipolar junction transistor, BJT), an insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT), and the like, which are not specifically mentioned in the embodiments of the present application. Each switching tube can comprise a first electrode, a second electrode and a control electrode, wherein the control electrode is used for controlling the on or off of the switching tube. When the switching tube is turned on, current can be transmitted between the first electrode and the second electrode of the switching tube, and when the switching tube is turned off, current cannot be transmitted between the first electrode and the second electrode of the switching tube. Taking a MOSFET as an example, the control electrode of the switching tube may be a gate electrode, the first electrode of the switching tube may be a source electrode of the switching tube, the second electrode may be a drain electrode of the switching tube, or the first electrode may be a drain electrode of the switching tube, and the second electrode may be a source electrode of the switching tube.

Referring to fig. 3 (a), a transmitter according to an embodiment of the present application may include at least one power amplifying circuit 20A. At least one power amplifying circuit is coupled to the power supply circuit 20B, respectively. At least one power amplification circuit 20A is coupled to a matching circuit 20C (or matching network) of the transmitter, respectively. The matching circuit 20C is coupled to an antenna 20D. The impedance of the matching circuit 20C may be adapted to the voltage output by the at least one power amplifying circuit 20A such that the power of the signal output by the matching circuit 20C to the antenna 20D is the same as the desired power.

In one possible design, as shown in fig. 3 (b), the transmitter may include a power amplifying circuit, denoted as first power amplifying circuit 301. The first power amplifying circuit 301 is coupled to the matching circuit, and may form part or all of the single-ended SCDPA. In this design, the matching circuit 20C of the transmitter may include, but is not limited to, a first matching circuit 302. Fig. 3 (b) shows a schematic diagram of a structure of a first matching circuit 302 according to an exemplary embodiment, an input terminal of the first matching circuit 302 is coupled to an output terminal of the first power amplifying circuit 301, an output terminal of the first matching circuit 302 is coupled to an antenna, the first matching circuit 302 may include a first inductor L1 and a first capacitor C1, and the first inductor L1 is coupled between the input terminal and the output terminal of the first matching circuit 302. The first capacitor C1 is coupled between the output terminal of the first matching circuit 302 and the ground terminal. Note that the structural description of the first matching circuit 302 in this example is only for illustration, and is not a specific limitation of the matching circuit 20C in the transmitter.

In another possible design, as shown in (c) of fig. 3, the at least one first power amplifying circuit 20A may include a plurality of power amplifying circuits. The plurality of power amplifying circuits are coupled to the matching circuit 20C, respectively, and may constitute part or all of the differential SCDPA. The plurality of power amplifying circuits may be denoted as a second power amplifying circuit 401 and a third power amplifying circuit 402, respectively. The operating levels of the plurality of power amplifying circuits are the same, for example, the transmitter is in the first transmission power mode, the power supply circuit 20B supplies the first level to the second power amplifying circuit 401, and supplies the first level to the third power amplifying circuit 402. For another example, in the second transmission mode, the power supply circuit 20B supplies the second power amplifying circuit 401 with the second level, and supplies the third power amplifying circuit 402 with the second level.

When the second power amplifying circuit 401 and the third power amplifying circuit 402 work, the digital adjustable driving signal SA received by the second power amplifying circuit 401 is different from the digital adjustable driving signal SB received by the third power amplifying circuit 402, wherein the digital adjustable driving signal SA received by the second power amplifying circuit 401 and the digital adjustable driving signal SB received by the third power amplifying circuit 402 have an inverse relation. For example, after the digital adjustable driving signal SA is input to the inverter, the signal output by the inverter is the digital adjustable driving signal SB. In such a design, multiple power amplifying circuits may form a differential SCDPA structure. In this design, the matching circuit 20C of the transmitter may be referred to as a second matching circuit 403. Fig. 3 (b) shows a schematic diagram of the structure of the second matching circuit 403 according to an exemplary embodiment. The second matching circuit 403 may have two inputs, input in1 and input in2, respectively, an output of the second power amplification circuit 401 may be coupled to the input in1, and an output of the third power amplification circuit 402 may be coupled to the input in2. The second matching circuit 403 may include a first winding N1, a second winding N2, and a second capacitor C1. A first end of the first winding N1 is coupled to the input terminal in1, and a second end of the first winding N1 is coupled to the input terminal in2. The first end of the second winding N2 is coupled to the output out of the matching circuit and the second end of the second winding is coupled to ground. One pole of the second capacitor C1 is coupled to the output terminal out, and the other pole is coupled to the ground terminal. When the first end of the first winding N1 is a high-potential end, the second end of the second winding is a high-potential end. Or the first end of the first winding N1 is a low potential end and the second end of the second winding is a low potential end. The description of the structure of the second matching circuit 403 in this example is merely for illustration, and is not a specific limitation of the matching circuit in the transmitter.

In an embodiment of the present application, as shown in fig. 4, any one of the at least one power amplifying circuits 20A may include a plurality of switched capacitor circuits 201. The plurality of switched capacitor circuits 201 are connected in parallel. For example, one end of each switched-capacitor circuit 201 may be coupled to a power supply circuit, and the other end of each switched-capacitor circuit 201 may be coupled to ground. Alternatively, each switched-capacitor circuit 201 may be disposed between the power supply circuit 20B and ground. In some examples, the structure of any one of the first power amplifying circuit 301, the second power amplifying circuit 401, and the third power amplifying circuit 402 in the foregoing examples may be the same as that of the power amplifying circuit provided in the embodiment of the present application.

The power supply circuit 20B may supply power to each switched capacitor circuit 201. The power supply circuit 20B may have the capability to provide a first level and a second level, wherein the first level is less than the second level. The power supply circuit 20B may selectively provide the switched capacitor circuit 201 with a first level and a second level. For example, the power supply circuit 20B may provide the first level and the second level to each of the switched capacitor circuits 201, so that each of the switched capacitor circuits 201 receives the first level or the second level, and the power supply circuit 20B may supply power to each of the switched capacitor circuits 201 at one of the first level and the second level. For another example, the power supply circuit 20B may provide a first level to each of the switched-capacitor circuits 201 to facilitate each of the switched-capacitor circuits 201 receiving the first level. For another example, the power supply circuit 20B may provide a second level to each of the switched-capacitor circuits 201 to facilitate each of the switched-capacitor circuits 201 receiving the second level.

The transmitter may include one or more configuration states. Different configuration states of the transmitter can realize different transmission modes of the transmitter. For example, the transmitter may be in a first configuration state, and may be enabled to operate in a first transmit power mode. The transmitter is in a second configuration state and may be enabled to operate in a second transmit power mode. In some examples, the power of the transmitted signal by the transmitter operating in the first transmit power mode is lower than the power of the transmitted signal by the transmitter operating in the second transmit power mode.

The transmitter operates in a first transmit power mode, and the amplitude modulation signal corresponding to the first transmit power mode may cause at least one switched capacitor circuit 201 of the plurality of switched capacitor circuits 201 to receive the first level provided by the power supply circuit 20B. The first level is a voltage corresponding to the first transmit power mode. The transmitter operates in the second transmission power mode, and the amplitude modulation signal corresponding to the second transmission power mode may enable at least one switched capacitor circuit 201 of the plurality of switched capacitor circuits 201 to receive a second level provided by the power supply circuit 20B, where the second level is a voltage corresponding to the second transmission power mode.

In the embodiment of the present application, the first transmission power mode and the second transmission power mode are only used as examples, and are not used as specific limitations that the SCDPA provided by the present application can support multiple transmission power modes. The SCDPA provided by the embodiment of the application can support a third transmitting power mode, a fourth transmitting power mode and the like. Description of the application the present application provides that SCDPA can support a plurality of transmit power modes, a first transmit power mode and a second transmit power mode are given below as examples. The first power supply in the first transmit power mode provides a first level that is less than the second level provided by the first power supply in the second transmit power mode. Among the first and second transmission power modes, the first transmission power mode may be referred to as a low power mode and the second transmission power mode may be referred to as a high power mode. Thus, the transmitter in the first configuration state may also be referred to as in a low power mode, or as a first transmit power mode. The transmitter is in the second configuration state, which may also be referred to as a high power mode, or as a second transmit power mode. The present application does not distinguish this too much. In conjunction with the foregoing description of the power supply circuit 20B, in the low power mode, the power supply circuit 20B provides the first level. In the high power mode, the power supply circuit 20B provides a second level. The operation of the switched capacitor circuit 201 in the low power mode and the high power mode will be described below with reference to the configuration of the switched capacitor circuit 201.

In an embodiment of the present application, referring to fig. 4 again, any one of the switched capacitor circuits 201 may include a first high-side switch HS1, a first low-side switch LS1, and a capacitor Cu. Wherein the first high-side switch HS1 and the first low-side switch LS1 are coupled in series. A plurality of switched-capacitor circuits 201 are connected in parallel, each switched-capacitor circuit 201 being coupled between the supply circuit 20B and ground. In any of the switched capacitor circuits 201, the first high-side switch HS1 may be coupled to the power supply circuit 20B, and the first low-side switch LS1 may be coupled to the ground. It can be seen that in any one of the switched capacitor circuits 201, the first high side switch HS1 and the first low side switch LS1 are coupled in series between the power supply circuit 20B and ground.

In any one of the switched capacitor circuits 201, the first high-side switch HS1 is coupled between the first power supply circuit 20B and the capacitor Cu, and the capacitor Cu is coupled to the matching circuit 20C. The first low-side switch LS1 is coupled between the capacitor Cu and the ground. As can be seen, the capacitor Cu is coupled between the matching circuit 20C and the connection point of the first high-side switch HS1 and the first low-side switch LS 1. In an embodiment of the present application, the high-side switch may refer to a switch near the terminal (VCC) of the power supply circuit 20B. The low side switch may refer to a switch near Ground (GND).

The first high-side switch HS1 may be configured to selectively receive a first steady-state signal and a first digitally adjustable drive signal, so that the power supply circuit 20B charges the capacitor Cu through the first high-side switch HS 1. The first high-side switch HS1 may receive a first steady-state signal. For example, in the high power mode, the first high side switch HS1 may receive a first steady state signal. The first high-side switch HS1 may also receive a first digitally adjustable drive signal. For example, in the low power mode, the first high side switch HS1 may receive a first digitally adjustable drive signal. It can be seen that the first high-side switch HS1 can receive one of the first steady-state signal and the first digitally adjustable drive signal in different power modes. The first low-side switch LS1 may be configured to selectively receive a second steady state signal and a second digitally adjustable drive signal to discharge the capacitor Cu through the first low-side switch LS 1. The first low-side switch LS1 may receive the second steady-state signal. For example, in the high power mode, the first low side switch LS1 may receive the second steady state signal. The first low-side switch LS1 may receive a second digitally adjustable drive signal. For example, in a low power mode, the first low side switch LS1 may receive a second digitally adjustable drive signal. It can be seen that the first low side switch LS1 can receive one of the second steady state signal and the second digitally adjustable drive signal in different power modes.

In the embodiment of the application, the digital adjustable driving signal can refer to a digital signal which can be generated by a modulation mode. A digital signal generally refers to a signal of two binary digital quantities at a high level and a low level. The digital signal may thus be a rectangular wave signal. For some types of switches, a high level may drive the switch on and a low level may drive the switch off (i.e., off). For other types of switches, a high level may drive the switch off and a low level may drive the switch on. It can be seen that the switch is turned on or off under the drive of the digital signal. The digital signal generated by the modulation scheme may carry information. For example, in a transmitter, the digitally adjustable drive signal may carry phase information of the communication signal, typically the phase modulated signal may be a digital signal carrying the phase information. The steady state signal may refer to a fixed level voltage signal.

In some examples, where the transmitter is in the first transmit power mode, also where the power supply circuit 20B provides the first level, the first high-side switch HS1 may receive the first digitally adjustable drive signal, which may cause the power supply circuit 20B to charge the capacitor Cu in the switching circuit through the first high-side switch HS 1. The first low-side switch LS1 may receive the second digitally adjustable drive signal, which may discharge the capacitor Cu through the first low-side switch LS 1. Because the first high-side switch HS1 and the first low-side switch LS1 can directly receive the digital adjustable driving signal, the power supply circuit 20B is not required to provide additional charges for the parasitic capacitance of the first high-side switch HS1 before the power supply circuit 20B charges the capacitor Cu and before the capacitor Cu discharges, thereby avoiding power loss, improving the charging and discharging speed of the power supply circuit 20B for the capacitor Cu, and improving the emission efficiency.

In some examples, the transmitter may receive the first steady state signal with the first high side switch HS1 in an on state in the case of the second transmit power mode, also where the power supply circuit 20B provides the second level. The power supply circuit 20B may charge the capacitor Cu through the first high-side switch HS 1. Since the first high-side switch HS1 has an on-resistance, the first high-side switch HS1 can perform a voltage division function, and the safety and reliability of the switched capacitor circuit 201 can be improved. The first low-side switch LS1 may receive the second steady-state signal, and put the first low-side switch LS1 in an on state. The capacitor Cu may be discharged through the first low-side switch LS 1. Since the first low-side switch LS1 has an on-resistance, the first low-side switch LS1 can perform a voltage division function, and the safety and reliability of the switched capacitor circuit can be improved.

Through the above description, in the transmitter provided by the embodiment of the present application, the driving signal of the first high-side switch HS1 and the driving signal of the first low-side switch LS1 can be flexibly matched under the condition that the power supply circuit 20B provides different voltages, so that the switched capacitor circuit 201 has low loss, high safety and reliability, and can improve the transmitting efficiency and transmitting power of the transmitter.

In some possible embodiments, the conduction period of the first high-side switch HS1 may partially overlap with the conduction period of the first low-side switch LS 1. Fig. 5 schematically shows that the digital drive signal S1 and the digital drive signal S2 are a first digitally tunable drive signal and a second digitally tunable drive signal, respectively.

The digital adjustable driving signal S1 is used for turning on and off the first high-side switch HS1, and the digital adjustable driving signal S2 is used for controlling turning on and off the first low-side switch LS 1. As shown in fig. 5, the period duration of the digital adjustable driving signal S1 is T, and is high in the period T1 of each period and low in the remaining periods. The period duration of the digital adjustable driving signal S2 is T, and is high in the period T2 of each period, and is low in the remaining periods. The digitally adjustable driving signals S1 and S2 are complementary signals, i.e. the time periods t1 and t2 are equal in duration and do not overlap each other. It will be appreciated that in an ideal situation, the falling edge of the digital adjustable driving signal S1 is at the same point in time as the rising edge of the digital adjustable driving signal S2, and the rising edge of the digital adjustable driving signal S1 is at the same point in time as the falling edge of the digital adjustable driving signal S2. At the rising edge and the falling edge of the digital adjustable driving signal S1, the digital adjustable driving signal S1 and the digital adjustable driving signal S2 may respectively make the first high-side switch HS1 and the first low-side switch LS1 in a conductive state.

In order to avoid the power supply circuit 20B from being connected to the ground, and reduce power consumption, a certain time delay may be spaced between the falling edge of the digital adjustable driving signal S1 and the rising edge of the digital adjustable driving signal S2, and a certain time delay may also be spaced between the rising edge of the digital adjustable driving signal S1 and the falling edge of the digital adjustable driving signal S2, so that the on period of the first high-side switch HS1 and the on period of the first low-side switch LS1 do not overlap.

In general, in view of the reliability of the switched capacitor circuit 201, the high level of the first digitally-adjustable drive signal received by the first high-side switch HS1 is less than or equal to the first level provided by the power supply circuit 20B and the low level of the first digitally-adjustable drive signal is greater than or equal to 0V in the first power output mode of the transmitter. The high level of the second digitally-adjustable driving signal received by the first low-side switch LS1 is less than or equal to the first level provided by the power supply circuit 20B, and the low level of the second digitally-adjustable driving signal is greater than or equal to 0V. The level of the third steady-state signal received by the second high-side switch HS2 may control the second high-side switch HS2 to be in a conductive state. For example, the level of the third steady-state signal received by the second high-side switch HS2 may be 0V. The level of the fourth steady-state signal received by the second low-side switch LS2 may control the second low-side switch LS2 to be in an on state. The level of the fourth steady-state signal as received by the second low-side switch LS2 may be the same as the first level provided by the power supply circuit 20B.

In the second power output mode, the high level of the third digitally-adjustable drive signal received by the second high-side switch HS2 is less than or equal to the first level provided by the power supply circuit 20B, and the low level of the third digitally-adjustable drive signal is greater than or equal to 0V. The high level of the fourth digital adjustable driving signal received by the second low-side switch LS2 is less than or equal to the second level provided by the power supply circuit 20B, and the low level of the fourth digital adjustable signal is greater than or equal to the first level provided by the power supply circuit 20B. The level of the first steady-state signal received by the first high-side switch HS1 may control the first high-side switch HS1 to be in a conductive state. The level of the first steady-state signal received as the first high-side switch HS1 is the same as the first level provided by the power supply circuit 20B. The level of the second steady-state signal received by the first low-side switch LS1 may control the first low-side switch LS1 to be in an on state. The level of the second steady-state signal received as the first low-side switch LS1 is the same as the first level provided by the power supply circuit 20B.

In one possible design, referring to fig. 6, the transmitter may further include a second high-side switch HS2 and a second low-side switch LS2. The second high-side switch HS2 is coupled between the supply circuit 20B and the first high-side switch HS1, or the first high-side switch HS1 is coupled to the supply circuit 20B via the second high-side switch HS 2. The second low-side switch LS2 is coupled between the first low-side switch LS1 and the ground terminal, or the first low-side switch LS1 is coupled to the ground terminal via the second low-side switch LS2.

The second high-side switch HS2 may selectively receive a third steady state signal and a third digitally adjustable drive signal. The second high-side switch HS2 may receive a third steady-state signal. For example, in the low power mode, the second high side switch HS2 may receive a third steady state signal. The second high-side switch HS2 may also receive a third digitally adjustable drive signal. For example, in the high power mode, the second high side switch HS2 may receive a third digitally adjustable drive signal. It can be seen that the second high side switch HS2 can receive one of the third steady state signal and the third digitally adjustable drive signal in different power modes. The second low-side switch LS2 may selectively receive a fourth steady state signal and a fourth digitally adjustable drive signal. The second low side switch LS2 may receive a fourth steady state signal. For example, in the low power mode, the second low side switch LS2 may receive a fourth steady state signal. The second low-side switch LS2 may also receive a fourth digitally adjustable drive signal. For example, in the high power mode, the second low side switch LS2 may receive a fourth digitally adjustable drive signal. It can be seen that the second low side switch LS2 can receive one of the fourth steady state signal and the fourth digitally adjustable drive signal in different power modes.

In some examples, referring to fig. 7 (a), in the first transmission power mode, the power supply circuit 20B may provide a first level, the second high-side switch HS2 may receive a third steady-state signal, and the second high-side switch HS2 is in a conductive state, so that the power supply circuit 20B is in communication with the first high-side switch HS 1. When the first high-side switch HS1 is in the on state, the power supply circuit 20B may charge the capacitor Cu through the second high-side switch HS2 and the first high-side switch HS 1. Since the second high-side switch HS2 has an on-resistance, the second high-side switch HS2 can perform a voltage division function, and the voltage input to the first high-side switch HS1 by the power supply circuit 20B is reduced, so that the safety and reliability of the switched capacitor circuit 201 can be improved. The second low-side switch LS2 may receive the fourth steady-state signal, and put the second low-side switch LS2 in a conductive state. When the first low-side switch LS1 is in the on state, the capacitor Cu can be discharged through the first low-side switch LS1 and the second low-side switch LS 2. Since the second low-side switch LS2 has an on-resistance, the second low-side switch LS2 can perform a voltage division function, and the safety and reliability of the switched capacitor circuit can be improved.

In some examples, referring to (B) of fig. 7, the transmitter may provide a second level in the second transmit power mode and the second high-side switch HS2 may receive a third digitally adjustable drive signal. The first high-side switch HS1 may receive a first steady-state signal, and be in a conductive state. When the second high-side switch HS2 is turned on, the power supply circuit 20B may charge the capacitor Cu in the switching circuit through the second high-side switch HS2 and the first high-side switch HS 1. Since the first high-side switch HS1 has a voltage dividing function, the voltage division of the second high-side switch HS2 can be reduced, and the second high-side switch HS2 is protected.

The second low-side switch LS2 may receive a fourth digitally adjustable drive signal. The first low-side switch LS1 may receive the second steady-state signal, in an on state. When the second low-side switch LS2 is turned on, the capacitor Cu can be discharged through the second low-side switch LS2 and the first low-side switch LS 1. The first low-side switch LS1 plays a role in voltage division, so that the voltage division of the second high-side switch HS2 can be reduced, and the second low-side switch LS2 is protected.

In some possible embodiments, the conduction period of the second high-side switch HS2 may partially overlap with the conduction period of the second low-side switch LS2. For example, the rising edge of the third digitally tunable drive signal received by the second high-side switch HS2 is at the same point in time as the falling edge of the fourth digitally tunable drive signal of the second low-side switch LS2. The falling edge of the third digitally tunable drive signal is at the same point in time as the rising edge of the fourth digitally tunable drive signal. At the rising and falling edges of the third digitally adjustable drive signal, the third digitally adjustable drive signal and the fourth digitally adjustable drive signal may respectively put the second high side switch HS2 and the second low side switch LS2 in a conductive state.

In order to avoid the power supply circuit 20B from being connected to the ground, and reduce power consumption, a certain time delay may be spaced between the falling edge of the third digital adjustable driving signal and the rising edge of the fourth digital adjustable driving signal, and a certain time delay may also be spaced between the rising edge of the third digital adjustable driving signal and the falling edge of the fourth digital adjustable driving signal, so that the on period of the second high-side switch HS2 and the on period of the second low-side switch LS2 do not overlap at all.

In one possible design, referring to fig. 8, each switched capacitor circuit 201 may further include a third high side switch HS3 and a third low side switch LS3. The third high-side switch HS3 may be connected in parallel with the second high-side switch HS 2. The third low-side switch LS3 may be connected in parallel with the second low-side switch LS 2.

In the first transmission power mode, the power supply circuit 20B provides a signal received by the third high-side switch HS3 at the first level, so that the third high-side switch HS3 is in a conductive state. For example, the third high-side switch HS3 may receive a third steady-state signal, which may place the third high-side switch HS3 in an on state. And the third steady-state signal received by the second high-side switch HS2 may cause the second high-side switch HS2 to also be in an on state. In this case, the on internal resistance of the third high-side switch HS3 is connected in parallel with the on internal resistance of the second high-side switch HS2, so that the on internal resistances of the two switches are reduced, which can reduce the output power loss of the power supply circuit 20B and improve the output power and efficiency of the switched capacitor circuit 201.

Similarly, the signal received by the third low-side switch LS3 may cause the third low-side switch LS3 to be in an on state. If the third low-side switch LS3 receives the fourth steady-state signal, the fourth steady-state signal may cause the third low-side switch LS3 to be in the on state. And the fourth steady state signal received by the second low side switch LS2 places the second low side switch LS2 in an on state. In this case, the on internal resistance of the third low-side switch LS3 is parallel to the on internal resistance of the second low-side switch LS2, so that the on internal resistances of the two switches are reduced, which can reduce the output power loss of the power supply circuit 20B, and is beneficial to improving the output power and efficiency of the switched capacitor circuit 201.

In the second transmit power mode, the power supply circuit 20B provides a second level and the third high-side switch HS3 receives a signal to turn off the third high-side switch HS 3. For example, the third high side switch HS3 may receive a fifth steady state signal that may control the third high side switch HS3 to open. The power supply circuit 20B charges the capacitor Cu via the second high-side switch HS2 and the first high-side switch HS 1. The signal received by the third low-side switch LS3 may cause the third low-side switch LS3 to be in an off state. For example, the third low-side switch LS3 may receive a sixth steady-state signal that may control the third low-side switch LS3 to open. The capacitor Cu may be discharged via the second low-side switch LS2 and the first low-side switch LS 1. In some possible designs, the level of the fifth steady state signal is the same as the second level. The level of the sixth steady-state signal is 0V.

In one possible implementation, the third high-side switch HS3 may be integrated with the second high-side switch HS2 to form a switch, which may improve the integration level of the switched capacitor circuit 201 and reduce the occupied chip area. The integrated switch may selectively receive a third steady state signal or a third digitally adjustable drive signal. Similarly, the third low-side switch LS3 may be integrated with the second low-side switch LS2 as one switch that may selectively receive the fourth steady-state signal or the fourth digitally adjustable drive signal.

As the transmit power requirements for transmitters increase, transmitters are required to support higher transmit power. The power supply circuit 20B provides a greater level, such as the power supply circuit 20B providing a third level to the switched capacitor circuit 201, where the third level is greater than the second level and greater than the first level. To improve the reliability and safety of the switched capacitor circuit 201, as shown in fig. 9, the first high-side switch HS1 may be coupled to the second high-side switch HS2 through at least one fourth high-side switch HS4, and the first low-side switch LS1 may be coupled to the second low-side switch LS2 through at least one fourth low-side switch LS 4. Wherein the number of the at least one fourth high-side switch HS4 is the same as the number of the at least one fourth low-side switch LS 4.

The higher the supply level of the power supply circuit 20B, the more the number of the fourth high-side switches HS4 may be, and each fourth high-side switch HS4 has an on internal resistance, and when the fourth high-side switch HS4 is in an on state, each fourth high-side switch HS4 plays a role in voltage division, so that the voltage division of the first high-side switch HS1 is reduced, and the first high-side switch HS1 is protected.

Similarly, the higher the supply level of the power supply circuit 20B, the greater the number of fourth low-side switches LS4 may be, each fourth low-side switch LS4 having an on internal resistance. When the fourth low-side switches LS4 are in the on state, each fourth low-side switch LS4 plays a role in voltage division, so that the voltage division of the first low-side switch LS1 is reduced, and the first low-side switch LS1 is protected.

Based on the transmitter provided in any one of the foregoing embodiments, the transmitter may further include a signal modulation module that may provide a steady state signal or a digitally adjustable driving signal to each switch. The signal modulation module may include a plurality of sub-signal modulation units. The plurality of sub-signal modulation units are in one-to-one correspondence with the plurality of switched capacitor circuits. Any sub-signal modulation unit may provide a first steady state signal or a first digitally tunable drive signal to the first high side switch HS1 in the corresponding switched capacitor circuit 201 and a second steady state signal or a second digitally tunable drive signal to the first low side switch LS 1.

In some examples, when each switched-capacitor circuit 201 includes a second high-side switch HS2 and a second low-side switch LS2, either of the sub-signal modulation units may provide a third steady-state signal or a third digitally tunable drive signal to the second high-side switch HS2 in the corresponding switched-capacitor circuit 201, and a fourth steady-state signal or a fourth digitally tunable drive signal to the second low-side switch LS 2.

In some examples, when each switched-capacitor circuit 201 includes a third high-side switch HS3 and a third low-side switch LS3, any one of the sub-signal modulation units may provide a third steady-state signal or a fifth steady-state signal to the third high-side switch HS3 in the corresponding switched-capacitor circuit 201 and a fourth steady-state signal or a sixth steady-state signal to the third low-side switch LS3 in the corresponding switched-capacitor circuit 201. The third steady-state signal may control the third high-side switch HS3 to be turned on, and the fifth steady-state signal may control the third high-side switch HS3 to be turned off. The fourth steady state signal may control the third low side switch LS3 to turn on and the sixth steady state signal may control the third low side switch LS3 to turn off.

In some examples, when each switched-capacitor circuit 201 includes at least one fourth high-side switch HS4 and at least one fourth low-side switch LS4, any one of the sub-signal modulation units may provide a seventh steady-state signal to each fourth high-side switch HS4 in the corresponding switched-capacitor circuit and an eighth steady-state signal to each fourth low-side switch LS 4. The seventh steady-state signal may control the fourth high-side switch HS4 to be turned on, and the eighth steady-state signal may control the fourth low-side switch LS4 to be turned on.

Based on the transmitters provided by any of the embodiments described above, in some possible implementations, the high-side switch in each switched-capacitor circuit 201 may be PMOS and the low-side switch may be NMOS. Referring to fig. 10, the first POMS PM1 may be implemented as the aforementioned first high-side switch HS1, and may selectively receive the first steady-state signal or the first digitally adjustable driving signal. The first NMOS NM1 may be implemented as the aforementioned first low-side switch LS1, and may selectively receive the second steady-state signal or the second digitally tunable driving signal.

In some examples, where the switched-capacitor circuit 201 includes the second high-side switch HS2 and the second low-side switch LS2, the second PMOS PM2 may be implemented as the aforementioned second high-side switch HS2, and may selectively receive the third steady-state signal or the third digitally-tunable drive signal. The second NMOS NM2 may be implemented as the aforementioned second low-side switch LS2, and may selectively receive the fourth steady-state signal or the fourth digitally tunable driving signal. In some examples, where the switched-capacitor circuit includes a third high-side switch HS3 and a third low-side switch LS3, the third PMOS PM3 may be implemented as the aforementioned third high-side switch HS3. The third NMOS NM3 may be implemented as the aforementioned third low-side switch LS3.

The source of the first POMS PM1 is coupled to the supply circuit 20B via a second PMOS PM2, and the drain of the first POMS PM1 is coupled to the first pole 1 of the capacitor Cu. The source of the second PMOS PM2 is coupled to the power supply circuit 20B, and the drain of the second PMOS PM2 is coupled to the source of the first POMS PM 1.

The source of the first NMOS NM1 is coupled to the ground terminal through the second NMOS NM 2. The drain of the first NMOS NM1 is coupled to a first pole 1 of said capacitance Cu. The second pole 2 of the capacitor Cu is coupled to the matching circuit 20C. The source of the second NMOS NM2 is coupled to the ground terminal, and the drain of the second NMOS NM2 is coupled to the source of the first NMOS NM 1.

The third PMOS PM3 may be connected in parallel with the second PMOS PM2, the source of the third PMOS PM3 is coupled with the power supply circuit 20B, and the drain of the third PMOS PM3 is coupled with the drain of the second PMOS PM 2. The third NMOS NM3 may be connected in parallel with the second NMOS NM2, and a drain of the third NMOS NM3 is coupled with a source of the second NMOS NM 2.

The gates of the first POMS PM1, the second PMOS PM2, the first NMOS NM1, the second NMOS NM2, the third PMOS PM3, and the third NMOS NM3 are configured to receive control signals, respectively. The control signal may be a steady state signal or a digitally modulated drive signal. The control signal may be provided by a corresponding sub-signal modulation unit of the switched capacitor circuit 201.

The operation of the switched capacitor circuit 201 is described below in connection with some possible scenarios. For example, in a scene where the first level is 0.9V and the second level is 1.8V provided by the power supply circuit 20B.

In the low power mode of the transmitter or in the low power mode of the switched capacitor circuit 201, please refer to (a) in fig. 11, the level provided by the switched capacitor circuit 201 receiving the power supply circuit 20B is 0.9V. The sub-signal modulation unit corresponding to the switched capacitor circuit 201 provides the digitally tunable driving signal S1 to the first POMS PM1 and the digitally tunable driving signal S2 to the first NMOS NM 1. The digitally tunable drive signal S1 may be inverted with respect to the digitally tunable drive signal S2. For example, after the digital adjustable driving signal S1 is input to the inverter, the signal output by the inverter may be the digital adjustable driving signal S2.

The sub-signal modulation unit provides a steady state signal S3 to the second PMOS PM2 and the third PMOS PM3, respectively. The level of the steady-state signal S3 may be 0V, and the second PMOS PM2 may be controlled to be turned on, and the third PMOS PM3 may be controlled to be turned on.

The sub-signal modulation unit supplies a steady-state signal S4 to the second NMOS NM2 and the third NMOS NM3, respectively. The level of the steady-state signal S4 may be 0.9V, and may control the second NMOS NM2 to be turned on and the third NMOS NM3 to be turned on.

Because the first POMS PM1 and the first NMOS NM1 respectively receive the digital modulatable signals, when the power supply circuit 20B charges the capacitor Cu, the parasitic capacitors of the first POMS PM1 and the first NMOS NM1 do not need to be charged, so that the loss of the power supply circuit 20B is avoided, and compared with the case that the second PMOS PM2 and the second NMOS NM2 respectively receive the digital modulatable signals, the first POMS PM1 and the first NMOS NM1 respectively receive the digital modulatable signals, so that the charging speed of the power supply circuit 20B to the capacitor Cu can be further increased. And, third PMOS PM3 and second PMOS PM2 are parallelly connected, and second NMOS NM2 and third NMOS NM3 are parallelly connected for the on-resistance of switch further reduces, improves output and efficiency.

The transmitter is operated in the high power mode or the switched capacitor circuit 201 is operated in the low power mode, please refer to (B) in fig. 11, and the level provided by the switched capacitor circuit 201 receiving the power supply circuit 20B is 1.8V. The sub-signal modulation unit corresponding to the switched capacitor circuit 201 provides the steady-state signal S5 to the first POMS PM1 and the steady-state signal S6 to the first NMOS NM 1. The level of the steady state signal S5 may be 0.9V. The level of the steady state signal S6 may be 0.9V.

The sub-signal modulation unit provides a digitally tunable drive signal S7 to the second PMOS PM2 and a digitally tunable drive signal S8 to the second NMOS NM 2. The digitally adjustable drive signal S7 may be inverted with respect to the digitally adjustable drive signal S8. For example, after the digital adjustable driving signal S7 is input to the inverter, the signal output by the inverter may be the digital adjustable driving signal S8.

The sub-signal modulation unit provides a steady state signal S9 to the third PMOS PM 3. The level of the steady-state signal S9 may be 1.8V, and the third PMOS PM3 may be controlled to be turned off. The sub-signal modulation unit supplies a steady state signal S10 to the third NMOS NM 3. The level of the steady-state signal S10 may be 0V, and the third NMOS NM3 may be controlled to be turned off.

The second PMOS PM2 and the second NMOS NM2 receive the digital modulatable signals respectively, so that when the power supply circuit 20B charges the capacitor Cu, the first POMS PM1 and the first NMOS NM1 are both in a conducting state, and have a voltage division function, so that the second PMOS PM2 and the second NMOS NM2 can be protected, and the reliability and the safety of the switched capacitor circuit 201 can be improved.

It can be seen that the driving signals of the first POMS PM1 and the first NMOS NM1 are flexibly configurable, which can not only reduce the loss of the power supply circuit 20B, improve the output power, but also improve the reliability and safety of the switched capacitor circuit 201.

The sub-signal modulation unit may receive the power mode signal and provide a driving signal to each switch. In one possible design, the sub-signal modulation unit may include unit circuits (or gates) capable of implementing logical operations and/or complex logical operations. The sub-signal modulation unit may include, but is not limited to, and gates, or gates, not gates (inverters), nand gates, nor gates, and nor gates, exclusive or gates, and the like.

The sub-signal modulation unit may receive a digitally adjustable driving signal (or phase modulation signal) and a power Mode signal mode_sel, where the power Mode signal mode_sel may be a signal of two binary digital quantities of high level and low level, for example, mode_sel is 1, and may represent a low power Mode; mode _ sel is 0 and may characterize the high power Mode. Alternatively, mode_sel is 0, which may characterize the low power Mode; a Mode _ sel of 1 may characterize the high power Mode. The low power Mode can be characterized by mode_sel being 1; mode _ sel is 0 and may characterize the high power Mode, illustrating the sub-signal modulation unit.

In one example, fig. 12 illustrates a logic circuit form of a sub-signal modulation unit, which may include a first logic branch, a second logic branch, a third logic branch, a fourth logic branch, and a first path, according to an exemplary embodiment. The first path is coupled to the third low-side switch LS3, and is configured to receive the power Mode signal mode_sel and output the power Mode signal mode_sel.

The first logic branch includes a first not gate N1, and an input terminal of the first not gate N1 is configured to receive a power Mode signal mode_sel. The output of the first not gate N1 is coupled to a third high-side switch HS3.

The second logic branch comprises a first and-gate A1 and a second not-gate N2. The two inputs of the first and-gate circuit A1 are configured to receive the power Mode signal mode_sel and the digitally adjustable drive signal, respectively, the output of the first and-gate circuit A1 is coupled to the input of the second not-gate circuit N2, and the output of the second not-gate circuit N2 is coupled to the first low-side switch LS1 and the first high-side switch HS1, respectively.

The third logic branch comprises a first or gate O1 and a third not gate N3. The two inputs of the first or-gate circuit O1 are configured to receive the power Mode signal mode_sel and the digitally adjustable drive signal, respectively, the output of the first or-gate circuit O1 is coupled to the input of the third not-gate circuit N3, and the output of the third not-gate circuit N3 is coupled to the second high-side switch HS2.

The fourth logic branch comprises a fourth nor gate N4 and a second or gate O2. The input of the fourth not-gate N4 is configured to receive the digitally tunable drive signal, the output of the fourth not-gate N4 is coupled to one input of the second or-gate O2, the other input of the second or-gate O2 is configured to receive the power Mode signal mode_sel, and the output of the second or-gate O2 is coupled to the second low-side switch LS2.

The sub-signal modulation unit may include a plurality of second logic branches for flexibly controlling the level of the steady-state signals of the first high-side switch HS1 and the first low-side switch LS1 or the level of the digitally adjustable driving signal. As shown in fig. 13, the output of one of the second logic branches T1 may be coupled to a first high-side switch HS1. The output of the further second logic branch T2 is coupled to a first low-side switch LS1. In such a design, the two second logic branches respectively process the driving signals of the first high-side switch HS1 and the driving signals of the first low-side switch LS1, so that flexibility of configuring the driving signals of the first high-side switch HS1 and the first low-side switch LS1 can be improved.

In addition, the embodiment of the present application further provides a switched capacitor circuit 201, where the switched capacitor circuit 201 may be the switched capacitor circuit 201 in any one of the transmitters provided in the foregoing embodiment. The structure and function of the switched capacitor circuit 201 are described in any of the foregoing embodiments of the switched capacitor circuit 201, and will not be described herein.

Embodiments of the present application further provide a switched capacitor digital power amplifier, which may include a signal modulation module in any of the above embodiments, a plurality of switched capacitor circuits 201 in any of the above embodiments, and a matching circuit 20C in any of the above embodiments. Based on the description in the foregoing embodiment, the switched capacitor digital power amplifier can support multiple transmitting powers, has lower power loss, can improve transmitting power and efficiency, and occupies a smaller chip area.

Based on the above embodiments, the embodiments of the present application further provide a signal processing method, which may be applied to a switched capacitor circuit. The power supply circuit may be coupled to the switched capacitor circuit for powering the power supply circuit. The switched-capacitor circuit may include the first high-side switch, a first low-side switch, and the capacitor. In some examples, the switched-capacitor circuit may be a switched-capacitor circuit in a switched-capacitor digital power amplifier provided in any of the embodiments described above, or a switched-capacitor circuit in a transmitter provided in any of the embodiments described above.

As shown in fig. 14, the signal processing method may include the steps of:

step S1401 selectively provides a first level and a second level to a switched capacitor circuit in a power amplification circuit, wherein the first level is less than the second level.

In step S1402, a first high-side switch of the switched-capacitor circuit selectively receives a first steady-state signal and a first digitally-adjustable driving signal.

In step S1403, the first low-side switch of the switched capacitor circuit selectively receives the second steady-state signal and the second digitally adjustable driving signal, the first high-side switch and the first low-side switch are coupled in series, and the capacitor is coupled between the connection point of the first high-side switch and the first low-side switch and the matching circuit.

It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the scope of the application. Thus, it is intended that the present application also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims

A transmitter comprising at least one power amplifying circuit and a matching circuit; the matching circuit is coupled to an antenna; the power amplifying circuit comprises a plurality of switch capacitor circuits which are connected in parallel; the power supply circuit is coupled with the plurality of switch capacitance circuits and supplies power to the plurality of switch capacitance circuits;

the power supply circuit is used for selectively providing power for the switch capacitor circuit at a first level and a second level, wherein the first level is smaller than the second level;

the switch capacitor circuit comprises a first high-side switch, a first low-side switch and a capacitor, wherein the first high-side switch and the first low-side switch are coupled between the power supply circuit and the ground in series, and the capacitor is coupled between a connection point of the first high-side switch and the first low-side switch and the matching circuit;

The first high-side switch is used for selectively receiving a first steady-state signal and a first digital adjustable driving signal, so that the power supply circuit charges the capacitor through the first high-side switch;

the first low-side switch is configured to selectively receive a second steady state signal and a second digitally adjustable drive signal to discharge the capacitor through the first low-side switch.
The transmitter of claim 1, wherein the transmitter comprises a first configuration state:

in the first configuration state:

the power supply circuit is used for providing the first level;

the first high-side switch is used for receiving the first digital adjustable driving signal;

the first low-side switch is used for receiving the second digital adjustable driving signal;

wherein the conduction period of the first high-side switch does not overlap with the conduction period of the first low-side switch.
A transmitter as claimed in claim 1 or 2, wherein the transmitter comprises a second configuration state:

in the second configuration state:

the power supply circuit is used for providing the second level;

the first high-side switch is used for receiving the first steady-state signal;

The first low-side switch is used for receiving the second steady-state signal.
A transmitter as claimed in any one of claims 1 to 3, wherein the switched capacitor circuit further comprises a second high side switch and a second low side switch;

the second high-side switch is coupled between the power supply circuit and the first high-side switch for selectively receiving a third steady-state signal and a third digitally adjustable drive signal;

the second low-side switch is coupled between the first low-side switch and the ground for selectively receiving a fourth steady-state signal and a fourth digitally adjustable drive signal.
The transmitter of claim 4, wherein the switched-capacitor circuit further comprises a third high-side switch and a third low-side switch; the third high-side switch is connected in parallel with the second high-side switch, and the third low-side switch is connected in parallel with the second low-side switch.
A transmitter as claimed in claim 4 or 5, wherein the transmitter comprises a first configuration state;

in the first configuration state:

the power supply circuit is used for providing the first level;

the second high-side switch is used for receiving the third steady-state signal;

The second low-side switch is configured to receive the fourth steady-state signal.
A transmitter as claimed in any one of claims 4 to 6, wherein the transmitter comprises a second configuration state;

in the second configuration state:

the power supply circuit is used for providing the second level;

the second high-side switch is used for receiving the third digital adjustable driving signal;

the second low-side switch is used for receiving the fourth digital adjustable driving signal;

wherein the conduction period of the second high-side switch and the conduction period of the second low-side switch do not overlap.
The transmitter of any of claims 1-7, wherein a source of the first high-side switch is coupled to the power supply circuit, a drain of the first high-side switch is coupled to a first pole of the capacitor, and a second pole of the capacitor is coupled to the matching circuit;

the source of the first low-side switch is coupled to the ground and the drain of the first low-side switch is coupled to a first pole of the capacitor.
The transmitter of claim 8, wherein if the switched-capacitor circuit comprises a second high-side switch and a second low-side switch, wherein a source of the first high-side switch is coupled to the power supply circuit through the second high-side switch and a source of the first low-side switch is coupled to the ground through the second low-side switch.
The transmitter of any of claims 1-9, wherein an impedance of the matching circuit is adapted to a voltage of a capacitive output of the plurality of switched-capacitor circuits.
A signal processing method, comprising:

selectively providing a first level and a second level to a switched capacitor circuit in a power amplification circuit, wherein the first level is less than the second level;

a first high-side switch of the switched-capacitor circuit selectively receives a first steady-state signal and a first digitally adjustable drive signal;

a first low-side switch of the switched capacitor circuit selectively receives a second steady state signal and a second digitally adjustable drive signal, the first high-side switch and the first low-side switch being coupled in series, the capacitor being coupled between a connection point of the first high-side switch and the first low-side switch and the matching circuit.
The method of claim 11, wherein if the first level is provided to the switched-capacitor circuit, the first high-side switch receives the first digitally-adjustable drive signal and the first low-side switch receives the second digitally-adjustable drive signal;

wherein the conduction period of the first high-side switch does not overlap with the conduction period of the first low-side switch.
The method of claim 11 or 12, wherein the first high-side switch receives the first steady-state signal and the first low-side switch receives the second steady-state signal if the second level is provided to the switched-capacitor circuit.
The method of claim 11, wherein the switched-capacitor circuit further comprises a second high-side switch and a second low-side switch; the second high-side switch is coupled with the first high-side switch, and the second low-side switch is coupled between the first low-side switch and the ground;

the method further comprises the steps of:

the second high-side switch selectively receives a third steady-state signal and a third digitally adjustable drive signal;

the second low side switch selectively receives a fourth steady state signal and a fourth digitally adjustable drive signal.
The method of claim 14, wherein the switched-capacitor circuit further comprises a third high-side switch and a third low-side switch; the third high-side switch is connected in parallel with the second high-side switch, and the third low-side switch is connected in parallel with the second low-side switch;

the method further comprises the steps of:

the third high-side switch receives the first digitally tunable drive signal and the third low-side switch receives the second digitally tunable drive signal if the first level is provided to the switched-capacitor circuit.