CN116897354A

CN116897354A - Semiconductor device and electronic device

Info

Publication number: CN116897354A
Application number: CN202280017789.4A
Authority: CN
Inventors: 黑川义元; 乡户宏充; 津田一树; 大下智; 力丸英史
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 2021-03-05
Filing date: 2022-02-24
Publication date: 2023-10-17

Abstract

A semiconductor device having a novel structure is provided. The semiconductor device includes: a cell array for performing a first level of product-sum operation and a second level of product-sum operation in the artificial neural network; a first circuit for inputting first data to the cell array; and a second circuit outputting second data from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In the first period, the first region is inputted with the t (t is a natural number of 2 or more) first data by the first circuit and outputs the t second data corresponding to the product-sum operation of the first hierarchy to the second circuit. The second region is inputted with the (t-1) th first data by the first circuit and outputs the (t-1) th second data corresponding to the product-sum operation of the second hierarchy to the second circuit.

Description

Semiconductor device and electronic device

Technical Field

The present specification describes a semiconductor device and the like.

Note that one embodiment of the present invention is not limited to the above-described technical field. Examples of the technical field of one embodiment of the present invention disclosed in the present specification and the like include a semiconductor device, an image pickup device, a display device, a light emitting device, a power storage device, a display system, an electronic device, a lighting device, an input/output device, a driving method thereof, and a manufacturing method thereof.

Background

The development of integrated circuits modeled by human brain structures is now increasingly hot. The integrated circuit is assembled with electronic circuitry as a brain structure and includes circuitry corresponding to "neurons" and "synapses" of the human brain. Therefore, the integrated circuit is sometimes referred to as "neuro-morph", "brain-morph" or "brain-inspire". The integrated circuit has a non-nomann type architecture, and can be expected to perform parallel processing with extremely low power consumption, compared with a non-nomann type architecture in which power consumption increases with an increase in processing speed.

A data processing model that mimics a neural network, including "neurons" and "synapses", is referred to as an Artificial Neural Network (ANN). By using artificial neural networks, it is even possible to infer with an accuracy equivalent to or exceeding that of a person. In the artificial neural network, the sum of weights of neuron outputs, that is, the product-sum operation is mainly performed.

Non-patent document 1 proposes a product-sum operation circuit using a nonvolatile memory element. In the product-sum operation circuit, a current corresponding to a multiplication operation of data corresponding to a multiplier stored in each memory element and input data corresponding to a multiplicand is output by an operation in a sub-threshold region of a transistor including silicon in a channel formation region in each memory element. In addition, in the product-sum operation circuit, data corresponding to the product-sum operation is acquired by using the sum of currents output from the memory elements of each column. Since the product-sum operation circuit includes a memory element, it is not necessary to read and write data from and to an external memory in the multiplication operation and the addition operation. Therefore, the number of data transfers due to reading, writing, and the like can be reduced, and reduction in power consumption can be expected.

[ Prior Art literature ]

[ non-patent literature ]

[ non-patent document 1] X.Guo et al., "Fast, energy-efficiency, robust, and Reproducible Mixed-Signal Neuromorphic Classifier Based on Embedded NOR Flash Memory Technology" IEDM2017, pp.151-154.

Disclosure of Invention

Technical problem to be solved by the invention

In addition, when the product-sum operation is performed by the product-sum operation circuit, power consumption may increase due to an increase in through current and the like caused by miniaturization of the transistor. In the computation processing such as the product-sum computation, it is important to increase not only the computation processing speed but also the computation processing capability per unit power.

In addition, by using a display system having a product-sum operation circuit for a glasses-type AR (Augmented Reality: augmented reality) device or the like, a high-level user experience can be provided in which a sensor function and an AI processing function are combined in addition to a display function. However, since it is assumed that the device is driven using a battery, there is a strict limitation on power consumption. Therefore, the arithmetic device for realizing this function is required to have low power consumption.

An object of one embodiment of the present invention is to provide a semiconductor device and the like having excellent arithmetic processing capability per unit power. An object of one embodiment of the present invention is to provide a semiconductor device and the like excellent in terms of reduction of power consumption. An object of one embodiment of the present invention is to provide a semiconductor device or the like capable of performing product-sum operation, which has a novel structure.

Note that one embodiment of the present invention does not need to achieve all the above objects, as long as at least one object can be achieved. The description of the above objects does not hinder the existence of other objects. Other objects than the above will be apparent from and will be obvious from the description of the specification, claims, drawings, and the like.

Means for solving the technical problems

One embodiment of the present invention is a semiconductor device including: a cell array for performing a first level of product-sum operation and a second level of product-sum operation in the artificial neural network; a first circuit for inputting first data to the cell array; and a second circuit outputting second data from the cell array. The cell array includes a plurality of cells. The cell array includes a first region and a second region. In the first period, the first region receives the first data of the t (t is a natural number of 2 or more) and outputs the second data of the t corresponding to the product-sum operation of the first level to the second circuit, and the second region receives the first data of the (t-1) and outputs the second data of the (t-1) corresponding to the product-sum operation of the second level to the second circuit.

One embodiment of the present invention is a semiconductor device including a cell array that performs a first level of product-sum operation and a second level of product-sum operation in an artificial neural network, a first circuit that inputs first data to the cell array, and a second circuit that outputs second data from the cell array, wherein the cell array includes a plurality of cells, the cell array includes a first region to which the first circuit inputs t (t is a natural number of 2 or more) and outputs the t second data corresponding to the first level of product-sum operation to the second circuit, and a second region to which the first circuit inputs the (t-1) first data and outputs the t (t-1) second data corresponding to the second level of product-sum operation to the second circuit, and during a second period, the first region is input with the first (t+1) first data by the first circuit and outputs the t (t+1) second data corresponding to the first product-sum operation to the second circuit, and the second region is output the second (t+1) second data corresponding to the second level of product-sum operation to the second circuit by the first circuit and the second data by the second circuit.

In the semiconductor device according to one embodiment of the present invention, the first data input to the second region is preferably data obtained by performing a nonlinear operation on the second data output from the first region.

In the semiconductor device according to one embodiment of the present invention, it is preferable that the semiconductor device further includes a third circuit that outputs the second data from the cell array, wherein the third circuit has a function of performing a nonlinear function-based operation on the second data.

In the semiconductor device according to one embodiment of the present invention, it is preferable that the cell includes a first transistor, a second transistor, and a capacitor, wherein the first transistor has a function of holding a first potential corresponding to weight data supplied to a gate of the second transistor through the first transistor in an off state, the capacitor has a function of changing the first potential held in the gate of the second transistor to a second potential according to a potential change of the first data supplied to one electrode, and the second transistor has a function of outputting the second data corresponding to the first data as an analog current to the other one of the source and the drain.

In the semiconductor device according to one embodiment of the present invention, the analog current is preferably a current that flows when the second transistor operates in the sub-threshold region.

In the semiconductor device according to one embodiment of the present invention, the first transistor preferably includes a semiconductor layer including a metal oxide in a channel formation region.

In the semiconductor device according to one embodiment of the present invention, the metal oxide preferably contains In, ga, and Zn.

In the semiconductor device according to one embodiment of the present invention, it is preferable that the second transistors each include a semiconductor layer including silicon in a channel formation region.

An embodiment of the present invention is an electronic device including the above semiconductor device, a driver circuit, a pixel circuit, a light-emitting element, and a light-receiving element, wherein the pixel circuit has a function of controlling light emission of the light-emitting element, the driver circuit has a function of controlling the pixel circuit, the semiconductor device includes a transistor included in a layer provided with the pixel circuit and a transistor included in a layer provided with the driver circuit, and the semiconductor device has a function of performing arithmetic processing using a current output from the light-receiving element as first data.

In the electronic device according to one embodiment of the present invention, the light receiving element includes an organic photodiode, and the light emitting element is an organic EL element.

In the electronic device according to one embodiment of the present invention, the light emitting element and the light receiving element are separated by photolithography.

Note that other aspects of the present invention are described in the following embodiments and drawings.

Effects of the invention

According to one embodiment of the present invention, a semiconductor device or the like having excellent arithmetic processing capability per unit power can be provided. According to one embodiment of the present invention, a semiconductor device or the like excellent in reduction of power consumption can be provided. According to one embodiment of the present invention, a semiconductor device or the like capable of performing product-sum operation with a novel structure can be provided.

The description of the plurality of effects does not hinder the existence of the effects of each other. Furthermore, one embodiment of the present invention need not have all of the above effects. In one embodiment of the present invention, objects, effects and novel features other than those described above will be naturally apparent from the description and drawings in the present specification.

Brief description of the drawings

Fig. 1 is a diagram illustrating a structural example of a semiconductor device.

Fig. 2A and 2B are diagrams illustrating a structural example of the semiconductor device.

Fig. 3A and 3B are diagrams illustrating a structural example of the semiconductor device.

Fig. 4A and 4B are diagrams illustrating a structural example of the semiconductor device.

Fig. 5 is a diagram illustrating a structural example of the semiconductor device.

Fig. 6 is a diagram illustrating a structural example of the semiconductor device.

Fig. 7 is a diagram illustrating a structural example of the semiconductor device.

Fig. 8 is a diagram illustrating a structural example of the semiconductor device.

Fig. 9 is a diagram illustrating a structural example of the semiconductor device.

Fig. 10 is a diagram illustrating a structural example of the semiconductor device.

Fig. 11A and 11B are diagrams illustrating a structural example of the semiconductor device.

Fig. 12 is a diagram illustrating a structural example of the semiconductor device.

Fig. 13A, 13B, and 13C are diagrams illustrating a structural example of the semiconductor device.

Fig. 14A, 14B, 14C, and 14D are diagrams illustrating a structural example of the semiconductor device.

Fig. 15A, 15B, and 15C are diagrams illustrating a structural example of the semiconductor device.

Fig. 16 is a diagram illustrating a structural example of the semiconductor device.

Fig. 17 is a diagram illustrating a configuration example of the semiconductor device.

Fig. 18A and 18B are diagrams illustrating a structural example of the display device.

Fig. 19A and 19B are diagrams illustrating a structural example of the display device.

Fig. 20 is a diagram illustrating a structural example of the display device.

Fig. 21A and 21B are diagrams illustrating a structural example of the display device.

Fig. 22A and 22B are diagrams illustrating a structural example of the display device.

Fig. 23A, 23B, 23C, and 23D are diagrams illustrating a structural example of the display device.

Fig. 24A and 24B are diagrams illustrating a structural example of the display device.

Fig. 25A, 25B, 25C, and 25D are diagrams illustrating structural examples of the display device.

Fig. 26A and 26B are diagrams illustrating a structural example of the display device.

Fig. 27A to 27G are diagrams illustrating structural examples of the display device.

Fig. 28 is a diagram illustrating a structural example of the display device.

Fig. 29A and 29B are diagrams illustrating a configuration example of the electronic device.

Fig. 30A and 30B are diagrams illustrating a configuration example of the electronic device.

Modes for carrying out the invention

Next, embodiments will be described. It is noted that an embodiment of the present invention is not limited to the following description, and one of ordinary skill in the art can easily understand the fact that the manner and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention should not be construed as being limited to the description of the embodiments described below.

Note that, in this specification and the like, ordinal numbers such as "first", "second", "third", and the like are added to avoid confusion of constituent elements. Therefore, the ordinal words do not limit the number of constituent elements. The ordinal words do not limit the order of the constituent elements. For example, in the present specification and the like, a constituent element referred to as "first" in one embodiment may be set as a constituent element referred to as "second" in other embodiments or claims. For example, in the present specification and the like, the constituent element referred to as "first" in one embodiment may be omitted in other embodiments or claims.

In the drawings, the same reference numerals are used to denote the same elements or elements having the same functions, the same elements made of the same materials, or elements formed simultaneously, and the like, and overlapping descriptions may be omitted.

In this specification, the power supply potential VDD may be simply referred to as potential VDD, or the like. Other components (e.g., signals, voltages, circuits, elements, electrodes, wiring, etc.) are also similar.

In addition, when the same symbol is used for a plurality of elements and it is necessary to distinguish them, a symbol for identification such as "_1", "_2", "_n", "_m, n" is sometimes added to the symbol. For example, the second wiring GL is denoted as the wiring gl_2.

(embodiment 1)

A semiconductor device according to an embodiment of the present invention will be described. The semiconductor device according to one embodiment of the present invention can be used for arithmetic processing of an artificial neural network. As the artificial neural network, for example, a hierarchical neural network can be applied.

In this specification and the like, a semiconductor device refers to all devices that can operate by utilizing semiconductor characteristics. In addition to a semiconductor element such as a transistor, a semiconductor circuit, an arithmetic device, or a memory device is one embodiment of a semiconductor device. Display devices (liquid crystal display devices, light-emitting display devices, and the like), projection devices, illumination devices, electro-optical devices, power storage devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to include semiconductor devices.

Fig. 1 is a block diagram of a semiconductor device in which a cell array and peripheral circuits thereof are combined, which can perform product-sum operation performed in operation processing of an artificial neural network (hereinafter, sometimes referred to as a neural network). The semiconductor device including the cell array and its peripheral circuits described in this embodiment mode is a circuit capable of performing product-sum operation, and is sometimes referred to as an arithmetic circuit.

The semiconductor device MAC includes a circuit XCS, a circuit WCS, a circuit WSD, a cell array CA, and a circuit ITRZ. The cell array CA includes cells IM (also referred to as memory cells) arranged in a matrix of m rows and n columns (m, n being a natural number of 2 or more).

The circuit XCS includes digital-to-analog (D/a) conversion circuits corresponding to respective rows of the cell array CA. The circuit XCS can supply analog signals corresponding to input data to the cells IM of each row of the cell array CA through the signal lines X [1] to X [ m ]. The circuit XCS is sometimes referred to as an X driver. The signal lines X1 to X m are sometimes called wirings XCL 1 to XCL m.

The circuit XCS is supplied with input data XDATA supplied to each row of the cell array CA. The input data XDATA is supplied to the signal lines X [1] to X [ m ] at a specified timing by the clock signal XCLK, the start pulse XSP and the latch signal XLA. As shown in fig. 2A, the circuit XCS includes a shift register SR1 and a latch circuit LAT1, for example. The input data XDATA is distributed to each row by the clock signal XCLK and the start pulse XSP input to the shift register SR1 and held in the latch circuit LAT1. And, the input data XDATA is output to the signal lines X [1] to X [ m ] at the timing of the latch signal XLAT.

The circuit WCS includes a D/a conversion circuit corresponding to each column of the cell array CA, and analog signals corresponding to weight data can be supplied from the signal lines W [1] to W [ n ] to the cells IM of each column of the cell array CA. The circuit WCS is sometimes referred to as a W driver. Further, the signal lines W [1] to W [ n ] are sometimes referred to as wirings WCL [1] to WCL [ n ].

The circuit WSD can supply signals of rows of the write object of the selection cell array CA from the signal lines G [1] to G [ m ]. Circuit WSD is sometimes referred to as a G driver. Further, the signal lines G [1] to G [ m ] are sometimes referred to as wirings WSL [1] to WSL [ m ].

The circuit ITRZ includes an analog-to-digital (a/D) conversion circuit corresponding to each column of the cell array CA, and can acquire digital signals corresponding to analog signals output from the cells IM of each column of the cell array CA to the signal lines Y [1] to Y [ n ]. The circuit ITRZ is sometimes referred to as a Y driver. The signal lines Y1 to Y n correspond to the signal lines W1 to W n, that is, correspond to wirings connected to the wirings WCL 1 to WCL n.

The circuit ITRZ outputs output data YDATA acquired from each row of the cell array CA. The output data YDATA is outputted as the output data YDATA of the digital signal by acquiring analog signals from the signal lines Y [1] to Y [ n ] at specified timings by the clock signal YCLK, the start pulse YSP, and the latch signal YLAT. As shown in fig. 2B, the circuit ITRZ includes a shift register SR2, a latch circuit LAT2, and a switch sw_y, for example. The data of the signal lines Y [1] to Y [ n ] are held in the latch circuit LAT 2. The data of the signal lines Y [1] to Y [ n ] held in the latch circuit LAT2 are outputted as output data YDATA at timing when the switch sw_y allocated to each column is turned on by the clock signal YCLK and the start pulse YSP inputted to the shift register SR 2.

Note that specific examples and working examples of the circuit XCS, the circuit WCS, the circuit WSD, the cell array CA, and the circuit ITRZ will be described in detail in embodiment 3.

Here, a hierarchical neural network is described. The hierarchical neural network comprises, for example, an input layer, one or more intermediate (hidden) layers, and an output layer. Fig. 3A shows a network diagram of a three-layer perceptron as an example of a hierarchical neural network. In fig. 3A, the first layer corresponds to an input layer, the second layer corresponds to an intermediate layer, and the third layer corresponds to an output layer.

Each layer of the neural network has one or more neurons NU. Fig. 3A shows m neurons in the first layer, n neurons in the second layer, and p neurons in the third layer (n, m, and p are natural numbers of 2 or more).

In fig. 3A, in the first layer as an input layer, data X1[1] to X1[ m ] are supplied to m neurons. Data X1[1] to X1[ m ] are output from each neuron of the first layer to each neuron of the second layer. In addition, in fig. 3A, in the third layer as an output layer, data X2[1] to X2[ n ] are supplied to p neurons. Neurons of the output layer output data Y2[1] to Y2[ p ] obtained by performing full connection processing of the data X2[1] to X2[ n ] and the weight data W2[1] to W2[ n ] (not shown).

Signals input to or output from neurons in a second layer corresponding to the intermediate layer are described with reference to fig. 3B. Fig. 3B shows data X1[1] to X1[ m ] input from each neuron in the first layer and weight data W1[1] to W1[ m ] included in the neurons in the second layer. Further, fig. 3B shows data Y1[1] to Y1[ m ] obtained by performing product-sum operation on the inputted data X1[1] to X1[ m ] and the weight data W1[1] to W1[ m ]. The data Y1[1] to Y1[ m ] are output to each neuron in the third layer as data X2[1] for nonlinear operation based on the activation function f.

For example, as shown in fig. 4A, each of the data X1[1] (t is a natural number of 2 or more) to X1[ m ] (t) is input to each layer of the neural network of fig. 3A, and the above-described each data is output from the above-described each layer. In addition, as shown in FIG. 4B, the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1) are input to and output from the layers of the neural network of FIG. 3A.

In the neural network, a product-sum operation Y1[ j ] (t) =Σw1[ i, j ] x1[ i ] (t) and a nonlinear operation X2[ j ] (t) =f (Y1 [ j ] (t)) are performed on the inputted t-th data X1[1] (t) to X1[ m ] (t) in a second layer as an intermediate layer, and a product-sum operation Y2[ k ] (t) =Σw2[ j, k ] x2[ j ] (t) is performed in a third layer as an output layer. Similarly, in the second layer as the intermediate layer, the product-sum operation Y1[ j ] (t-1) =Σw1[ i, j ] x1[ i ] (t-1) and the nonlinear operation X2[ j ] (t-1) =f (Y1 [ j ] (t-1)) are performed on the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1), and in the third layer as the output layer, the product-sum operation Y2[ k ] (t) =Σw2[ j, k ] x2[ j ] (t-1) are performed. Note that the layers for performing the product-sum operation are sometimes referred to as a first layer and a second layer, and for example, the second layer as an intermediate layer is sometimes referred to as a first layer and the third layer as an output layer is sometimes referred to as a second layer. I, j, k in each expression are natural numbers. The nonlinear operation is an operation performed by using a nonlinear function f (X) of X. As the nonlinear function f (X), there are sigmoid function, reLU function, and the like.

Fig. 5 is a diagram of dividing the area of the cell array CA shown in fig. 1 according to the neural network shown in fig. 4A and 4B. The product-sum operation Y1[ j ] (t) =Σw2[ j, k ] x2[ j ] (t-1) in the m rows and n columns in the intermediate layer with respect to the t-th data X1[1] (t) to X1[ m ] (t) is divided into the region (area) L1, and the product-sum operation Y2[ k ] (t-1) =Σw2[ j, k ] x2[ j ] (t-1) in the n rows and p columns in the output layer with respect to the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1) is divided into the region L2.

By adopting the structure of fig. 5, the product-sum operation in the plurality of layers of the neural network can be performed using one cell array CA, whereby a low-power-consumption operation processing apparatus capable of efficiently performing the operation processing can be provided.

Fig. 6 is a timing chart when the region of the cell array CA shown in fig. 1 is divided and operated as shown in fig. 5. Hereinafter, a case will be described in which the weight data W1[ i, j ] is stored in the cells IM of the ith row and jth column (i=1 to m, j=1 to n) of the cell array CA. In addition, a case will be described in which the weight data W2[ i, j ] is stored in the cells IM in the (n+i) th column (i=1 to n, j=1 to p) of the (m+i) th row of the cell array CA.

At time TX0, nonlinear operation data X2[1] (t-1) to X2[ n ] (t-1) in the intermediate layer of the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1) with respect to the t-th data X1[1] (t) to X1[ m ] (t), are sequentially input to the circuit XCS. The nonlinear operation data X2[1] (t-1) to X2[ n ] (t-1) in the intermediate layer of the (t-1) th data X1[1] (t) to X1[ m ] (t), the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1) are sequentially supplied to the latch circuit of the circuit XCS in synchronization with the clock signal XCLK.

At time TX1, the t-th analog signal Y1[1] (t-1) =Σw1[ i,1] x1[ i ] (t-1) to Y1[ n ] (t-1) =Σw1[ i, n ] x1[ i ] (t-1), the (t-2) -th analog signal Y2[1] (t-2) =Σw2[ j,1] x2[ j ] (t-2) to Y2[ p ] (t-2) =Σw2[ j, p ] x1[ j ] (t-2) and supplied to the signal lines Y [1] to Y [ n ], Y [ n+1] to Y [ n+p ]. The (t-1) th output data Y1[1] (t-1) to Y1[ n ] (t-1), the (t-2) th analog signal Y2[1] (t-2) to Y2[ p ] (t-2) and the (t-2) th output data Y2[1] (t-2) to Y2[ p ] (t-2) are generated by the a/D conversion circuits corresponding to the respective columns of the cell array CA corresponding to the (t-1) th analog signals Y1[1] (t-1) to Y1[ n ] (t-1).

At time TX2, the latch signal YLAT is set to the H level, whereby the (t-1) th data Y1[1] (t-1) to Y1[ n ] (t-1), the (t-2) th data Y2[1] (t-2) to Y2[ l ] (t-2) are supplied to the latch circuit of the circuit ITRZ and sequentially output in synchronization with the clock signal YCLK.

At time TX3, the latch signal XLAT is brought to the H level, whereby the (t-1) th analog signals X1[1] (t) to X1[ m ] (t) corresponding to the t-th data X1[1] (t) to X1[ m ] (t), the (t-1) th analog signals X2[1] (t-1) to X2[ n ] (t-1) corresponding to the nonlinear operation data X1[1] (t-1) to X2[ n ] (t-1) in the intermediate layer with respect to the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1), are generated by the D/a conversion circuit corresponding to each row of the cell array CA and supplied to the signal lines X1 ] to X [ m ], X [ m+1] to X [ m+n ].

During the period (first period) from time TX0 to time TX3, the (t-1) th data X1[1] (t-1) to X1[ m ] (t-1) are input in the region L1 (first region) of fig. 5, whereby the (t-1) th data Y1[1] (t-1) to Y1[ n ] (t-1) corresponding to the product-sum operation of the region L1 can be output. Further, in the period (first period) from time TX0 to time TX3, the (t-2) th data X2[1] (t-2) to X2[ m ] (t-2) are input in the region L2 (second region) of fig. 5, whereby the (t-2) th data Y2[1] (t-2) to Y2[ n ] (t-2) corresponding to the product-sum operation of the region L2 can be output.

At time TX4, nonlinear operation data X2[1] (t) to X2[ n ] (t) in the intermediate layer of the (t+1) th data X1[1] (t+1) to X1[ m ] (t+1), the t-th data X1[1] (t) to X1[ m ] (t) are sequentially input to the circuit XCS. The nonlinear operation data X2[1] (t) to X2[ n ] (t) in the intermediate layer of the (t+1) th data X1[1] (t+1) to X1[ m ] (t+1), the t-th data X1[1] (t) to X1[ m ] (t) are sequentially supplied to the latch circuit of the circuit XCS in synchronization with the clock signal XCLK.

At time TX5, the t-th analog signal Y1[1] (t) =Σw1[ i,1] x1[ i ] (t) to Y1[ n ] (t) =Σw1[ i, n ] x1[ i ] (t), the (t-1) -th analog signal Y2[1] (t-1) =Σw2[ j,1] x2[ j ] (t-1) to Y2[ p ] (t-1) =Σw2[ j, p ] x1[ j ] (t-1) of each column of the cell array CA is determined and supplied to the signal lines Y [1] to Y [ n ], Y [ n+1] to Y [ n+p ]. The t-th output data Y1[1] (t) to Y1[ n ] (t), the (t-1) -th output data Y2[1] (t-1) to Y2[ p ] (t-1) corresponding to the t-th analog signals Y1[1] (t) to Y1[ n ] (t), the (t-1) -th analog signals Y2[1] (t-1) to Y2[ p ] (t-1) are generated by the A/D conversion circuits corresponding to the respective columns of the cell array CA.

At time TX6, the latch signal YLAT is set to the H level, whereby the (t) th data Y1[1] (t) to Y1[ n ] (t), the (t-1) th data Y2[1] (t-1) to Y2[ l ] (t-1) are supplied to the latch circuit of the circuit ITRZ and sequentially output in synchronization with the clock signal YCLK.

At time TX7, the latch signal XLAT is brought to the H level, whereby the (t+1) th analog signals X1[1] (t+1) to X1[ m ] (t+1) corresponding to the (t+1) th data X1[1] (t+1) to X1[ m ] (t+1), the t th analog signals X2[1] (t) to X2[ n ] (t) corresponding to the nonlinear operation data X1[1] (t) to X2[ n ] (t) in the intermediate layer with respect to the t th data X1[1] (t) to X1[ m ] (t), are generated by the D/a conversion circuit corresponding to each row of the cell array CA and supplied to the signal lines X [1] to X [ m ], X [ m+1] to X [ m ] (not shown).

In the period (second period) from time TX4 to time TX7, the t-th data X1[1] (t) to X1[ m ] (t) are input in the region L1 (first region) of fig. 5, whereby the t-th data Y1[1] (t) to Y1[ n ] (t) corresponding to the product-sum operation of the region L1 can be output. Further, in the period (second period) from time TX4 to time TX7, (t-1) th data X2[1] (t-1) to X2[ m ] (t-1) are input in the region L2 (second region) of fig. 5, whereby (t-1) th data Y2[1] (t-1) to Y2[ n ] (t-1) corresponding to the product-sum operation of the region L2 can be output.

Here, it is preferable to have the following structure: outputting the t-th data Y1[1] (t) to Y1[ n ] (t) according to the period of the clock signal YCLK and performing a nonlinear operation X2[ j ] (t) =f (Y1 [ j ] (t)) in the intermediate layer corresponding to the t-th data; storing the nonlinear operation result through First-In First-Out (FIFO); and reading out nonlinear operation data X2[1] (t) to X2[ n ] (t) through the FIFO according to the period of the clock signal XCLK. By adopting such a configuration, the respective operation speeds of the D/a conversion circuit and the a/D conversion circuit can be set to appropriate values, whereby reduction in power consumption and the like can be achieved.

Further, it is preferable to have the following structure: the period of the clock signal YCLK is made the same as that of the clock signal XCLK so that the timing of outputting the t-th data Y1[1] (t) to Y1[ n ] (t) and the timing of performing the nonlinear operation X2[ j ] (t) =f (Y1 [ j ] (t)) in the intermediate layer corresponding to the t-th data are performed in synchronization with the clock signal XCLK in the same manner as the timing of inputting X2[ j ] (t). By adopting such a structure, it is not necessary to prepare a first-in first-out (FIFO) or the like structure for storing the nonlinear operation result and reading out the nonlinear operation result in synchronization with the clock signal XCLK, whereby the structure of the semiconductor device can be simplified.

With the above configuration, product-sum operation corresponding to a plurality of layers of the neural network can be performed using one cell array, whereby a low-power-consumption operation process capable of efficiently performing the operation process can be provided.

(embodiment 2)

In this embodiment, a structure different from the semiconductor device described in the above embodiment will be described. Note that, the above description is referred to for the portions overlapping with embodiment 1, and a detailed description thereof is omitted.

In this embodiment, a case where an operation is performed in one example of the hierarchical neural network described in fig. 3A of embodiment 1 is described. As an example, fig. 7 shows the following case: regarding the data X1[1] (t) to X1[ m ] (t) of the t (t is a natural number of 2 or more), the data X1[1] (t) to X1[ m ] (t) are input or output between the first layer and the second layer of the neural network, and the data X2[1] (t) to X2[ n ] (t) are input or output between the second layer and the third layer of the neural network.

In the neural network, a product-sum operation Y1[ j ] (t) =Σw1[ i, j ] x1[ i ] (t) and a nonlinear operation X2[ j ] (t) =f (Y1 [ j ] (t)) are performed on the inputted t-th data X1[1] (t) to X1[ m ] (t) in a second layer (also referred to as a first layer) as an intermediate layer, and a product-sum operation Y2[ k ] (t) =Σw2[ j, k ] x2[ j ] (t) is performed in a third layer (also referred to as a second layer) as an output layer. I, j, k in each expression are natural numbers. The nonlinear operation is an operation performed by using a nonlinear function f (X) of X. As the nonlinear function f (X), there are sigmoid function, reLU function, and the like.

Fig. 8 is a diagram of dividing the area of the cell array CA according to the neural network shown in fig. 7. The cell array CA shown in FIG. 8 includes cells IM connected to the (m+n) rows (n+p) columns of signal lines X [1] to X [ m ] and X [ m+1] to X [ m+n ] and signal lines Y [1] to X [ n ] and X [ n+1] to X [ n+p ]. In the cell array CA shown in FIG. 8, the signal lines X [1] to X [ m+n ] are inputted with the t-th data X [1] (t) to X [1] [ m ] (t) and the t-th data X [ 2 ] [1] (t) to X [ 2 ] [ n ] (t). In the cell array CA shown in fig. 8, the signal lines Y [1] to Y [ n+p ] are input with the t-th data Y1[1] (t) to Y1[ n ] (t) and the t-th data Y2[1] (t) to Y2[ p ] (t). That is, the product-sum operation Y1[ j ] (t) =Σw1[ i, j ] x1[ i ] (t) of m rows and n columns in the second layer, which is the intermediate layer with respect to the t-th data X1[1] (t) to X1[ m ] (t), is allocated to the region L1, and the product-sum operation Y2[ k ] (t) =Σw2[ j, k ] x2[ j ] (t) of n rows and p columns in the third layer, which is the output layer with respect to the t-th data X2[1] (t) to X2[ n ] (t), is allocated to the region L2.

Fig. 9 is a driving timing chart of the semiconductor device in which the cell array CA is divided into the regions as shown in fig. 8. Note that the cells IM of the ith column and jth column (i=1 to m, j=1 to n) of the cell array CA store weight data w1[ i, j ]. Further, the cells IM of the (m+i) th row (n+j) th column (i=1 to n, j=1 to p) of the cell array CA store weight data w2[ i, j ].

At time TX10, analog signals X1[1] (t) to X1[ m ] (t) corresponding to the tth data are supplied to the signal lines X [1] to X [ m ]. In the region L1 of the cell array CA, an operation corresponding to m rows and n columns of product-sum operations Σw1[ i, j ] x1[ i ] (t) is performed.

At time TX11, analog signals Y1[1] (t) =Σw1[ i,1] x1[ i ] (t) to Y1[ n ] (t) =Σw1[ i, n ] x1[ i ] (t) of each column of the region L1 of the cell array CA are determined and supplied to the signal lines Y [1] to Y [ n ].

At time TX12, analog signals X2[1] (t) to X2[ n ] (t) obtained by performing nonlinear operation on the analog signals y1[1] (t) to y1[ n ] (t) are supplied to signal lines X [ m+1] to X [ m+n ]. In the region L2 of the cell array CA, an operation corresponding to a product-sum operation Σw2[ j, k ] x2[ j ] (t) of n rows and p columns is performed.

At time TX13, analog signals Y2[1] (t) =Σw2[ j,1] x2[ j ] (t) to Y2[ L ] (t) =Σw2[ j, n ] x2[ j ] (t) of each column of the region L2 of the cell array CA are determined and supplied to the signal lines Y [ n+1] to Y [ n+p ]. Here, the analog signals y2[1] (t) to y2[ p ] (t) correspond to the result of performing the arithmetic processing of the neural network of fig. 7 on the t-th data.

At time TX20, analog signals X1[1] (t+1) to X1[ m ] (t+1) corresponding to the (t+1) th data are supplied to signal lines X1 ] to X [ m ]. In the region L1 of the cell array CA, an operation corresponding to m rows and n columns of product-sum operations Σw1[ i, j ] x1[ i ] (t+1) is performed.

At time TX21, analog signals Y1[1] (t+1) =Σw1[ i,1] x1[ i ] (t+1) to Y1[ n ] (t+1) =Σw1[ i, n ] x1[ i ] (t+1) of each column of the region L1 of the cell array CA are determined and supplied to the signal lines Y [1] to Y [ n ].

At time TX22, analog signals X2[1] (t+1) to X2[ n ] (t+1) obtained by performing nonlinear operation on analog signals y1[1] (t+1) to y1[ n ] (t+1) are supplied to signal lines X [ m+1] to X [ m+n ]. In the region L2 of the cell array CA, a product-sum operation Σw2[ j, k ] x2[ j ] (t+1) corresponding to n rows and p columns is performed.

At time TX23, analog signals Y2[1] (t+1) =Σw2[ j,1] x2[ j ] (t+1) to Y2[ L ] (t+1) =Σw2[ j, n ] x2[ j ] (t+1) of each column of the region L2 of the cell array CA are determined and supplied to the signal lines Y [ n+1] to Y [ n+p ]. Here, the analog signals y2[1] (t+1) to y2[ l ] (t+1) correspond to the result of performing the arithmetic processing of the neural network of fig. 7 on the (t+1) th data.

Fig. 10 shows an example of a peripheral circuit of the semiconductor device MAC2 including the cell array CA that can perform the arithmetic processing of the present embodiment. The semiconductor device MAC2 includes a circuit XCS, a circuit WCS, a circuit WSD, a cell array CA, a circuit ITRZ, and a circuit ACT. The cell array CA includes matrix-like cells IM arranged in (m+n) rows and (n+p) columns. The semiconductor device MAC2 is different from the semiconductor device MAC of the above embodiment 1 in that: the former includes a circuit ACT between signal lines Y [1] to Y [ n ] and signal lines X [ m+1] to X [ m+n ].

The circuit ACT includes a circuit having a function of performing nonlinear operations corresponding to the respective columns of the cell array CA. The circuit ACT can acquire an analog signal obtained by performing nonlinear operation based on analog signals output from each column of the cell array CA to the signal lines Y [1] to Y [ n ]. In addition, by outputting the analog signal to the signal lines X [ m+1] to X [ m+n ], it can be supplied to the cells IM of each row of the cell array CA.

Further, it is preferable to have a structure in which an analog signal supplied from the circuit ACT and an analog signal supplied from the circuit XCS can be selectively supplied to the signal lines X [ m+1] to X [ m+n ]. In addition, the signal lines Y [1] to Y [ n ] preferably have a structure in which an analog signal can be supplied to the circuit ITRZ in addition to the circuit ACT. By adopting this configuration, the number of rows and columns of the regions L1 and L2 can be flexibly changed according to the configuration of the neural network to be operated. Note that an analog signal from the circuit XCS or the circuit ACT may be selectively supplied to a plurality of all of the signal lines X [1] to X [ m+n ] or the signal lines X [1] to X [ m+n ]. In addition, the analog signal can be selectively supplied to the circuit ITRZ or the circuit ACT from all of the signal lines Y [1] to Y [ n+p ] or a plurality of the signal lines Y [1] to Y [ n+p ]. Further, the signal lines X [1] to X [ m+n ] and the signal lines Y [1] to Y [ n+p ] to which the analog signals are not supplied can be electrically disconnected as appropriate by analog switches or the like.

Fig. 11A shows a configuration example of a circuit ACT having a function of performing nonlinear operation. In fig. 11A, two columns of cell arrays CA are used as a pair when positive and negative weight data are used.

In the structure shown in fig. 11A, the operation corresponding to the flow of the paired signal lines Y respectively based on the positive and negative weight data held by the paired cells IM as shown in fig. 11B is explained _P [j]And Y _N [j]Analog current I of (2) ⁺ And I ^- Is a nonlinear operation structure of the (c).

Analog current I shown in FIGS. 11A and 11B ⁺ Is the current output from the column corresponding to the positive weight data. In addition, the analog current I ^- Is the current output from the column corresponding to the negative weight data. In the configuration shown in FIG. 11A, the circuit ACT is shown at I ⁺ >I ^- I.e., the final result of the product-sum operation is positive and can output a value corresponding to (I ⁺ -I ^- ) Analog current I of (2) _RELU . On the other hand, in the configuration shown in FIG. 11A, the circuit ACT is shown at I ⁺ <I ^- I.e. the final result of the product-sum operation is negative, an analog current I equivalent to 0 can be output _RELU . That is, an output equivalent to a result obtained by performing a nonlinear operation using a ReLU function can be obtained based on the result of the product-sum operation.

With the above configuration, a low power consumption semiconductor device can be provided in which a product-sum operation equivalent to a plurality of layers of a neural network can be efficiently performed in one cell array without performing analog-to-digital conversion or digital-to-analog conversion in the middle of the operation.

Embodiment 3

In this embodiment, a configuration example of the cell array and the peripheral circuit thereof described in the above embodiment will be described.

< structural example of cell array CA >

Fig. 12 shows a configuration example of a semiconductor device that performs a product-sum operation of weight data of positive or "0" and input data of positive or "0". The semiconductor device MAC1 shown in fig. 12 is a circuit that performs a product-sum operation of weight data corresponding to a potential held by each cell and input data (first data) to be input, and performs an operation of an activation function using intermediate data (second data) of the product-sum operation. The weight data and the input data may be, for example, analog data or multi-value data (discrete data).

The semiconductor device MAC1 includes a circuit WCS, a circuit XCS, a circuit WSD, a circuit SWS1, a circuit SWS2, a cell array CA, and circuits ITRZ [1] to ITRZ [ n ].

The cell array CA includes cells IM [1,1] to IM [ m, n ] (where m is an integer of 1 or more, n is an integer of 1 or more) and cells IMref [1] to IMref [ m ]. The cells IM [1,1] to IM [ m, n ] each have a function of holding a potential corresponding to the amount of current corresponding to the weight data, and the cells IMref [1] to IMref [ m ] have a function of supplying a potential corresponding to input data required at the time of a product-sum operation with the held weight data to the wirings XCL [1] to XCL [ m ].

In the cell array CA of fig. 12, the cells are arranged in a matrix of n+1 rows and m columns, but the cell array CA may have a configuration in which the cells are arranged in a matrix of 2 rows or more and 2 columns or more, and when the semiconductor device MAC and the semiconductor device MAC2 described in embodiment 1 and embodiment 2 are used, the cells IM corresponding to the respective regions may be provided.

The cells IM [1,1] to IM [ m, n ] each include, for example, a transistor F1, a transistor F2, and a capacitor C5, and the cells IMref [1] to IMref [ m ] each include, for example, a transistor F1m, a transistor F2m, and a capacitor C5m.

In particular, the size (e.g., channel length, channel width, structure of transistors, etc.) of the transistor F1 included in each of the cells IM [1,1] to IM [ m, n ] is preferably equal, and the size of the transistor F2 included in each of the cells IM [1,1] to IM [ m, n ] is preferably equal. In addition, the size of the transistor F1m included in each of the cells IMref [1] to IMref [ m ] is preferably equal, and the size of the transistor F2m included in each of the cells IMref [1] to IMref [ m ] is preferably equal. In addition, the transistor F1 and the transistor F1m are preferably equal in size, and the transistor F2m are preferably equal in size.

By equalizing the sizes of the transistors, the electrical characteristics of the transistors can be made substantially the same. Therefore, by making the sizes of the transistors F1 included in each of the cells IM [1,1] to IM [ m, n ] equal and making the sizes of the transistors F2 included in each of the cells IM [1,1] to IM [ m, n ] equal, the cells IM [1,1] to IM [ m, n ] can perform almost the same operation under the same condition. Here, the same conditions refer to, for example, potentials input to the source, drain, gate, and the like of the transistor F1, potentials input to the source, drain, gate, and the like of the transistor F2, and voltages input to the cells IM [1,1] to IM [ m, n ], respectively. In addition, by equalizing the sizes of the transistors F1m included in each of the cells IMref [1] to IMref [ m ] and equalizing the sizes of the transistors F2m included in each of the cells IMref [1] to IMref [ m ], the operations of the cells IMref [1] to IMref [ m ] and the results of the operations can be made substantially the same, for example. Under the same conditions, almost the same work can be performed. Here, the same condition refers to, for example, the potentials input to the source, drain, gate, and the like of the transistor F1m, the potentials input to the source, drain, gate, and the like of the transistor F2m, and the voltages input to the respective cells IMref [1] to IMref [ m ], and the like.

Note that unless otherwise specified, both include a case where the transistor F1 and the transistor F1m finally operate in a linear region when in an on state. In other words, the following cases are included: the gate voltage, source voltage and drain voltage of each transistor are within a voltage range operating in a linear region. However, one embodiment of the present invention is not limited thereto. For example, the transistors F1 and F1m may be operated in the saturation region or in the linear region or in the saturation region when in the on state.

In addition, unless otherwise specified, both include a case where the transistor F2 and the transistor F2m operate in a subthreshold region (that is, a case where the gate-source voltage in the transistor F2 or the transistor F2m is lower than the threshold voltage, more preferably, a case where the drain voltage increases exponentially with respect to the gate-source voltage). In other words, the following cases are included: the gate voltage, source voltage and drain voltage of each transistor are within a voltage range operating in the sub-threshold region. Therefore, the transistor F2 and the transistor F2m are operated such that an off-state current flows between the source and the drain.

The transistor F1 and/or the transistor F1m is preferably a transistor (also referred to as an OS transistor) including a metal oxide (also referred to as an oxide semiconductor) in a channel formation region, for example. Further, the channel formation region of the transistor F1 and/or the transistor F1m is more preferably an oxide containing at least one of indium, gallium, and zinc. In addition, an oxide containing at least one of indium, an element M (for example, one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like) and zinc may be used instead of the oxide.

By using an OS transistor as the transistor F1 and/or the transistor F1m, leakage current of the transistor F1 and/or the transistor F1m can be suppressed, whereby power consumption of the semiconductor device can be reduced. Specifically, since the leakage current from the holding node to the wiring XCL or the wiring WCL in the non-conductive state of the transistor F1 and/or the transistor F1m can be made very small, the refresh operation of the potential of the holding node can be reduced. Further, the power consumption of the semiconductor device can be reduced by reducing the refresh operation. In addition, by making the leakage current from the holding node to the wiring WCL or the wiring XCL extremely small, the cell can hold the potential of the holding node for a long period of time, and therefore the operation accuracy of the semiconductor device can be improved.

Further, by using an OS transistor as the transistor F2 and/or the transistor F2m, it is possible to operate in a wide current range in a sub-threshold region, whereby current consumption can be reduced. Further, by using an OS transistor as the transistor F2 and/or the transistor F2m, the transistor F1m, and the transistor F2 and/or the transistor F2m can be manufactured simultaneously, and thus the manufacturing process of the semiconductor device can be shortened in some cases. As the transistor F2 and/or the transistor F2m, a transistor including silicon in a channel formation region (hereinafter, referred to as a Si transistor) may be used in addition to an OS transistor. As the silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, monocrystalline silicon, or the like can be used, for example.

In addition, when a semiconductor device or the like is highly integrated on a chip or the like, heat may be generated in the chip due to circuit driving. Since the temperature of the transistor increases due to the heat generation, the characteristics of the transistor change, which may cause a change in field effect mobility, a decrease in operating frequency, or the like. The OS transistor is higher in heat resistance than the Si transistor, and therefore, a change in field effect mobility due to a temperature change is less likely to occur, and a decrease in operating frequency is less likely to occur. Therefore, by using the OS transistor, operations, processing, and the like are easily performed even in a high-temperature environment. When a semiconductor device having high resistance to driving heat generation is formed, an OS transistor is preferably used as the transistor.

In each of the cells IM [1,1] to IM [ m, n ], the first terminal of the transistor F1 is electrically connected to the gate of the transistor F2. A first terminal of the transistor F2 is electrically connected to the wiring VE. A first terminal of the capacitor C5 is electrically connected to the gate of the transistor F2.

In each of the cells IMref [1] to IMref [ m ], a first terminal of the transistor F1m is electrically connected to a gate of the transistor F2 m. The first terminal of the transistor F2m is electrically connected to the wiring VE. A first terminal of the capacitor C5m is electrically connected to the gate of the transistor F2 m.

In fig. 12, the back gates are shown in the transistors F1, F2, F1m, and F2m, but the connection relationship of the back gates is not shown, but the object to which the back gates are electrically connected may be determined at the time of design. For example, in a transistor including a back gate, the gate may be electrically connected to the back gate in order to increase the on-state current of the transistor. In other words, for example, the gate of the transistor F1 may be electrically connected to the back gate, or the gate of the transistor F1m may be electrically connected to the back gate. In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring for electrically connecting the back gate of the transistor and an external circuit or the like may be provided, and a potential may be supplied to the back gate of the transistor through the external circuit or the like.

Although the transistors F1 and F2 shown in fig. 12 include back gates, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, the transistors F1 and F2 shown in fig. 12 may be transistors having a structure not including a back gate, that is, a single gate structure. In addition, a structure in which a part of the transistors includes a back gate and the other part of the transistors does not include the back gate may be also employed.

Note that although the transistors F1 and F2 shown in fig. 12 are n-channel transistors, the semiconductor device according to one embodiment of the present invention is not limited to this. For example, part or all of the transistors F1 and F2 may be replaced with p-channel transistors. When a part or the whole of the transistors F1 and F2 is replaced with a p-channel transistor, the voltage supplied by the wiring, the potential of the node NN, the potential of the node NNref, and the like described in the specification or the like may be changed as necessary to perform a desired operation of the transistors F1 and F2.

The examples of the change of the structure and the polarity of the transistor are not limited to the use of the transistors F1 and F2. For example, the structures, polarities, and the like of the transistors F1m, F2m, the transistors F3[1] to F3[ n ], the transistors F4[1] to F4[ n ], and the transistors described in other parts of the specification or the transistors shown in other drawings may be similarly changed.

The wiring VE is a wiring for passing a current between the first terminal and the second terminal of each transistor F2 of the cells IM [1,1], IM [ m,1], IM [1, n ] and IM [ m, n ], and is used as a wiring for passing a current between the first terminal and the second terminal of each transistor F2m of the cells IMref [1] and IMref [ m ]. For example, the wiring VE is used as a wiring for supplying a constant voltage. The constant voltage may be, for example, a low-level potential, a ground potential, or the like.

In the cell IM [1,1], the second terminal of the transistor F1 is electrically connected to the wiring WCL [1], and the gate of the transistor F1 is electrically connected to the wiring WSL [ 1]. A second terminal of the transistor F2 is electrically connected to the wiring WCL [1], and a second terminal of the capacitor C5 is electrically connected to the wiring XCL [ 1]. Note that in the cell IM [1,1] shown in fig. 12, a connection portion of the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node NN [1,1].

In the cell IM [ m,1], the second terminal of the transistor F1 is electrically connected to the wiring WCL [1], and the gate of the transistor F1 is electrically connected to the wiring WSL [ m ]. A second terminal of the transistor F2 is electrically connected to the wiring WCL [1], and a second terminal of the capacitor C5 is electrically connected to the wiring XCL [ m ]. Note that in the cell IM [ m,1] shown in fig. 12, a connection portion of the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node NN [ m,1].

In the cell IM [1, n ], the second terminal of the transistor F1 is electrically connected to the wiring WCL [ n ], and the gate of the transistor F1 is electrically connected to the wiring WSL [ 1]. A second terminal of the transistor F2 is electrically connected to the wiring WCL [ n ], and a second terminal of the capacitor C5 is electrically connected to the wiring XCL [ 1]. Note that in the cell IM [1, n ] shown in fig. 12, a connection portion of the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node NN [1, n ].

In the cell IM [ m, n ], the second terminal of the transistor F1 is electrically connected to the wiring WCL [ n ], and the gate of the transistor F1 is electrically connected to the wiring WSL [ m ]. A second terminal of the transistor F2 is electrically connected to the wiring WCL [ n ], and a second terminal of the capacitor C5 is electrically connected to the wiring XCL [ m ]. Note that in the cell IM [ m, n ] shown in fig. 12, a connection portion of the first terminal of the transistor F1, the gate of the transistor F2, and the first terminal of the capacitor C5 is represented as a node NN [ m, n ].

In the cell IMref [1], the second terminal of the transistor F1m is electrically connected to the wiring XCL [1], and the gate of the transistor F1m is electrically connected to the wiring WSL [1]. A second terminal of the transistor F2m is electrically connected to the wiring XCL [1], and a second terminal of the capacitor C5 is electrically connected to the wiring XCL [1]. Note that in the cell IMref [1] shown in fig. 12, a connection portion of the first terminal of the transistor F1m, the gate of the transistor F2m, and the first terminal of the capacitor C5 is represented as a node NNref [1].

In the cell IMref [ m ], a second terminal of the transistor F1m is electrically connected to the wiring XCL [ m ], and a gate of the transistor F1m is electrically connected to the wiring WSL [ m ]. A second terminal of the transistor F2m is electrically connected to the wiring XCL [ m ], and a second terminal of the capacitor C5 is electrically connected to the wiring XCL [ m ]. Note that in the cell IMref [ m ] shown in fig. 12, a connection portion of the first terminal of the transistor F1m, the gate of the transistor F2m, and the first terminal of the capacitor C5 is represented as a node NNref [ m ].

The nodes NN [1,1] to NN [ m, n ] and the nodes NNref [1] to NNref [ m ] are used as holding nodes for the respective cells.

In the cells IM [1,1] to IM [ m, n ], for example, in the case where the transistor F1 is in an on state, the transistor F2 has a diode-connected structure. The constant voltage supplied from the wiring VE is set to the ground potential (GND), the transistor F1 is in an on state, and a current of the current amount I flows from the wiring WCL to the second terminal of the transistor F2, and the potential of the gate (node NN) of the transistor F2 at this time is determined in accordance with the current amount I. Since the transistor F1 is in an on state, it is desirable that the potential of the second terminal of the transistor F2 is equal to the gate (node NN) of the transistor F2. Here, by placing the transistor F1 in an off state, the potential of the gate (node NN) of the transistor F2 is held. Thus, the transistor F2 can flow a current of the current amount I corresponding to the ground potential of the first terminal of the transistor F2 and the potential of the gate (node NN) of the transistor F2 between the source and the drain of the transistor F2. In this specification and the like, such an operation is referred to as "setting (programming) the amount of current flowing between the source and the drain of the transistor F2 of the cell IM to I", and the like.

The circuit SWS1 includes, for example, transistors F3[1] to F3[ n ]. A first terminal of the transistor F3[1] is electrically connected to the wiring WCL [1], a second terminal of the transistor F3[1] is electrically connected to the circuit WCS, and a gate of the transistor F3[1] is electrically connected to the wiring SWL 1. The first terminal of the transistor F3[ n ] is electrically connected to the wiring WCL [ n ], the second terminal of the transistor F3[ n ] is electrically connected to the circuit WCS, and the gate of the transistor F3[ n ] is electrically connected to the wiring SWL 1.

As the transistors F3[1] to F3[ n ], for example, transistors usable for the transistor F1 and/or the transistor F2 can be used. In particular, as the transistors F3[1] to F3[ n ], OS transistors are preferably used.

The circuit SWS1 is used as a circuit which makes the circuit WCS and each of the wirings WCL [1] to WCL [ n ] in a conductive state or a non-conductive state.

The circuit SWS2 includes, for example, transistors F4[1] to F4[ n ]. A first terminal of the transistor F4[1] is electrically connected to the wiring WCL [1], a second terminal of the transistor F4[1] is electrically connected to an input terminal of the circuit ITRZ [1], and a gate of the transistor F4[1] is electrically connected to the wiring SWL 2. A first terminal of the transistor F4[ n ] is electrically connected to the wiring WCL [ n ], a second terminal of the transistor F4[ n ] is electrically connected to an input terminal of the circuit ITRZ [ n ], and a gate of the transistor F4[ n ] is electrically connected to the wiring SWL 2.

As the transistors F4[1] to F4[ n ], for example, transistors usable for the transistor F1 and/or the transistor F2 can be used. In particular, as the transistors F4[1] to F4[ n ], OS transistors are preferably used.

The circuit SWS2 has a function of bringing a wiring WCL [1] and a circuit ITRZ [1] into a conductive state or a nonconductive state between a wiring WCL [ n ] and a circuit ITRZ [ n ].

The circuit WCS has a function of transmitting data stored in each cell in the cell array CA.

The circuit XCS is electrically connected to the wiring XCL [1] to the wiring XCL [ m ]. The circuit XCS has a function of causing a current amount corresponding to reference data described later or a current amount corresponding to input data to flow through the cells IMref [1] to IMref [ m ] in the cell array CA.

The circuit WSD is electrically connected to the wirings WSL [1] to WSL [ m ]. The circuit WSD has a function of supplying a predetermined signal to the wirings WSL [1] to WSL [ m ] to select a row of the memory cells CA to be weight data written when weight data is written to the cells IM [1,1] to IM [ m, n ]. That is, the wirings WSL [1] to WSL [ m ] are used as write word lines.

The circuit WSD is electrically connected to, for example, the wirings SWL1 and SWL 2. The circuit WSD has a function of supplying a predetermined signal to the wiring SWL1 to bring the circuit WCS into a conductive state or a nonconductive state with the cell array CA, and a function of supplying a predetermined signal to the wiring SWL2 to bring the circuits ITRZ [1] to ITRZ [ n ] into a conductive state or a nonconductive state with the cell array CA.

The circuits ITRZ [1] to ITRZ [ n ] each include, for example, an input terminal and an output terminal. For example, an output terminal of the circuit ITRZ [1] is electrically connected to the wiring OL [1], and an output terminal of the circuit ITRZ [ n ] is electrically connected to the wiring OL [ n ].

The circuits ITRZ [1] to ITRZ [ n ] each have a function of converting a current into a voltage corresponding to an amount thereof when the input terminal is inputted with the current and outputting the voltage from the output terminal. The voltage may be, for example, an analog voltage, a digital voltage, or the like. The circuits ITRZ [1] to ITRZ [ n ] may each include a semiconductor device that performs a function operation. At this time, for example, the function operation may be performed by the semiconductor device using the converted voltage, and the operation result may be output to the wirings OL [1] to OL [ n ].

In particular, when performing the operation of the hierarchical neural network, as the nonlinear function, for example, a sigmoid function, a tanh function, a softmax function, a ReLU function, a threshold function, or the like can be used.

< structural examples of Circuit WCS and Circuit XCS >

A configuration example of the circuit WCS and the circuit XCS is described.

First, the circuit WCS is explained. Fig. 13A is a block diagram showing an example of the circuit WCS. In fig. 13A, a circuit SWS1, a transistor F3, a wiring SWL1, and a wiring WCL are also illustrated in order to illustrate electrical connection of the circuit WCS and its surrounding circuits. The transistor F3 is any one of the transistors F3[1] to F3[ n ] in the semiconductor device MAC1 of fig. 12, and the wiring WCL is any one of the wirings WCL [1] to WCL [ n ] in the semiconductor device MAC1 of fig. 12.

As an example, the circuit WCS shown in fig. 13A includes a switch SWW. A first terminal of the switch SWW is electrically connected to a second terminal of the transistor F3, and a second terminal of the switch SWW is electrically connected to the wiring VINIL 1. The wiring VINIL1 is used as a wiring for supplying a potential for initialization to the wiring WCL, and the potential for initialization may be a ground potential (GND), a low level potential, a high level potential, or the like. The switch SWW is in an on state only when a potential for initialization is supplied to the wiring WCL, and is in an off state otherwise.

As the switch SWW, for example, an analog switch, a transistor, or the like can be used. When a transistor is used as the switch SWW, the transistor may be a transistor having the same structure as the transistors F1 and F2. In addition, mechanical switches may be used in addition to electrical switches.

In addition, as an example, the circuit WCS of fig. 13A includes a plurality of current sources CS. Specifically, the circuit WCS has a circuit for converting K bits (2 ^K Value) (K is an integer of 1 or more) as an amount of current, in which case the circuit WCS includes 2 ^K -1 current source CS. The circuit WCS includes a current source CS outputting information corresponding to the value of the first bit as a current, two current sources CS outputting information corresponding to the value of the second bit as a current, and 2 ^K-1 And a current source CS for outputting information corresponding to the K-th bit value as a current.

In fig. 13A, each current source CS includes a terminal T1 and a terminal T2. The terminal T1 of each current source CS is electrically connected to the second terminal of the transistor F3 in the circuit SWS 1. In addition, a terminal T2 of one current source CS and a wiring DW [1 ]]Electrically connected, terminal T2 of both current sources CS is connected to wiring DW [2 ]]Electric connection, 2 ^K-1 Terminals T2 of the current sources CS are connected to the wiring DW [ K ]]And (5) electric connection.

Multiple current sources CS in circuit WCS have the same constant current I _Wut And a function of outputting from the respective terminals T1. Note that, in practice, in the manufacturing stage of the semiconductor device MAC1, an error may be generated due to fluctuation in the electrical characteristics of the transistors in the respective current sources CS. Accordingly, the terminals T1 of the plurality of current sources CS output the constant current I _Wut The error of (2) is preferably within 10%, more preferably within 5%, and still more preferably within 1%. In the present embodiment, it is assumed that a constant current I is output from a terminal T1 of a plurality of current sources CS in the circuit WCS _Wut The description is made without error.

Wiring DW [1 ]]To wiring DW [ K ]]Is used as a transmitter to output a constant voltage from a current source CS electrically connected theretoConstant current I _Wut Wiring of control signals of (a) is provided. Specifically, for example, in the wiring DW [1 ] ]Is electrically connected to the wiring DW [1 ] when supplied with a high-level potential]Is used as constant current to make I _Wut Flows through the second terminal of the transistor F3 and is connected to the wiring DW [1 ]]Is electrically connected to the wiring DW [1 ] when supplied with a low-level potential]Does not output I from current source CS _Wut . In addition, for example, in the wiring DW [2 ]]Is electrically connected to the wiring DW [2 ] when supplied with a high-level potential]For a total of 2I _Wut Is passed through the second terminal of the transistor F3 at the wiring DW [2 ]]Is electrically connected to the wiring DW [2 ] when supplied with a low-level potential]Does not output a total of 2I from the current source CS _Wut Is set, is provided. In addition, for example, in the wiring DW [ K ]]Is electrically connected to the wiring DW [ K ] when supplied with a high-level potential]2 of (2) ^K-1 The total of 2 current sources CS ^K-1 I _Wut Is passed through the second terminal of the transistor F3 at the wiring DW [ K ]]Is electrically connected to the wiring DW [ K ] when supplied with a low-level potential]Does not output a total of 2 ^K-1 I _Wut Is set, is provided.

Is electrically connected to the wiring DW [1 ]]The current supplied by one current source CS corresponding to the value of the first bit is electrically connected to the wiring DW 2]The current supplied by the two current sources CS corresponding to the second bit is electrically connected to the wiring DW [ K ]]The amount of current supplied by the K current sources CS corresponds to the value of the K-th bit. Consider the circuit WCS when K is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", the wiring DW [1 ] ]Is supplied with a high-level potential and wiring DW [2]]Is supplied with a low-level potential. At this time, as a constant current, I _Wut Flows from circuit WCS to the second terminal of transistor F3 of circuit SWS 1. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "1", the wiring DW [1 ]]Is supplied with a low-level potential and wiring DW [2]]Is supplied with a high-level potential. At this time, as a constant current, 2I _Wut Flows from circuit WCS to the second terminal of transistor F3 of circuit SWS 1. In addition, for example, when the value of the first bit is "1" and the value of the second bit is "1", the wiring DW [1 ]]Wire DW [2]]Is supplied with a high-level potential. At this time, as a constant current, 3I _Wut Slave circuit WCS streamingTo the second terminal of transistor F3 of circuit SWS 1. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "0", the wiring DW [1 ]]Wire DW [2]]Is supplied with a low-level potential. At this time, a constant current does not flow from the circuit WCS to the second terminal of the transistor F3 of the circuit SWS 1.

Note that, in fig. 13A, a circuit WCS in which K is an integer of 3 or more is shown, and in the case where K is 1, a configuration in which a current source CS electrically connected to the wiring DW [2] to the wiring DW [ K ] is not provided may be adopted as the circuit WCS in fig. 13A. In the case where K is 2, the circuit WCS shown in fig. 13A may be configured so that a current source CS electrically connected to the wirings DW [3] to DW [ K ] is not provided.

Next, a specific configuration example of the current source CS will be described.

The current source CS1 shown in fig. 14A is a circuit usable as the current source CS in the circuit WCS of fig. 13A, and the current source CS1 includes a transistor Tr1 and a transistor Tr2.

The first terminal of the transistor Tr1 is electrically connected to the wiring VDDL, and the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr1, and the first terminal of the transistor Tr2. A second terminal of the transistor Tr2 is electrically connected to the terminal T1, and a gate of the transistor Tr2 is electrically connected to the terminal T2. The terminal T2 is electrically connected to the wiring DW.

The wiring DW is any one of the wirings DW [1] to DW [ K ] of fig. 13A.

The wiring VDDL is used as a wiring for supplying a constant voltage. The constant voltage may be, for example, a high level potential.

When the constant voltage supplied by the wiring VDDL is set to a high-level potential, the first terminal of the transistor Tr1 is input with the high-level potential. In addition, the potential of the second terminal of the transistor Tr1 is set to a potential lower than the high-level potential. At this time, the first terminal of the transistor Tr1 is used as a drain, and the second terminal of the transistor Tr1 is used as a source. In addition, the gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, and thus the gate-source voltage of the transistor Tr1 is 0V. Therefore, when the threshold voltage of the transistor Tr1 is within an appropriate range, the current in the sub-threshold region A range of current (drain current) flows between the first terminal and the second terminal of the transistor Tr 1. In the case where the transistor Tr1 is an OS transistor, the amount of the current is preferably 1.0×10, for example ^-8 A or less, more preferably 1.0X10 ^-12 A or less, more preferably 1.0X10 ^-15 A is less than or equal to A. Further, for example, the current is more preferably in a range that increases exponentially with respect to the gate-source voltage. That is, the transistor Tr1 is used as a current source through which a current in a current range at the time of operation in the sub-threshold region flows. The current is equivalent to I _Wut Or the following I _Xut 。

The transistor Tr2 is used as a switching element. Further, when the potential of the first terminal of the transistor Tr2 is higher than the potential of the second terminal of the transistor Tr2, the first terminal of the transistor Tr2 is used as the drain, and the second terminal of the transistor Tr2 is used as the source. In addition, the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, and thus the back gate-source voltage is 0V. Therefore, in the case where the threshold voltage of the transistor Tr2 is within an appropriate range, the transistor Tr2 is in an on state when the high-level potential is input to the gate of the transistor Tr2, and the transistor Tr2 is in an off state when the low-level potential is input to the gate of the transistor Tr 2. Specifically, when the transistor Tr2 is in the on state, a current of a current range of the above-described sub-threshold region flows from the second terminal of the transistor Tr1 to the terminal T1, and when the transistor Tr2 is in the off state, the current does not flow from the second terminal of the transistor Tr1 to the terminal T1.

Note that the circuit of the current source CS usable in the circuit WCS of fig. 13A is not limited to the current source CS1 of fig. 14A. For example, the current source CS1 has a structure in which the back gate of the transistor Tr2 and the second terminal of the transistor Tr2 are electrically connected, but a structure in which the back gate of the transistor Tr2 is electrically connected to other wirings may be adopted. Fig. 14B shows such a configuration example. The current source CS2 shown in fig. 14B has a structure in which the back gate of the transistor Tr2 is electrically connected to the wiring VTHL. In the current source CS2, since the wiring VTHL is electrically connected to an external circuit or the like, a predetermined potential can be supplied to the back gate of the transistor Tr2 by supplying the predetermined potential to the wiring VTHL by the external circuit or the like. Thereby, the threshold voltage of the transistor Tr2 can be changed. By increasing the threshold voltage of the transistor Tr2, the off-state current of the transistor Tr2 can be made small.

In addition, for example, the current source CS1 has a structure in which the back gate of the transistor Tr1 and the second terminal of the transistor Tr1 are electrically connected, but a structure in which the voltage between the back gate of the transistor Tr2 and the second terminal is held by a capacitor may be adopted. Fig. 14C shows such a configuration example. The current source CS3 shown in fig. 14C includes a transistor Tr3 and a capacitor C6 in addition to the transistors Tr1 and Tr 2. The current source CS3 differs from the current source CS1 in that: a second terminal of the transistor Tr1 and a back gate of the transistor Tr1 are electrically connected through the capacitor C6; and a first terminal electrically connecting the back gate of the transistor Tr1 and the transistor Tr 3. The current source CS3 has a structure in which the second terminal of the transistor Tr3 is electrically connected to the wiring VTL, and the gate of the transistor Tr3 is electrically connected to the wiring VWL. In the current source CS3, the transistor Tr3 is turned on by supplying a high-level potential to the wiring VWL, so that the wiring VTL and the back gate of the transistor Tr1 can be turned on. At this time, a predetermined potential can be input from the wiring VTL to the back gate of the transistor Tr 1. Further, by supplying a low-level potential to the wiring VWL to turn the transistor Tr3 off, the voltage between the second terminal of the transistor Tr1 and the back gate of the transistor Tr1 can be held by the capacitor C6. That is, by determining the voltage supplied to the back gate of the transistor Tr1 by the wiring VTL, the threshold voltage of the transistor Tr1 can be changed, and the threshold voltage of the transistor Tr1 can be fixed by the transistor Tr3 and the capacitor C6.

In addition, for example, a current source CS4 shown in fig. 14D may be used as a circuit of the current source CS usable in the circuit WCS of fig. 13A. The current source CS4 has a structure in which the back gate of the transistor Tr2 of the current source CS3 of fig. 14C is electrically connected to the wiring VTHL without being electrically connected to the second terminal of the transistor Tr 2. That is, in the current source CS4, as in the current source CS2 of fig. 14B, the threshold voltage of the transistor Tr2 can be changed according to the potential supplied by the wiring VTHL.

When a large current flows between the first terminal and the second terminal of the transistor Tr1 in the current source CS4, the on-state current of the transistor Tr2 needs to be increased in order to flow the current from the terminal T1 to the outside of the current source CS4. At this time, in the current source CS4, by supplying a high-level potential to the wiring VTHL to lower the threshold voltage of the transistor Tr2 and raise the on-state current of the transistor Tr2, a large current flowing between the first terminal and the second terminal of the transistor Tr1 can be caused to flow from the terminal T1 to the outside of the current source CS4.

Using the current sources CS1 to CS4 shown in fig. 14A to 14D as the current source CS in the circuit WCS of fig. 13A, the circuit WCS can be caused to output a current corresponding to the weight data of K bits. The amount of current may be, for example, an amount of current flowing between the first terminal and the second terminal in a range in which the transistor F1 operates in the sub-threshold region.

The circuit WCS shown in fig. 13B may be used as the circuit WCS in fig. 13A. The circuit WCS of FIG. 13B has a wiring DW [1]]To wiring DW [ K ]]A structure of the current source CS of fig. 14A is connected to each. In addition, in the transistor Tr1[1]]Is w 1]Transistors Tr1[2 ]]Is w 2]And transistor Tr1[ K]Has a channel width w [ K ]]When the ratio of the channel widths is w 1]：w[2]：w[K]＝1：2：2 ^K-1 . Since the current flowing between the source and the drain of the transistor operating in the sub-threshold region is proportional to the channel width, the circuit WCS shown in fig. 13B can output a current corresponding to the weight data of K bits as in the circuit WCS of fig. 13A.

The transistor Tr1 (including the transistor Tr1[1] to the transistor Tr2[ K ]), the transistor Tr2 (including the transistor Tr2[1] to the transistor Tr2[ K ]), and the transistor Tr3 may use, for example, transistors usable for the transistor F1 and/or the transistor F2. In particular, the transistor Tr1 (including the transistor Tr1[1] to the transistor Tr2[ K ]), the transistor Tr2 (including the transistor Tr2[1] to the transistor Tr2[ K ]), and the transistor Tr3 preferably use OS transistors.

Next, a specific example of the circuit XCS will be described.

Fig. 13C is a block diagram showing an example of the circuit XCS. Note that in fig. 13C, a wiring XCL is also illustrated in order to illustrate electrical connection of the circuit WCS with its surrounding circuits. The wiring XCL is any one of the wiring XCL [1] to the wiring XCL [ m ] in the semiconductor device MAC1 of fig. 12.

As an example, the circuit XCS shown in fig. 13C includes a switch SWX. A first terminal of the switch SWX is electrically connected to the wiring XCL and the plurality of current sources CS, and a second terminal of the switch SWX is electrically connected to the wiring VINIL 2. The wiring VINIL2 is used as a wiring for supplying a potential for initialization to the wiring XCL, and the potential for initialization may be a ground potential (GND), a low-level potential, a high-level potential, or the like. In addition, the potential supplied by the wiring VINIL2 for initialization can be made equal to the potential supplied by the wiring VINIL 1. The switch SWX is turned on only when a potential for initialization is supplied to the wiring XCL, and is turned off otherwise.

The switch SWX may be, for example, a switch usable for the switch SWW.

The circuit configuration of the circuit XCS shown in fig. 13C may be substantially the same as that of the circuit WCS shown in fig. 14A. Specifically, the circuit XCS has a function of outputting reference data as an amount of current and outputs L bits (2 ^L Value) (L is an integer of 1 or more) is output as the current amount, in which case the circuit XCS includes 2 ^L -1 current source CS. The circuit XCS includes a current source CS outputting information corresponding to the value of the first bit as a current, two current sources CS outputting information corresponding to the value of the second bit as a current, and 2 ^L-1 And a current source CS for outputting information corresponding to the value of the L-th bit as a current.

The reference data outputted by the circuit XCS as a current may be, for example, information that the value of the first bit is "1" and the values of the second and subsequent bits are "0".

In FIG. 13C, a terminal T2 of a current source CS and a wiring DX [1 ]]Electrically connected, terminal T2 of both current sources CS is connected to wiring DX [2 ]]Electric connection, 2 ^L-1 Terminals T2 of the current sources CS are connected to the wiring DX [ L ]]And (5) electric connection.

Multiple current sources CS in circuit XCS have the same constant current will I _Xut And a function of outputting from the respective terminals T1. Wiring DX [1 ]]To wiring DX [ L ]]Is used as a transmitter to output I from a current source CS electrically connected thereto _Xut Control signal of (2)Wiring of numbers. That is, the circuit XCS has the AND wiring DX [1 ]]To wiring DX [ L ]]The amount of current corresponding to the transmitted L-bit information flows through the function of the wiring XCL. Note that the data can be transmitted to the wiring DX [1 ] for each row by the shift register, the latch circuit, or the like described in embodiment mode 1]To wiring DX [ L ]]Is controlled by a control signal of (a).

Specifically, consider herein the circuit XCS when L is 2. For example, when the value of the first bit is "1" and the value of the second bit is "0", the wiring DX [1 ]]Is supplied with a high level potential and wiring DX [2 ] ]Is supplied with a low-level potential. At this time, as a constant current, I _Xut From circuit XCS to wire XCL. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "1", the wiring DX [1 ]]Is supplied with a low level potential and wiring DX [2 ]]Is supplied with a high-level potential. At this time, as a constant current, 2I _Xut From circuit XCS to wire XCL. In addition, for example, when the value of the first bit is "1" and the value of the second bit is "1", the wiring DX [1 ]]Wiring DX [2 ]]Is supplied with a high-level potential. At this time, as a constant current, 3I _Xut From circuit XCS to wire XCL. In addition, for example, when the value of the first bit is "0" and the value of the second bit is "0", the wiring DX [1 ]]Wiring DX [2 ]]Is supplied with a low-level potential. At this time, a constant current does not flow from the circuit XCS to the wiring XCL. Note that in this case, in this specification or the like, a current which is also denoted as a current amount 0 sometimes flows from the circuit XCS to the wiring XCL. In addition, the current amounts 0 and I outputted by the circuit XCS can be reduced _Xut 、2I _Xut 、3I _Xut The input data output by the circuit XCS, in particular, the current amount I output by the circuit XCS _Xut As reference data output by the circuit XCS.

When an error occurs due to fluctuation of the electrical characteristics of transistors in each current source CS of the circuit XCS, a constant current I is outputted from each of the terminals T1 of the plurality of current sources CS _Xut The error of (2) is preferably within 10%, more preferably within 5%, and still more preferably within 1%. In the present embodiment, it is assumed that a constant current I is output from a terminal T1 of a plurality of current sources CS in a circuit XCS _Xut The description is made without error.

In addition, as the current source CS of the circuit WCS, any one of the current sources CS1 to CS4 of fig. 14A to 14D is adopted as the current source CS of the circuit XCS. At this time, the wiring DW shown in fig. 14A to 14D may be replaced with the wiring DX. Thus, the circuit XCS can flow a current in the current range of the sub-threshold region through the wiring XCL as reference data or L-bit input data.

The circuit XCS of fig. 13C may have the same circuit configuration as the circuit WCS shown in fig. 13B. In this case, the circuit WCS shown in fig. 13B may be replaced with the circuit XCS, the wiring DW [1] may be replaced with the wiring DX [1], the wiring DW [2] may be replaced with the wiring DX [2], the wiring DW [ K ] may be replaced with the wiring DX [ L ], the switch SWW may be replaced with the switch SWX, and the wiring VINIL2 may be replaced with the wiring VINIL 1.

< structural example of Circuit ITRZ >

Here, a configuration example of a circuit which can be used for the circuits ITRZ [1] to ITRZ [ n ] in the semiconductor device MAC1 of fig. 12 is described.

The circuit ITRZ1 shown in fig. 15A is one example of a circuit that can be used for the circuits ITRZ [1] to ITRZ [ n ] of fig. 12. Note that in fig. 15A, in order to show electrical connection of the circuit ITRZ1 and its surrounding circuits, the circuit SWS2, the wiring WCL, the wiring SWL2, and the transistor F4 are also shown. In addition, the wiring WCL is any one of the wirings WCL [1] to WCL [ n ] in the semiconductor device MAC1 of fig. 12, and the transistor F4 is any one of the transistors F4[1] to F4[ n ] in the semiconductor device MAC1 of fig. 12.

The circuit ITRZ1 of fig. 15A is electrically connected to the wiring WCL through the transistor F4. In addition, the circuit ITRZ1 is electrically connected to the wiring OL. The circuit ITRZ1 has a function of converting the amount of current flowing from the circuit ITRZ1 to the wiring WCL or the amount of current flowing from the wiring WCL to the circuit ITRZ1 into an analog voltage and outputting the analog voltage to the wiring OL. That is, the circuit ITRZ1 includes a current-voltage conversion circuit.

As an example, the circuit ITRZ1 of fig. 15A includes a resistor R5 and an operational amplifier OP1.

The inverting input terminal of the operational amplifier OP1 is electrically connected to the first terminal of the resistor R5 and the second terminal of the transistor F4. The non-inverting input terminal of the operational amplifier OP1 is electrically connected to the wiring VRL. The output terminal of the operational amplifier OP1 is electrically connected to the second terminal of the resistor R5 and the wiring OL.

The wiring VRL is used as a wiring for supplying a constant voltage. The constant voltage may be, for example, a ground potential (GND), a low-level potential, or the like.

When the circuit ITRZ1 has the structure of fig. 15A, the amount of current flowing from the wiring WCL through the transistor F4 through the circuit ITRZ1 or the amount of current flowing from the circuit ITRZ1 through the transistor F4 through the wiring WCL can be converted into an analog voltage and output to the wiring OL.

In particular, when the constant voltage supplied by the wiring VRL is the ground potential (GND), the inverting input terminal of the operational amplifier OP1 is virtually grounded, and thus the analog voltage output to the wiring OL may be a voltage based on the ground potential (GND).

In addition, the circuit ITRZ1 of fig. 15A is configured to output an analog voltage, but the circuit configuration applicable to the circuits ITRZ [1] to ITRZ [ n ] of fig. 12 is not limited thereto. For example, as shown in fig. 15B, the circuit ITRZ1 may also have a structure including an analog-to-digital conversion circuit ADC. Specifically, in the circuit ITRZ2 of fig. 15B, the input terminal of the analog-to-digital conversion circuit ADC is electrically connected to the output terminal of the operational amplifier OP1 and the second terminal of the resistor R5, and the output terminal of the analog-to-digital conversion circuit ADC is electrically connected to the wiring OL. By adopting such a structure, the circuit ITRZ2 of fig. 15B can output a digital signal to the wiring OL. Note that the digital signal input to the wiring OL can be converted into a serial signal by the shift register, the latch circuit, the switch, or the like described in embodiment mode 1 and output to the outside.

In addition, when the digital signal output to the wiring OL in the circuit ITRZ2 is 1 bit (binary), the circuit ITRZ2 may be replaced with the circuit ITRZ3 shown in fig. 15C. The circuit ITRZ3 of fig. 15C has a structure in which the comparator CMP1 is provided in the circuit ITRZ1 of fig. 15A. Specifically, in the circuit ITRZ3, a first input terminal of the comparator CMP1 is electrically connected to an output terminal of the operational amplifier OP1 and a second terminal of the resistor R5, a second input terminal of the comparator CMP1 is electrically connected to the wiring VRL2, and an output terminal of the comparator CMP1 is electrically connected to the wiring OL. The wiring VRL2 is used as a wiring that supplies a potential to be compared with the potential of the first terminal of the comparator CMP 1. By adopting such a configuration, the circuit ITRZ3 in fig. 15C can output a low-level potential or a high-level potential (binary digital signal) to the wiring OL in accordance with the voltage obtained by converting the amount of current flowing between the source and the drain of the transistor F4 by the current-voltage conversion circuit and the magnitude of the voltage supplied to the wiring VRL 2.

In addition, the circuits ITRZ [1] to ITRZ [ n ] usable for the semiconductor device MAC1 of fig. 12 are not limited to the circuits ITRZ1 to ITRZ3 shown in fig. 15A to 15C, respectively. For example, when the semiconductor device MAC1 is used in the operation of the hierarchical neural network, the circuits ITRZ1 to ITRZ3 preferably include semiconductor devices that perform function operations. As the semiconductor device performing the function operation, a semiconductor device such as a sigmoid function, a tanh function, a softmax function, a ReLU function, or a threshold function can be used.

Note that one embodiment of the present invention is not limited to the circuit configuration of the semiconductor device MAC1 described in this embodiment. The circuit configuration of the semiconductor device MAC1 may be changed according to circumstances. For example, as shown in the semiconductor device MAC1A of fig. 16, the structure of the semiconductor device MAC1 may be changed to a structure in which the circuit SWS1 is not provided. In the semiconductor device MAC1, the current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [ n ] can be stopped by the circuit SWS1, whereas in the semiconductor device MAC1A, the current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [ n ] can be stopped by the circuit WCS. Specifically, for example, when the circuit WCS of fig. 13A is used as the circuit WCS in the semiconductor device MAC1A and the current source CS1 of fig. 14A is used as the current source CS, a low-level potential may be input to each of the wirings DW [1] to DW [ K ] to turn off the switch SWW. By making the circuit WCS operate as such, a current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [ n ] can be stopped. Thus, by stopping the current flowing from the circuit WCS to the wiring WCL [1] to the wiring WCL [ n ] by the circuit WCS, the operation can be performed using the semiconductor device MAC1A instead of using the semiconductor device MAC1.

< working example of semiconductor device >

Next, an operation example of the semiconductor device MAC1 will be described.

Fig. 17 is a timing chart of an operation example of the semiconductor device MAC 1. The timing chart of fig. 17 shows the wiring SWL1, the wiring SWL2, and the wiring WSL [ i ] in the period from time T11 to time T23 and the vicinity thereof](i is an integer of 1 to m-1 inclusive), wiring WSL [ i+1]]Wiring XCL [ i ]]Wiring XCL [ i+1]]Node NN [ i, j](j is an integer of 1 to n-1), and node NN [ i+1, j]Node NNref [ i ]]Node NNref [ i+1]]Is a change in the potential of (a). The timing chart of FIG. 17 also shows the flow-through cells IM [ i, j ]]The current amount I between the first terminal and the second terminal of the transistor F2 in (1) _F2 [i，j]Flow-through cell IMref [ i ]]The current amount I between the first terminal and the second terminal of the transistor F2m _F2m [i]Flow-through cell IM [ i+1, j]The current amount I between the first terminal and the second terminal of the transistor F2 in (1) _F2 [i+1，j]And a flow-through cell IMref [ i+1]]The current amount I between the first terminal and the second terminal of the transistor F2m _F2m [i+1]Each of which varies.

The circuit WCS of the semiconductor device MAC1 uses the circuit WCS of fig. 13A, and the circuit XCS of the semiconductor device MAC1 uses the circuit XCS of fig. 13C.

Note that in this working example, the potential of the wiring VE is the ground potential GND. Before time T11, the potentials of nodes NN [ i, j ], NN [ i+1, j ], NNref [ i ] and NNref [ i+1] are set to the ground potential GND as initial settings. Specifically, for example, the potential of the wiring VINIL1 in fig. 13A for initialization is set to the ground potential GND, and the potential of the nodes NN [ i, j ] and NN [ i+1, j ] can be set to the ground potential GND by turning on the switch SWW, the transistor F3, and the transistors F1 in the cells IM [ i, j ] and IM [ i+1, j ]. For example, the potential of the wiring VINIL2 of fig. 13C for initialization is set to the ground potential GND, and the potential of the nodes NNref [ i, j ] and NNref [ i+1, j ] can be set to the ground potential GND by turning on the switches SWX and the transistors F1m in the cells IMref [ i, j ] and IMref [ i+1, j ].

In a period from time T11 to time T12, a High-level potential (High in fig. 17) is applied to the wiring SWL1, and a Low-level potential (Low in fig. 17) is applied to the wiring SWL 2. Therefore, a high-level potential is applied to each gate of the transistors F3[1] to F3[ n ], each of the transistors F3[1] to F3[ n ] becomes on, a low-level potential is applied to each gate of the transistors F4[1] to F4[ n ], and each of the transistors F4[1] to F4[ n ] becomes off.

In addition, a low-level potential is applied to the wirings WSL [ i ], WSL [ i+1] during the period from time T11 to time T12. Accordingly, a low-level potential is applied to the gate of the transistor F1 in the cells IM [ i,1] to IM [ i, n ] of the i-th row of the cell array CA and the gate of the transistor F1m in the cell IMref [ i ], and the transistor F1m each become an off state. In addition, a low-level potential is applied to the gate of the transistor F1 in the cells IM [ i+1,1] to IM [ i+1, n ] of the i+1 th row of the cell array CA and the gate of the transistor F1m in the cell IMref [ i+1], and the transistor F1m each become an off state.

In addition, the ground potential GND is applied to the wirings XCL [ i ], XCL [ i+1] during the period from time T11 to time T12. Specifically, for example, when the wiring XCL in fig. 13C is the wiring XCL [ i ] or the wiring XCL [ i+1], the potential for initializing the wiring VINIL2 is set to the ground potential GND, and the switch SWX is turned on, whereby the potentials of the wiring XCL [ i ] and the wiring XCL [ i+1] can be set to the ground potential GND.

In addition, in each case where the wiring WCL in fig. 13A is each of the wirings WCL [1] to WCL [ K ] during the period from time T11 to time T12, the wirings DW [1] to DW [ K ] are not inputted with weight data. In addition, in each case where the wiring XCL in fig. 13C is each of the wirings XCL [1] to XCL [ K ], no input data is input to the wirings DX [1] to DX [ L ]. Here, the wirings DW [1] to DW [ K ] in the circuit WCS of fig. 13A are all inputted with low-level potentials, and the wirings DX [1] to DX [ L ] in the circuit XCS of fig. 13C are all inputted with low-level potentials.

In addition, during the period from time T11 to time T12, a current does not flow through the wiring WCL [ j ]]Wiring XCL[i]Wiring XCL [ i+1 ]]. Thus, I _F2 [i，j]、I _F2m [i]、I _F2 [i+1，j]、I _F2m [i+1]Is 0.

During the period from time T12 to time T13, a high-level potential is applied to the wiring WSL [ i ]. Therefore, a high-level potential is applied to the gate of the transistor F1 in the cells IM [ i,1] to IM [ i, n ] of the i-th row of the cell array CA and the gate of the transistor F1m in the cell IMref [ i ], and the transistor F1m each become an on state. In addition, during the period from time T12 to time T13, a low-level potential is applied to the wirings WSL [1] to WSL [ m ] other than the wiring WSL [ i ], and the transistor F1 in the cells IM [1,1] to IM [ m, n ] of the cell array CA other than the i-th row and the transistor F1m in the cells IMref [1] to IMref [ m ] other than the i-th row are in an off state.

Then, from time T12 onward, the ground potential GND is applied to the wirings XCL [1] to XCL [ m ].

During the period from time T13 to time T14, the current amount I ₀ [i，j]The current from circuit WCS passes through transistor F3 j as weight data]Flows to the cell array CA. Specifically, when the wiring WCL in fig. 13A is the wiring WCL [ j ]]At this time, the wiring DW [1]]To wiring DW [ K ]]Is input with a signal corresponding to the weight data, thereby the current I ₀ [i，j]From circuit WCS to transistor F3 j]Is provided for the second terminal of (c). That is, when the value of the K-bit signal to be input as weight data is α [ i, j](α[i，j]Is 0 or more and 2 ^K -an integer of 1 or less), I is established ₀ [i，j]＝α[i，j]×I _Wut 。

In addition, when alpha [ i, j]Hold I when 0 ₀ [i，j]=0, so that strictly speaking current does not flow from circuit WCS through transistor F3[ j ]]Flows to the cell array CA, but is sometimes described as "I" in this specification or the like ₀ [i，j]Current flow of=0 ", and the like.

During the period from time T13 to time T14, the cells IM [ i, j ] of the ith row of the cell array CA]A first terminal of the transistor F1 and the wiring WCL [ j ]]Cells IM [1, j ] of the cell array CA except for the ith row are in a conductive state]To unit IM [ m, j ]]Of the transistor F1 in (a)First terminal and wiring WCL [ j ]]Is in a non-conductive state, thus the current amount I ₀ [i，j]Is from wiring WCL [ j ]]Flow to element IM [ i, j ]]。

Here, by making the unit IM [ i, j ]]The transistor F1 in (a) is in an on state, and the cell IM [ i, j ]]The transistor F2 in (a) has a diode connection structure. Thus, in the current slave wiring WCL [ j ]]Flow to element IM [ i, j ]]At this time, the potential of the gate of the transistor F2 and the potential of the second terminal of the transistor F2 are substantially equal. The potential depends on the slave wiring WCL [ j ]]Flow to element IM [ i, j ]]And the potential of the first terminal of the transistor F2 (GND here). In the working example, through the current quantity I ₀ [i，j]Is from wiring WCL [ j ]]Flow to element IM [ i, j ]]The gate of the transistor F2 (node NN [ i, j]) The potential of (2) becomes V _g [i，j]. That is, in the transistor F2, the gate-source voltage becomes V _g [i，j]GND, the current amount I ₀ [i，j]Is set to a current flowing between the first terminal and the second terminal of the transistor F2.

Here, the threshold voltage of the transistor F2 is V _th [i，j]In the case of (1), the amount of current I when the transistor F2 operates in the subthreshold region ₀ [i，j]Can be represented by the following formula (1.1).

[ formula 1]

I ₀ [i，j]＝I _a exp{J(V _g [i，j]-V _th [i，j])}…(1.1)

Note that I _a Represents V _g [i，j]Is V (V) _th [i，j]The drain current at the time J represents a correction coefficient determined by temperature, device structure, and the like.

In addition, during the period from time T13 to time T14, the current amount I _ref0 The current flows from the circuit XCS to the wiring XCL [ i ] as reference data]. Specifically, when the interconnect XCL in FIG. 13C is the interconnect XCL [ i ]]Wiring DX [1 ] in this case]Is inputted with a high level potential, wiring DX [2 ]]To wiring DX [ K ]]Is input with a low level potential, current I _ref0 From circuit XCS to wire XCL [ i ]]. That is, establish I _ref0 ＝I _Xut 。

In addition, during the period from time T13 to time T14, the cell IMref [ i ]]A first terminal of the transistor F1m and a wiring XCL [ i ]]Is in a conducting state, so the current amount I _ref0 Is from wiring XCL [ i ]]Flows to unit IMref [ i ]]。

AND cell IM [ i, j ]]Also, through cell IMref [ i ]]The transistor F1m in (a) is in an on state, and the cell IMref [ i ]]The transistor F2m in (a) has a diode connection structure. Therefore, in the current slave wiring XCL [ i ]]Flows to unit IMref [ i ]]In this case, the potential of the gate of the transistor F2m is substantially equal to the potential of the second terminal of the transistor F2 m. The potential depends on the slave wiring XCL [ i ]]Flows to unit IMref [ i ]]And the potential of the first terminal of the transistor F2m (GND here). In the working example, through the current quantity I _ref0 Is from wiring XCL [ i ]]Flows to unit IMref [ i ]]The gate of transistor F2 (node NNref [ i ]]) Becomes V _gm [i]And wiring XCL [ i ] at this time ]The potential of (2) is also V _gm [i]. That is, in the transistor F2m, the gate-source voltage becomes V _gm [i]GND, the current amount I _ref0 Is set to a current flowing between the first terminal and the second terminal of the transistor F2 m.

Here, the threshold voltage of the transistor F2m is V _thm [i]In the case of (1), the amount of current I when the transistor F2m operates in the subthreshold region _ref0 Can be represented by the following formula (1.2). Note that the correction coefficient J and the unit IM [ i, J ]]The same as the transistor F2 in (a). For example, the device structure, the size (channel length, channel width) of the transistor are the same. In addition, although there is unevenness in the correction coefficient J of each transistor due to unevenness in manufacturing, the unevenness is suppressed to such an extent that the following discussion is satisfied with sufficient accuracy in practical use.

[ formula 2]

I _ref0 ＝I _a exp{J(V _gm [i]-V _thm [i])}…(1.2)

Here, the weight coefficient w [ i, j ] as weight data is defined as the following formula (1.3).

[ arithmetic 3]

w[i,j]＝exp{J(V _g [i，]-V _th [i,j]-V _gm [4]+V _thm [i])}…(1.3)

Thus, expression (1.1) can be rewritten as expression (1.4) below.

[ calculation formula 4]

When the current I outputted by the current source CS of the circuit WCS of FIG. 13A _Wut Current I output by current source CS of circuit XCS of fig. 13C _Xut When equal, w [ i, j ] is established]＝α[i，j]. That is, when I _Wut And I _Xut When equal, alpha [ i, j]Corresponding to the value of the weight data, thus I _Wut And I _Xut Preferably equal.

During the period from time T14 to time T15, a low-level potential is applied to the wiring WSL [ i ]. Accordingly, a low-level potential is applied to the gate of the transistor F1 in the cells IM [ i,1] to IM [ i, n ] of the i-th row of the cell array CA and the gate of the transistor F1m in the cell IMref [ i ], and the respective transistors F1 and F1m become off-states.

When unit IM [ i, j ]]When the transistor F1 in (a) is turned off, the capacitor C5 holds the gate of the transistor F2 (node NN [ i, j]) Potential of (1) and wiring XCL [ i ]]V of the difference in potential of (a) _g [i，j]-V _gm [i]. In addition, when the cell IMref [ i ]]When the transistor F1 in (a) is turned off, the capacitor C5m holds the gate of the transistor F2m (node NNref [ i ]]) Potential of (1) and wiring XCL [ i ]]0 of the difference in potential between (a) and (b). Note that the voltage held by the capacitor C5m in accordance with the transistor characteristics of the transistor F1m or the transistor F2m in the operation from the time T13 to the time T14 is sometimes a voltage other than 0 (here, for example, V _ds ). At this time, node NNref [ i ]]Is regarded as the potential of the wiring XCL [ i ]]V is added to the potential of (2) _ds Is required to be a potential of (2).

During the period from time T15 to time T16, GND is applied to the wiring XCL [ i ]. Specifically, for example, when the wiring XCL in fig. 13C is the wiring XCL [ i ], the potential of the wiring XCL [ i ] can be set to the ground potential GND by setting the potential for initialization of the wiring VINIL2 to the ground potential GND and turning on the switch SWX.

Therefore, the potential of the node NN [ i,1] to the node NN [ i, n ] varies due to the capacitive coupling through the capacitor C5 in each of the cells IM [ i,1] to IM [ i, n ] of the i-th row, and the potential of the node NNref [ i ] varies due to the capacitive coupling through the capacitor C5m in the cell IMref [ i ].

Node NN [ i,1]To node NN [ i, n]The potential change of (1) is wiring XCL [ i ]]Is multiplied by the amount of change in the potential depending on each cell IM i,1 in the cell array CA]To unit IM [ i, n ]]The potential of the capacitive coupling coefficient of the structure of (a). The capacitive coupling coefficient is calculated from the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, and the like. In cell IM [ i,1]To unit IM [ i, n ]]In each case, when the capacitive coupling coefficient through the capacitor C5 is p, the cell IM [ i, j]Node NN [ i, j ]]The potential of (a) decreases by p (V) from time T14 to time T15 _gm [i]-GND)。

Similarly, in the wiring XCL [ i ]]Due to the change of the potential of the pass cell IMref [ i ]]Capacitor C5m of the capacitor and node NNref [ i ]]The potential of (2) also varies. When the capacitive coupling coefficient through the capacitor C5m is p as same as that of the capacitor C5, the cell IMref [ i ]]Node NNref [ i ] of (C)]The potential of (a) decreases by p (V) from time T14 to time T15 _gm [i]-GND). In the timing chart of fig. 17, p=1 as an example. Therefore, node NNref [ i ] during time T15 to time T16]Is GND.

Thus, cell IM [ i, j]Node NN [ i, j ]]The potential of (1) drops, so that the transistor F2 becomes off, and similarly, the cell IMref [ i ]]Node NNref [ i ] of (C)]The potential of the transistor F2m is lowered and the transistor F2m is also turned off. Thus, during the period from time T15 to time T16, I _F2 [i，j]I _F2m [i]Each 0.

During the period from time T16 to time T17, a high-level potential is applied to the wiring WSL [ i+1 ]. Accordingly, a high-level potential is applied to the gate of the transistor F1 in the i+1 th row of the cell array CA to the gate of the transistor F1 in the cell IM [ i+1, n ] and the transistor F1m in the cell IMref [ i+1], and the respective transistors F1 and F1m become on states. In addition, during the period from time T16 to time T17, a low-level potential is applied to the wirings WSL [1] to WSL [ m ] other than the wiring WSL [ i+1], and the transistors F1 in the cells IM [1,1] to IM [ m, n ] of the cell array CA other than the i+1th row and the transistors F1m in the cells IMref [1] to IMref [ m ] other than the i+1th row are in an off state.

Then, from time T16 onward, the ground potential GND is applied to the wirings XCL [1] to XCL [ m ].

During the period from time T17 to time T18, the current amount I ₀ [i+1，j]The current from circuit WCS passes through transistor F3 j as weight data]Flows to the cell array CA. Specifically, when the wiring WCL in fig. 13A is the wiring WCL [ j+1 ]]At this time, the wiring DW [1]]To wiring DW [ K ]]Is input with a signal corresponding to the weight data, thereby the current I ₀ [i+1，j]From circuit WCS to transistor F3 j]Is provided for the second terminal of (c). That is, when the value of the K-bit input signal to be input as weight data is α [ i+1, j](α[i+1，j]Is 0 or more and 2 ^K -an integer of 1 or less), I is established ₀ [i+1，j]＝α[i+1，j]×I _Wut 。

Furthermore, when alpha [ i+1, j ]]Hold I when 0 ₀ [i+1，j]=0, so that strictly speaking current does not flow from circuit WCS through transistor F3[ j ]]Flows to the cell array CA, but is equal to I in this specification and the like ₀ [i，j]The case of =0 is also sometimes denoted as "I ₀ [i+1，j]Current flow of=0 ", and the like.

At this time, the cells IM [ i+1, j ] of the i+1th row of the cell array CA]A first terminal of the transistor F1 and the wiring WCL [ j ]]The cells IM [1, j ] of the cell array CA except for the (i+1) th row are in a conductive state]To unit IM [ m, j ]]A first terminal of the transistor F1 and the wiring WCL [ j ] ]Is in a non-conductive state, thus the current amount I ₀ [i+1，j]Is from wiring WCL [ j ]]Flow to element IM [ i+1, j ]]。

Furthermore, by making the unit IM [ i+1, j ]]The transistor F1 in (a) is in an on state, and the cell IM [ i+1, j ]]The transistor F2 in (a) has a diode connection structure. Thus, in the current slave wiring WCL [ j ]]Flow to element IM [ i+1, j ]]At this time, the potential of the gate of the transistor F2 and the potential of the second terminal of the transistor F2 are substantially equal. The potential depends on the slave wiring WCLj]Flow to element IM [ i+1, j ]]And the potential of the first terminal of the transistor F2 (GND here). In the present working example, due to the current amount I ₀ [i+1，j]Is from wiring WCL [ j ]]Flow to element IM [ i+1, j ]]Thus the gate of transistor F2 (node NN [ i+1, j)]) The potential of (2) becomes V _g [i+1，j]. That is, in the transistor F2, the gate-source voltage becomes V _g [i+1，j]GND, the current amount I ₀ [i+1，j]Is set to a current flowing between the first terminal and the second terminal of the transistor F2.

Here, the threshold voltage of the transistor F2 is V _th [i+1，j]In the case of (1), the amount of current I when the transistor F2 operates in the subthreshold region ₀ [i+1，j]Can be represented by the following formula (1.5). Note that and cell IM [ i, j]Transistor F2 in (a) and unit IMref [ i ]]The transistor F2m in (a) is the same, and the correction coefficient is J.

[ calculation formula 5]

I ₀ [i+1，j]＝I _a exp{J(Vg[i+1,j]-V _th [i+1,j])}…(1.5)

In addition, during the period from time T17 to time T18, the current amount I _ref0 The current flows from the circuit XCS to the wiring XCL [ i+1 ] as reference data]. Specifically, as in the period from time T13 to time T14, the interconnect XCL in fig. 13C is the interconnect XCL [ i+1 ]]Wiring DX [1 ] in this case]Is inputted with a high level potential, wiring DX [2 ]]To wiring DX [ K ]]Is input with a low level potential, current I _ref0 ＝I _Xut From circuit XCS to wire XCS [ i+1 ]]。

During the period from time T17 to time T18, due to the cell IMref [ i+1 ]]A first terminal of the transistor F1m and a wiring XCL [ i+1 ]]The current amount I is changed to the conduction state _ref0 The current flowing through the wiring XCL [ i+1 ]]Flows to unit IMref [ i+1 ]]。

AND cell IM [ i+1, j]Also, by making the cell IMref [ i+1 ]]The transistor F1m in (1) is in an on state, and the cell IMref [ i+1, j]The transistor F2m in (a) has a diode connection structure. Therefore, in the current slave wiring XCL [ i+1 ]]Flows to unit IMref [ i+1 ]]In this case, the gate of the transistor F2m and the second terminal of the transistor F2m are substantially equal in potential. The potential depends on the slave wiring XCL [ i+1 ]]Flows to the unitIMref[i+1]And the potential of the first terminal of the transistor F2m (GND here). In the working example, through the current quantity I _ref0 The current flowing through the wiring XCL [ i+1 ] ]Flows to unit IMref [ i+1]]The gate of transistor F2 (node NNref [ i+1]]) Becomes V _gm [i+1]The wiring XCL [ i+1] at this time]The potential of (2) is also V _gm [i+1]. That is, in the transistor F2m, the gate-source voltage becomes V _gm [i+1]GND, the current amount I _ref0 Is set to a current flowing between the first terminal and the second terminal of the transistor F2 m.

Here, the threshold voltage of the transistor F2m is V _thm [i+1，j]In the case of (1), the amount of current I when the transistor F2m operates in the subthreshold region _ref0 Can be represented by the following formula (1.6). Note that the correction coefficient J and the unit IM [ i+1, J ]]The same as the transistor F2 in (a).

[ arithmetic 6]

I _ref0 ＝Ia _exp {J(V _gm [i+1]-V _thm [i+1])}…(1.6)

Here, the weight coefficient w [ i+1, j ] as weight data is defined as follows.

[ calculation formula 7]

Thus, expression (1.5) can be rewritten as expression (1.6) below.

[ calculation formula 8]

When the current I outputted by the current source CS of the circuit WCS of FIG. 13A _Wut Current I output by current source CS of circuit XCS of fig. 13C _Xut When equal, w [ i+1, j ] is established]＝α[i+1，j]. That is, when I _Wut And I _Xut When equal, alpha [ i+1, j]Corresponding to the value of the weight data, thus I _Wut And I _Xut Preferably equal.

During the period from time T18 to time T19, a low-level potential is applied to the wiring WSL [ i+1 ]. Accordingly, a low-level potential is applied to the gate of the transistor F1 in the i+1 th row of the cell array CA to the cells IM [ i+1,1] to IM [ i+1, n ] and the gate of the transistor F1m in the cell IMref [ i+1], and the respective transistors F1 and F1m become off-states.

When cell IM [ i+1, j]When the transistor F1 in (1) is turned off, the capacitor C5 holds the gate of the transistor F2 (node NN [ i+1, j]) Potential of (1) and wiring XCL [ i+1]]V of the difference in potential of (a) _g [i+1，j]-V _gm [i+1]. In addition, when cell IMref [ i+1]]When the transistor F1 in (a) is turned off, the capacitor C5m holds the gate of the transistor F2m (node NNref [ i+1]) Potential of (1) and wiring XCL [ i+1]]0 of the difference in potential between (a) and (b). Note that the voltage held by the capacitor C5m in accordance with the transistor characteristics of the transistor F1m or the transistor F2m in the operation from the time T18 to the time T19 is sometimes a voltage other than 0 (here, for example, V _ds ). At this time, node NNref [ i+1]]The potential of (1) is regarded as the potential of the wiring XCL [ i+1]]V is added to the potential of (2) _ds Is required to be a potential of (2).

During the period from time T19 to time T20, the wiring XCL [ i+1] is applied with the ground potential GND. Specifically, for example, when the wiring XCL in fig. 13C is the wiring XCL [ i+1], the potential of the wiring XCL [ i+1] can be set to the ground potential GND by setting the potential for initialization of the wiring VINIL2 to the ground potential GND to turn on the switch SWX.

Therefore, the potential of the node NN [ i,1] to the node NN [ i+1, n ] varies due to the capacitive coupling through the capacitor C5 in each of the cells IM [ i+1,1] to IM [ i+1, n ] of the i+1-th row, and the potential of the node NNref [ i+1] varies due to the capacitive coupling through the capacitor C5m in the cell IMref [ i+1 ].

Node NN [ i+1,1]To node NN [ i+1, n]The potential change of (1) is wiring XCL [ i+1 ]]The change amount of the potential of (1) is multiplied by the value depending on each cell IM [ i+1,1 ] in the cell array CA]To unit IM [ i+1, n ]]The potential of the capacitive coupling coefficient of the structure of (a). The capacitive coupling coefficient is calculated from the capacitance of the capacitor C5, the gate capacitance of the transistor F2, the parasitic capacitance, and the like. In cell IM [ i+1,1]To unit IM [ i+1, n ]]In each of them, inAND cell IM [ i,1]To unit IM [ i, n ]]The capacitive coupling coefficients through the capacitor C5 are the same, and when the capacitive coupling coefficient through the capacitor C5 is p, the unit IM [ i+1, j ]]Node NN [ i+1, j ]]The potential of (a) decreases by p (V) from time T18 to time T19 _gm [i+1]-GND)。

Similarly, in the wiring XCL [ i+1 ]]Due to the change of the potential of the pass cell IMref [ i+1 ]]Capacitor C5m of the capacitor and node NNref [ i+1 ]]The potential of (2) also varies. When the capacitive coupling coefficient through the capacitor C5m is p as same as that of the capacitor C5, the cell IMref [ i+1 ]]Node NNref [ i+1 ]]The potential of (a) decreases by p (V) from time T18 to time T19 _gm [i+1]-GND). In the timing chart of fig. 17, p=1 as an example. Therefore, node NNref [ i+1 ] during time T20 to time T21 ]Is GND.

Thus, cell IM [ i+1, j]Node NN [ i+1, j ]]The potential of (1) drops, so that the transistor F2 becomes off, and as such, the cell IMref [ i+1 ]]Node NNref [ i+1 ]]The potential of the transistor F2m is lowered and the transistor F2m is also turned off. Thus, during the period from time T19 to time T20, I _F2 [i+1，j]I _F2m [i+1]Each 0.

During the period from time T20 to time T21, a low-level potential is applied to the wiring SWL 1. Therefore, a low-level potential is applied to each gate of the transistors F3[1] to F3[ n ], and the transistors F3[1] to F3[ n ] each become an off state.

During the period from time T21 to time T22, a high-level potential is applied to the wiring SWL 2. Therefore, a high-level potential is applied to each gate of the transistors F4[1] to F4[ n ], and the transistors F4[1] to F4[ n ] each become an on state.

During the period from time T22 to time T23, the current amount I _ref0 X [ i ]]X [ i ] times]I _ref0 The current flows as input data from the circuit XCS to the wiring XCL [ i ]]. Specifically, for example, when the wiring XCL in fig. 13C is the wiring XCL [ i ]]When according to x [ i ]]Value wiring DX [1]]To wiring DX [ K ]]Is respectively inputted with a high level potential or a low level potential as an amount of current x [ i ]]I _ref0 ＝x[i]I _Xut From circuit XCS to Wiring XCL [ i ]]. Note that in this working example, x [ i ]]Corresponding to the value of the input data. At this time, the wiring XCL [ i ]]The potential of (2) is changed from 0 to V _gm [i]+ΔV[i]。

In the wiring XCL [ i ]]Due to the potential change of the ith row of cells IM [ i, 1] passing through the cell array CA]To unit IM [ i, n ]]The capacitor C5 in each is capacitively coupled and the node NN [ i,1]To node NN [ i, n]The potential of (2) also varies. Thus, cell IM [ i, j]Node NN [ i, j ]]The potential of (2) becomes V _g [i，j]+pΔV[i]。

In the same way, in the wiring XCL [ i ]]Due to the change of the potential of the pass cell IMref [ i ]]Capacitor C5m of the capacitor and node NNref [ i ]]The potential of (2) also varies. Thus, cell IMref [ i ]]Node NNref [ i ] of (C)]The potential of (2) becomes V _gm [i]+pΔV[i]。

Accordingly, during the period from time T22 to time T23, the amount of current I flowing between the first terminal and the second terminal of the transistor F2 ₁ [i，j]An amount of current I flowing between the first terminal and the second terminal of the transistor F2m _ref1 [i，j]Can be expressed as follows.

[ arithmetic 9]

I ₁ [i，j]＝I _a exp{J(V _g [i，j]+pΔV[i]-V _th [i，j])}

＝I ₀ [i，j]exp(JpΔV[i])…(1.9)

[ arithmetic 10]

I _ref1 [i]＝I _a exp{J(V _gm [i]+pΔV[i]-V _thm [i])}

＝x[i]I _ref0 …(1.10)

According to the formulas (1.9) and (1.10), x [ i ] can be represented by the following formula (1.11).

[ arithmetic 11]

x[i]＝exp(JpΔV[i])…(1.11)

Thus, expression (1.9) can be rewritten as expression (1.12) below.

[ arithmetic formula 12]

I ₁ [i，j]＝x[i]w[i，j]I _ref0 …(1.12)

That is, the amount of current flowing between the first terminal and the second terminal of the transistor F2 in the unit IM [ i, j ] is proportional to the product of the weight coefficient w [ i, j ] as the weight data and the input data x [ i ].

During the period from time T22 to time T23, the current amount I _ref0 X [ i+1 ]]X [ i+1 ] times]I _ref0 The current flows from the circuit XCS to the wiring XCL [ i+1 ] as input data]. Specifically, for example, when the wiring XCL in fig. 13C is the wiring XCL [ i+1 ]]When according to x [ i+1 ]]Value wiring DX [1 ]]To wiring DX [ K ]]Is respectively inputted with a high level potential or a low level potential as a current amount x [ i+1 ]]I _ref0 ＝x[i+1]I _Xut From circuit XCS to wire XCS [ i+1 ]]. Note that in this working example, x [ i+1 ]]Corresponding to the value of the input data. At this time, the wiring XCL [ i+1 ]]The potential of (2) is changed from 0 to V _gm [i+1]+ΔV[i+1]。

In the wiring XCL [ i+1 ]]Due to the cells IM [ i+1,1 ] passing through the i+1th row of the cell array CA]To unit IM [ i+1, n ]]The capacitor C5 in each is capacitively coupled and node NN [ i+1,1 ]]To node NN [ i+1, n]The potential of (2) also varies. Thus, cell IM [ i+1, j]Node NN [ i+1, j ]]The potential of (2) becomes V _g [i+1，j]+pΔV[i+1]。

Similarly, in the wiring XCL [ i+1 ]]Due to the change of the potential of the pass cell IMref [ i+1 ]]Capacitor C5m of the capacitor and node NNref [ i+1 ]]The potential of (2) also varies. Thus, cell IMref [ i+1 ]]Node NNref [ i+1 ]]The potential of (2) becomes V _gm [i+1]+pΔV[i+1]。

Accordingly, during the period from time T22 to time T23, the amount of current I flowing between the first terminal and the second terminal of the transistor F2 ₁ [i+1，j]An amount of current I flowing between the first terminal and the second terminal of the transistor F2m _ref1 [i+1，j]Can be expressed as follows.

[ arithmetic 13]

I ₁ [i+1，j]

＝I _a exp{J(V _g [i+1，j]+pΔV[i+1]-V _th [i+1，j])}

＝I ₀ [i+1，j]exp(JpΔV[i+1])…(1.13)

[ arithmetic 14]

I _ref1 [i+1]

＝I _a exp{J(V _gm [i+1]+pΔV[i+1]-V _thm [i+1])}

＝x[i+1]I _ref0 …(1.14)

According to the formulas (1.13) and (1.14), x [ i+1] can be represented by the following formula (1.15).

[ calculation formula 15]

x[i+1]＝exp(JpΔV[i+1])…(1.15)

Thus, expression (1.13) can be rewritten as expression (1.16) below.

[ calculation formula 16]

I ₁ [i+1，j]＝x[i+1]w[i+1，j]I _ref0 …(1.16)

That is, the amount of current flowing between the first terminal and the second terminal of the transistor F2 in the unit IM [ i+1, j ] is proportional to the product of w [ i+1, j ] as weight data and x [ i+1] as input data.

Here, consider the slave conversion circuit ITRZ [ j ]]Through transistor F4 j]And wiring WCL [ j ]]Flow to element IM [ i, j ]]Unit IM [ i+1, j ]]Is a sum of the amounts of current. At the sum of the current amounts of I _S [j]When I _S [j]Can be represented by the following formula (1.17) according to the formulas (1.12) and (1.16).

[ arithmetic 17]

I _S [j]＝I ₁ [i,j]+I ₁ [i+1，j]

＝I _ref0 (x[i]w[i,j]+x[i+1]w[i+1，j])…(1.17)

Thus, the amount of current outputted from the conversion circuit ITRZ [ j ] is an amount of current proportional to the sum of the weight coefficients w [ i, j ] and w [ i+1, j ] as weight data and the values x [ i ] and x [ i+1] of the input data.

Note that, in the above working example, although the sum of the amounts of current flowing through the cells IM [ i, j ] and the cells IM [ i+1, j ] is used, the sum of the amounts of current flowing through the cells IM [1, j ] to the cells IM [ m, j ] as a plurality of cells may be used. In this case, expression (1.17) may be rewritten as expression (1.18) below.

[ calculation formula 18]

/>

Therefore, the semiconductor device MAC1 including the cell arrays CA of 3 rows and 2 columns or more can perform the product-sum operation as described above. In this case, by using the cells of one of the columns in the semiconductor device MAC1 as the holding current amount I _ref0 xI _ref0 The product-sum operation processing of the remaining columns in the plurality of columns can be simultaneously performed. In other words, by increasing the number of columns of the cell array, a semiconductor device capable of realizing high-speed product-sum operation processing can be provided.

The working example of the semiconductor device MAC1 is suitable for the case of performing the sum-product operation of the positive weight data and the positive input data.

In the present embodiment, the case where the transistor in the semiconductor device MAC1 is an OS transistor or a Si transistor has been described, but one embodiment of the present invention is not limited to this. As the transistor in the semiconductor device MAC1, for example, a transistor including Ge or the like in a channel formation region, a transistor including a compound semiconductor such as gallium nitride in a channel formation region, a transistor including a carbon nanotube in a channel formation region, a transistor including an organic semiconductor in a channel formation region, and the like can be used.

Note that this embodiment mode can be appropriately combined with other embodiment modes shown in this specification.

Embodiment 4

In this embodiment mode, a display device including the semiconductor device is described. By including the display device with a semiconductor device capable of performing an arithmetic process of an artificial neural network, a display device capable of performing an arithmetic process with excellent arithmetic efficiency can be realized. In this embodiment, a schematic plan view and a schematic cross-sectional view of a light-emitting element, a structural example of a light-emitting element and a light-receiving element, and a structural example of a cross-sectional view of a display device are described.

< structural example of display device >

Fig. 18A is a diagram showing a perspective view of the display device 10. In the display device 10 shown in fig. 18A, the structures of the layer 20, the layer 50, and the layer 60 provided between the substrate 11 and the substrate 12 are schematically shown. Fig. 18A shows the display portion 13, the light receiving portion 14, and the input/output terminal 15 in the layer 60.

A layer 20 is provided on the substrate 11. The layer 20 is provided with a driving circuit 30 and an arithmetic circuit 40, for example. Layer 20 includes a transistor 21 (also referred to as a Si transistor) including silicon in a channel formation region 22. The substrate 11 is, for example, a silicon substrate. The silicon substrate is preferable because it has higher thermal conductivity than the glass substrate.

The transistor 21 may be, for example, a transistor including single crystal silicon in a channel formation region. In particular, when a transistor including single crystal silicon in a channel formation region is used as a transistor provided in the layer 20, on-state current of the transistor can be increased. This is preferable because the circuit included in the layer 20 can be driven at high speed. Since the transistor including single crystal silicon in the channel formation region can be formed by micromachining with a channel length of 3nm to 10nm, an accelerator such as a CPU or GPU, an application processor, or the like may be provided in addition to the dedicated arithmetic circuit 40 and/or the driving circuit 30 such as an artificial neural network (hereinafter, sometimes referred to as a neural network). The arithmetic circuit 40 may be the semiconductor device described in embodiments 1 to 3.

The driving circuit 30 includes, for example, a gate driving circuit, a source driving circuit, and the like. The gate driver circuit, the source driver circuit, and the like may be disposed so as to overlap the display portion 13 and/or the light receiving portion 14. Thus, the width of the non-display region (also referred to as a frame) on the outer periphery of the display portion 13 of the display device 10 can be made extremely small compared with the case where the drive circuit 30 and the display portion 13 are arranged, and the small-sized display device 10 can be realized. In addition, when the driving circuit 30 is disposed on the outer periphery of the display portion 13 of the display device 10, the gate driving circuit and the source driving circuit are disposed on the outer periphery in a concentrated manner, but the driving circuit 30 may be disposed in a region overlapping the display portion 13 in a divided manner.

The arithmetic circuit 40 includes the semiconductor devices described in embodiments 1 to 3. Therefore, product-sum operation processing in the artificial neural network can be performed, and inference processing based on hierarchical neural networks such as a Deep Neural Network (DNN), a Convolutional Neural Network (CNN), for example, can be performed. The arithmetic circuit 40 can perform product-sum arithmetic using minute current corresponding to the voltage of the analog value, so that arithmetic processing using minute current flowing through the light receiving element 62 as input data can be performed. Therefore, the circuit is advantageous in terms of reduction in area, reduction in power consumption, improvement in operation efficiency, and the like. The light receiving element 62 is an element that converts an optical signal into an electrical signal, and is also called a photoelectric conversion element.

Layer 20 has layer 50 disposed thereon. The layer 50 is provided with a pixel circuit section 51P including a plurality of pixel circuits 51 and a cell array CA including a plurality of cells IM. Layer 50 includes a transistor 52 (also referred to as an OS transistor) including a metal oxide (also referred to as an oxide semiconductor) in a channel formation region 54. Note that the layer 50 may be a structure that is stacked on the layer 20. Alternatively, a structure in which bonding is performed by forming the layer 50 on another substrate may be used.

As the transistor 52 of the OS transistor, a transistor including an oxide including at least one of indium, an element M (element M is aluminum, gallium, yttrium, or tin), and zinc in a channel formation region is preferably used. Such an OS transistor has a characteristic that an off-state current is extremely low. Therefore, in particular, when an OS transistor is used as a transistor provided in the pixel circuit 51 and the cell IM, analog data written in the pixel circuit 51 and the cell IM can be held for a long period of time, which is preferable.

Layer 50 has layer 60 disposed thereon. Layer 60 has substrate 12 disposed thereon. The substrate 12 is preferably a layer made of a light-transmitting substrate or a light-transmitting material. The layer 60 includes a display portion 13 provided with a plurality of light emitting elements 61 and a light receiving portion 14 provided with a plurality of light receiving elements 62. In addition, the layer 60 may be provided in a manner of being laminated on the layer 50. As the light-emitting element 61, for example, an organic electroluminescent element (also referred to as an "organic EL element") or the like can be used. However, the light-emitting element 61 is not limited to this, and for example, an inorganic EL element made of an inorganic material may be used. Note that "organic EL element" and "inorganic EL element" are sometimes collectively referred to as "EL element". The light-emitting element 61 may contain an inorganic compound such as quantum dots. For example, by using quantum dots for the light emitting layer, the quantum dots can be used as a light emitting material. For example, by using an organic photodiode or the like as the light receiving element 62, a part of the process for manufacturing the light receiving element 62 may be the same as the process for manufacturing the organic electroluminescent element.

As shown in fig. 18A, the display device 10 according to one embodiment of the present invention has a structure in which the light emitting element 61, the pixel circuit 51, and the driving circuit 30 are stacked, and therefore, the pixel circuit 51 can be arranged at an extremely high density, and the definition of pixels can be greatly improved. Such a display device 10 is extremely high in definition, and is therefore suitable for VR devices such as head-mounted displays and glasses-type AR devices. For example, since the display device 10 has a display portion with extremely high definition, in a structure in which the display portion of the display device 10 is viewed through an optical member such as a lens, a user cannot see pixels even if the display portion is enlarged with the lens, whereby display with high immersion can be achieved

Further, as shown in fig. 18A, the display device 10 according to one embodiment of the present invention can have a structure in which the light receiving element 62, the cell array CA, and the arithmetic circuit 40 are stacked, and therefore can perform arithmetic processing with excellent arithmetic efficiency using a minute current output from the light receiving element 62 as input data. Further, since the display device 10 may have a structure in which the light receiving unit 14 is disposed in a position close to the display unit 13, the user's eyes and/or the periphery thereof can be photographed while the user's eyes are looking at the image. In addition, the cells IM in the cell array CA can hold analog data written according to minute currents. The arithmetic circuit 40 that performs product-sum arithmetic processing using minute currents can perform arithmetic operation with excellent arithmetic efficiency.

Fig. 18B shows a block diagram of each structure of layers 20, 50, and 60 in fig. 18A. The driving circuit 30 in the layer 20 outputs signals GS, DS (e.g., GS is a signal for driving a gate line, DS is a signal corresponding to image data) for controlling the pixel circuit portion 51P in the layer 50. The pixel circuit portion 51P in the layer 50 outputs a current I corresponding to image data to the light emitting element 61 (not shown) included in the display portion 13 in the layer 60 _EL . The display portion 13 in the layer 60 includesThe light-emitting element 61 (not shown) generates a current I _EL And emits light so that the user can see the image.

In the block diagram shown in fig. 18B, a light receiving element 62 (not shown) included in the light receiving section 14 in the layer 60 outputs a current I flowing by capturing an image around the display device 10 _PS . Current I _PS Is output to the cell array CA in the layer 50 and the arithmetic circuit 40 in the layer 20. The cell array CA in the layer 50 depends on the current I from the light receiving section 14 in the layer 60 _PS And the control signal of the operation circuit 40 in the layer 20 outputs a signal D corresponding to the product-sum operation to the operation circuit 40 in the layer 20 _MAC . The arithmetic circuit 40 in the layer 20 may perform an inference process based on the neural network ANN.

The layer 50 provided on the layer 20 may have a structure of more than two layers. For example, as shown in fig. 19A, layers 50_1, 50_2 including transistors as OS transistors may be employed. The layer 20 may have a structure of two or more layers by a bonding process or the like. For example, as shown in fig. 19B, layers 20_1 and 20_2 including Si transistors may be used instead of the layer 50 and the layer 20. The layers 20_1 and 20_2 including Si transistors can be bonded together by connecting electrodes (not shown) provided with TSVs (Through Silicon Via: through silicon vias) using the micro bumps 23 or the like.

< three-dimensional Structure of sensor and semiconductor device >

Next, a three-dimensional structure in the case where a semiconductor device capable of performing calculation using the output of a sensor such as a light receiving element provided in a part of a display device is provided in the display device 10 will be described. The display device 10 shown in fig. 20 includes a layer PDL, a layer ERL, a layer CCL, and a layer PHL. The layer CCL and the layer PHL are provided with the respective structures of the semiconductor device MAC1 or MAC 1A. The circuit PTC disposed in the layer CCL includes circuits PTR [1] to PTR [ m ].

The circuit PTR 1 has a function of bringing the wiring EIL 1 and the wiring XCL 1 into a conductive state or a nonconductive state. Similarly, the circuit PTR [ i ] has a function of bringing the wiring EIL [ i ] and the wiring XCL [ i ] into a conductive state or a non-conductive state, and the circuit PTR [ m ] has a function of bringing the wiring EIL [ m ] and the wiring XCL [ m ] into a conductive state or a non-conductive state. That is, the circuits PTR [1] to PTR [ m ] are all used as switching elements.

Note that in fig. 20, the display device 10 is shown in a three-dimensional structure, and therefore arrows indicating the x direction, the y direction, and the z direction are attached to fig. 20. Note that, as an example, the x direction, the y direction, and the z direction here denote directions orthogonal to each other. In this specification and the like, one of the x direction, the y direction, and the z direction is sometimes referred to as "first direction". In addition, the other one is sometimes referred to as "second direction". In addition, the remaining one is sometimes referred to as "third direction".

The layer CCL is located above the layer PHL, the layer ERL is located above the layer CCL, and the layer PDL is located above the layer ERL. That is, a layer PHL, a layer CCL, a layer ERL, and a layer PDL are sequentially stacked in the z direction.

As an example, the layer PDL includes a sensor array SCA. The sensor array SCA includes a plurality of electrodes and a plurality of sensors, and in fig. 20, as an example, electrodes DNK [1] to DNK [ m ] (where m is an integer of 1 or more) are shown as a plurality of electrodes, and sensors SNC [1] to SNC [ m ] are shown as a plurality of sensors. In addition, as an example, m electrodes DNK are arranged in a matrix on the layer PDL, and the sensors SNC 1 to SNC m are provided on the respective electrodes DNK 1 to DNK m.

Note that, in the layer PDL shown in fig. 20, the symbol electrode DNK [1], the electrode DNK [ i ] (where i is an integer of 1 to m) and the electrode DNK [ m ] are selected and shown from the electrode DNK [1] to the electrode DNK [ m ]. In the layer PDL shown in fig. 20, a symbol sensor SNC [1], a sensor SNC [ i ], and a sensor SNC [ m ] are selected and shown from the sensors SNC [1] to SNC [ m ].

The sensors SNC 1 to SNC m have a function of converting sensed information into an amount of current and outputting the amount of current. In addition, the electrodes DNK 1 to DNK m are used as terminals for outputting the current amounts in the sensors SNC 1 to SNC m, respectively. As the sensor SNC, for example, a light receiving element can be used. By using light receiving elements as the sensors SNC [1] to SNC [ m ], the layer PDL can function as a part of the image sensor. In this case, the light intensity range that the light receiving element can sense preferably includes the intensity of light irradiated in the environment using the light receiving element. Fig. 20 shows a display device 10 using a sensor SNC including a photodiode PD as a light receiving element. As the photodiode PD, an organic light emitting diode which can be provided in the same layer as the light emitting element is preferably used.

The circuit configuration of the sensor SNC [ i ] may be such that one of the input terminal and the output terminal of the photodiode PD in the sensor SNC [ i ] is electrically connected to the wiring EIL [ i ] via the electrode DNK [ i ]. The circuit configuration of the sensor SNC [ i ] may be configured to include a switch or the like for cutting off power supply to suspend the sensor SNC [ i ]. Further, a light emitting element (not shown) for display may be provided in the same layer as the sensor SNC [ i ].

The layer ERL includes wirings EIL [1] to EIL [ m ]. Note that as the layer ERL shown in fig. 20, a symbol wiring EIL [1], a wiring EIL [ i ], a wiring EIL [ m ] are selected and shown from the wiring EIL [1] to the wiring EIL [ m ].

The wiring EIL 1 is electrically connected to the electrode DNK 1 of the layer PDL. The wiring EIL [ i ] is electrically connected to the electrode DNK [ i ] of the layer PDL. The wiring EIL [ m ] is electrically connected to the electrode DNK [ m ] of the layer PDL.

Specifically, for example, in a plan view of the display device 10 (along a line of sight in a direction opposite to an arrow of a z-axis in fig. 20), plugs (sometimes referred to as contact holes or the like) or the like are provided at portions where the electrodes DNK [1] to DNK [ m ] intersect the wirings EIL [1] to EIL [ m ], respectively, to electrically connect each of the electrodes DNK [1] to DNK [ m ] and each of the wirings EIL [1] to EIL [ m ].

Therefore, the wirings EIL [1] to EIL [ m ] are used as the following paths: when each of the sensors SNC 1 to SNC m senses information, a current of an amount corresponding to the information output from each of the sensors SNC 1 to SNC m flows.

The layer PDL preferably has a structure that enables each of the sensors SNC [1] to SNC [ m ] to sense sequentially and enables a current to flow sequentially through each of the wirings EIL [1] to EIL [ m ]. In this case, for example, a configuration in which signal lines for selecting the sensors SNC 1 to SNC m are provided as the layer PDL may be adopted, and the sensors SNC 1 to SNC m may be operated sequentially by sequentially transmitting signals or the like to the signal lines.

In addition, in the case where the sensors SNC [1] to SNC [ m ] are light receiving elements constituted by photodiodes or the like, for example, in the layer PDL of the display device 10, the output terminal (cathode) of the photodiodes may be electrically connected to the electrode DNK. Alternatively, as a structural example of the layer PDL of the other display device 10, an input terminal (anode) of the photodiode may be electrically connected to the electrode DNK.

In addition, in the case where the sensors SNC 1 to SNC m are light receiving elements composed of photodiodes or the like, for example, filters for irradiating light to only one sensor SNC out of the sensors SNC 1 to SNC m are provided, whereby the sensors SNC 1 to SNC m can be operated sequentially. Since the number of sensors SNC is m, the number of filters for irradiating light to only one sensor SNC is m. In addition, when filters that do not irradiate light to any of the sensors SNC 1 to SNC m are prepared in addition, the filters are m+1 types. When the layer PDL is irradiated with light, the sensors SNC 1 to SNC m can be sequentially sensed by sequentially switching the filters.

In the case where the sensors SNC 1 to SNC m are light receiving elements such as photodiodes, the display device 10 may be configured to emit light to each of the sensors SNC 1 to SNC m. By being configured to irradiate light individually, light can be sequentially irradiated to each of the sensors SNC 1 to SNC m, and the sensors SNC 1 to SNC m can be sequentially sensed.

As an example, the layer CCL includes a circuit PTC and a cell array CA. In addition, as an example, the layer PHL includes a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2. As shown in fig. 20, the cell array CA may be located above a circuit XCS, a circuit WCS, a circuit WSD, a circuit ITS, a circuit SWS1, and a circuit SWS2, which are peripheral circuits of the cell array CA.

The cell array CA includes a plurality of cells. The plurality of cells in the cell array CA have a function of holding weight data for performing product-sum operation, a function of performing multiplication operation of the weight data and input data, and the like.

The cell array CA is electrically connected to a plurality of wirings. Specifically, for example, fig. 20 shows a structure in which the cell array CA is electrically connected to the wirings WCL [1] to WCL [ n ] (where n is an integer of 1 or more), the wirings WSL [1] to WSL [ m ], and the wirings XCL [1] to XCL [ m ]. In particular, the wirings WCL [1] to WCL [ n ] are used as wirings for electrically connecting the circuit SWS1 and the circuit SWS2. That is, it can be said that the circuit SWS1 is electrically connected to the circuit SWS2 through the cell array CA by using the wirings WCL [1] to WCL [ n ]. Note that in fig. 20, the wirings WSL [1] to WSL [ m ], XCL [1] to XCL [ m ], and WCL [1] to WCL [ n ] all extend in the z direction.

In addition, one of the plurality of cells of the cell array CA is electrically connected to any one of the wirings WCL [1] to WCL [ n ], any one of the wirings WSL [1] to WSL [ m ], and any one of the wirings XCL [1] to XCL [ m ]. Therefore, the plurality of cells in the cell array CA are arranged in a matrix of at least m rows and n columns.

The circuit WCS has a function of supplying an amount of current corresponding to the weight data to the wirings WCL [1] to WCL [ n ]. Therefore, the circuit WCS is electrically connected to the wirings WCL [1] to WCL [ n ] through the circuit SWS 1.

The circuit SWS1 has a function of bringing the circuit WCS into a conductive state or a nonconductive state with the wiring WCL [1] to the wiring WCL [ n ] respectively.

The circuit WSD is electrically connected to the wirings WSL [1] to WSL [ m ]. The circuit WSD has a function of supplying a predetermined signal to the wirings WSL [1] to WSL [ m ] to select a row of the memory cells CA to be weight data written when weight data is written to the cells included in the cell array CA. That is, the wirings WSL [1] to WSL [ m ] are used as write word lines.

The circuit XCS is electrically connected to the wiring XCL [1] to the wiring XCL [ m ]. The circuit XCS has a function of causing a current of an amount corresponding to reference data described later or a current of an amount corresponding to input data to flow through the wirings XCL [1] to XCL [ m ].

The circuit PTC includes circuits PTR 1 to PTR m. A first terminal of the circuit PTR 1 is electrically connected to the wiring XCL 1, a first terminal of the circuit PTR i is electrically connected to the wiring XCL i, and a first terminal of the circuit PTR m is electrically connected to the wiring XCL m.

In addition, a second terminal of the circuit PTR [1] is electrically connected to the wiring EIL [1] of the layer ERL, a second terminal of the circuit PTR [ i ] is electrically connected to the wiring EIL [ i ] of the layer ERL, and a second terminal of the circuit PTR [ m ] is electrically connected to the wiring EIL [ m ] of the layer ERL.

Specifically, for example, in a plan view of the display device 10, a plug or the like is provided at a portion where the second terminal of each of the circuits PTR [1] to PTR [ m ] crosses each of the wirings EIL [1] to EIL [ m ], and the second terminal of each of the circuits PTR [1] to PTR [ m ] is electrically connected to each of the wirings EIL [1] to EIL [ m ].

The circuit ITS has a function of obtaining the amount of current flowing through the wirings WCL [1] to WCL [ n ], and outputting the result corresponding to the amount of current to the wirings OL [1] to OL [ n ]. Thus, the circuit ITS is electrically connected to each of the wirings WCL [1] to WCL [ n ] through the circuit SWS 2. In addition, the circuit ITS is electrically connected to each of the wirings OL [1] to OL [ n ].

The circuit SWS2 has a function of bringing the circuit ITS and each of the wirings WCL [1] to WCL [ n ] into a conductive state or a non-conductive state.

As an example, the wirings EIL [1] to EIL [ m ] in the layer ERL of fig. 20 preferably extend in the x-direction. That is, for example, the direction in which the wirings EIL [1] to EIL [ m ] extend along the line of sight in the y direction is preferably substantially parallel to the wirings XCL [1] to XCL [ m ], and more preferably parallel. In addition, for example, in a plan view, the wirings EIL [1] to EIL [ m ] are preferably substantially parallel, and more preferably parallel, to the wirings XCL [1] to XCL [ m ] in the layer CCL.

As described above, by using the display device 10 shown in fig. 20, the arrangement portion of the sensor array SCA on the display device including the arithmetic circuit (layer CCL) can be determined almost freely. Thus, for example, the sensor array SCA may be arranged at or near the center of the display device in a plan view. In addition, the layout of the arithmetic circuit in the layer CCL is not dependent on the arrangement portion of the sensor array SCA, and thus the degree of freedom in the layout of the arithmetic circuit and wiring and the like around the arithmetic circuit can be improved.

< three-dimensional Structure of drive Circuit, pixel Circuit, and light-emitting element >

Fig. 21A and 21B show a configuration example of the pixel circuit 51 shown in fig. 18A and the light-emitting element 61 connected to the pixel circuit 51. Fig. 21A is a diagram showing connection of elements, and fig. 21B is a diagram schematically showing the upper and lower relationship of the layer 20 including the driving circuit 30, the layer 50 including the plurality of transistors included in the pixel circuit 51, and the layer 60 including the light emitting element 61.

The pixel circuit 51 shown as an example in fig. 21A and 21B includes a transistor 52A, a transistor 52B, a transistor 52C, and a capacitor 53. Note that the number of transistors, the number of capacitors, and the electrical connection between elements included in the pixel circuit 51 are not limited to those shown in fig. 21A and 21B, and other structures may be employed. The transistors 52A, 52B, and 52C may be formed using OS transistors. Each of the OS transistors of the transistors 52A, 52B, and 52C preferably includes a back gate electrode, and may have a structure in which the same signal as the gate electrode is supplied to the back gate electrode or a structure in which a signal different from the gate electrode is supplied to the back gate electrode.

The transistor 52B includes a gate electrode electrically connected to the transistor 52A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to the wiring ANO. The wiring ANO is a wiring for supplying a potential for supplying current to the light emitting element 61.

The transistor 52A includes a first terminal electrically connected to the gate electrode of the transistor 52B, a second terminal electrically connected to the wiring SL serving as a source line, and a gate electrode. The transistor 52A has a function of controlling a conductive state or a nonconductive state according to the potential of the wiring GL1 serving as a gate line.

The transistor 52C includes a first terminal electrically connected to the wiring V0, a second terminal electrically connected to the light-emitting element 61, and a gate electrode. The transistor 52C has a function of controlling a conductive state or a nonconductive state according to the potential of the wiring GL2 serving as a gate line. The wiring V0 is a wiring for supplying a reference potential, and is a wiring for outputting a current flowing through the pixel circuit 51 to the driving circuit 30 or the arithmetic circuit 40.

The capacitor 53 includes a conductive film electrically connected to the gate electrode of the transistor 52B and a conductive film electrically connected to the second electrode of the transistor 52C.

The light emitting element 61 includes a first electrode electrically connected to the first electrode of the transistor 52B and a second electrode electrically connected to the wiring VCOM. The wiring VCOM is a wiring for supplying a potential for supplying current to the light-emitting element 61.

Thereby, the intensity of light emitted by the light emitting element 61 can be controlled in accordance with an image signal supplied to the gate electrode of the transistor 52B. Further, unevenness in the gate-source voltage of the transistor 52B can be suppressed in accordance with the reference potential of the wiring V0 supplied through the transistor 52C.

Further, a current value usable for setting of a pixel parameter may be output from the wiring V0. More specifically, the wiring V0 may be used as a monitor line that outputs the current flowing through the transistor 52B or the current flowing through the light emitting element 61 to the outside. The current output to the wiring V0 is converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, the digital signal may be converted by an a-D converter or the like and output to the arithmetic circuit 40 or the like.

The light-emitting element described in one embodiment of the present invention is a self-luminous light-emitting element such as an organic EL element (also referred to as an OLED (Organic Light Emitting Diode: organic light-emitting diode)). The light-emitting element electrically connected to the pixel circuit may be a self-light-emitting element such as an LED (Light Emitting Diode: light-emitting diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode: quantum dot light-emitting diode), or a semiconductor laser.

In the structure shown in fig. 21B, the wiring electrically connecting the pixel circuit 51 and the driving circuit 30 can be shortened, so that the wiring resistance of the wiring can be reduced. Accordingly, data writing can be performed at high speed, so that the display device 10 can be driven at high speed. Thus, even if the pixel circuit 51 in the display device 10 is increased, a sufficient frame period can be ensured, and the pixel density of the display device 10 can be increased. In addition, by increasing the pixel density of the display device 10, the sharpness of an image displayed on the display device 10 can be improved. For example, the pixel density of the display device 10 may be 1000ppi or more, 5000ppi or more, or 7000ppi or more. Accordingly, the display device 10 may be, for example, an AR or VR display device, and may be suitably used for an electronic device in which a display unit such as a head mount display is located close to a user.

The layers 20, 50, and 60 shown in fig. 21A and 21B may be provided with the arithmetic circuit 40, the cell array CA, and the photodiode PD as the light receiving element described in embodiment 3. Accordingly, the display device 10 may have a structure including an arithmetic circuit and a driving circuit, a pixel circuit and a cell array, and a light emitting element and a light receiving element.

As described above, the display device 10 according to one embodiment of the present invention can have a structure in which the light emitting element 61, the pixel circuit 51, and the driving circuit 30 are stacked, and thus can greatly increase the aperture ratio (effective display area ratio) of the pixel. Further, the pixel circuits 51 can be arranged at extremely high density, whereby the pixels can be made extremely high in definition. Such a display device 10 is extremely high in definition, and is therefore suitable for VR devices such as head-mounted displays and glasses-type AR devices. For example, since the display device 10 has a display portion with extremely high definition, in a structure in which the display portion of the display device 10 is viewed through an optical member such as a lens, a user cannot see pixels even if the display portion is enlarged with the lens, whereby display with high immersion can be realized.

Further, since the display device 10 according to one embodiment of the present invention has a structure in which the light receiving element 62, the cell array CA, and the arithmetic circuit 40 are stacked, arithmetic processing with excellent arithmetic efficiency using a minute current output from the light receiving element 62 as input data can be performed. Further, since the display device 10 may have a structure in which the light receiving unit 14 is disposed in a position close to the display unit 13, the user's eyes and/or the periphery thereof can be photographed while the user's eyes are looking at the image. In addition, the cells IM in the cell array CA can hold analog data written according to minute currents. The arithmetic circuit 40 that performs product-sum arithmetic processing using minute currents can perform arithmetic operation with excellent arithmetic efficiency.

< schematic top plan view of light-emitting element and schematic sectional view thereof >

Fig. 22A is a schematic top view showing an example of a structure in which a light emitting element and a light receiving element are arranged in one pixel in the display device 10 according to one embodiment of the present invention. The display device 10 includes a plurality of light emitting elements 61R that emit red light, a plurality of light emitting elements 61G that emit green light, a plurality of light emitting elements 61B that emit blue light, and a plurality of light receiving elements 62. In fig. 22A, in order to easily distinguish the light-emitting elements 61, a symbol R, G, B is attached to the light-emitting region of each light-emitting element 61. The PD is attached to the light receiving region of each light receiving element 62.

The light emitting elements 61R, 61G, 61B, and the light receiving elements 62 are each arranged in a matrix. Fig. 22A shows an example in which the light emitting elements 61R, 61G, and 61B are arranged in the X direction and the light receiving element 62 is arranged thereunder. Fig. 22A shows an example of a structure in which light emitting elements 61 that emit light of the same color are arranged in the Y direction intersecting the X direction. In the display device 10 shown in fig. 22A, for example, the pixel 80 may be constituted by a sub-pixel including the light emitting element 61R, a sub-pixel including the light emitting element 61G, and a sub-pixel including the light emitting element 61B, which are arranged in the X direction, and a sub-pixel including the light receiving element 62 provided under these sub-pixels.

As the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B, an EL element such as an OLED or a QLED is preferably used. Examples of the light-emitting substance included in the EL element include: a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), an inorganic compound (quantum dot material, etc.), a substance that exhibits thermally activated delayed fluorescence (Thermally activated delayed fluorescence: TADF) material), or the like. As the TADF material, a material having a thermal equilibrium state between a singlet excited state and a triplet excited state may be used. The light emission lifetime (excitation lifetime) of such TADF material is short, so that the efficiency degradation in the high-luminance region of the light-emitting element can be suppressed.

As the light receiving element 62, for example, a pn-type or pin-type photodiode can be used. The light receiving element 62 is used as a photoelectric conversion element that detects light incident on the light receiving element 62 and generates electric charges. The amount of charge generated depends on the amount of light incident.

In particular, as the light receiving element 62, an organic photodiode having a layer containing an organic compound is preferably used. The organic photodiode is easily thinned, lightened, and enlarged in area, and has a high degree of freedom in shape and design, so that it can be applied to various display devices.

In one embodiment of the present invention, an organic EL element is used as the light emitting element 61, and an organic photodiode is used as the light receiving element 62. The organic EL element and the organic photodiode can be formed on the same substrate. Therefore, the organic photodiode can be mounted in a display device using an organic EL element. In addition, when the organic EL elements and the organic photodiodes are to be separated from each other, a photolithography method is preferably used. Thus, gaps between the light emitting elements, between the organic photodiodes, and between the light emitting elements and the organic photodiodes can be reduced, and a display device having a high aperture ratio can be realized, for example, as compared with when a shadow mask such as a metal mask is used.

Fig. 22A shows a common electrode 81 and a connection electrode 82. Here, the connection electrode 82 is electrically connected to the common electrode 81. The connection electrode 82 is provided outside the display portion in which the light emitting element 61 and the light receiving element 62 are arranged. In fig. 22A, a common electrode 81 having a region overlapping with the light emitting element 61, the light receiving element 62, and the connection electrode 82 is shown by a broken line.

The connection electrode 82 may be disposed along the outer circumference of the display portion. For example, the display unit may be provided along one side of the outer periphery of the display unit, or may be provided across two or more sides of the outer periphery of the display unit. That is, when the top surface of the display portion is rectangular, the top surface of the connection electrode 82 may be in the form of a band, an L-shape, a "" shape (bracket shape), a quadrangle, or the like.

Fig. 22B is a schematic top view showing a structural example of the display device 10, and is also a modified example of the display device 10 shown in fig. 22A. The display device 10 shown in fig. 22B is different from the display device 10 shown in fig. 22A in that a light emitting element 61IR that emits infrared light is included. The light emitting element 61IR may emit near infrared light (light having a wavelength of 750nm or more and 1300nm or less), for example.

In the example shown in fig. 22B, the light-emitting elements 61R, 61G, and 61B, and 61IR are arranged in the X direction and the light-receiving element 62 is arranged thereunder. The light receiving element 62 has a function of detecting infrared light.

Fig. 23A is a sectional view corresponding to the chain line A1-A2 in fig. 22A, and fig. 23B is a sectional view corresponding to the chain line B1-B2 in fig. 22A. In addition, fig. 23C is a sectional view corresponding to the chain line C1-C2 in fig. 22A, and fig. 23D is a sectional view corresponding to the chain line D1-D2 in fig. 22A. The light-emitting element 61R, the light-emitting element 61G, the light-emitting element 61B, and the light-receiving element 62 are provided over the substrate 83. In addition, when the display device 10 includes the light-emitting element 61IR, the light-emitting element 61IR is provided over the substrate 83.

In the present specification and the like, for example, when "B on a" or "B under a" is described, it is not necessarily required to have a region where a and B are in contact.

Fig. 23A shows a cross-sectional structure example of the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B. Fig. 23B shows an example of a cross-sectional structure of the light receiving element 62.

The light-emitting element 61R includes a pixel electrode 84R, a hole-injecting layer 85R, a hole-transporting layer 86R, a light-emitting layer 87R, an electron-transporting layer 88R, a common layer 89, and a common electrode 81. The light-emitting element 61G includes a pixel electrode 84G, a hole-injecting layer 85G, a hole-transporting layer 86G, a light-emitting layer 87G, an electron-transporting layer 88G, a common layer 89, and a common electrode 81. The light-emitting element 61B includes a pixel electrode 84B, a hole-injecting layer 85B, a hole-transporting layer 86B, a light-emitting layer 87B, an electron-transporting layer 88B, a common layer 89, and a common electrode 81. The light receiving element 62 includes a pixel electrode 84PD, a hole transport layer 86PD, a light receiving layer 90, an electron transport layer 88PD, a common layer 89, and a common electrode 81.

Hereinafter, when matters common to the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, and the like are described, they may be referred to as the hole injection layer 85. Note that when matters common to the hole transport layer 86R, the hole transport layer 86G, the hole transport layer 86B, the hole transport layer 86PD, and the like are described, they are sometimes referred to as the hole transport layer 86. Note that when matters common to the light-emitting layers 87R, 87G, 87B and the like are described, they are sometimes referred to as the light-emitting layers 87. Note that when matters common to the electron transport layer 88R, the electron transport layer 88G, the electron transport layer 88B, the electron transport layer 88PD, and the like are described, they are sometimes referred to as the electron transport layer 88.

The common layer 89 is used as an electron injection layer in the light emitting element 61. On the other hand, the common layer 89 is used as an electron transport layer in the light receiving element 62. Thus, the light receiving element 62 may not include the electron transport layer 88PD.

The hole injection layer 85, the hole transport layer 86, the electron transport layer 88, and the common layer 89 can be said to be functional layers.

The pixel electrode 84, the hole injection layer 85, the hole transport layer 86, the light emitting layer 87, and the electron transport layer 88 may be provided separately for each element. The common layer 89 and the common electrode 81 are provided across the light emitting element 61R, the light emitting element 61G, the light emitting element 61B, and the light receiving element 62.

The light emitting element 61 and the light receiving element 62 include a hole blocking layer and an electron blocking layer in addition to the layers shown in fig. 23A. The light-emitting element 61 and the light-receiving element 62 may include a layer containing a bipolar substance (a substance having high electron-transport property and hole-transport property) or the like.

A gap is provided between the common layer 89 and an insulating layer 92 described later. This can suppress contact between the common layer 89 and the side surface of the light-emitting layer 87, the side surface of the light-receiving layer 90, the side surface of the hole-transporting layer 86, and the side surface of the hole-injecting layer 85. This suppresses short-circuiting in the light emitting element 61 and short-circuiting in the light receiving element 62.

The shorter the distance between the light emitting layers 87, for example, the easier the above-mentioned voids are formed. For example, when the distance is set to 1 μm or less, preferably 500nm or less, more preferably 200nm or less, 100nm or less, 90nm or less, 70nm or less, 50nm or less, 30nm or less, 20nm or less, 15nm or less, or 10nm or less, the above-mentioned voids can be suitably formed.

Fig. 23A shows a structure in which the pixel electrode 84, the hole injection layer 85, the hole transport layer 86, the light emitting layer 87, the electron transport layer 88, the common layer 89 (electron injection layer), and the common electrode 81 are provided in this order from below in the light emitting element 61. Fig. 23B shows a structure in which the pixel electrode 84PD, the hole transport layer 86PD, the light receiving layer 90, the electron transport layer 88PD, the common layer 89, and the common electrode 81 are provided in this order from below in the light receiving element 62, but one embodiment of the present invention is not limited thereto. For example, the light-emitting element 61 may be provided with a pixel electrode, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, a hole injection layer, and a common electrode in this order from below, and the light-receiving element 62 may be provided with a pixel electrode, an electron transport layer, a light-receiving layer, a hole transport layer, and a common electrode in this order from below. In this case, the hole injection layer included in the light emitting element 61 may be used as a common layer, which may be provided between the hole transport layer included in the light receiving element 62 and the common electrode. In addition, in the light emitting element 61, the electron injection layer may be separated for each element.

The case where the electron transport layer is provided above the hole transport layer will be described below, but for example, by changing "electron" to "hole" or "hole" to "electron" or the like, the following description may be used even when the electron transport layer is provided below the hole transport layer.

The hole injection layer is a layer containing a material having high hole injection property, which injects holes from the anode to the hole transport layer. Examples of the material having high hole injection property include an aromatic amine compound and a composite material containing a hole-transporting material and an acceptor material (electron acceptor material).

The hole transport layer is a layer that transports holes injected from the anode to the light emitting layer through the hole injection layer. The hole transport layer is a layer containing a hole transporting material. As the hole transporting material, a material having a hole mobility of 10 is preferably used ^-6 cm ² Materials above/Vs. Note that as long as the hole transport property is higher than the electron transport property, substances other than the above may be used. As the hole transporting material, a material having high hole transporting property such as a pi-electron rich heteroaromatic compound (for example, a carbazole derivative, a thiophene derivative, a furan derivative, or the like), an aromatic amine (a compound having an aromatic amine skeleton), or the like is preferably used.

The electron transport layer is a layer that transports electrons injected from the cathode to the light emitting layer through the electron injection layer. The electron transport layer is a layer containing an electron transport material. As the electron transporting material, an electron mobility of 1X 10 is preferably used ^-6 cm ² Materials above/Vs. Note that as long as the electron transport property is higher than the hole transport property, substances other than the above may be used. Examples of the electron-transporting material include materials having high electron-transporting properties such as a metal complex containing a quinoline skeleton, a metal complex containing a benzoquinoline skeleton, a metal complex containing an oxazole skeleton, a metal complex containing a thiazole skeleton, an oxadiazole derivative, a triazole derivative, an imidazole derivative, an oxazole derivative, a thiazole derivative, a phenanthroline derivative, a quinoline derivative containing a quinoline ligand, a benzoquinoline derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a pyridine derivative, a bipyridine derivative, a pyrimidine derivative, and a nitrogen-containing heteroaromatic compound.

The electron injection layer is a layer containing a material having high electron injection property, which injects electrons from the cathode to the electron transport layer. As the material having high electron injection properties, alkali metal, alkaline earth metal, or a compound containing the above can be used. As the material having high electron injection properties, a composite material containing an electron-transporting material and a donor material (electron-donor material) may be used.

Examples of the electron injection layer include lithium, cesium, ytterbium, lithium fluoride (LiF), cesium fluoride (CsF), and calcium fluoride (CaF) ₂ ) 8- (hydroxyquinoxaline) lithium (abbreviation: liq), lithium 2- (2-pyridyl) phenoxide (abbreviation: liPP), lithium 2- (2-pyridyl) -3-hydroxypyridine (abbreviation: liPPy), lithium 4-phenyl-2- (2-pyridyl) phenol (abbreviation: liPPP), lithium oxide (LiO _x ) Alkali metal, alkaline earth metal, cesium carbonate, or the like, or a compound thereof.

Alternatively, a material having electron-transporting property may be used as the electron injection layer. For example, a compound having an unshared electron pair and having an electron-deficient heteroaromatic ring may be used for a material having electron-transporting properties. Specifically, a compound having at least one of a pyridine ring, a diazine ring (pyrimidine ring, pyrazine ring, pyridazine ring), and a triazine ring can be used.

Further, the lowest unoccupied molecular orbital (LUMO: lowest Unoccupied Molecular Orbital) of the organic compound having an unshared electron pair is preferably not less than-3.6 eV and not more than-2.3 eV. In general, the highest occupied molecular orbital (HOMO: highest Occupied Molecular Orbital) energy level and LUMO energy level of an organic compound can be estimated using CV (cyclic voltammetry), photoelectron spectroscopy, light absorption spectroscopy, reverse electron spectroscopy, or the like.

For example, as the organic compound having an unshared electron pair, 4, 7-diphenyl-1, 10-phenanthroline (abbreviated as BPhen), 2, 9-bis (naphthalen-2-yl) -4, 7-diphenyl-1, 10-phenanthroline (abbreviated as NBPhen), and diquinoxalino [2,3-a:2',3' -c ] phenazine (abbreviated as HATNA), 2,4, 6-tris [3' - (pyridin-3-yl) biphenyl-3-yl ] -1,3, 5-triazine (abbreviated as TmPPyTz), and the like. In addition, NBPhen has a high glass transition temperature (Tg) as compared with BPhen, and thus has high heat resistance.

The light-emitting layer is a layer containing a light-emitting substance. The light emitting layer may comprise one or more light emitting substances. As the light-emitting substance, a substance that emits light of blue, violet, bluish violet, green, yellowish green, yellow, orange, red, or the like is suitably used. Further, as the light-emitting substance, a substance that emits near infrared light may be used.

Examples of the luminescent material include a fluorescent material, a phosphorescent material, a TADF material, and a quantum dot material.

Examples of the fluorescent material include pyrene derivatives, anthracene derivatives, triphenylene derivatives, fluorene derivatives, carbazole derivatives, dibenzothiophene derivatives, dibenzofuran derivatives, dibenzoquinoxaline derivatives, quinoxaline derivatives, pyridine derivatives, pyrimidine derivatives, phenanthrene derivatives, naphthalene derivatives, and the like.

Examples of the phosphorescent material include an organometallic complex (particularly iridium complex) having a 4H-triazole skeleton, a 1H-triazole skeleton, an imidazole skeleton, a pyrimidine skeleton, a pyrazine skeleton or a pyridine skeleton, an organometallic complex (particularly iridium complex) having a phenylpyridine derivative having an electron-withdrawing group as a ligand, a platinum complex, a rare earth metal complex, and the like.

The light-emitting layer may contain one or more organic compounds (host material, auxiliary material, etc.) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of the hole transporting material and the electron transporting material described in this embodiment mode can be used. Furthermore, as one or more organic compounds, bipolar materials or TADF materials may also be used.

For example, the light-emitting layer preferably contains a combination of a phosphorescent material, a hole-transporting material that easily forms an exciplex, and an electron-transporting material. By adopting such a structure, light emission of ExTET (Excilex-Triplet Energy Transfer: exciplex-triplet energy transfer) utilizing energy transfer from an Exciplex to a light-emitting substance (phosphorescent material) can be obtained efficiently. Further, by selecting a combination of an exciplex which emits light overlapping with the wavelength of the absorption band on the lowest energy side of the light-emitting substance, energy transfer can be made smooth, and light emission can be obtained efficiently. By adopting the above structure, high efficiency, low voltage driving, and long life of the light emitting element can be achieved at the same time.

The light-emitting layer 87R included in the light-emitting element 61R contains a light-emitting organic compound that emits light having intensity at least in a red wavelength region. The light-emitting layer 87G included in the light-emitting element 61G contains a light-emitting organic compound that emits light having intensity at least in the green wavelength region. The light-emitting layer 87B included in the light-emitting element 61B contains a light-emitting organic compound that emits light having intensity at least in the blue wavelength region. The light receiving layer 90 included in the light receiving element 62 contains, for example, an organic compound having detection sensitivity to a wavelength region of visible light.

A conductive film having transparency to visible light is used as one of the pixel electrode 84 and the common electrode 81, and a conductive film having reflectivity is used as the other. By making the pixel electrode 84 light transmissive and making the common electrode 81 reflective, the display device 10 can be a bottom emission type (bottom emission structure) display device. On the other hand, by making the pixel electrode 84 reflective and the common electrode 81 light transmissive, the display device 10 can be a top-emission type (top-emission structure) display device. Note that by making both the pixel electrode 84 and the common electrode 81 light transmissive, the display device 10 can be a double-sided emission type (double-sided emission structure) display device.

In addition, the light emitting element 61 preferably has an optical microcavity resonator (microcavity) structure. Thereby, light emitted from the light-emitting layer 87 can be resonated between the pixel electrode 84 and the common electrode 81, and light emitted from the light-emitting element 61 can be enhanced.

When the light-emitting element 61 has a microcavity structure, one of the common electrode 81 and the pixel electrode 84 is preferably an electrode having both light transmittance and reflectivity (semi-transparent-semi-reflective electrode), and the other of the common electrode 81 and the pixel electrode 84 is preferably an electrode having reflectivity (reflective electrode). Here, the semi-transmissive-semi-reflective electrode may have a stacked structure of a reflective electrode and an electrode (also referred to as a transparent electrode) having transparency to visible light. Note that the transparent electrode may be referred to as an optical adjustment layer.

The transparent electrode has a light transmittance of 40% or more. For example, a pair of light-emitting elements 61 is preferably usedAn electrode having a transmittance of 40% or more of visible light (light having a wavelength of 400nm or more and less than 750 nm). The reflectance of the semi-transmissive/semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is preferably 1×10 ^-2 And Ω cm or less. When the light-emitting element that emits near-infrared light is used for a display device, the transmittance and reflectance of the electrode for near-infrared light (light having a wavelength of 750nm or more and 1300nm or less) are preferably also within the above-described numerical ranges.

An insulating layer 92 is provided so as to cover the end portion of the pixel electrode 84R, the end portion of the pixel electrode 84G, the end portion of the pixel electrode 84B, and the end portion of the pixel electrode 84 PD. The end of the insulating layer 92 is preferably tapered. If not required, the insulating layer 92 may not be provided.

For example, the hole injection layer 85R, the hole injection layer 85G, the hole injection layer 85B, and the hole transport layer 86PD each have a region in contact with the top surface of the pixel electrode 84 and a region in contact with the surface of the insulating layer 92. In addition, an end portion of the hole injection layer 85R, an end portion of the hole injection layer 85G, an end portion of the hole injection layer 85B, and an end portion of the hole transport layer 86PD are over the insulating layer 92.

As shown in fig. 23A, a gap is provided between the light emitting elements 61 that emit light of different colors, for example, between two light emitting layers 87. In this manner, for example, the light-emitting layer 87R, the light-emitting layer 87G, and the light-emitting layer 87B are preferably provided so as not to contact each other. Thus, it is possible to appropriately prevent current from flowing through the adjacent two light emitting layers 87 to cause unintended light emission. Accordingly, the contrast of the display device 10 can be improved, and thus the display quality of the display device 10 can be improved.

The common electrode 81 is provided with a protective layer 91. The protective layer 91 has a function of preventing impurities such as water from diffusing from above to each light emitting element.

The protective layer 91 may have, for example, a single-layer structure or a stacked-layer structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 91.

In this specification and the like, the "silicon oxynitride film" means a film having an oxygen content greater than a nitrogen content in its composition. By "silicon oxynitride film" is meant a film having a nitrogen content greater than the oxygen content in its composition.

As the protective layer 91, a stacked film of an inorganic insulating film and an organic insulating film may be used. For example, it is preferable to have a structure in which an organic insulating film is sandwiched between a pair of inorganic insulating films. Also, an organic insulating film is preferably used as the planarizing film. Thus, the top surface of the flat organic insulating film can be realized, the coverage of the inorganic insulating film thereon can be improved, and the barrier property can be improved. Further, since the top surface of the protective layer 91 is flat, it is preferable to provide a structure (for example, a color filter, an electrode of a touch sensor, or a lens array) above the protective layer 91, since the influence of the concave-convex shape due to the structure below can be reduced.

Note that when the insulating layer 92 is not provided in fig. 23A and 23B, the interval between light-emitting elements can be shortened. For example, fig. 24A and 24B show diagrams in which the insulating layer 92 is omitted. The region 92R between the light emitting elements in fig. 24A and 24B may include an insulating layer containing an organic material. For example, the region 92R may be filled with an acrylic resin, a polyimide resin, an epoxy resin, an imine resin, a polyamide resin, a polyimide amide resin, a silicone resin, a siloxane resin, a benzocyclobutene resin, a phenol resin, a precursor of these resins, or the like. The region 92R may be filled with a photosensitive resin. As the photosensitive resin, a photoresist may be used. Positive type materials or negative type materials may be used as the photosensitive resin.

Fig. 23C shows an example of a cross-sectional structure of the display device 10 in the Y direction, specifically, a cross-sectional structure of the light emitting element 61R and the light receiving element 62. The light emitting elements 61G and 61B may be arranged in the Y direction similarly to the light emitting element 61R.

Fig. 23D shows a connection portion 93 to which the connection electrode 82 and the common electrode 81 are electrically connected. The connection portion 93 has a common electrode 81 provided on the connection electrode 82 in contact therewith, and a protective layer 91 is provided so as to cover the common electrode 81. Further, an insulating layer 92 is provided so as to cover the end portion of the connection electrode 82.

Structural example of light-emitting element

As shown in fig. 25A, the light-emitting element includes an EL layer 686 between a pair of electrodes (an electrode 672 and an electrode 688). The EL layer 686 may be formed of a plurality of layers such as the layer 4420, the light-emitting layer 4411, and the layer 4430. The layer 4420 may include, for example, a layer containing a substance having high electron injection property (an electron injection layer), a layer containing a substance having high electron transport property (an electron transport layer), or the like. The light-emitting layer 4411 includes, for example, a light-emitting compound. The layer 4430 may include, for example, a layer containing a substance having high hole injection property (a hole injection layer) and a layer containing a substance having high hole transport property (a hole transport layer).

The structure including the layer 4420, the light-emitting layer 4411, and the layer 4430 which are provided between a pair of electrodes can be used as a single light-emitting unit, and the structure of fig. 25A is referred to as a single structure in this specification.

Fig. 25B shows a modified example of the EL layer 686 included in the light-emitting element shown in fig. 25A. Specifically, the light-emitting element shown in FIG. 25B includes a layer 4430-1 over an electrode 672, a layer 4430-2 over a layer 4430-1, a light-emitting layer 4411 over a layer 4430-2, a layer 4420-1 over a light-emitting layer 4411, a layer 4420-2 over a layer 4420-1, and an electrode 688 over a layer 4420-2. For example, when electrode 672 is used as an anode and electrode 688 is used as a cathode, layer 4430-1 is used as a hole injection layer, layer 4430-2 is used as a hole transport layer, layer 4420-1 is used as an electron transport layer, and layer 4420-2 is used as an electron injection layer. Alternatively, when electrode 672 is used as a cathode and electrode 688 is used as an anode, layer 4430-1 is used as an electron injection layer, layer 4430-2 is used as an electron transport layer, layer 4420-1 is used as a hole transport layer, and layer 4420-2 is used as a hole injection layer. By adopting the layer structure shown in fig. 25B, carriers can be efficiently injected into the light-emitting layer 4411, whereby recombination efficiency of carriers within the light-emitting layer 4411 can be improved.

As shown in fig. 25C, a structure in which a plurality of light-emitting layers (light-emitting layers 4411, 4412, and 4413) are provided between the layers 4420 and 4430 is also a modification example of a single structure.

As shown in fig. 25D, a structure in which a plurality of light emitting units (EL layers 686a and 686 b) are connected in series with an intermediate layer (charge generation layer) 4440 interposed therebetween is referred to as a series structure in this specification. In this specification and the like, the structure shown in fig. 25D is referred to as a series structure, but is not limited thereto, and for example, the series structure may be referred to as a stacked structure. By adopting the series structure, a light-emitting element capable of emitting light with high luminance can be realized.

Note that in fig. 25C and 25D, as shown in fig. 25B, the layers 4420 and 4430 may have a stacked structure including two or more layers.

A structure in which light emission colors (here, blue (B), green (G), and red (R)) are formed for each light emitting element is referred to as a SBS (Side By Side) structure.

In addition, when comparing the single structure, the series structure, and the SBS structure, power consumption can be reduced in the order of the SBS structure, the series structure, and the single structure. The SBS structure is preferably employed when power consumption is desired to be reduced. On the other hand, the single structure and the tandem structure are preferable because the manufacturing process is simpler than that of the SBS structure, and thus the manufacturing cost can be reduced or the manufacturing yield can be improved.

The light-emitting element can have a red, green, blue, cyan, magenta, yellow, white, or the like light-emitting color depending on the material constituting the EL layer 686. In addition, when the light emitting element has a microcavity structure, color purity can be further improved.

The white light-emitting element preferably has a structure in which the light-emitting layer contains two or more kinds of light-emitting substances. In order to obtain white light emission, two or more kinds of light-emitting substances each having a complementary color relationship may be selected. For example, by placing the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer in a complementary relationship, a light-emitting element that emits light in white over the entire light-emitting element can be obtained. The same applies to a light-emitting element including three or more light-emitting layers.

The light-emitting layer preferably contains two or more kinds of light-emitting substances each of which emits light such as R (red), G (green), B (blue), Y (yellow), O (orange), and the like. Alternatively, two or more luminescent materials each of which emits light and contains two or more spectral components in R, G, B are preferably contained.

< structural example of light-emitting element and light-receiving element >

The display device according to one embodiment of the present invention has a top emission structure that emits light in a direction opposite to a substrate over which a light-emitting element is formed. In this embodiment mode, a display device having a top emission structure and including a light emitting element and a light receiving element will be described as an example.

Note that in this specification and the like, unless otherwise specified, even in the case of describing a structure including a plurality of elements (light-emitting elements, light-emitting layers, and the like), letters of symbols are omitted when common portions among the elements are described. For example, when a common item is described in the light-emitting layer 383R, the light-emitting layer 383G, or the like, the light-emitting layer 383 may be referred to as a light-emitting layer 383.

The display device 380A shown in fig. 26A includes a light-receiving element 370PD, a light-emitting element 370R that emits light of red (R), a light-emitting element 370G that emits light of green (G), and a light-emitting element 370B that emits light of blue (B).

Each light emitting element is sequentially stacked with a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, a light emitting layer, an electron transport layer 384, an electron injection layer 385, and a common electrode 375. The light-emitting element 370R includes a light-emitting layer 383R, the light-emitting element 370G includes a light-emitting layer 383G, and the light-emitting element 370B includes a light-emitting layer 383B. The light-emitting layer 383R contains a light-emitting substance that emits red light, the light-emitting layer 383G contains a light-emitting substance that emits green light, and the light-emitting layer 383B contains a light-emitting substance that emits blue light.

The light emitting element is an electroluminescent element that emits light to the side of the common electrode 375 by applying a voltage between the pixel electrode 371 and the common electrode 375.

The light receiving element 370PD has a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, an active layer 373, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 stacked in this order.

The light receiving element 370PD is a photoelectric conversion element that receives light incident from outside the display device 380A and converts it into an electrical signal.

In this embodiment mode, a case where the pixel electrode 371 is used as an anode and the common electrode 375 is used as a cathode in both the light-emitting element and the light-receiving element will be described. That is, by driving the light receiving element by applying a reverse bias between the pixel electrode 371 and the common electrode 375, it is possible to detect light incident to the light receiving element to generate electric charges and take out the electric charges in a current manner.

In the display device of this embodiment, an organic compound is used for the active layer 373 of the light receiving element 370PD. The layers other than the active layer 373 of the light receiving element 370PD may have the same structure as the light emitting element. Thus, the light receiving element 370PD can be formed simultaneously with the formation of the light emitting element, by adding a step of forming the active layer 373 in the step of manufacturing the light emitting element. Further, the light emitting element and the light receiving element 370PD may be formed over the same substrate. Therefore, the light receiving element 370PD can be provided in the display device without greatly increasing the manufacturing process.

In the display device 380A, an active layer 373 of the light-receiving element 370PD and a light-emitting layer 383 of the light-emitting element are formed, respectively, and other layers are used in common for the light-receiving element 370PD and the light-emitting element. However, the structures of the light receiving element 370PD and the light emitting element are not limited thereto. The light-receiving element 370PD and the light-emitting element may include other layers formed separately, in addition to the active layer 373 and the light-emitting layer 383. The light receiving element 370PD and the light emitting element preferably use one or more layers (common layers) in common. Thus, the light receiving element 370PD can be provided in the display device without greatly increasing the manufacturing process.

As an electrode on the light extraction side of the pixel electrode 371 and the common electrode 375, a conductive film that transmits visible light is used. Further, as the electrode on the side from which light is not extracted, a conductive film that reflects visible light is preferably used.

The light-emitting element included in the display device of this embodiment mode preferably has an optical microcavity resonator (microcavity) structure. Therefore, one of the pair of electrodes included in the light-emitting element is preferably an electrode (semi-transparent/semi-reflective electrode) having transparency and reflectivity to visible light, and the other is preferably an electrode (reflective electrode) having reflectivity to visible light. When the light emitting element has a microcavity structure, light emission obtained from the light emitting layer can be resonated between the two electrodes, and light emitted from the light emitting element can be enhanced.

Note that the semi-transmissive/semi-reflective electrode may have a stacked structure of a reflective electrode and an electrode (also referred to as a transparent electrode) having transparency to visible light.

The transparent electrode has a light transmittance of 40% or more. For example, in the light-emitting element, an electrode having a transmittance of 40% or more with respect to visible light (light having a wavelength of 400nm or more and less than 750 nm) is preferably used. The reflectance of the semi-transmissive/semi-reflective electrode to visible light is 10% or more and 95% or less, preferably 30% or more and 80% or less. The reflectance of the reflective electrode to visible light is 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes is preferably 1×10 ^-2 And Ω cm or less. When the light-emitting element emits near-infrared light (light having a wavelength of 750nm or more and 1300nm or less), the transmittance or reflectance of these electrodes for near-infrared light preferably satisfies the above numerical range as the transmittance or reflectance for visible light.

The light emitting element includes at least a light emitting layer 383. The light-emitting element may include, as a layer other than the light-emitting layer 383, a layer containing a substance having high hole-injecting property, a substance having high hole-transporting property, a hole-blocking material, a substance having high electron-transporting property, a substance having high electron-injecting property, an electron-blocking material, a bipolar substance (a substance having high electron-transporting property and hole-transporting property), or the like.

For example, the light emitting element and the light receiving element may use one or more of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer in common. The light emitting element and the light receiving element may each have one or more of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer.

The hole injection layer is a layer containing a material having high hole injection property, which injects holes from the anode to the hole transport layer. As the material having high hole injection property, an aromatic amine compound or a composite material containing a hole transporting material and an acceptor material (electron acceptor material) can be used.

In the light-emitting element, the hole-transporting layer is a layer that transports holes injected from the anode to the light-emitting layer through the hole-injecting layer. In the light-receiving element, the hole-transporting layer is a layer that transports holes generated according to light incident into the active layer to the anode. The hole transport layer is a layer containing a hole transporting material. As the hole transporting material, a material having a hole mobility of 1X 10 is preferably used ^-6 cm ² Materials above/Vs. Note that as long as the hole transport property is higher than the electron transport property, substances other than the above may be used. As the hole transporting material, a material having high hole transporting property such as a pi-electron rich heteroaromatic compound (for example, a carbazole derivative, a thiophene derivative, a furan derivative, or the like) or an aromatic amine (a compound having an aromatic amine skeleton) is preferably used.

In the light-emitting element, the electron-transporting layer is a layer that transports electrons injected from the cathode to the light-emitting layer through the electron-injecting layer. In the light receiving element, the electron transport layer is a layer that transports electrons generated based on light incident into the active layer to the cathode. The electron transport layer is a layer containing an electron transport material. As the electron transporting material, an electron mobility of 1X 10 is preferably used ^-6 cm ² Materials above/Vs. Note that as long as the electron transport property is higher than the hole transport property, substances other than the above may be used. Examples of the electron-transporting material include a metal complex containing a quinoline skeleton, a metal complex containing a benzoquinoline skeleton, a metal complex containing an oxazole skeleton, a metal complex containing a thiazole skeleton, an oxadiazole derivative, a triazole derivative, an imidazole derivative, an oxazole derivative, a thiazole derivative, a phenanthroline derivative, a quinoline derivative containing a quinoline ligand, a benzoquinoline derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a pyridine derivative, a bipyridine derivative, a pyrimidine derivative, and a nitrogen-containing heteroaromatic compoundMaterials having high electron-transport properties, such as electron-transporting heteroaromatic compounds.

The light-emitting layer 383 is a layer containing a light-emitting substance. The light emitting layer 383 may contain one or more light emitting substances. As the light-emitting substance, a substance exhibiting a light-emitting color such as blue, violet, bluish violet, green, yellowish green, yellow, orange, or red is suitably used. Further, as the light-emitting substance, a substance that emits near infrared light may be used.

The light-emitting layer 383 may contain one or more organic compounds (host materials, auxiliary materials, and the like) in addition to the light-emitting substance (guest material). As the one or more organic compounds, one or both of the hole transporting material and the electron transporting material described in this embodiment mode can be used. Furthermore, as one or more organic compounds, bipolar materials or TADF materials may also be used.

For example, the light-emitting layer 383 preferably contains a combination of a phosphorescent material, a hole-transporting material that easily forms an exciplex, and an electron-transporting material. By adopting such a structure, light emission of ExTET (Excilex-Triplet Energy Transfer: exciplex-triplet energy transfer) utilizing energy transfer from an Exciplex to a light-emitting substance (phosphorescent material) can be obtained efficiently. Further, by selecting a combination of an exciplex which exhibits luminescence overlapping with the wavelength of the absorption band on the lowest energy side of the light-emitting substance, energy transfer can be made smooth, and luminescence can be obtained efficiently. By adopting the above structure, high efficiency, low voltage driving, and long life of the light emitting element can be achieved at the same time.

Regarding the combination of the materials forming the exciplex, the HOMO level (highest occupied molecular orbital level) of the hole transport material is preferably a value equal to or higher than the HOMO level of the electron transport material. The LUMO level (lowest unoccupied molecular orbital level) of the hole transport material is preferably a value equal to or higher than the LUMO level of the electron transport material. The LUMO and HOMO levels of a material can be determined from electrochemical properties (reduction and oxidation potentials) of the material measured by Cyclic Voltammetry (CV) measurement.

Note that the formation of an exciplex can be confirmed by, for example, the following method: comparing the emission spectrum of the hole transporting material, the emission spectrum of the electron transporting material, and the emission spectrum of a mixed film obtained by mixing these materials, it is explained that an exciplex is formed when a phenomenon is observed in which the emission spectrum of the mixed film shifts to the long wavelength side (or has a new peak on the long wavelength side) than the emission spectrum of each material. Alternatively, when transient PL of the hole transporting material, transient PL of the electron transporting material, and transient PL of a mixed film obtained by mixing these materials are compared, transient PL of the mixed film is observed to have a long lifetime component or a proportion of a delayed component is increased as compared with the transient PL of each material, and transient response such as a difference in the transient PL life is observed, and the formation of an exciplex is described. In addition, the above-described transient PL may be referred to as transient Electroluminescence (EL). In other words, the formation of exciplex can be confirmed by observing the difference in transient response compared with the transient EL of the hole transporting material, the transient EL of the electron transporting material, and the transient EL of the mixed film of these materials.

The active layer 373 includes a semiconductor. Examples of the semiconductor include inorganic semiconductors such as silicon and organic semiconductors containing organic compounds. In this embodiment mode, an example in which an organic semiconductor is used as a semiconductor included in the active layer 373 is described. By using an organic semiconductor, the light-emitting layer 383 and the active layer 373 can be formed by the same method (for example, a vacuum evaporation method), and manufacturing equipment can be used in common, so that this is preferable.

As a material of the n-type semiconductor included in the active layer 373, fullerene (e.g., C ₆₀ 、C ₇₀ Etc.), fullerene derivatives, and the like. Fullerenes have a football shape that is energetically stable. The HOMO level and LUMO level of fullerenes are deep (low). Since fullerenes have a deep LUMO level, electron acceptors (acceptors) are extremely high. In general, when pi electron conjugation (resonance) expands on a plane like benzene, electron donor property (donor property) becomes high. On the other hand, fullerenes have a spherical shape, and although pi electrons widely spread, electron acceptors become high. When the electron acceptors are high, charge separation is caused at high speed and high efficiency, and therefore, the composition is advantageous for a light-receiving element. C (C) ₆₀ 、C ₇₀ All have a broad absorption band in the visible region, especially C ₇₀ Pi-electron conjugated species greater than C ₆₀ Also in the long wavelength region, a broad absorption band is preferable. In addition, examples of fullerene derivatives include [6,6 ]]phenyl-C71-butanoic acid methyl ester (PC 70BM for short) or [6,6 ]]phenyl-C61-butanoic acid methyl ester (abbreviated as PC60 BM) or 1',1",4',4" -tetrahydro-bis [1,4 ]]Methanonaphtho (methanonaphtho) [1,2:2',3',56, 60:2",3"][5，6]Fullerene-C60 (abbreviated as ICBA) and the like.

Examples of the material of the n-type semiconductor include a metal complex having a quinoline skeleton, a metal complex having a benzoquinoline skeleton, a metal complex having an oxazole skeleton, a metal complex having a thiazole skeleton, an oxadiazole derivative, a triazole derivative, an imidazole derivative, an oxazole derivative, a thiazole derivative, a phenanthroline derivative, a quinoline derivative, a benzoquinoline derivative, a quinoxaline derivative, a dibenzoquinoxaline derivative, a pyridine derivative, a bipyridine derivative, a pyrimidine derivative, a naphthalene derivative, an anthracene derivative, a coumarin derivative, a rhodamine derivative, a triazine derivative, a quinone derivative, and the like.

Examples of the p-type semiconductor material contained in the active layer 373 include organic semiconductor materials having an electron donor property such as Copper (II) phthalocyanine (CuPc), tetraphenyldibenzo-bisindenopyrene (DBP), zinc phthalocyanine (Zinc Phthalocyanine: znPc), tin phthalocyanine (SnPc), and quinacridone.

Examples of the p-type semiconductor material include carbazole derivatives, thiophene derivatives, furan derivatives, and compounds having an aromatic amine skeleton. Examples of the material of the p-type semiconductor include naphthalene derivatives, anthracene derivatives, pyrene derivatives, triphenylene derivatives, fluorene derivatives, pyrrole derivatives, benzofuran derivatives, benzothiophene derivatives, indole derivatives, dibenzofuran derivatives, dibenzothiophene derivatives, indolocarbazole derivatives, porphyrin derivatives, phthalocyanine derivatives, naphthalocyanine derivatives, quinacridone derivatives, polyphenylene derivatives, polyparaphenylene derivatives, polyfluorene derivatives, polyvinylcarbazole derivatives, and polythiophene derivatives.

The HOMO level of the organic semiconductor material having electron donating property is preferably shallower (higher) than the HOMO level of the organic semiconductor material having electron accepting property. The LUMO level of the organic semiconductor material having electron donating property is preferably shallower (higher) than that of the organic semiconductor material having electron accepting property.

As the organic semiconductor material having electron accepting property, spherical fullerenes are preferably used, and as the organic semiconductor material having electron donating property, organic semiconductor materials having shapes similar to a plane are preferably used. Molecules of similar shapes have a tendency to aggregate easily, and when the same molecule is aggregated, carrier transport properties can be improved due to the close energy levels of molecular orbitals.

For example, the active layer 373 is preferably formed by co-evaporation of an n-type semiconductor and a p-type semiconductor. Further, an n-type semiconductor and a p-type semiconductor may be stacked to form the active layer 373.

The light-emitting element and the light-receiving element may use a low-molecular compound or a high-molecular compound, and may contain an inorganic compound. The layers constituting the light emitting element and the light receiving element can be formed by a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an inkjet method, a coating method, or the like.

For example, a polymer compound such as poly (3, 4-ethylenedioxythiophene)/poly (styrenesulfonic acid) (PEDOT/PSS) and an inorganic compound such as molybdenum oxide and copper iodide (CuI) can be used as the hole transporting material. Further, an inorganic compound such as zinc oxide (ZnO) may be used as the electron transporting material.

As the active layer 373, poly [ [4, 8-bis [5- (2-ethylhexyl) -2-thienyl ] benzo [1,2-b ] that is used as a donor may be used: 4,5-b' ] dithiophene-2, 6-diyl ] -2, 5-thiophenediyl [5, 7-bis (2-ethylhexyl) -4, 8-dioxo-4 h,8 h-benzo [1,2-c:4,5-c' ] dithiophene-1, 3-diyl ] ] polymer (PBDB-T for short) or PBDB-T derivative. For example, a method of dispersing a receptor material into PBTB-T or a PBDB-T derivative, or the like can be used.

In addition, three or more materials may be mixed in the active layer 373. For example, a third material may be mixed in addition to the n-type semiconductor material and the p-type semiconductor material in order to expand the wavelength region. In this case, the third material may be a low molecular compound or a high molecular compound.

The display device 380B shown in fig. 26B is different from the display device 380A in that the light receiving element 370PD and the light emitting element 370R have the same structure.

The light-receiving element 370PD and the light-emitting element 370R use the active layer 373 and the light-emitting layer 383R in common.

Here, the light receiving element 370PD preferably has the same structure as a light emitting element that emits light having a longer wavelength than the light to be detected. For example, the light receiving element 370PD configured to detect blue light may have the same configuration as one or both of the light emitting element 370R and the light emitting element 370G. For example, the light receiving element 370PD configured to detect green light may have the same configuration as the light emitting element 370R.

By having the same structure for the light-receiving element 370PD and the light-emitting element 370R, the number of deposition steps and the number of masks can be reduced as compared with a structure in which the light-receiving element 370PD and the light-emitting element 370R include layers formed separately. Therefore, the manufacturing process and manufacturing cost of the pixel portion can be reduced.

In addition, compared with the case where the light receiving element 370PD and the light emitting element 370R have a structure including separately formed layers, in the case where the light receiving element 370PD and the light emitting element 370R have the same structure, the margin of misalignment can be reduced. Thus, the aperture ratio of the pixel can be improved and the light extraction efficiency can be improved. Thereby, the lifetime of the light emitting element can be made longer. In addition, the display device can display high brightness. In addition, the definition of the display device can be improved.

The light-emitting layer 383R contains a light-emitting material that emits red light. The active layer 373 includes an organic compound that absorbs light having a wavelength shorter than that of red light (for example, one or both of green light and blue light). The active layer 373 preferably includes an organic compound that does not easily absorb red light and absorbs light having a shorter wavelength than the red light. Thus, red light can be efficiently extracted from the light emitting element 370R, and the light receiving element 370PD can detect light having a wavelength shorter than that of the red light with high accuracy.

In addition, although the light emitting element 370R and the light receiving element 370PD have the same structure in the display device 380B, the light emitting element 370R and the light receiving element 370PD may have optical adjustment layers having different thicknesses.

The display device 380C shown in fig. 27A and 27B includes a light-receiving element 370SR, a light-emitting element 370G, and a light-emitting element 370B which emit red (R) light and have a light-receiving function. The structures of the light-emitting element 370G and the light-emitting element 370B can be referred to the display device 380A and the like.

The light-receiving and emitting element 370SR is formed by stacking a pixel electrode 371, a hole injection layer 381, a hole transport layer 382, an active layer 373, a light-emitting layer 383R, an electron transport layer 384, an electron injection layer 385, and a common electrode 375 in this order. The light-receiving element 370SR has the same structure as the light-emitting element 370R and the light-receiving element 370PD in the display device 380B.

Fig. 27A shows a case where the light-receiving and emitting element 370SR is used as a light-emitting element. Fig. 27A shows an example in which the light emitting element 370B emits blue light, the light emitting element 370G emits green light, and the light receiving and emitting element 370SR emits red light.

Fig. 27B shows a case where the light receiving and emitting element 370SR is used as a light receiving element. Fig. 27B shows an example in which the light receiving and emitting element 370SR receives blue light emitted from the light emitting element 370B and green light emitted from the light emitting element 370G.

The light emitting element 370B, the light emitting element 370G, and the light receiving element 370SR each include a pixel electrode 371 and a common electrode 375. In this embodiment mode, a case where the pixel electrode 371 is used as an anode and the common electrode 375 is used as a cathode will be described as an example. By applying a reverse bias between the pixel electrode 371 and the common electrode 375 to drive the light-receiving and emitting element 370SR, light incident to the light-receiving and emitting element 370SR can be detected and charges generated, whereby it can be extracted as current.

The light-receiving and emitting element 370SR can be said to have a structure in which an active layer 373 is added to the light-emitting element. In other words, the light-emitting element 370SR can be formed simultaneously with the formation of the light-emitting element by adding the step of forming the active layer 373 to the step of manufacturing the light-emitting element. In addition, the light-emitting element and the light-receiving element may be formed over the same substrate. Therefore, the display portion can be provided with one or both of the photographing function and the sensing function without greatly increasing the manufacturing process.

The order of lamination of the light-emitting layer 383R and the active layer 373 is not limited. Fig. 27A and 27B show examples in which an active layer 373 is provided over the hole transport layer 382, and a light-emitting layer 383R is provided over the active layer 373. The order of stacking the light-emitting layer 383R and the active layer 373 may be changed.

The light-emitting and receiving element may not include at least one of the hole injection layer 381, the hole transport layer 382, the electron transport layer 384, and the electron injection layer 385. The light-emitting and receiving element may include other functional layers such as a hole blocking layer and an electron blocking layer.

In the light-receiving and emitting element, a conductive film that transmits visible light is used as an electrode on the side from which light is extracted. Further, a conductive film that reflects visible light is used as an electrode on the side where light is not extracted.

The functions and materials of the layers constituting the light-emitting and light-receiving elements are the same as those of the layers constituting the light-emitting and light-receiving elements, and therefore detailed description thereof is omitted.

Fig. 27C to 27G show examples of the stacked structure of the light-receiving and emitting element.

The light-emitting and receiving element shown in fig. 27C includes a first electrode 377, a hole-injecting layer 381, a hole-transporting layer 382, a light-emitting layer 383R, an active layer 373, an electron-transporting layer 384, an electron-injecting layer 385, and a second electrode 378.

Fig. 27C shows an example in which a light-emitting layer 383R is provided over the hole-transporting layer 382 and an active layer 373 is stacked over the light-emitting layer 383R.

As shown in fig. 27A to 27C, the active layer 373 and the light-emitting layer 383R may also be in contact with each other.

Further, a buffer layer is preferably provided between the active layer 373 and the light-emitting layer 383R. In this case, the buffer layer preferably has hole transport property and electron transport property. For example, a substance having bipolar properties is preferably used as the buffer layer. Alternatively, at least one layer of a hole injection layer, a hole transport layer, an electron injection layer, a hole blocking layer, an electron blocking layer, and the like may be used as the buffer layer. Fig. 27D shows an example in which a hole transport layer 382 is used as a buffer layer.

By providing a buffer layer between the active layer 373 and the light-emitting layer 383R, transfer of excitation energy from the light-emitting layer 383R to the active layer 373 can be suppressed. In addition, the buffer layer may be used to adjust the optical path length (cavity length) of the microcavity structure. Therefore, high light emission efficiency can be obtained from the light-receiving and emitting element including the buffer layer between the active layer 373 and the light-emitting layer 383R.

Fig. 27E shows an example of a stacked structure in which a hole-transporting layer 382-1, an active layer 373, a hole-transporting layer 382-2, and a light-emitting layer 383R are stacked in this order over a hole-injecting layer 381. The hole transport layer 382-2 is used as a buffer layer. The hole transport layer 382-1 and the hole transport layer 382-2 may contain the same material or different materials. In addition, a layer which can be used for the buffer layer described above may be used instead of the hole transport layer 382-2. In addition, the positions of the active layer 373 and the light-emitting layer 383R may be changed.

The light-emitting and receiving element shown in fig. 27F is different from the light-emitting and receiving element shown in fig. 27A in that a hole-transporting layer 382 is not included. In this manner, the light-emitting element may not include at least one of the hole injection layer 381, the hole transport layer 382, the electron transport layer 384, and the electron injection layer 385. The light-emitting and receiving element may include other functional layers such as a hole blocking layer and an electron blocking layer.

The light-emitting and receiving element shown in fig. 27G is different from the light-emitting and receiving element shown in fig. 27A in that the active layer 373 and the light-emitting layer 383R are not included, and a layer 389 which serves as both a light-emitting layer and an active layer is included.

As a layer which serves as both the light-emitting layer and the active layer, for example, a layer containing three materials of an n-type semiconductor which can be used for the active layer 373, a p-type semiconductor which can be used for the active layer 373, and a light-emitting substance which can be used for the light-emitting layer 383R can be used.

Further, the absorption band on the lowest energy side of the absorption spectrum of the mixed material of the n-type semiconductor and the p-type semiconductor preferably does not overlap with the maximum peak of the emission spectrum (PL spectrum) of the light-emitting substance, and more preferably has a sufficient distance.

At least a part of this embodiment can be implemented in combination with other embodiments described in this specification as appropriate.

< structural example of sectional view >

Fig. 28 is a cross-sectional view showing a structural example of the display device 10. In the display device 10, a transistor 310 having a channel formed over a substrate 301 and a transistor 320 having a semiconductor layer including a metal oxide, which forms a channel, are stacked.

An insulating layer 261 is provided so as to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. Further, an insulating layer 262 is provided so as to cover the conductive layer 251, and the conductive layer 252 is provided over the insulating layer 262. Both the conductive layer 251 and the conductive layer 252 are used as wirings. Further, an insulating layer 263 and an insulating layer 332 are provided so as to cover the conductive layer 252, and the transistor 320 is provided over the insulating layer 332. Further, an insulating layer 265 is provided so as to cover the transistor 320, and the capacitor 240 is provided over the insulating layer 265. Capacitor 240 is electrically connected to transistor 320 through plug 274.

The transistor 320 can be used as a transistor constituting a pixel circuit or a transistor constituting a memory cell. Further, the transistor 310 may be used as a transistor constituting a memory unit, a transistor constituting a driving circuit for driving the pixel circuit, or a transistor constituting an arithmetic circuit. The transistors 310 and 320 can be used as transistors constituting various circuits such as an arithmetic circuit and a memory circuit.

The transistor 310 is a transistor having a channel formation region in the substrate 301. As the substrate 301, a semiconductor substrate such as a single crystal silicon substrate can be used. Transistor 310 includes a portion of substrate 301, conductive layer 311, low resistance region 312, insulating layer 313, and insulating layer 314. The conductive layer 311 is used as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311, and is used as a gate insulating layer. The low resistance region 312 is a region doped with impurities in the substrate 301, and is used as a source or a drain. The insulating layer 314 is provided so as to cover the side surface of the conductive layer 311, and is used as an insulating layer.

In addition, an element separation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301.

The transistor 320 is a transistor using a metal oxide (also referred to as an oxide semiconductor) in a semiconductor layer which forms a channel.

The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327.

The insulating layer 332 functions as a barrier layer which prevents diffusion of impurities such as water or hydrogen from the substrate 301 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 to the insulating layer 332 side. As the insulating layer 332, for example, a film which is less likely to be diffused by hydrogen or oxygen than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, a silicon nitride film, or the like can be used.

The insulating layer 332 is provided with a conductive layer 327, and the insulating layer 326 is provided so as to cover the conductive layer 327. The conductive layer 327 is used as a first gate electrode of the transistor 320, and a portion of the insulating layer 326 is used as a first gate insulating layer. At least a portion of the insulating layer 326 which is in contact with the semiconductor layer 321 is preferably an oxide insulating film such as a silicon oxide film. The top surface of insulating layer 326 is preferably planarized.

The semiconductor layer 321 is disposed on the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide (also referred to as an oxide semiconductor) film having semiconductor characteristics. The semiconductor layer 321 preferably uses a metal oxide containing at least one of indium, an element M (element M is aluminum, gallium, yttrium, or tin), and zinc. An OS transistor using such a metal oxide for a channel formation region has a characteristic that off-state current is very low. Therefore, when an OS transistor is used as a transistor provided in a pixel circuit, analog data written to the pixel circuit can be held for a long period of time, so that it is preferable. Similarly, when an OS transistor is used as a transistor for a memory cell, analog data written to the memory cell can be held for a long period of time, which is preferable.

A pair of conductive layers 325 are provided so as to be in contact with the top surface of the semiconductor layer 321 and serve as a source electrode and a drain electrode.

Further, an insulating layer 328 is provided so as to cover the top surface and the side surfaces of the pair of conductive layers 325, the side surfaces of the semiconductor layer 321, and the like, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 can be used as a barrier layer in which impurities such as water or hydrogen diffuse from the insulating layer 264 or the like to the semiconductor layer 321 and oxygen is desorbed from the semiconductor layer 321. As the insulating layer 328, an insulating film similar to the insulating layer 332 described above can be used.

Openings reaching the semiconductor layer 321 are provided in the insulating layer 328 and the insulating layer 264. An insulating layer 323 and a conductive layer 324 which are in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325, and the top surface of the semiconductor layer 321 are embedded in the opening. The conductive layer 324 is used as a second gate electrode, and the insulating layer 323 is used as a second gate insulating layer.

The top surface of the conductive layer 324, the top surface of the insulating layer 323, and the top surface of the insulating layer 264 are planarized to have substantially uniform heights, and an insulating layer 329 and an insulating layer 265 are provided so as to cover them.

The insulating layers 264 and 265 are used as interlayer insulating layers. The insulating layer 329 serves as a barrier against diffusion of impurities such as water or hydrogen from the insulating layer 265 or the like to the transistor 320. As the insulating layer 329, an insulating film similar to the insulating layer 328 and the insulating layer 332 can be used.

A plug 274 electrically connected to one of the pair of conductive layers 325 is provided so as to be embedded in the insulating layer 265, the insulating layer 329, and the insulating layer 264.

The capacitor 240 includes a conductive layer 241, a conductive layer 245, and an insulating layer 243 therebetween. The conductive layer 241 is used as one electrode of the capacitor 240, the conductive layer 245 is used as the other electrode of the capacitor 240, and the insulating layer 243 is used as a dielectric of the capacitor 240.

The conductive layer 241 is disposed on the insulating layer 261 and embedded in the insulating layer 254. The conductive layer 241 is electrically connected to one of a source and a drain of the transistor 310 through a plug 271 embedded in the insulating layer 261. The insulating layer 243 is provided so as to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

An insulating layer 255 is provided so as to cover the capacitor 240, and the light emitting element 61, the light receiving element 62, and the like are provided over the insulating layer 255. The light emitting element 61 and the light receiving element 62 are provided with a protective layer 91, and a substrate 420 is bonded to the top surface of the protective layer 91 by a resin layer 419. As the substrate 420, a substrate having light transmittance can be used.

The pixel electrode 84 of the light emitting element 61 and the pixel electrode 84PD of the light receiving element 62 are electrically connected to one of the source and the drain of the transistor 310 through the plug 256 embedded in the insulating layer 255, the conductive layer 241 embedded in the insulating layer 254, and the plug 271 embedded in the insulating layer 261.

With this configuration, the OS transistors constituting the pixel circuits and the cells can be arranged directly below the light receiving element and the light emitting element, and the driving circuit, the arithmetic circuit, and the like can be arranged, so that the display device having high performance can be miniaturized.

Embodiment 5

In one embodiment of the present invention, an electronic device in which the display device according to one embodiment of the present invention can be used will be described. The electronic device according to one embodiment of the present invention may also be suitable for wearable electronic devices for VR, AR applications.

Fig. 29A is a perspective view of a goggle-type electronic device 100 as an example of a wearable electronic device. In the electronic device 100 shown in fig. 29A, a pair of display devices 10_l, 10_r are included in a housing 101. The housing 101 includes an acceleration sensor such as a gyro sensor, and can detect the direction of the head of the user and display an image corresponding to the direction.

In this specification and the like, for example, in the case where the content common to the display devices 10_l and 10_r is described or in the case where it is not necessary to distinguish them, it is simply referred to as "display device 10". The display device 10 described in the above embodiment can be used for the display devices 10_l, 10_r shown in fig. 29A.

As described in embodiment 4, since the display device 10 according to one embodiment of the present invention can have a structure in which a light emitting element, a pixel circuit, and a driving circuit are stacked, the aperture ratio (effective display area ratio) of a pixel can be greatly improved. In addition, the pixel circuits can be arranged in extremely high density, whereby the pixels can be made extremely high in definition. Such a display device 10 is extremely high in definition, and is therefore suitable for VR devices such as head-mounted displays and glasses-type AR devices. For example, since the display device 10 has a display portion with extremely high definition, in a structure in which the display portion of the display device 10 is viewed through an optical member such as a lens, a user cannot see pixels even if the display portion is enlarged with the lens, whereby display with high immersion can be realized.

As described in embodiment 4, since the display device 10 according to one embodiment of the present invention has a structure in which the light receiving elements, the cell array, and the arithmetic circuit are stacked, it is possible to perform arithmetic processing with excellent arithmetic efficiency using a minute current output from the light receiving elements as input data. Further, since the display device 10 may have a structure in which the light receiving portion is disposed in a position close to the display portion, the user's eyes and/or the periphery thereof can be photographed while the user's eyes are viewing the image. Therefore, a neural network-based inference process using the image data as input data can be performed. In addition, the cells in the cell array can hold analog data written according to minute currents. In addition, an arithmetic circuit that performs product-sum arithmetic processing using minute currents can perform arithmetic operation with excellent arithmetic efficiency.

Fig. 29B is a perspective view showing the back surface, bottom surface, and right side surface of the electronic device 100 illustrated in fig. 29A.

In fig. 29B, the housing 101 of the electronic device 100 includes, for example, a mounting portion 106, a buffer member 107, a pair of lenses 108, and the like, in addition to the pair of display devices 10_l and 10_r. The display portions 13 in the pair of display devices 10_l, 10_r are respectively provided in positions inside the housing 101 visible through the lens 108.

The light receiving portions 14 of the pair of display devices 10_l and 10_r are provided at positions where information on the eyes and the surrounding area of the user can be obtained. Note that the light receiving unit 14 may acquire information on the eyes and the periphery of the user via the lens 108 inside the housing 101, or may acquire the information without via the lens 108.

The housing 101 shown in fig. 29B is provided with an input terminal 109 and an output terminal 110. A cable supplying an image signal (image data) from a video output device or the like or electric power or the like for charging a battery provided in the housing 101 may be connected to the input terminal 109. The output terminal 110 is used as a sound output terminal, for example, and can be connected to headphones or earphones.

The housing 101 preferably has a mechanism in which the left and right positions of the lens 108 and the display devices 10_l and 10_r can be adjusted so that the lens 108 and the display devices 10_l and 10_r are positioned at the most appropriate positions according to the positions of eyes of the user. Furthermore, it is preferable to have a mechanism in which the focus is adjusted by changing the distance between the lens 108 and the display devices 10_l and 10_r.

The cushioning member 107 is a portion that contacts the face (forehead, cheek, etc.) of the user. By closely contacting the buffer member 107 with the face of the user, light leakage can be prevented, and thus the feeling of immersion can be further improved. The cushioning member 107 preferably uses a soft material to seal against the face of the user when the electronic device 100 is mounted on the user. When such a material is used, it is preferable not only to make the user feel skin friendly, but also to prevent the user from feeling cold when it is put on in a colder season or the like. When the buffer member 107, the mounting portion 106, or other members that contact the skin of the user are configured to be detachable, cleaning and exchange are easy, which is preferable.

The electronic device according to an embodiment of the present invention may further include an earphone 106A. The earphone 106A includes a communication section (not shown), and has a wireless communication function. The earphone 106A may output sound data by using a wireless communication function. The headset 106A may also include a vibration mechanism to be used as a bone conduction headset. The earphone 106A may be directly connected to the mounting portion 106 or connected by a wire.

Fig. 30A is a perspective view of a glasses-type electronic device 100A shown as another example of a wearable electronic device. In the electronic device 100A shown in fig. 30A, a pair of display devices 10_l, 10_r are included in a housing 101.

The electronic device 100A may project the images displayed by the display portion 13 of the display devices 10_l, 10_r on the display region 104 in the optical member 103. Since the optical member 103 has light transmittance, the user can see the image displayed on the display area 104 in overlapping with the transmitted image seen through the optical member 103. Accordingly, the electronic apparatus 100A is an electronic device capable of AR display.

Although not shown, the housing 101 is provided with a wireless receiver or a connector connectable to a cable, so that a video signal or the like can be supplied to the housing 101. Further, by disposing an acceleration sensor such as a gyro sensor in the housing 101, the direction of the head of the user can be detected and an image corresponding to the direction can be displayed on the display area 104.

Next, a method of projecting an image onto the display area 104 of the electronic device 100A is described with reference to fig. 30B. The display device 10, the lens 111, and the reflective plate 112 are provided in the housing 101. Further, a portion corresponding to the display region 104 of the optical member 103 includes a reflecting surface 113 serving as a half mirror.

Light 115 emitted from the display device 10 is reflected by the reflection plate 112 to the optical member 103 side through the lens 111. In the interior of the optical member 103, the light 115 is repeatedly totally reflected at the end face of the optical member 103, and when reaching the reflection surface 113, an image is projected on the reflection surface 113. Thus, the user can see both the light 115 reflected on the reflecting surface 113 and the transmitted light 116 passing through the optical member 103 (including the reflecting surface 113).

Fig. 30B shows an example in which both the reflection plate 112 and the reflection surface 113 have curved surfaces. Thereby, the degree of freedom of the optical design can be improved as compared with the case where they are planar, so that the thickness of the optical member 103 can be reduced. The reflection plate 112 and the reflection surface 113 may be planar.

As the reflection plate 112, a member having a mirror surface may be used, and the reflection plate preferably has a high reflectance. Further, as the reflecting surface 113, a half mirror using reflection of a metal film may be used, but when a prism or the like using total reflection is used, the transmittance of the transmitted light 116 may be improved.

Here, the housing 101 preferably has a mechanism for adjusting the distance or angle between the lens 111 and the display device 10. Thus, focus adjustment, image enlargement, image reduction, and the like can be performed. For example, one or both of the lens 111 and the display device 10 may be movable in the optical axis direction.

The housing 101 preferably has a mechanism capable of adjusting the angle of the reflection plate 112. By changing the angle of the reflection plate 112, the position of the display region 104 where an image is displayed can be changed. Thus, the display region 104 can be arranged at the most appropriate position according to the position of the eyes of the user.

At least a part of the structural example shown in the present embodiment and the drawings corresponding to the structural example may be appropriately combined with other structural examples, drawings, and the like.

< notes concerning the description of the present specification and the like >

Next, explanation will be given of the above embodiment and each structure in the embodiment.

The structure shown in each embodiment mode can be combined with the structure shown in other embodiment modes as appropriate to constitute one embodiment mode of the present invention. Further, when a plurality of structural examples are shown in one embodiment, these structural examples may be appropriately combined.

Furthermore, the content (or a part thereof) described in one embodiment may be applied/combined/replaced with other content (or a part thereof) described in the embodiment and/or content (or a part thereof) described in another embodiment or another embodiments.

The content described in the embodiments refers to the content described in the various drawings or the content described in the specification by the article.

Further, by combining the drawing (or a part thereof) shown in one embodiment with other parts of the drawing, other drawings (or a part thereof) shown in the embodiment, and/or drawings (or a part thereof) shown in another embodiment or embodiments, more drawings can be constituted.

In this specification and the like, constituent elements are classified according to functions and are represented by blocks independent of each other in a block diagram. However, it is difficult to classify constituent elements by function in an actual circuit or the like, and one circuit may involve a plurality of functions or a plurality of circuits may involve one function. Accordingly, the division of blocks in the block diagrams is not limited to the constituent elements described in the specification, and may be appropriately different according to circumstances.

In the drawings, the size, thickness of layers, or regions are sometimes exaggerated for clarity of illustration. Accordingly, the present invention is not limited to the dimensions in the drawings. The drawings are shown in any size for clarity, and are not limited to the shapes, values, etc. shown in the drawings. For example, unevenness in signal, voltage, or current due to noise, timing deviation, or the like may be included.

In this specification and the like, when describing a connection relation of a transistor, expressions of "one of a source and a drain" (a first electrode or a first terminal), "the other of the source and the drain" (a second electrode or a second terminal) are used. This is because the source and drain of the transistor are interchanged according to the structure, operating conditions, or the like of the transistor. Note that the source and the drain of the transistor may be appropriately replaced with a source (drain) terminal, a source (drain) electrode, or the like as appropriate.

In this specification and the like, the "electrode" or the "wiring" does not limit the functions of the constituent elements. For example, an "electrode" is sometimes used as part of a "wiring" and vice versa. Further, "electrode" or "wiring" includes a case where a plurality of "electrodes" or "wirings" are formed integrally, and the like.

In this specification and the like, the voltage and the potential can be appropriately changed. The voltage refers to a potential difference from a reference potential, and when the reference potential is, for example, a ground voltage (ground voltage), the voltage may be referred to as a potential. The ground potential does not necessarily mean 0V. Note that the potentials are opposite, and the potential supplied to the wiring or the like sometimes varies according to the reference potential.

In this specification and the like, words such as "film" and "layer" may be exchanged with each other according to the situation or state. For example, the "conductive layer" may be replaced with the "conductive film" in some cases. In addition, the "insulating film" may be replaced with an "insulating layer" in some cases.

In this specification and the like, a switch means an element having a function of controlling whether or not to flow a current by changing to a conductive state (on state) or a nonconductive state (off state). Alternatively, the switch refers to an element having a function of selecting and switching a current path.

In this specification and the like, for example, a channel length refers to a distance between a source and a drain in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is in an on state) and a gate overlap or a region where a channel is formed in a top view of the transistor.

In this specification and the like, for example, a channel width refers to a length of a region where a semiconductor (or a portion where a current flows in the semiconductor when a transistor is in an on state) and a gate electrode overlap, or a portion where a source and a drain oppose each other in a region where a channel is formed.

In this specification and the like, "a and B connected" includes a case where a and B are electrically connected in addition to a case where a and B are directly connected. The description of "a and B are electrically connected" refers to a case where an object having a certain electrical action is present between a and B, and an electrical signal of a and B can be transmitted and received.

In this specification and the like, a device manufactured using a Metal Mask or an FMM (Fine Metal Mask) is sometimes referred to as a device having a MM (Metal Mask) structure. In this specification and the like, a device manufactured without using a metal mask or an FMM is sometimes referred to as a device having a MML (Metal Mask Less) structure.

In this specification or the like, a structure in which light-emitting layers are formed or applied to light-emitting elements of respective colors (for example, blue (B), green (G), and red (R)) is sometimes referred to as a SBS (Side By Side) structure. In this specification and the like, a light-emitting element that can emit white light is sometimes referred to as a white light-emitting element. The white light-emitting element can realize a full-color display by combining with a colored layer (e.g., a color filter).

Further, the light emitting element can be roughly classified into a single structure and a series structure. The single structure device preferably has the following structure: a light emitting unit is included between a pair of electrodes, and the light emitting unit includes one or more light emitting layers. In order to obtain white light emission, the light emitting layers may be selected so that the light emission of two or more light emitting layers is in a complementary relationship. For example, by placing the light-emitting color of the first light-emitting layer and the light-emitting color of the second light-emitting layer in a complementary relationship, a structure in which the light-emitting element emits light in white as a whole can be obtained. The same applies to a light-emitting element including three or more light-emitting layers.

The device of the tandem structure preferably has the following structure: two or more light emitting units are included between a pair of electrodes, and each light emitting unit includes one or more light emitting layers. In order to obtain white light emission, a structure may be employed in which light emitted from the light-emitting layers of the plurality of light-emitting units is combined to obtain white light emission. Note that the structure to obtain white light emission is the same as that in the single structure. In the device having the tandem structure, an intermediate layer such as a charge generation layer is preferably provided between the plurality of light emitting cells.

In addition, in the case of comparing the white light emitting element (single structure or series structure) and the light emitting element of the SBS structure, the power consumption of the light emitting element of the SBS structure can be made lower than that of the white light emitting element. Devices intended to reduce power consumption preferably employ light emitting elements of SBS structure. On the other hand, a manufacturing process of the white light emitting element is simpler than that of the light emitting element of the SBS structure, and thus manufacturing cost can be reduced or manufacturing yield can be improved, which is preferable.

[ description of the symbols ]

CA: cell array, IM: unit, ITRZ: circuit, MAC: semiconductor device, WCS: circuit, WSD: circuit, XCLK: clock signal, XCS: circuit, XDATA: input data, XLAT: latch signal, XSP: start pulse, YCLK: clock signal, YDATA: output data, YLAT: latch signal, YSP: start pulse

Claims

1. A semiconductor device, comprising:

a cell array for performing a first level of product-sum operation in the artificial neural network and a second level of product-sum operation;

a first circuit for inputting first data to the cell array; and

a second circuit outputting second data from the cell array,

wherein the cell array includes a plurality of cells,

The cell array includes a first region and a second region,

in the first period, the first region is inputted with the first data by the first circuit, and outputs the second data corresponding to the t-th of the product-sum operation of the first hierarchy to the second circuit, and the second region is inputted with the first data by the first circuit, and outputs the second data corresponding to the (t-1) th of the product-sum operation of the second hierarchy to the second circuit.

2. A semiconductor device, comprising:

a first circuit for inputting first data to the cell array; and

a second circuit outputting second data from the cell array,

wherein the cell array includes a plurality of cells,

the cell array includes a first region and a second region,

during a first period, the first region is inputted with the first data by the first circuit and outputs the second data corresponding to the t-th of the first-level product-sum operation to the second circuit, the second region is inputted with the first data by the first circuit and outputs the second data corresponding to the (t-1) th of the second-level product-sum operation to the second circuit,

And, during a second period, the first region is inputted with the first data of the (t+1) th level and outputs the second data of the (t+1) th level corresponding to the product-sum operation of the first level to the second circuit, and the second region is inputted with the first data of the t th level and outputs the second data of the t th level corresponding to the product-sum operation of the second level to the second circuit.

3. The semiconductor device according to claim 1 or 2,

wherein the first data input to the second region is data obtained by performing a nonlinear operation on the second data output from the first region.

4. The semiconductor device according to any one of claims 1 to 3, further comprising:

a third circuit outputting the second data from the cell array,

wherein the third circuit has a function of performing a nonlinear function-based operation on the second data.

5. The semiconductor device according to any one of claim 1 to 4,

wherein the unit comprises:

a first transistor;

a second transistor; and

the electrical characteristics of the capacitor are that,

wherein the first transistor has a function of holding a first potential corresponding to weight data supplied to a gate of the second transistor through the first transistor in an off state,

The capacitor has a function of changing the first potential held in the gate of the second transistor to a second potential according to a potential change of the first data supplied to one electrode,

and the second transistor has a function of outputting the second data corresponding to the first data as an analog current to the other of the source and the drain.

6. The semiconductor device according to claim 5,

wherein the analog current is a current through which the second transistor flows when operating in a subthreshold region.

7. The semiconductor device according to claim 5 or 6,

wherein the first transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

8. The semiconductor device according to claim 7,

wherein the metal oxide comprises In, ga, and Zn.

9. The semiconductor device according to any one of claim 5 to 8,

wherein the second transistors each include a semiconductor layer containing silicon in a channel formation region.

10. An electronic device, comprising:

the semiconductor device according to any one of claims 1 to 9;

a driving circuit;

a pixel circuit;

a light emitting element; and

the light receiving element is arranged on the light receiving element,

Wherein the pixel circuit has a function of controlling light emission of the light emitting element,

the driving circuit has a function of controlling the pixel circuit,

the semiconductor device includes a transistor included in a layer provided with the pixel circuit and a transistor included in a layer provided with the driving circuit,

the semiconductor device has a function of performing arithmetic processing using the current output from the light receiving element as the first data.

11. The electronic device according to claim 10,

wherein the light receiving element comprises an organic photodiode,

and the light emitting element is an organic EL element.

12. The electronic device according to claim 10 or 11,

wherein the light emitting element and the light receiving element are separated by photolithography.