CN116896920A - display device - Google Patents

display device Download PDF

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Publication number
CN116896920A
CN116896920A CN202310190157.4A CN202310190157A CN116896920A CN 116896920 A CN116896920 A CN 116896920A CN 202310190157 A CN202310190157 A CN 202310190157A CN 116896920 A CN116896920 A CN 116896920A
Authority
CN
China
Prior art keywords
disposed
layer
display device
light shielding
power line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310190157.4A
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Chinese (zh)
Inventor
金慧玟
郑京薰
朴明勳
柳炳昌
李东勳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Display Co Ltd
Original Assignee
Samsung Display Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Display Co Ltd filed Critical Samsung Display Co Ltd
Publication of CN116896920A publication Critical patent/CN116896920A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/86—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H10K50/865—Arrangements for improving contrast, e.g. preventing reflection of ambient light comprising light absorbing layers, e.g. light-blocking layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/126—Shielding, e.g. light-blocking means over the TFTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/8791—Arrangements for improving contrast, e.g. preventing reflection of ambient light
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features

Abstract

A display device, comprising: a data line; a first power line; a second power line; a pixel disposed in the display region and connected to the data line, the first power line, and the second power line; a transistor disposed in a non-display region located around the display region and connected to the data line and the first power line; and a first light shielding layer extending from a portion of the second power supply line to the transistor and disposed on the transistor.

Description

Display device
Cross Reference to Related Applications
This application claims priority from korean patent application No. 10-2022-0042870, filed on 6/4/2022, the contents of which are incorporated herein by reference in their entirety.
Technical Field
The present disclosure relates to a display device.
Background
Electronic devices that provide images to users, such as smart phones, digital cameras, notebook computers, navigation units, and smart televisions, include display devices for displaying images. The display device generates an image and provides the image to a user through a display screen thereof.
The display device includes a display panel including pixels that generate an image and a driver that drives the pixels. The pixels are connected to a data line receiving a data voltage, a scan line receiving a scan signal, and a transmission line receiving a transmission signal. The pixels receive data voltages in response to the scan signals. The pixels emit light having a brightness corresponding to the data voltage in response to the emission signal to display an image.
The pixels are susceptible to static electricity. When static electricity is applied to the pixels through the data lines, the pixels may be damaged. Accordingly, a structure for preventing static electricity from being applied to the pixels is required.
Disclosure of Invention
The present disclosure provides a display device capable of protecting an antistatic element from light.
Embodiments of the inventive concept provide a display apparatus including: a data line; a first power line; a second power line; a pixel disposed in the display region and connected to the data line, the first power line, and the second power line; a transistor disposed in a non-display region located around the display region and connected to the data line and the first power line; and a first light shielding layer extending from a portion of the second power supply line to the transistor and disposed on the transistor.
Embodiments of the inventive concept provide a display apparatus including: a data line; a first power line; a second power line; a pixel disposed in the display region and connected to the data line, the first power line, and the second power line; a transistor disposed in a non-display region located around the display region and connected to the data line and the first power line; and a first light shielding layer extending from a portion of the second power supply line to the transistor and disposed on the transistor. The first light shielding layer is provided with a plurality of grooves defined in one side of the first light shielding layer.
According to the above, since the first light shielding layer is provided on the semiconductor layer of the antistatic element and the second light shielding layer is provided below the semiconductor layer, external light is blocked from affecting the semiconductor layer. Accordingly, the antistatic element is protected from external light, and the characteristics of the antistatic element are not changed.
Drawings
The above and other advantages of the present disclosure will become readily apparent by reference to the following detailed description when considered in conjunction with the accompanying drawings, wherein:
fig. 1 is a perspective view of a display device according to an embodiment of the present disclosure;
fig. 2 is a cross-sectional view of the display device shown in fig. 1;
fig. 3 is a cross-sectional view of the display panel shown in fig. 2;
fig. 4 is a plan view of the display panel shown in fig. 2;
fig. 5 is a cross-sectional view of the pixel shown in fig. 4;
fig. 6 is an equivalent circuit diagram of the antistatic circuit shown in fig. 4;
fig. 7, 8, 9, 10, 11, 12, 13, and 14 are plan views of the structure of the antistatic element shown in fig. 6;
FIG. 15 is a cross-sectional view taken along line I-I' shown in FIG. 14;
FIG. 16 is a cross-sectional view taken along line II-II' shown in FIG. 14;
FIG. 17 is a cross-sectional view taken along line III-III' shown in FIG. 14;
FIG. 18 is a cross-sectional view taken along line IV-IV' shown in FIG. 14;
fig. 19 is a plan view of a structure of an antistatic circuit according to an embodiment of the present disclosure;
fig. 20 and 21 are sectional views of the antistatic element shown in fig. 19; and is also provided with
Fig. 22 is a plan view of the structure of an antistatic circuit according to an embodiment of the present disclosure.
Detailed Description
In this disclosure, it will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present.
Like numbers refer to like elements throughout. In the drawings, the thickness, ratio, and size of the parts are exaggerated for the purpose of effectively describing the technical contents.
As used herein, the term "and/or" may include any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Accordingly, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Spatially relative terms, such as "below," "beneath," "lower," "above," and "upper" may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.
Fig. 1 is a perspective view of a display device DD according to an embodiment of the disclosure.
Referring to fig. 1, the display device DD may have a rectangular shape defined by a long side extending in a first direction DR1 and a short side extending in a second direction DR2 intersecting the first direction DR 1. However, the shape of the display device DD is not limited to a rectangular shape, and the display device DD may have various shapes such as a circular shape and other polygonal shapes.
Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 may be referred to as a third direction DR3. In the present disclosure, the expression "when viewed in a plane" or "in a plan view" may mean a state viewed in the third direction DR3.
The upper surface of the display device DD may be referred to as a display surface DS, and may be a planar surface defined by the first direction DR1 and the second direction DR 2. The image IM generated by the display means DD may be provided to the user via the display surface DS.
The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display the image IM, and the non-display area NDA may not display the image IM. The non-display area NDA may surround the display area DA and may define an edge of the display device DD printed in a predetermined color.
The display device DD is applicable to a large-sized electronic device such as a television, a monitor, or an outdoor billboard, and a medium-sized and small-sized electronic device such as a personal computer (e.g., a notebook computer or a tablet computer), a personal digital assistant, a car navigation unit, a game unit, a smart phone, or a camera. However, these are merely examples, and the display device DD may be applied to other electronic devices without departing from the concept of the present disclosure.
Fig. 2 is a cross-sectional view of the display device DD shown in fig. 1.
As an example, fig. 2 shows a cross section of the display device DD when viewed in the first direction DR 1.
Referring to fig. 2, the display device DD may include a display panel DP, an input sensing unit ISP, an anti-reflection layer RPL, a window WIN, a panel protection film PPF, and first and second adhesive layers AL1 and AL2.
The display panel DP may be a flexible display panel. The display panel DP may be a light emitting display panel, however, should not be particularly limited. For example, the display panel DP may be an organic light emitting display panel or an inorganic light emitting display panel. The light emitting layer of the organic light emitting display panel may include an organic light emitting material. The light emitting layer of the inorganic light emitting display panel may include quantum dots or quantum rods. Hereinafter, the organic light emitting display panel will be described as a representative example of the display panel DP.
The input sensing unit ISP may be disposed on the display panel DP. The input sensing unit ISP may include a plurality of sensing parts (not shown) to sense an external input through a capacitive method. The input sensing unit ISP may be directly manufactured on the display panel DP when the display device DD is manufactured, however, should not be limited thereto or thereby. According to an embodiment, the input sensing unit ISP may be attached to the display panel DP through an adhesive layer after being manufactured separately from the display panel DP.
The anti-reflection layer RPL may be disposed on the input sensing unit ISP. The anti-reflection layer RPL may be directly manufactured on the input sensing unit ISP when the display device DD is manufactured, however, the present disclosure should not be limited thereto or by this. According to an embodiment, the anti-reflection layer RPL may be attached to the input sensing unit ISP through an adhesive layer after being manufactured as a separate panel.
The anti-reflection layer RPL may be an external light reflection preventing film. The anti-reflection layer RPL may reduce the reflectivity for external light incident to the display panel DP from above the display device DD. External light may not be perceived by the user through the anti-reflection layer RPL.
The window WIN may be disposed on the anti-reflection layer RPL. The window WIN may protect the display panel DP, the input sensing unit ISP, and the anti-reflection layer RPL from external scratches and impacts.
The panel protection film PPF may be disposed under the display panel DP. The panel protection film PPF may protect the lower portion of the display panel DP. The panel protection film PPF may include a flexible plastic material such as polyethylene terephthalate (PET).
The first adhesive layer AL1 may be disposed between the display panel DP and the panel protective film PPF. The display panel DP and the panel protective film PPF may be coupled to each other through the first adhesive layer AL 1. The second adhesive layer AL2 may be disposed between the window WIN and the anti-reflection layer RPL, and the window WIN and the anti-reflection layer RPL may be coupled to each other through the second adhesive layer AL 2.
Fig. 3 is a sectional view of the display panel DP shown in fig. 2.
As an example, fig. 3 shows a cross section of the display panel DP when viewed in the first direction DR 1.
Referring to fig. 3, the display panel DP may include a substrate SUB, a circuit element layer DP-CL disposed on the substrate SUB, a display element layer DP-OL disposed on the circuit element layer DP-CL, and a thin film encapsulation layer TFE disposed on the display element layer DP-OL.
The substrate SUB may include a display area DA and a non-display area NDA surrounding the display area DA. The substrate SUB may comprise a glass material or a flexible plastic material such as Polyimide (PI). The display element layers DP-OL may be disposed in the display area DA.
A plurality of pixels may be disposed in the circuit element layer DP-CL and the display element layer DP-OL. Each pixel may include a transistor disposed in the circuit element layer DP-CL and a light emitting element disposed in the display element layer DP-OL and connected to the transistor. The pixels will be described in detail later.
A thin film encapsulation layer TFE may be disposed over the circuit element layer DP-CL to cover the display element layer DP-OL. The thin film encapsulation layer TFE can protect the pixels from moisture, oxygen, and foreign matter.
Fig. 4 is a plan view of the display panel DP shown in fig. 2.
Referring to fig. 4, the display device DD may include a display panel DP, a scan driver SDV, a data driver DDV, a light emitting driver EDV, a plurality of pads PD, and an antistatic circuit ASC.
The display panel DP may have a rectangular shape in a plan view, the rectangular shape having a long side extending in the first direction DR1 and a short side extending in the second direction DR2, however, the shape of the display panel DP should not be limited thereto or thereby. The display panel DP may include a display area DA and a non-display area NDA surrounding the display area DA.
The display panel DP may include a plurality of pixels PX, a plurality of scan lines SL1 to SLm, a plurality of data lines DL1 to DLn, a plurality of emission lines EL1 to ELm, first and second control lines CSL1 and CSL2, and first and second power lines PL1 and PL2. Each of "m" and "n" is a natural number greater than 0.
The pixels PX may be arranged in the display area DA. The scan driver SDV and the light emitting driver EDV may be disposed in the non-display area NDA adjacent to the long side of the display panel DP, respectively. The data driver DDV may be disposed in the non-display area NDA adjacent to one of the short sides of the display panel DP. The data driver DDV may be disposed adjacent to the lower end of the display panel DP when viewed in a plane.
The scan lines SL1 to SLm may extend in the second direction DR2, and may be connected to the pixels PX and the scan driver SDV. The data lines DL1 to DLn may extend in the first direction DR1 and may be connected to the pixels PX and the data driver DDV. The emission lines EL1 to ELm may extend in the second direction DR2 and may be connected to the pixels PX and the emission driver EDV.
The first power line PL1 may extend in the first direction DR1 and may be disposed in the non-display area NDA. The first power line PL1 may be disposed between the display area DA and the light emitting driver EDV. The first power line PL1 may extend toward the display area DA and may be connected to the pixels PX. The first voltage may be applied to the pixel PX via the first power line PL 1.
The second power line PL2 may be disposed in the non-display area NDA. The second power line PL2 may extend along a long side of the display panel DP and the other short side at which the data driver DDV is not disposed in the display panel DP. The second power line PL2 may be disposed outside the scan driver SDV and the light emitting driver EDV. The second power line PL2 may extend toward the display area DA and may be connected to the pixels PX. A second voltage having a lower level than the first voltage may be applied to the pixel PX via the second power line PL 2.
The first control line CSL1 may be connected to the scan driver SDV and may extend toward the lower end of the display panel DP. The second control line CSL2 may be connected to the light emitting driver EDV and may extend toward the lower end of the display panel DP. The data driver DDV may be disposed between the first control line CSL1 and the second control line CSL 2.
The pad PD may be disposed in the non-display area NDA adjacent to the lower end of the display panel DP. The pad PD may be disposed closer to the lower end of the display panel DP than the data driver DDV. The data driver DDV, the first power line PL1, the second power line PL2, the first control line CSL1, and the second control line CSL2 may be connected to the pad PD. The data lines DL1 to DLn may be connected to the data driver DDV, and the data driver DDV may be connected to the pads PD corresponding to the data lines DL1 to DLn.
Although not shown in the drawings, the display device DD may further include a timing controller for controlling operations of the scan driver SDV, the data driver DDV, and the light emitting driver EDV, and a voltage generator generating the first voltage and the second voltage. The timing controller and the voltage generator may be connected to the corresponding pad PD through a printed circuit board.
The scan driver SDV may generate a plurality of scan signals, and the scan signals may be applied to the pixels PX through the scan lines SL1 to SLm. The data driver DDV may generate a plurality of data voltages, and the data voltages may be applied to the pixels PX through the data lines DL1 to DLn. The light emitting driver EDV may generate a plurality of emission signals, and the emission signals may be applied to the pixels PX through the emission lines EL1 to ELm.
The pixel PX may receive the data voltage in response to the scan signal. The pixel PX may emit light having a luminance corresponding to the data voltage in response to the emission signal, and thus an image may be displayed.
The antistatic circuit ASC may be disposed in the non-display area NDA between the data driver DDV and the display area DA. The antistatic circuit ASC may prevent static electricity from being applied to the pixels PX through the data lines DL1 to DLn.
The antistatic circuit ASC may be connected to the data lines DL1 to DLn. The first power line PL1 may extend toward the antistatic circuit ASC and may be connected to the antistatic circuit ASC. The second power supply line PL2 may extend toward the antistatic circuit ASC, and may protect elements of the antistatic circuit ASC from light. This will be described in detail later.
Fig. 5 is a cross-sectional view of the pixel PX shown in fig. 4.
Referring to fig. 5, the pixel PX may include a transistor TR and a light emitting element OLED. The light emitting element OLED may include a first electrode (or anode) AE, a second electrode (or cathode) CE, a hole control layer HCL, an electron control layer ECL, and a light emitting layer EML.
The transistor TR and the light emitting element OLED may be disposed on the substrate SUB. As an example, one transistor TR is shown in fig. 5, however, the pixel PX may include a plurality of transistors and at least one capacitor to drive the light emitting element OLED.
The display area DA may include a light emitting area EA corresponding to each pixel PX and a non-light emitting area NEA located around the light emitting area EA. The light emitting element OLED may be disposed in the light emitting area EA.
The lower metal layer BML may be disposed on the substrate SUB, and the buffer layer BFL may be disposed on the lower metal layer BML. The buffer layer BFL may be an inorganic layer. The buffer layer BFL may be disposed on the substrate SUB to cover the lower metal layer BML. The lower metal layer BML will be described in detail with reference to fig. 7.
The transistor TR may include semiconductor layers (or active layers) S, C and D and a gate G. The semiconductor layers S, C and D may include polycrystalline silicon, amorphous silicon, or a metal oxide semiconductor.
The semiconductor layer may be doped with an N-type dopant or a P-type dopant. The semiconductor layer may include a highly doped region and a lowly doped region. The highly doped region may have a conductivity greater than that of the low doped region, and may constitute a source region S and a drain region D of the transistor TR. The low doped region may constitute the channel region C. The source region S, the channel region C, and the drain region D of the transistor TR may be formed of a semiconductor layer. The source region S and the drain region D may substantially serve as a source and a drain of the transistor TR.
The first insulating layer INS1 may be disposed on the semiconductor layer. The gate electrode G of the transistor TR may be disposed on the first insulating layer INS 1. The gate G may overlap the channel region C when viewed in a plane.
The second insulating layer INS2 may be disposed on the gate electrode G. The third insulation layer INS3 may be disposed on the second insulation layer INS 2. The third insulation layer INS3 may be defined as an interlayer insulation layer.
The connection electrode CNE may include a first connection electrode CNE1 and a second connection electrode CNE2 that connect the transistor TR to the light emitting element OLED. The first connection electrode CNE1 may be disposed on the third insulating layer INS3, and may be connected to the drain region D via a first contact hole CH1 defined through the first, second, and third insulating layers INS1, INS2, and INS 3.
The fourth insulating layer INS4 may be disposed on the first connection electrode CNE1. The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the first connection electrode CNE1. The fourth insulating layer INS4 may be defined as a planarization insulating layer.
The second connection electrode CNE2 may be disposed on the fourth insulation layer INS 4. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a second contact hole CH2 defined through the fourth insulation layer INS 4.
The fifth insulating layer INS5 may be disposed on the second connection electrode CNE2. The layers from the buffer layer BFL to the fifth insulating layer INS5 may be defined as the circuit element layer DP-CL. Each of the first to third insulating layers INS1 to INS3 may be an inorganic layer. Each of the fourth insulating layer INS4 and the fifth insulating layer INS5 may be an organic layer.
The first electrode AE may be disposed on the fifth insulating layer INS 5. The first electrode AE may be connected to the second connection electrode CNE2 via a third contact hole CH3 defined through the fifth insulating layer INS 5. The pixel defining layer PDL may be disposed on the first electrode AE and the fifth insulating layer INS5, and the pixel defining layer PDL is provided with a pixel opening px_op defined through the pixel defining layer PDL to expose a predetermined portion of the first electrode AE.
The hole control layer HCL may be disposed on the first electrode AE and the pixel defining layer PDL. The hole control layer HCL may include a hole transport layer and a hole injection layer.
The emission layer EML may be disposed on the hole control layer HCL. The light emitting layer EML may be disposed in the pixel opening px_op. The light emitting layer EML may include an organic material and/or an inorganic material. The light emitting layer EML may generate light having one of red, green, and blue.
The electron control layer ECL may be disposed on the emission layer EML and the hole control layer HCL. The electron control layer ECL may include an electron transport layer and an electron injection layer. The hole control layer HCL and the electron control layer ECL may be disposed in common in the light emitting region EA and the non-light emitting region NEA.
The second electrode CE may be disposed on the electronic control layer ECL. The second electrode CE may be commonly disposed throughout each pixel PX. The layers constituting the light emitting element OLED may be referred to as display element layers DP-OL. The circuit element layer DP-CL and the display element layer DP-OL may be referred to as a pixel layer PXL.
The thin film encapsulation layer TFE may be disposed on the second electrode CE, and may cover the pixels PX. Although not shown in the drawings, the thin film encapsulation layer TFE may include two inorganic layers and an organic layer disposed between the two inorganic layers. The inorganic layer may protect the pixels PX from moisture and oxygen. The organic layer may protect the pixels PX from foreign substances such as dust particles.
The first voltage may be applied to the first electrode AE via the transistor TR, and the second voltage may be applied to the second electrode CE. The holes and electrons injected into the emission layer EML may be recombined to generate excitons, and the light emitting element OLED may emit light by the excitons returning from an excited state to a ground state.
Fig. 6 is an equivalent circuit diagram of the antistatic circuit ASC shown in fig. 4.
Referring to fig. 6, the data line DL and the first and second power lines PL1 and PL2 may extend in the first direction DR1 and may be arranged in the second direction DR 2. The data line DL may be a part of the data lines DL1 to DLn. As an example, the data lines DL may be five data lines arranged from the leftmost side in the second direction DR2 among the data lines DL1 to DLn.
The first power line PL1 may receive the first voltage ELVDD, and the second power line PL2 may receive the second voltage ELVSS having a lower level than the first voltage ELVDD.
The antistatic circuit ASC may include a plurality of antistatic elements ASD arranged in the second direction DR 2. The antistatic element ASD may be connected to the data line DL and the first power line PL1. Since the antistatic elements ASD have substantially the same structure, hereinafter, one antistatic element ASD connected to one data line DL will be described in detail.
The antistatic element ASD may include a transistor E-TR and first and second capacitors C1 and C2. The transistors E-TR may include NMOS transistors. The transistor E-TR may include an oxide semiconductor.
The transistors E-TR may be connected to the data line DL and the first power line PL1. The second power line PL2 may be disposed adjacent to the first power line PL1. The first light shielding layer SHL1 extending from a portion of the second power line PL2 may be disposed to overlap the transistors E-TR. The first light shielding layer SHL1 may block light from reaching the transistor E-TR from above the transistor E-TR. This structure will be described in detail later with reference to a cross-sectional view of the transistor E-TR.
The first capacitor C1 may be disposed between the transistor E-TR and the data line DL, and may be connected to the transistor E-TR and the data line DL. The second capacitor C2 may be disposed between the transistor E-TR and the first power supply line PL1, and may be connected to the transistor E-TR and the first power supply line PL1.
The transistors E-TR may include a source region SC, a drain region DR, a gate GT, and a dummy gate DGT. The transistor E-TR may include a semiconductor layer SML (refer to fig. 8), and the source region SC and the drain region DR may be formed of the semiconductor layer. The source region SC and the drain region DR may substantially serve as the source and drain of the transistor E-TR.
The source region SC may be connected to the data line DL. The drain region DR may be connected to the first power line PL1. The gate GT may be connected to a dummy gate DGT.
The gate GT may serve as a first electrode of each of the first capacitor C1 and the second capacitor C2. Each of the first capacitor C1 and the second capacitor C2 may include a second electrode facing the first electrode, and the second electrode will be shown in the layout and cross section of the underlying transistor E-TR. A second electrode of the first capacitor C1 may be connected to the data line DL, and a second electrode of the second capacitor C2 may be connected to the first power line PL1.
Static electricity may be applied to the data line DL, however, static electricity may be charged to the first capacitor C1 and the second capacitor C2 to be discharged, and thus, static electricity may not be applied to the pixel PX. Accordingly, static electricity can be prevented from being applied to the pixels PX by the static electricity preventing circuit ASC.
Fig. 7 to 14 are plan views of the structure of the antistatic element ASD shown in fig. 6.
A sequential stacked structure of the transistor E-TR, the first and second capacitors C1 and C2, the first and second power lines PL1 and PL2, and the data line DL is shown in fig. 7 to 14.
Referring to fig. 7, a lower metal layer BML may be disposed on the substrate SUB shown in fig. 5. The lower metal layer BML may include a plurality of second light shielding layers SHL2. The second light shielding layer SHL2 may include a conductive material.
Each of the second light shielding layers SHL2 may be formed as the dummy gate DGT described with reference to fig. 6. The second light shielding layer SHL2 may extend in the first direction DR1, and may be arranged in the second direction DR 2. A portion of each of the second light shielding layers SHL2 may protrude in a direction opposite to the second direction DR2 as the first protruding portion PRT1.
Referring to fig. 8, a semiconductor pattern SMP may be disposed on the lower metal layer BML. The semiconductor pattern SMP may include a plurality of semiconductor layers SML. The semiconductor layer SML may extend in the first direction DR1 and may be arranged in the second direction DR 2. The second light shielding layers SHL2 may be disposed to overlap the semiconductor layers SML, respectively, when viewed in a plane.
The semiconductor layer SML may include an oxide semiconductor including a metal oxide semiconductor. Each of the semiconductor layers SML may include a plurality of regions that are distinguished from each other according to whether or not a metal oxide is reduced. The region where the metal oxide is reduced (hereinafter referred to as a reduction region) may have higher electrical conductivity than the region where the metal oxide is not reduced (hereinafter referred to as an unreduced region). The reduction region may correspond to the source region SC and the drain region DR. The unreduced region may substantially correspond to the channel region CA.
Each of the semiconductor layers SML may form a drain region DR, a source region SC, and a channel region CA of the transistor E-TR. The drain region DR, the source region SC, and the channel region CA may be arranged in the first direction DR 1. The channel region CA may be disposed between the drain region DR and the source region SC. The second light shielding layer SHL2 may be disposed to entirely overlap the channel region CA when viewed in a plane.
Hereinafter, the current pattern is illustrated with a thick line as a hatched area, and the previous pattern is illustrated with a thin line to more clearly show the current pattern.
Referring to fig. 9, a first gate pattern GPT1 may be disposed on the semiconductor pattern SMP. The first gate pattern GPT1 may include a plurality of gate electrodes GT. The gate GT may extend in the first direction DR1 and may be arranged in the second direction DR 2. Each of the gates GT may serve as a gate GT of a transistor E-TR. A portion of each of the gate electrodes GT may protrude in a direction opposite to the second direction DR2, and may serve as a second protruding portion PRT2.
The gate GT may be set to entirely overlap the channel region CA when viewed in a plane. A portion of the first gate pattern GPT1 overlapping the semiconductor layer SML may be defined as a gate electrode GT. Further, a portion of the semiconductor layer SML overlapping the gate electrode GT may be defined as a channel region CA.
Referring to fig. 10, the second gate pattern GPT2 may be disposed on the first gate pattern GPT 1. The second gate pattern GPT2 may include a plurality of first metals ME1 and a plurality of second metals ME2. The first metal ME1 may be arranged in the second direction DR 2. The second metal ME2 may be arranged in the second direction DR 2. The first metal ME1 and the second metal ME2 may be spaced apart from each other in the first direction DR 1.
The first metal ME1 may partially overlap one end portion of the gate GT when viewed in a plane. The first metal ME1 may be disposed adjacent to the source region SC. The second metal ME2 may partially overlap the other end of the gate GT opposite to the one end when viewed in a plane. The second metal ME2 may be disposed adjacent to the drain region DR.
The first capacitor C1 may be formed of a gate GT and a first metal ME1 overlapping the gate GT. The gate GT may serve as a first electrode of the first capacitor C1, and the first metal ME1 may serve as a second electrode of the first capacitor C1.
The second capacitor C2 may be formed of a gate GT and a second metal ME2 overlapping the gate GT. The gate GT may serve as a first electrode of the second capacitor C2, and the second metal ME2 may serve as a second electrode of the second capacitor C2.
Referring to fig. 11, a plurality of first-first contact holes CH1-1 may be defined to expose the source region SC. The plurality of first-second contact holes CH1-2 may be defined to expose the first metal ME1 adjacent to the source region SC.
The plurality of first to third contact holes CH1 to 3 may be defined to expose the drain region DR. The plurality of first to fourth contact holes CH1 to 4 may be defined to expose the second metal ME2 adjacent to the drain region DR. The first to fifth contact holes CH1 to 5 may be defined to expose the first protruding portion PRT1, and the first to sixth contact holes CH1 to 6 may be defined to expose the second protruding portion PRT2.
The first to fifth contact holes CH1 to 5 may overlap the first protruding portion PRT1 of the lower metal layer BML when viewed in a plane. The first to sixth contact holes CH1 to 6 may overlap the second protruding portion PRT2 of the first gate pattern GPT1 when viewed in a plane. The structures of the first-first contact hole CH1-1 to the first-sixth contact hole CH1-6 in cross section will be described later in detail with reference to a cross-sectional view of the transistor E-TR.
Referring to fig. 12, the first electrode pattern EPT1 may be disposed on the second gate pattern GPT 2. The first electrode pattern EPT1 may include a first power line PL1, a plurality of first-first connection electrodes CNE1-1, and a plurality of first-second connection electrodes CNE1-2.
The first power line PL1 may extend in the first direction DR1 at the left side of the transistor E-TR disposed at the leftmost side and may extend in the second direction DR2 at the upper side of the transistor E-TR when viewed in a plane.
The first power line PL1 may include a plurality of first power lines PL1' extending from a portion of the first power line PL1 extending in the second direction DR2 toward the transistor E-TR in a direction opposite to the first direction DR 1. The first power supply line PL1' may be arranged in the second direction DR 2.
The first-first connection electrode CNE1-1 may extend in the first direction DR1 and then may extend in the second direction DR2, and thus, the first-first connection electrode CNE1-1 may be disposed on the source region SC and a portion of the first metal ME1 adjacent to the source region SC. The first-first connection electrode CNE1-1 extending in the second direction DR2 may overlap with the source region SC and a portion of the first metal ME1 adjacent to the source region SC when viewed in a plane.
The first-first connection electrode CNE1-1 may be connected to the source region SC via the first-first contact hole CH 1-1. The first-first connection electrode CNE1-1 may be connected to the first metal ME1 via the first-second contact hole CH 1-2.
The first power line PL1' may be disposed on the drain region DR and a portion of the second metal ME2 adjacent to the drain region DR. The first power line PL1' may overlap with the drain region DR and a portion of the second metal ME2 adjacent to the drain region DR when viewed in a plane.
The first power line PL1' may be connected to the drain region DR via the first to third contact holes CH 1-3. The first power line PL1' may be connected to the second metal ME2 via the first to fourth contact holes CH 1-4.
The first-second connection electrode CNE1-2 may be disposed on the first protruding portion PRT1 of the second light shielding layer SHL2 and the second protruding portion PRT2 of the gate electrode GT. The first-second connection electrode CNE1-2 may overlap the first protruding portion PRT1 and the second protruding portion PRT2 when viewed in a plane.
The first-second connection electrode CNE1-2 may be connected to the first and second protruding portions PRT1 and PRT2 via the first-fifth contact holes CH1-5 and the first-sixth contact holes CH1-6, respectively. Accordingly, the second light shielding layer SHL2 may be connected to the gate electrode GT through the first-second connection electrode CNE 1-2. The second light shielding layer SHL2 may serve as a dummy gate DGT.
Referring to fig. 13, a plurality of second-first contact holes CH2-1 may be defined over portions of the first-first connection electrode CNE1-1 that do not overlap the source region SC and the first metal ME 1. The structure of the second-first contact hole CH2-1 in cross section will be described later in detail with reference to a cross-sectional view of the transistor E-TR.
Referring to fig. 14, the second electrode pattern EPT2 may be disposed on the first electrode pattern EPT 1. The second electrode pattern EPT2 may include a second power line PL2, a data line DL, and a first light shielding layer SHL1.
The second power supply line PL2 may extend in the first direction DR1, and may be arranged in the second direction DR 2. The second power supply lines PL2 may be disposed adjacent to the transistors E-TR, respectively. The second power line PL2 may be insulated from the first power line PL1 extending in the second direction DR2 while crossing the first power line PL 1.
The data lines DL may extend in the first direction DR1 and may be arranged in the second direction DR 2. The data line DL may be connected to the first-first connection electrode CNE1-1 via the second-first contact hole CH 2-1. Accordingly, the data line DL may be connected to the source region SC and the first metal ME1 via the first-first connection electrode CNE1-1.
Each of the transistors E-TR may be disposed between one data line DL and one second power line PL2 adjacent to each other. As an example, the h-th transistor E-TR may be disposed between the h-th data line DL and the h-th second power line PL 2. In this embodiment, h is a natural number greater than 0.
Each of the first power lines PL1' may be disposed between the data line DL and the second power line PL 2. As an example, the h first power line PL1' may be disposed between the h data line DL and the h second power line PL 2.
The first light shielding layer SHL1 may extend from a portion of the second power line PL2 to the transistor E-TR, and may be disposed on the transistor E-TR. The h first light shielding layer SHL1 may extend from a portion of the h second power line PL2 toward the h data line DL.
The first light shielding layer SHL1 may include a side OS facing the data line DL. At least one groove GV may be defined in each of the one sides OS of the first light shielding layer SHL 1. As an example, two grooves GV are defined in each of one side of the first light shielding layer SHL1, however, the number of grooves GV should not be limited thereto or by this.
The first light shielding layer SHL1 may entirely overlap the channel region CA when viewed in a plane. Further, the first light shielding layer SHL1 may overlap with a portion of the gate electrode GT and a portion of the first metal ME1 and a portion of the second metal ME2 when viewed in a plane.
The first light shielding layer SHL1 may not overlap the first power line PL1' and the first-first connection electrode CNE1-1 when viewed in a plane. The first light shielding layer SHL1 may be disposed between the first-first contact hole CH1-1 and the first-second contact hole CH1-2 and the first-third contact hole CH1-3 and the first-fourth contact hole CH1-4 when viewed in a plane. The first light shielding layer SHL1 may overlap the first-second connection electrode CNE1-2 when viewed in a plane.
According to the planar structure shown in fig. 7 to 14, the data lines DL may be arranged at regular intervals in the second direction DR 2. Further, the first power line PL1' and the second power line PL2 may be arranged at regular intervals in the second direction DR 2. In this case, elements such as the transistors E-TR and the first and second capacitors C1 and C2 can be regularly arranged, and thus the layout of the elements can be easily designed.
Fig. 15 is a sectional view taken along line I-I' shown in fig. 14.
Referring to fig. 14 and 15, a second light shielding layer SHL2 may be disposed on the substrate SUB. The buffer layer BFL may be disposed on the substrate SUB to cover the second light shielding layer SHL2.
The semiconductor layer SML may be disposed on the buffer layer BFL. The semiconductor layer SML may include a source region SC, a drain region DR, and a channel region CA. The second light shielding layer SHL2 may be disposed under the semiconductor layer SML, and may entirely overlap the channel region CA when viewed in a plane.
The first insulating layer INS1 may be disposed on the buffer layer BFL to cover the semiconductor layer SML. The gate electrode GT may be disposed on the first insulating layer INS 1. The gate GT may completely overlap the channel region CA when viewed in plane.
The second insulating layer INS2 may be disposed on the first insulating layer INS1 to cover the gate electrode GT. The first metal ME1 and the second metal ME2 may be disposed on the second insulating layer INS2 and may be spaced apart from each other. As described above, the first capacitor C1 may be formed of the first metal ME1 and the gate GT overlapping the first metal ME1, and the second capacitor C2 may be formed of the second metal ME2 and the gate GT overlapping the second metal ME2.
A third insulating layer INS3 may be disposed on the second insulating layer INS2 to cover the first metal ME1 and the second metal ME2. The third insulating layer INS3 may be defined as an interlayer insulating layer covering the transistors E-TR.
The first power line PL1' and the first-first connection electrode CNE1-1 may be disposed on the third insulating layer INS 3. The first-first connection electrode CNE1-1 may be connected to the source region SC via a first-first contact hole CH1-1 defined through the first, second, and third insulating layers INS1, INS2, INS 3. The first-first connection electrode CNE1-1 may be connected to the first metal ME1 via first-second contact holes CH1-2 defined through the third insulating layer INS 3. Accordingly, the first-first connection electrode CNE1-1 may be connected to the source region SC and the first capacitor C1.
The first power line PL1' may be connected to the drain region DR via first-third contact holes CH1-3 defined through the first, second, and third insulating layers INS1, INS2, and INS 3. The first power line PL1' may be connected to the second metal ME2 via first to fourth contact holes CH1-4 defined through the third insulating layer INS 3. Accordingly, the first power line PL1' may be connected to the drain region DR and the second capacitor C2.
The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the first power line PL1' and the first-first connection electrode CNE1-1. The fourth insulating layer INS4 may be defined as a planarized insulating layer providing a planarized upper surface.
The first light shielding layer SHL1 and the data line DL may be disposed on the fourth insulating layer INS 4. The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the first light shielding layer SHL1 and the data line DL. The first power line PL1' may be disposed on a layer different from a layer on which the first light shielding layer SHL1 and the data line DL are disposed, and the first light shielding layer SHL1 may be disposed on the same layer as the data line DL.
The first light shielding layer SHL1 may be disposed on the transistors E to TR, and may be disposed to overlap the channel region CA when viewed in a plane. The data line DL may be connected to the first-first connection electrode CNE1-1 via a second-first contact hole CH2-1 defined through the fourth insulating layer INS 4. The data line DL may be connected to the source region SC and the first capacitor C1 via a first-first connection electrode CNE1-1.
The first light shielding layer SHL1 and the second light shielding layer SHL2 may block light from being incident on the semiconductor layer SML (e.g., the channel region CA) of the transistor E-TR. In the case where light is supplied to the semiconductor layer SML of the transistor E-TR, the threshold voltage characteristics of the transistor E-TR may be changed by the light. That is, the threshold voltage may shift.
In fig. 6, the transistor E-TR may be maintained in an off state. However, in the case where the threshold voltage characteristic of the transistor E-TR is changed, the transistor E-TR may malfunction, and thus the transistor E-TR may be turned on. In this case, the data line DL may be short-circuited with the first power line PL 1'.
According to the present embodiment, the first light shielding layer SHL1 and the second light shielding layer SHL2 can block light incident on the semiconductor layer SML of the transistor E-TR from above and below the transistor E-TR. Accordingly, the threshold voltage characteristics of the transistor E-TR may not be changed.
The first and second metals ME1 and ME2, the first power line PL1', and the first-first connection electrode CNE1-1 may be disposed to overlap the semiconductor layer SML when viewed in a plane. Accordingly, the first and second metals ME1 and ME2, the first power line PL1', and the first-first connection electrode CNE1-1 may block light from traveling to the semiconductor layer SML.
Fig. 16 is a sectional view taken along line II-II' shown in fig. 14. Fig. 17 is a sectional view taken along line III-III' shown in fig. 14. Fig. 18 is a sectional view taken along line IV-IV' shown in fig. 14.
In fig. 16 to 18, the same reference numerals denote the same elements as those in fig. 15, and thus detailed description of the same elements will be omitted.
Referring to fig. 14, 15 and 16, a channel region CA may be defined on the second light shielding layer SHL2, a gate GT may be disposed above the channel region CA, and a second metal ME2 may be disposed on the gate GT. The second power line PL2 may be disposed on the second metal ME 2.
The second power line PL2 may be disposed on the fourth insulating layer INS 4. The fifth insulating layer INS5 may be disposed on the fourth insulating layer INS4 to cover the second power supply line PL2. The first light shielding layer SHL1 may extend from the second power line PL2 and may be disposed on the transistor E-TR. The first power line PL1' may be disposed on a layer different from a layer on which the second power line PL2 and the data line DL are disposed, and the second power line PL2 may be disposed on the same layer as the data line DL.
Referring to fig. 14 and 17, the first-second connection electrode CNE1-2 may be disposed on the third insulating layer INS3, and the fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the first-second connection electrode CNE1-2.
The first-second connection electrode CNE1-2 may be connected to the second light shielding layer SHL2 via first-fifth contact holes CH1-5 defined through the buffer layer BFL and the first through third insulating layers INS1 through INS 3. The second light shielding layer SHL2 may include a first protruding portion PRT1 of the lower metal layer BML. The buffer layer BFL and the first through third insulating layers INS1 through INS3 may be disposed between the first-second connection electrodes CNE1-2 and the second light shielding layer SHL2.
The first-second connection electrodes CNE1-2 may be connected to the gate electrode GT via first-sixth contact holes CH1-6 defined through the second and third insulating layers INS2 and INS 3. The gate electrode GT may include a second protruding portion PRT2 of the first gate pattern GPT 1. The second insulating layer INS2 and the third insulating layer INS3 may be disposed between the first-second connection electrodes CNE1-2 and the gate electrode GT. The gate electrode GT may be connected to the dummy gate electrode DGT formed of the second light shielding layer SHL2 through the first-second connection electrode CNE1-2.
Referring to fig. 18, a groove GV may be defined in the first light shielding layer SHL1 disposed on the fourth insulating layer INS 4. The GAS may be generated from the fourth insulating layer INS4, which is an organic layer. When the groove GV is defined in the first light shielding layer SHL1, the GAS generated from the fourth insulating layer INS4 can be easily discharged upward via the groove GV.
Fig. 19 is a plan view of the structure of an antistatic circuit ASC' according to an embodiment of the present disclosure. Fig. 20 and 21 are sectional views of the antistatic element shown in fig. 19.
As an example, fig. 19 is a plan view corresponding to the plan view of fig. 14, and fig. 20 and 21 are sectional views corresponding to the sectional views of fig. 15 and 18, respectively. Hereinafter, in fig. 19, features different from those of the antistatic circuit ASC shown in fig. 14 will be described focusing on the antistatic circuit ASC'.
Referring to fig. 19, the second electrode pattern EPT2 may include a first power line PL1. The data line DL, the second power line PL2, and the first light shielding layer SHL1' may be disposed at a lower position than the first power line PL1. The cross-sectional structure will be described in detail with reference to fig. 20 and 21. As an example, the second power supply line PL2 is indicated by a thick line in fig. 19.
In essence, the data line DL shown in fig. 19 may be disposed on the same layer as the first-first connection electrode CNE1-1 shown in fig. 14, and may be integrally provided with the first-first connection electrode CNE1-1, respectively.
The groove GV may not be defined in the side OS of the first light shielding layer SHL 1'. However, a groove GV 'overlapping the first-second connection electrode CNE1-2 may be defined in the first light shielding layer SHL 1'. Accordingly, the first light shielding layer SHL1' may be disposed so as not to overlap the first-second connection electrode CNE1-2 when viewed in a plane.
Referring to fig. 20 and 21, the data line DL may be disposed on the third insulating layer INS 3. The first light shielding layer SHL1' and the second power line PL2 may be disposed on the third insulating layer INS 3. The fourth insulating layer INS4 may be disposed on the third insulating layer INS3 to cover the data line DL, the first light shielding layer SHL1', and the second power line PL2. The first power line PL1' may be disposed on the fourth insulating layer INS 4.
The data line DL may be connected to the source region SC via first-first contact holes CH1-1 defined through the first, second, and third insulating layers INS1, INS2, and INS3, and may be connected to the first metal ME1 via first-second contact holes CH1-2 defined through the third insulating layer INS 3.
The first power line PL1' may be connected to the drain region DR via first-third contact holes CH1-3 defined through the first through fourth insulating layers INS1 through INS4, and may be connected to the second metal ME2 via first-fourth contact holes CH1-4 defined through the third and fourth insulating layers INS3 and INS 4.
The first light shielding layer SHL1' may be disposed on the third insulating layer INS3, and may block light from traveling to the semiconductor layer SML. Since the first light shielding layer SHL1 'is not disposed on the fourth insulating layer INS4, a groove GV through which the GAS generated from the fourth insulating layer INS4 is discharged may not be defined in the first light shielding layer SHL1' (refer to fig. 18).
Fig. 22 is a plan view of the structure of an antistatic circuit asc″ according to an embodiment of the present disclosure.
As an example, fig. 22 is a plan view corresponding to the plan view of fig. 14, and hereinafter, in fig. 22, features different from those of the antistatic circuit ASC shown in fig. 14 will be described, which will concentrate on the antistatic circuit ASC ".
Referring to fig. 22, the first light shielding layer SHL1″ of the antistatic circuit asc″ may not overlap the first-second connection electrodes CNE1-2, and may not define the grooves GV and GV'. The first light shielding layer SHL1″ may be disposed to overlap at least the channel region CA to block light incident on the channel region CA of the semiconductor layer SML.
Although the embodiments of the present disclosure have been described, it should be understood that the present disclosure should not be limited to these embodiments, but various changes and modifications can be made by one of ordinary skill in the art within the spirit and scope of the present disclosure as hereinafter claimed. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the inventive concept should be determined from the claims.

Claims (17)

1. A display device, comprising:
a data line;
a first power line;
a second power line;
a pixel disposed in the display region and connected to the data line, the first power line, and the second power line;
a transistor disposed in a non-display region located around the display region and connected to the data line and the first power line; and
and a first light shielding layer extending from a portion of the second power supply line to the transistor and disposed on the transistor.
2. The display device according to claim 1, wherein the transistor is provided between the data line and the second power supply line.
3. The display device of claim 1, wherein the first light shielding layer comprises at least one groove defined in one side of the first light shielding layer.
4. A display device according to claim 3, wherein the one side of the first light shielding layer faces the data line.
5. The display device according to claim 1, wherein the first power supply line is provided on a layer different from a layer on which the second power supply line and the data line are provided.
6. The display device according to claim 1, further comprising:
An interlayer insulating layer covering the transistor; and
a planarization insulating layer disposed on the interlayer insulating layer,
wherein the first power line is disposed on the interlayer insulating layer, the planarization insulating layer covers the first power line, and the second power line and the data line are disposed on the planarization insulating layer.
7. The display device according to claim 1, wherein the transistor comprises:
a semiconductor layer including a source region connected to the data line, a drain region connected to the first power line, and a channel region disposed between the source region and the drain region; and
and a gate electrode disposed on the semiconductor layer and overlapping the channel region when viewed in a plane.
8. The display device according to claim 7, wherein the first light shielding layer overlaps with the channel region when viewed in the plane.
9. The display device according to claim 7, further comprising:
a first metal disposed on the gate electrode and connected to the data line; and
a second metal disposed on the gate electrode and connected to the first power line.
10. The display device according to claim 9, wherein the first light shielding layer overlaps with a portion of the gate electrode and a portion of the first metal and a portion of the second metal when viewed in the plane.
11. The display device according to claim 7, further comprising:
and a second light shielding layer disposed under the semiconductor layer and overlapping the channel region.
12. The display device according to claim 11, wherein the second light shielding layer is connected to the gate electrode.
13. The display device according to claim 12, further comprising:
a connection electrode disposed on the gate electrode and the second light shielding layer; and
and an insulating layer disposed between the gate electrode and the connection electrode and between the second light shielding layer and the connection electrode, wherein the connection electrode is connected to the gate electrode and the second light shielding layer via a contact hole defined through the insulating layer.
14. The display device according to claim 13, wherein the first light shielding layer overlaps with the connection electrode when viewed in the plane.
15. The display device according to claim 13, wherein the first light-shielding layer does not overlap with the connection electrode when viewed in the plane.
16. The display device according to claim 1, further comprising:
an interlayer insulating layer covering the transistor; and
A planarization insulating layer disposed on the interlayer insulating layer,
wherein the second power line and the data line are disposed on the interlayer insulating layer, the planarization insulating layer covers the second power line and the data line, and the first power line is disposed on the planarization insulating layer.
17. The display device according to any one of claims 1 to 16, wherein the first power supply line receives a first voltage, and the second power supply line receives a second voltage having a level lower than that of the first voltage.
CN202310190157.4A 2022-04-06 2023-03-02 display device Pending CN116896920A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2022-0042870 2022-04-06
KR1020220042870A KR20230144155A (en) 2022-04-06 2022-04-06 Display device

Publications (1)

Publication Number Publication Date
CN116896920A true CN116896920A (en) 2023-10-17

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Application Number Title Priority Date Filing Date
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US (1) US20230329046A1 (en)
KR (1) KR20230144155A (en)
CN (1) CN116896920A (en)

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US20230329046A1 (en) 2023-10-12

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