CN116895692A - Semiconductor assembly and method for manufacturing the same - Google Patents
Semiconductor assembly and method for manufacturing the same Download PDFInfo
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- CN116895692A CN116895692A CN202211550535.7A CN202211550535A CN116895692A CN 116895692 A CN116895692 A CN 116895692A CN 202211550535 A CN202211550535 A CN 202211550535A CN 116895692 A CN116895692 A CN 116895692A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 163
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 55
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 210000000746 body region Anatomy 0.000 claims description 67
- 238000002955 isolation Methods 0.000 claims description 30
- 229910044991 metal oxide Inorganic materials 0.000 claims description 20
- 150000004706 metal oxides Chemical class 0.000 claims description 20
- 238000005530 etching Methods 0.000 claims description 16
- 125000006850 spacer group Chemical group 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 7
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 4
- 230000010354 integration Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 118
- 239000011229 interlayer Substances 0.000 description 10
- 238000009792 diffusion process Methods 0.000 description 9
- 238000009826 distribution Methods 0.000 description 9
- 230000015556 catabolic process Effects 0.000 description 8
- 238000005468 ion implantation Methods 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 8
- 229920005591 polysilicon Polymers 0.000 description 8
- 238000005137 deposition process Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 5
- 239000002019 doping agent Substances 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/404—Multiple field plate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66704—Lateral DMOS transistors, i.e. LDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Abstract
The invention discloses a semiconductor component and a manufacturing method thereof. The substrate has a first conductivity type, the well region has a second conductivity type and is arranged on the substrate, the first groove and the second groove are arranged in the well region, the first groove is internally provided with a first field plate and a first dielectric layer which surround the first field plate, the second groove is internally provided with a second field plate and a second dielectric layer which surround the second field plate, the first grid is arranged above the first field plate, the source electrode is arranged on the first side of the first groove, the drain electrode is arranged on the second side of the second groove, and the source electrode, the first groove, the second groove and the drain electrode are sequentially arranged along the first direction.
Description
Technical Field
The present invention relates generally to integrated circuit technology, and more particularly to an integrated circuit structure including a lateral diffusion trench type metal oxide semiconductor device and a method of fabricating the same.
Background
Metal-oxide semiconductor field effect transistor (MOSFET) is the most commonly used component in integrated circuits, and includes horizontal structures such as laterally diffused metal-oxide semiconductor (LDMOS) Field Effect Transistors (FETs), and vertical structures such as planar gate MOSFET (planar gate MOSFET) and trench gate MOSFET (trench gate MOSFET). In order to achieve the high voltage resistance effect, the lengths of a field plate (field plate) and a drift region (drift region) may be enlarged in a laterally diffused metal oxide semiconductor field effect transistor, or the depth of a trench may be enlarged in a trench type gate metal oxide semiconductor field effect transistor, however, these methods may cause problems such as an increase in the size of a device, incompatibility with other devices, and increase in process difficulty, so that there is a need in the industry for a metal oxide semiconductor device capable of meeting various requirements in an integrated circuit.
Disclosure of Invention
In view of the above, the present invention provides an integrated circuit structure including a lateral diffusion trench type metal oxide semiconductor device and a method for fabricating the same, which can simultaneously form a lateral diffusion trench type metal oxide semiconductor (LDMOS) device, a Lateral Diffusion Metal Oxide Semiconductor (LDMOS) device and a Complementary Metal Oxide Semiconductor (CMOS) device on the same semiconductor substrate by using a Bipolar-CMOS-DMOS (BCD) technology, and can reduce the trench depth, improve the process difficulty, increase the breakdown voltage, reduce the on-resistance, etc. of the lateral diffusion trench type metal oxide semiconductor device.
According to an embodiment of the present invention, a semiconductor device is provided, which includes a substrate, a well region, a first trench, a second trench, a first gate, a source electrode, and a drain electrode. The substrate has a first conductivity type, the well region has a second conductivity type and is arranged on the substrate, the first groove and the second groove are arranged in the well region, the first groove is internally provided with a first field plate and a first dielectric layer which surround the first field plate, the second groove is internally provided with a second field plate and a second dielectric layer which surround the second field plate, the first grid is arranged above the first field plate, the source electrode is arranged on the first side of the first groove, the drain electrode is arranged on the second side of the second groove, and the source electrode, the first groove, the second groove and the drain electrode are sequentially arranged along the first direction.
According to an embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, including the steps of: providing a substrate having a first conductivity type; forming a well region with a second conductivity type on the substrate; forming a first trench and a second trench in the well region; depositing a dielectric layer in the first groove and the second groove in a forward direction, and filling a conductive layer on the dielectric layer; etching the conductive layers in the first trench and the second trench to form a first recess on the first field plate and a second recess on the second field plate, respectively; filling dielectric materials in the first recess and the second recess to form a first dielectric isolation part and a second dielectric isolation part respectively; etching the dielectric layer and the first dielectric isolation part in the first groove to form a first groove; forming a first grid electrode in the first groove; and forming a source region and a drain region in the well region, wherein the source region is located at a first side of the first trench and the drain region is located at a second side of the second trench.
Drawings
For easier understanding, reference is made to the drawings and their detailed description when reading the present invention. Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the various elements of the invention. Moreover, for the sake of clarity, various features in the drawings may not be drawn to actual scale, and thus the dimensions of some features in some of the drawings may be exaggerated or reduced on purpose.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.
Fig. 3 is a schematic perspective view and a schematic sectional view of a partial region of a semiconductor device according to another embodiment of the present invention.
Fig. 4 is a schematic perspective view of a semiconductor device according to another embodiment of the invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.
FIG. 7 is a schematic cross-sectional view of a semiconductor device in a conductive state according to an embodiment of the present invention
Fig. 8 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.
Fig. 9 is a schematic cross-sectional view of a semiconductor device in an on-state according to another embodiment of the present invention.
Fig. 10 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.
Fig. 11 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention.
Fig. 12, 13, 14, 15 and 16 are schematic cross-sectional views of stages of a method of fabricating an integrated circuit structure according to an embodiment of the present invention, including three discrete semiconductor device regions.
Fig. 17 is a schematic cross-sectional view of a stage of a method of fabricating an integrated circuit structure according to another embodiment of the invention, wherein two rows of doped regions are included under a trench.
Fig. 18 is a schematic cross-sectional view of a stage of a method of fabricating an integrated circuit structure according to another embodiment of the invention, wherein more than four rows of doped regions are included under the trench.
Fig. 19 is a schematic cross-sectional view of a stage of a method of fabricating an integrated circuit structure according to another embodiment of the invention, wherein doped regions laterally adjacent to each other are included under trenches.
Fig. 20 is a schematic diagram showing the distribution of voltage equipotential lines in the off state and the on state of a semiconductor device according to an embodiment of the present invention.
Wherein reference numerals are as follows:
100. 100-1, 100-2, 100-3, 100-4, 200, 300 … semiconductor assembly
101 … substrate
102 … buried layer
103 … well region
104 … epitaxial layer
105-1 … first groove
105-2 … second groove
105-3 … third groove
105-4 … fourth groove
105-5 … fifth groove
106 … dielectric layer
106-1 … first dielectric layer
106-2 … second dielectric layer
106-3 … third dielectric layer
106-4 … fourth dielectric layer
107 … conductive layer
107-1 … first field plate
107-2 … second field plate
107-3 … third field plate
107-4 … fourth field plate
108-1 … first dielectric spacer
108-2 … second dielectric spacer
108-3 … third dielectric spacer
109-1 … first grid
109-2 … second grid
109C … gate connection
110 … current path
111 … source electrode
111S … Source region
113 … drain electrode
113D … drain region
115 … field plate contact
116 … interconnect structure
117-1 … first matrix region
117-2 … second matrix region
118 … heavily doped region
119 … gate contact
120 … interlayer dielectric layer
121 … epitaxial layer
123. 151, 153, … well region
125. 145 … patterned hard mask
127-1 … first recess
127-2 … second recess
127-3 … third recess
129. 131 … groove
135. 137 … shallow trench isolation structure
141. 143 … doped region
147-1 … first groove
147-2 … second groove
155 … gate dielectric layer
157. 159 … gate
161S, 163S, 165S … source regions
161D, 163D, 165D … drain region
171. 181, 191 and … source electrode
173. 183, 193 … drain electrode
179. 189, 199, … gate contact
202a … first row
204a … second row
202b … third line
204b … fourth row
202a-1, 202a-2, 202a-3, 202a-4, 202a-5, … first doped region
202b-1, 202b-2, 202b-3, 202b-4, 202b-5, … first doped region
204a-1, 204a-2, 204a-3, 204a-4, 204a-5, … second doped region
204b-1, 204b-2, 204b-3, 204b-4, 204b-5, … second doped region
210 … inversion layer
230. 230-1, 230-2 … current
240-1 … first initiation region
240-2 … second initiation region
400-1, 400-2, 400-3, 400-4, 400-5 and … cross-sectional structures
1000 … first region
2000 … second region
3000 … third region
10 … first side
20 … second side
Depth of H1, H2 …
Steps S101, S103, S105, S107, S109, S111, S113, S115, S117 and 117 …
100-off, 100-on … voltage equipotential line distribution
a-a … section tangent
Detailed Description
The invention provides several different embodiments that can be used to implement different features of the invention. For simplicity of explanation, the invention also describes examples of specific components and arrangements. These examples are provided for the purpose of illustration only and are not intended to be limiting in any way. For example, the following description of a first feature being formed on or over a second feature may refer to "the first feature being in direct contact with the second feature" or may refer to "there being other features between the first feature and the second feature" such that the first feature and the second feature are not in direct contact. Furthermore, various embodiments of the present invention may use repeated reference characters and/or textual notations. These repeated reference characters and notations are used to make the description more concise and clear, rather than to indicate a relationship between different embodiments and/or configurations.
In addition, for the spatially related narrative terms mentioned in the present invention, for example: "under …", "low", "lower", "above", "over", "upper", "top", "bottom" and the like are used for ease of description to describe one component or feature's relative to another component(s) or feature(s) in the figures. In addition to the orientation shown in the drawings, these spatially dependent terms are also used to describe possible orientations of the semiconductor device in use and operation. With the semiconductor device oriented differently (rotated 90 degrees or other orientations), the spatially relative descriptors describing its orientation should be interpreted in a similar manner.
Although the invention has been described in the language of first, second, third, etc., to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section, which does not itself connote or imply any preceding ordinal number or order of arrangement of elements or methods of manufacture. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of embodiments of the present invention.
The term "about" or "substantially" as referred to herein generally means within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the amounts provided in the specification are about amounts, i.e., without a specific recitation of "about" or "substantially," what is meant by "about" or "substantially" may still be implied.
The terms "coupled," "coupled," and "electrically connected," as used herein, encompass any direct or indirect means of electrical connection. For example, if a first element is coupled to a second element, that connection may be directly to the second element or indirectly to the second element through other means of attachment or connection.
While the invention is described below with respect to specific embodiments, the principles of the invention are applicable to other embodiments. Furthermore, specific details are omitted so as not to obscure the spirit of the present invention, and the omitted details are within the knowledge of those skilled in the art.
The invention relates to an integrated circuit structure comprising a lateral diffusion trench type metal oxide semiconductor (LDMOS) component and a manufacturing method thereof, which can simultaneously form the lateral diffusion trench type metal oxide semiconductor (trench LDMOS) component, the Lateral Diffusion Metal Oxide Semiconductor (LDMOS) component and a Complementary Metal Oxide Semiconductor (CMOS) component on the same semiconductor substrate by using a power integrated circuit process integration technology (Bipolar-CMOS-DMOS, and enable the lateral diffusion trench type metal oxide semiconductor component to achieve the effects of reducing the trench depth, improving the process difficulty, improving the breakdown voltage, reducing the on-resistance and the like.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention. As shown in fig. 1, in one embodiment, the semiconductor device 100 includes a substrate 101 having a first conductivity type, such as a p-type silicon substrate, a well region 103 disposed on the substrate 101, the well region 103 having a second conductivity type opposite to the first conductivity type, such as a deep N-type well (DNW) or an N-epi (N-epi) silicon. The semiconductor device 100 further includes a first trench 105-1 and a second trench 105-2 disposed in the well region 103, wherein a first field plate 107-1 and a first dielectric layer 106-1 are disposed in the first trench 105-1 around the first field plate 107-1, and a second field plate 107-2 and a second dielectric layer 106-2 are disposed in the second trench 105-2 around the second field plate 107-2. In this embodiment, the first gate 109-1 is also disposed in the first trench 105-1 and is located above the first field plate 107-1, the first gate 109-1 and the first field plate 107-1 are separated by the first dielectric isolation portion 108-1, the first dielectric isolation portion 108-1 covers the first field plate 107-1, the first gate 109-1 may be disposed in the first dielectric isolation portion 108-1, and when viewed along a direction perpendicular to the surface of the substrate 101 (e.g. along the Z-axis direction), the first gate 109-1 and the first field plate 107-1 may not be aligned with each other, so as to generate a misalignment, for example, the first gate 109-1 may be offset to the right (e.g. along the X-axis direction) compared to the first field plate 107-1. In some embodiments, the first gate 109-1, the first field plate 107-1, and the second field plate 107-2 may be formed of the same conductive material, such as polysilicon, doped polysilicon, metal silicide, metal, or other conductive material, and the first dielectric layer 106-1, the second dielectric layer 106-2, and the first dielectric spacer 108-1 may also be formed of the same dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric material.
In addition, the semiconductor device 100 further includes a first body region 117-1 disposed on the first side 10 of the first trench 105-1, a second body region 117-2 disposed between the first trench 105-1 and the second trench 105-2, the first body region 117-1 and the second body region 117-2 having a first conductivity type, such as p-body regions (p-bodies), and the first body region 117-1 and the second body region 117-2 having a dopant concentration of the first conductivity type dopant greater than a dopant concentration of the second conductivity type dopant of the well region 103. The first body region 117-1 and the second body region 117-2 are formed in the well region 103 near the top surface of the well region 103, and the bottom surfaces of the first body region 117-1 and the second body region 117-2 are both higher than the top surface of the first field plate 107-1. The semiconductor device 100 further includes a source region 111S disposed in the first body region 117-1 and adjacent to a top surface of the first body region 117-1, and a drain region 113D disposed in the well region 103 on the second side 20 of the second trench 105-2 and adjacent to a top surface of the well region 103. In addition, the semiconductor device 100 further includes an interlayer dielectric layer 120 covering the well region 103. The source electrode 111 extends through the interlayer dielectric layer 120 and down into the first body region 117-1, and is electrically coupled to the source region 111S in an adjacent manner. The drain electrode 113 extends through the interlayer dielectric layer 120 and down into the well region 103, and is electrically coupled to the drain region 113D adjacent thereto. The field plate contact (field plate contact) 115 extends through the interlayer dielectric 120 and downward into the second body region 117-2 and is electrically coupled to the second body region 117-2. In this embodiment, the source electrode 111 is disposed on the first side 10 of the first trench 105-1, the drain electrode 113 is disposed on the second side 20 of the second trench 105-2, and the source electrode 111, the first trench 105-1, the second trench 105-2 and the drain electrode 113 are sequentially arranged along the first direction (e.g. from right to left along the X-axis direction). Further, in some embodiments, the potential of the first field plate 107-1 may be the same as the potential of the first gate 109-1 (e.g., both positive potentials), or the potential of the first field plate 107-1 may be the same as the potential of the source electrode 111 (e.g., both ground potentials).
Referring to fig. 1 and 20, according to an embodiment of the present invention, a gate dielectric layer 155 is disposed between the first gate 109-1 and the first body region 117-1, so that when a specific bias (e.g., positive potential) is applied to the first gate 109-1, the conductivity of the first body region 117-1 adjacent to the gate dielectric layer is increased to form a conductive channel. According to one embodiment of the present invention, when the first gate 109-1 is biased (e.g., positive potential), a conduction channel is formed in the first body region 117-1, and when the first field plate 107-1 and the second field plate 107-2 are biased, the electric field distribution or potential distribution in the well region 103 surrounding the first trench 105-1 and the second trench 105-2 can be adjusted while avoiding the generation of high-strength electric field in the local region. Thus, during operation of the semiconductor device 100, current is allowed to flow from the drain electrode 113 down the second side 20 of the second trench 105-2 to under the second trench 105-2, then under the first trench 105-1, then up the first side 10 of the first trench 105-1 through the conductive via in the first body region 117-1, and finally to the source electrode 111, such that the semiconductor device 100 of the present invention has a U-shaped current path 110. In addition, with respect to the second body region 117-2 disposed between the first trench 105-1 and the second trench 105-2, since the conductivity type of the second body region 117-2 is different from the conductivity type of the well region 103, during operation of the semiconductor device 100, current does not flow from the well region 103 into the second body region 117-2, and a potential is applied to the second body region 117-2 via the field plate contact 115, it is also possible to regulate the electric field distribution or the potential distribution in the well region 103 below the second body region 117-2. The embodiment of the present invention utilizes the PN junction (PN junction) between the substrate 101 and the well 103, so that the first side 10 of the first trench 105-1 and the second side 20 of the second trench 105-2 can both disperse the voltage, thereby achieving the effect that the voltage drop is more evenly distributed on the current path. In addition, even though the depths of the first trench 105-1 and the second trench 105-2 are reduced, the semiconductor device 100 can achieve the same withstand voltage capability achieved by only a single deep trench. According to the embodiment of the invention, since the first trench 105-1 and the second trench 105-2 have reduced depths, not only the process difficulty of the semiconductor device 100 can be reduced, but also the stress of the deep trench on the wafer during the process of manufacturing the semiconductor device can be reduced, thereby being beneficial to integrated circuit process integration (BCD) and improving the process yield.
Fig. 2 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. As shown in fig. 2, in an embodiment, the semiconductor device 100 may further include a buried layer 102 disposed under the well region 103, for example, between the well region 103 and the substrate 101, wherein the buried layer 102 has a second conductivity type, for example, an n-type buried layer (n-type buried layer, NBL). In this embodiment, the semiconductor device 100 further includes a third trench 105-3 and a fourth trench 105-4, and the first trench 105-1, the second trench 105-2, the third trench 105-3 and the fourth trench 105-4 are all disposed in the well region 103 and extend downward into the buried layer 102, but do not penetrate the bottom surface of the buried layer 102. In the second trench 105-2, the second dielectric isolation portion 108-2 covers the second field plate 107-2, the third trench 105-3 is provided therein with the third field plate 107-3 and the third dielectric layer 106-3 surrounding the third field plate 107-3, the second gate 109-2 is disposed in the third trench 105-3 and is separated from the third field plate 107-3 by the third dielectric isolation portion 108-3, the third dielectric isolation portion 108-3 covers the third field plate 107-3, the second gate 109-2 is disposed in the third dielectric isolation portion 108-3, and when viewed along a direction (e.g., Z-axis direction) perpendicular to the surface of the substrate 101, the second gate 109-2 and the third field plate 107-3 may not be aligned with each other, e.g., the second gate 109-2 may be offset to the left as compared to the third field plate 107-3. In addition, a gate dielectric layer 155 is present between the second gate 109-2 and the first body region 117-1. The fourth trench 105-4 is provided with a fourth field plate 107-4 and a fourth dielectric layer 106-4 surrounding the fourth field plate 107-4, the source electrode 111 is disposed between the first trench 105-1 and the third trench 105-3, the drain electrode 113 is disposed between the fourth trench 105-4 and the second trench 105-2, and the third trench 105-3, the source electrode 111, the first trench 105-1, the second trench 105-2, the drain electrode 113 and the fourth trench 105-4 are sequentially arranged along a first direction (e.g., from right to left along an X-axis direction). In this embodiment, the top surface of the fourth field plate 107-4 is higher than the top surfaces of the first field plate 107-1, the second field plate 107-2, and the third field plate 107-3. In other embodiments, the top surface of the fourth field plate 107-4 may be at the same level as the top surfaces of the first field plate 107-1, the second field plate 107-2, and the third field plate 107-3. In addition, a gate contact 119 penetrates the interlayer dielectric layer 120 and is electrically coupled to the first gate 109-1. Other components of the semiconductor assembly 100 of fig. 2 may be referred to in fig. 1 with the same reference numerals and their description will not be repeated here.
Fig. 3 is a schematic perspective view and a schematic sectional view of a partial region of a semiconductor device according to another embodiment of the present invention. As shown in fig. 3, in one embodiment, the semiconductor device 100 includes a third trench 105-3, a first trench 105-1, a second trench 105-2, and a fourth trench 105-4 sequentially arranged along a first direction (e.g., along an X-axis direction from right to left), the trenches are disposed in the well region 103, and each of the third trench 105-3, the first trench 105-1, the second trench 105-2, and the fourth trench 105-4 includes a third field plate 107-3, a first field plate 107-1, a second field plate 107-2, and a fourth field plate 107-4, which are surrounded by a third dielectric layer 106-3, the first dielectric layer 106-1, the second dielectric layer 106-2, and the fourth dielectric layer 106-4. Furthermore, in some embodiments, the top surface of the fourth field plate 107-4 may be higher than the top surfaces of the first field plate 107-1, the second field plate 107-2, and the third field plate 107-3, the first dielectric spacer 108-1 overlies the first field plate 107-1, the third dielectric spacer 108-3 overlies the third field plate 107-3, and the top surfaces of the first dielectric spacer 108-1 and the third dielectric spacer 108-3 may be flush with the top surface of the fourth field plate 107-4.
In addition, the semiconductor device 100 of fig. 3 further includes a first gate 109-1 disposed on the top surface of the first dielectric isolation portion 108-1, a second gate 109-2 disposed on the top surface of the third dielectric isolation portion 108-3, and long axes of the first gate 109-1 and the second gate 109-2 extending substantially along a second direction (e.g., Y-axis direction), wherein in this embodiment, the first gate 109-1 and the second gate 109-2 are both located on the well region 103. The semiconductor device 100 of fig. 3 further includes a gate connection portion 109C extending from a sidewall of the first gate 109-1 along a first direction (e.g., an X-axis direction) and protruding from the sidewall of the first gate 109-1, wherein the gate connection portion 109C extends to a sidewall of the second gate 109-2, and the gate connection portion 109C is also disposed on the well 103. As shown in fig. 3, the first gate electrode 109-1, the second gate electrode 109-2, and the gate connection portion 109C may constitute an H-type structure on the XY plane, the gate connection portion 109C is disposed between the first gate electrode 109-1 and the second gate electrode 109-2, and spacers may be disposed on respective two opposite outer sidewalls of the first gate electrode 109-1, the second gate electrode 109-2, and the gate connection portion 109C.
In addition, fig. 3 also shows a schematic cross-sectional view of a partial region of the semiconductor device 100 along the cross-sectional line a-a, as shown in fig. 3, the semiconductor device 100 further includes a body region, such as a first body region 117-1, disposed under the gate connection portion 109C, and the first body region 117-1 extends from under one side of the gate connection portion 109C along a second direction (e.g., Y-axis direction) and protrudes between the first trench 105-1 and an upper region of the third trench 105-3. The semiconductor device 100 further includes a second body region 117-2 between the first trench 105-1 and the second trench 105-2, wherein the first body region 117-1 and the second body region 117-2 are both of a first conductivity type, such as a p-type body region, and are both disposed in the well region 103 of a second conductivity type. In addition, the semiconductor device 100 further includes a source region 111S located between the first trench 105-1, the third trench 105-3 and the gate connection portion 109C, and three sides of the source region 111S are adjacent to the first trench 105-1, the third trench 105-3 and the gate connection portion 109C, respectively. In addition, a heavily doped region 118 of the first conductivity type, such as a P-type heavily doped region (p+ region), may be disposed in the first body region 117-1, which may have a dopant concentration greater than that of the first body region 117-1. Heavily doped region 118 adjoins source region 111S, and first body region 117-1 extends below source region 111S and heavily doped region 118. In operation of the semiconductor device 100, the heavily doped region 118 and the source region 111S may be electrically coupled to the same potential (e.g., ground potential), but are not limited thereto.
As shown in fig. 3, the semiconductor device 100 further includes a drain region 113D located between the second trench 105-2 and the fourth trench 105-4 and disposed in the well region 103. The drain region 113D and the source region 111S are doped regions of the second conductivity type, for example, n-type doped regions. In this embodiment, the first gate 109-1, the second gate 109-2 and the gate connection 109C are planar gate structures, and the first gate 109-1, the second gate 109-2 and the gate connection 109C may be formed from polysilicon, doped polysilicon, metal or other conductive material simultaneously using deposition, photolithography and etching processes. In addition, the long axis extending direction (second direction, for example, Y-axis direction) of the first gate electrode 109-1 and the second gate electrode 109-2 may have an angle of non-zero degrees, for example, an angle of about 90 degrees, with the long axis extending direction (first direction, for example, X-axis direction) of the gate connection portion 109C, but is not limited thereto. In the embodiment of fig. 3, the channel region of the semiconductor device 100 is located under the planar gate structure formed by the gate connection portion 109C and is located in the first body region 117-1 under the gate connection portion 109C, and either one of the first gate 109-1 and the second gate 109-2 may be used as a conductive line structure for transmitting electrical signals to the gate connection portion 109C. According to the embodiment of the invention, since the first gate 109-1 and the second gate 109-2 are disposed directly above the first trench 105-1 and the third trench 105-3, respectively, and may extend along the same direction (e.g., Y-axis direction) as the corresponding trenches, the first gate 109-1 and the second gate 109-2 may be prevented from occupying additional wafer area. In addition, other components of the semiconductor assembly 100 of fig. 3 may refer to the related description of the components having the same reference numerals in fig. 1 and are not repeated here.
Fig. 4 is a schematic perspective view of a semiconductor device according to another embodiment of the invention. As shown in fig. 4, in this embodiment, the first gate 109-1 and the first field plate 107-1 of the semiconductor device 100 are connected to each other without being separated by a dielectric spacer (not shown), and the first gate 109-1 and the first field plate 107-1 are respectively formed by different regions of the same conductive layer in the first trench 105-1, for example, polysilicon, doped polysilicon, metal silicide, metal or other conductive material, and the potential of the first field plate 107-1 may be the same as the potential of the first gate 109-1 (for example, both positive potentials). In this embodiment, the first body region 117-1 and the second body region 117-2 are disposed in the well region 103 along two opposite sides of the first trench 105-1, the first body region 117-1 abuts one side of the first trench 105-1, the second body region 117-2 abuts the other side of the first trench 105-1, the second body region 117-2 is located between the first trench 105-1 and the second trench 105-2, and the first body region 117-1 and the second body region 117-2 are both of the first conductivity type, such as a p-type body region. In some embodiments, both the first body region 117-1 and the second body region 117-2 extend downward from the top surface height of the first trench 105-1 by a depth H1, the depth H1 being, for example, about 0.3 micrometers (μm) to 2 μm, and the depth H2 of the first trench 105-1 being, for example, about 0.5 micrometers (μm) to 10 μm. In some embodiments, the depth H1 of the first body region 117-1 and the second body region 117-2 may be about 3% to 60% of the depth H2 of the first trench 105-1, but is not limited thereto. In the embodiment of fig. 4, a channel region (not shown) of the semiconductor device 100 is located at a side of the first gate 109-1 within the first trench 105-1 and is located in the first body region 117-1. In addition, other components of the semiconductor assembly 100 of fig. 4 may refer to the related description of the components having the same reference numerals in fig. 1 and are not repeated here.
Fig. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. As shown in fig. 5, in one embodiment, the semiconductor device 100 may include an epitaxial layer 104 of a first conductivity type, such as a p-type epitaxial layer, disposed on a substrate 101 of the first conductivity type, and a well region 103 of a second conductivity type, such as an n-type well region, disposed in the epitaxial layer 104. In this embodiment, the semiconductor device 100 uses the drain electrode 113 as a mirror symmetry center, and the second trench 105-2, the second body region 117-2, the first trench 105-1, the first body region 117-1 and the third trench 105-3 are sequentially arranged along the first direction (e.g., the X-axis direction) towards the right and the left, the source region 111S is disposed in the first body region 117-1, and the drain region 113D is disposed between two adjacent second trenches 105-2. The first gate 109-1, the first field plate 107-1, and the first dielectric layer 106-1 are disposed within the first trench 105-1. The second gate 109-2, the third field plate 107-3, and the third dielectric layer 106-3 are disposed within the third trench 105-3. A gate dielectric layer 155 is present between the first gate 109-1 and the first body region 117-1, the source region 111S, and another gate dielectric layer 155 is also present between the second gate 109-2 and the first body region 117-1, the source region 111S. A second field plate 107-2 and a second dielectric layer 106-2 are disposed within the second trench 105-2. In addition, the second field plate 107-2 and the second body region 117-2 may be electrically coupled to an interconnection structure (interconnect) 116 such that the second field plate 107-2 and the second body region 117-2 are electrically coupled to each other. The source electrode 111, the drain electrode 113, the gate contact 119 and the interconnect structure 116 are all disposed in the interlayer dielectric layer 120, the source electrode 111 is electrically coupled to the source region 111S, the drain electrode 113 is electrically coupled to the drain region 113D, and the two gate contacts 119 are electrically coupled to the first gate 109-1 and the second gate 109-2, respectively, and other parts of the semiconductor device 100 of fig. 5 may be referred to as related descriptions of the parts having the same reference numerals in fig. 2 and will not be repeated herein.
Fig. 6 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. As shown in fig. 6, in one embodiment, the semiconductor device 100-1 not only includes the first trench 105-1 to the fourth trench 105-4 as shown in fig. 2, but also includes the fifth trench 105-5 disposed between the first trench 105-1 and the second trench 105-2. The fifth trench 105-5 is disposed in the well region 103, and for the semiconductor device 100-1 having the buried layer 102, the bottom of the fifth trench 105-5 extends further into the buried layer 102.
Underneath each trench 105-1-105-5 there may be a pair of doped regions of differing conductivity types, such as first doped regions 202a-1, 202a-2, 202a-3, 202a-4, 202a-5 of the second conductivity type and second doped regions 204a-1, 204a-2, 204a-3, 204a-4, 204a-5 of the first conductivity type. According to an embodiment, the first doped regions 202a-1, 202a-2, 202a-5 are located in the buried layer 102, and the first doped regions 202a-1, 202a-2, 202a-5 are disposed under the first trench 105-1, the second trench 105-2 and the fifth trench 105-5, respectively. The first doped regions 202a-1, 202a-2, 202a-5 may be located at substantially the same depth and aligned in a first row 202a. The second doped regions 204a-1, 204a-2, 204a-5 are located in the buried layer 102, and the second doped regions 204a-1, 204a-2, 204a-5 are disposed below the first doped regions 202a-1, 202a-2, 202a-5, respectively. The second doped regions 204a-1, 204a-2, 204a-5 may be located at substantially the same depth and arranged in a second row 202b. According to an embodiment of the present invention, the projections of the first doped regions 202a-1, 202a-2, 202a-5 partially overlap the projections of the first, second and fifth trenches 105-1, 105-2, 105-5, respectively, and the projections of the second doped regions 204a-1, 204a-2, 204a-5 partially overlap the projections of the first, second and fifth trenches 105-1, 105-2, 105-5, respectively, as viewed along the depth direction (e.g., Z-axis direction) of the trenches 105-1-105-5.
According to an embodiment of the present invention, each of the first doped regions 202a-1 to 202a-5 located in the first row 202a is adjacent to each of the second doped regions 204a-1 to 204a-5 located in the second row 202b such that adjacent ones of the first doped regions 202a-1 to 202a-5 and the second doped regions 204a-1 to 204a-5 are in contact with each other, and a ratio between widths (i.e., dimensions along the X direction) of the first doped regions 202a-1 to 202a-5 and the adjacent ones of the second doped regions 204a-1 to 204a-5 is between 0.5 and 2, for example, between 0.9 and 1.1. The average doping concentration of the first doped regions 202a-1 to 202a-5 and/or the average doping concentration of the second doped regions 204a-1 to 204a-5 may be higher than the doping concentrations of the buried layer 102 and the well region 103. The ratio between the average doping concentration of the first doped regions 202a-1 to 202a-5 and the average doping concentration of the second doped regions 204a-1 to 204a-5 is between 0.1 and 10, for example between 0.9 and 1.1. By properly adjusting the width relationship and the doping concentration relationship between the first doped regions 202a-1 to 202a-5 and the second doped regions 204a-1 to 204a-5, the first doped regions 202a-1 to 202a-5 of the first row 202a and the second doped regions 204a-1 to 204a-5 of the second row 202b form a super junction (super junction) like structure, which is beneficial to further reducing the on-resistance (R) of the semiconductor device 100-1 ON ) And increasing the breakdown voltage (V) BR )。
Fig. 7 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention in a conductive state. As shown in fig. 7, taking the semiconductor device 100-1 as an example, when the first gate electrode109-1 are biased in an on state such that a portion of current 230 flows from the source region (not shown) through the well region 103, the buried layer 102, the first doped region 202a-1, the buried layer 102, the first doped region 202a-5, the buried layer 102, the first doped region 202a-2, the buried layer 102, the well region 103, and finally reaches the drain region 113D (not shown). Since the first doped regions 202a-1, 202a-2, 202a-5 have the same conductivity type as the buried layer 102 and the average doping concentration of the first doped regions 202a-1, 202a-2, 202a-5 is higher than that of the buried layer 102, the semiconductor device 100-1 may have a lower on-resistance (R ON ). According to one embodiment, when the semiconductor device 100-1 is in the on state, the field plates in the trenches 105-1-105-5 may also be biased (e.g., forward biased) simultaneously, such that the inversion layer 210 is generated under the trenches 105-1-105-5. Since the inversion layer 210 has a lower resistance than the well region 103, when a portion of the current from the source region flows through the inversion layer 210, a smaller voltage drop is generated and a lower on-Resistance (RON) is provided.
On the other hand, when the semiconductor device 100-1 is in the off state, depletion regions are generated in the first doped regions 202a-1, 202a-2, 202a-5 and the adjacent second doped regions 204a-1, 204a-2, 204 a-5. Since the resistance of the depletion region is higher than those of the buried layer 102 and the well region 103, it is advantageous to increase the breakdown Voltage (VBR) of the semiconductor device 100-1.
Fig. 8 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. As shown in fig. 8, the semiconductor device 100-2 is similar to the semiconductor device 100-1 shown in fig. 6, and the main difference is that the semiconductor device 100-2 includes not only the first row 202a formed by the first doped regions 202a-1 to 202a-5, but also the third row 202b formed by the first doped regions 202b-1 to 202b-5, or the 2n-1 row formed by other first doped regions, where n is an integer greater than 2, for example, the fifth row (not shown), the seventh row (not shown)..2n-1, etc. In addition, the semiconductor device 100-2 includes not only the second row 204a formed by the second doped regions 204a-1 to 204a-5, but also the fourth row 204b formed by the second doped regions 204b-1 to 204b-5 or the 2 n-th row formed by the other second doped regions, wherein n is an integer greater than 2, for example, including the sixth row (not shown), the eighth row (not shown)..2n-th row, etc.
In one embodiment, the rows of the first doped regions and the rows of the second doped regions are alternately arranged along the depth direction (e.g., Z direction) of the trenches 105-1 to 105-5, and the first doped regions arranged in the same row have a substantially close depth and the second doped regions arranged in the same row have a substantially close depth.
Similarly, by properly adjusting the width and doping concentration relationships between the first doped regions 202a-1 to 202a-5, 202b-1 to 202b-5 and the second doped regions 204a-1 to 204a-5, 204b-1 to 204b-5, the first doped regions 202a-1 to 202a-5, 202b-1 to 202b-5 and the second doped regions 204a-1 to 204a-5, 204b-1 to 204b-5 alternately arranged along the depth direction (e.g., Z direction) of the trench form a super junction structure, which is advantageous for further reducing the on-resistance (R) of the semiconductor device 100-2 ON ) And increasing the breakdown voltage (V) BR )。
Fig. 9 is a schematic cross-sectional view of a semiconductor device in an on state according to an embodiment of the present invention. As shown in fig. 9, when the first gate 109-1 is turned on and the semiconductor device 10O-2 is turned on, a portion of the current 230-1 flows from the source region (not shown) through the well 103, the buried layer 102, the first doped region 202a-1, the buried layer 102, the first doped region 202a-5, the buried layer 102, the first doped region 202a-2, the buried layer 102, the well 103, and finally reaches the drain region 113D (not shown). Meanwhile, another portion of current 230-2 flows from the source region (not shown) through the well region 103, the buried layer 102, the first doped region 202b-1, the buried layer 102, the first doped region 202b-5, the buried layer 102, the first doped region 202b-2, the buried layer 102, the well region 103, and finally reaches the drain region 113D (not shown). Since the conductivity type of the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, 202b-5 is the same as the conductivity type of the buried layer 102, and the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, 202b-5 have an average doping concentration that is higher than the average doping concentration of the buried layer 102, the semiconductor device 100-2 may have a lower on-resistance (R ON ). According to one embodiment, when the semiconductor device 100-2 is in the on state, the field plates in the trenches 105-1-105-5 may also be biased (e.g., forward biased) simultaneously such that an inversion layer is created under each trench 105-1-105-5. Since the inversion layer has lower resistance than the well region 103, when a part of the current from the source region flows through the inversion layer, a smaller voltage drop is generated and the on-resistance (R ON )。
On the other hand, when the semiconductor device 100-2 is in the off state, the adjacent rows 202a, 202b, 204a, 204b generate depletion regions. The breakdown voltage (V) of the semiconductor device 100-2 is facilitated because the resistance of the depletion region is higher than the resistances of the buried layer 102 and the well region 103 BR ) Is improved.
Fig. 10 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. As shown in fig. 10, the semiconductor device 100-3 is similar to the semiconductor device 100-2 shown in fig. 8, with the main difference that the first trench 105-1 and the second trench 105-2 of the semiconductor device 100-3 are not provided with a second doped region of a first conductivity type (e.g., p-type) or are further not provided with a first doped region of a second conductivity type (e.g., n-type), but are replaced by a first start region 240-1 and a second start region 240-2. The first start region 240-1 is disposed under the first trench 105-1, the second start region 240-2 is disposed under the second trench 105-2, and the first start region 240-1 and the second start region 240-2 may be partial regions of the buried layer 102, such that the overall conductivity type of the first start region 240-1 and the second start region 240-2 is the second conductivity type (e.g., n-type). Since the second doped region of the first conductivity type through which the current cannot pass is not provided under the first trench 105-1 and the second trench 105-2, the current from the source electrode 111 or the drain electrode 113 more easily flows into a wider deep region under the first trench 105-1 and the second trench 105-2, and then And then turns to flow through the first doped regions 202a-5 and 202b-5 to facilitate the on-resistance (R ON ) Is reduced.
Fig. 11 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the invention. As shown in fig. 11, the semiconductor device 100-4 is similar to the semiconductor device 100-2 shown in fig. 8, with the main difference that the average width (or first average width) of the second doped regions 204a-1, 204a-2, 204b-1, 204b-2 under the first trench 105-1 and the second trench 105-2 of the semiconductor device 100-4 is smaller than the average width (or second average width) of the second doped regions 204a-5, 204b-5 under the fifth trench 105-5. Because the width of the second doped region under the first trench 105-1 and the second trench 105-2 is narrower, the current from the source electrode 111 or the drain electrode 113 flows more easily into the deeper region under the first trench 105-1 and the second trench 105-2, and then turns to flow through the first doped regions 202a-5 and 202b-5, thereby facilitating the on-resistance (R ON ) Is reduced.
Fig. 12, 13, 14, 15 and 16 are schematic cross-sectional views of stages of a method of fabricating an integrated circuit structure according to an embodiment of the present invention, including three discrete semiconductor device regions. Referring to fig. 12, an integrated circuit structure according to an embodiment of the present invention includes at least three discrete semiconductor device regions, namely, a region of the semiconductor device 100 (hereinafter referred to as a first region), a region of the semiconductor device 200 (hereinafter referred to as a second region), and a region of the semiconductor device 300 (hereinafter referred to as a third region), wherein the semiconductor device 100 may be any of the embodiments of fig. 1-5, and the semiconductor device 100 of fig. 2 is exemplified herein, the semiconductor device 200 is, for example, a Laterally Diffused Metal Oxide Semiconductor (LDMOS) device, and the semiconductor device 300 is, for example, a Complementary Metal Oxide Semiconductor (CMOS) device.
Referring to fig. 12, first, as shown in a cross-sectional structure 400-1, a first conductive type substrate 101, for example, a p-type substrate is provided, a second conductive type buried layer 102, for example, an n-type buried layer, is formed in the first region 1000 and the third region 3000 of the substrate 101, then an epitaxial layer 121 of the first conductive type, for example, a p-type epitaxial layer, is formed on the substrate 101, and the epitaxial layer 121 covers the buried layer 102. Then, a photolithography process is used to form a patterned mask that shields the third region, and then the same ion implantation process is used to simultaneously form the well region 103 of the second conductivity type in the epitaxial layer 121 of the first region 1000 and the second region 2000. The patterned mask that obscures the third region is then removed. Next, a patterned mask is formed to cover the first region 1000 and the third region 3000, and another ion implantation process is used to form a well region 123 of the first conductivity type in the epitaxial layer 121 of the second region 2000. Thereafter, a patterned hard mask is formed, and an etching process is performed using the patterned hard mask as an etching mask, thereby forming third trenches 105-3, first trenches 105-1, second trenches 105-2, and fourth trenches 105-4 in the well region 103 of the first region 1000 in order from right to left. With continued reference to fig. 12, as shown in the cross-sectional structure 400-2, in step S101, a dielectric layer 106 is formed in each trench of the first region 1000, on the well 103 and the well 123 of the second region 2000, and on the epitaxial layer 121 of the third region 3000 by using a deposition process, and then, in each trench of the first region 1000, a conductive layer 107 is filled by using a deposition process and a Chemical Mechanical Planarization (CMP) process, such that a top surface of the conductive layer 107 is level with a top surface of the dielectric layer 106, and the conductive layer 107 is, for example, polysilicon, but is not limited thereto.
Next, referring to fig. 13, in step S103, a patterned hard mask 125 is formed in the first region, the second region and the third region, the opening of the patterned hard mask 125 in the first region corresponds to the third trench 105-3, the first trench 105-1 and the second trench 105-2, and the openings of the patterned hard mask 125 in the second region and the third region correspond to the predetermined region where the trench is subsequently formed. The same etching process is performed using the patterned hard mask 125 as an etching mask, while removing portions of the conductive layer 107 and portions of the dielectric layer 106 near the top surface within the third trench 105-3, the first trench 105-1, and the second trench 105-2, while forming a third recess 127-3 within the third trench 105-3 over the third field plate 107-3, forming a first recess 127-1 within the first trench 105-1 over the first field plate 107-1, and forming a second recess 127-2 within the second trench 105-2 over the second field plate 107-2, while also etching a plurality of trenches 129 in the second region, and etching a plurality of trenches 131 in the third region. With continued reference to fig. 13, in step S105, dielectric materials are filled in the third recess 127-3, the first recess 127-1, and the second recess 127-2 of the first region to form a third dielectric isolation portion 108-3, a first dielectric isolation portion 108-1, and a second dielectric isolation portion 108-2, respectively, using the same deposition process and Chemical Mechanical Planarization (CMP) process, while dielectric materials are filled in the plurality of trenches 129 of the second region and the plurality of trenches 131 of the third region to form a plurality of shallow trench isolation (shallow trench isolation, STI) structures 135 of the second region and a plurality of shallow trench isolation structures 137 of the third region.
Then, referring to fig. 14, in step S107, a patterned mask is formed to cover the predetermined region, and an ion implantation process of the first conductivity type is performed in the second region to form a doped region 141, such as a p-type doped region, in the well region 103 of the second conductivity type. Then, the patterned mask masking the predetermined region is removed. Next, a patterned mask is formed to block another predetermined region, and a second conductive-type ion implantation process is performed in the second region to form a doped region 143, for example, an n-type doped region, in the well region 103 of the second conductive type. With continued reference to fig. 14, at step S109, a patterned hard mask 145 is formed over the first region, the second region, and the third region, the patterned hard mask 145 of the first region having openings corresponding to the third trench 105-3 and the first trench 105-1, and a portion of the dielectric layer 106 and the first dielectric isolation portion 108-1 within the first trench 105-1 of the first region are removed using an etching process to form a first recess 147-1, while a portion of the dielectric layer 106 and the third dielectric isolation portion 108-3 within the third trench 105-3 are removed to form a second recess 147-2.
Next, referring to fig. 15, in step S111, a gate dielectric layer 155 is formed in the second region by using a thermal oxidation process through the opening (as shown in fig. 14) of the patterned hard mask 145 in the second region, and a gate dielectric layer 155 is simultaneously formed on the well region 103 between the third trench 105-3 and the first trench 105-1 in the first region. Thereafter, the entire patterned hard mask 145 is removed, and first body region 117-1 and second body region 117-2 (e.g., both p-type body regions) are formed in the first region using a first conductivity type ion implantation process, and simultaneously first conductivity type well region 151 (e.g., p-type well region) is formed in the third region, followed by second conductivity type well region 153 (e.g., n-type well region) formed in the third region using a second conductivity type ion implantation process. With continued reference to fig. 15, in step S113, a first gate 109-1 is formed in the first recess 147-1 of the first region and a second gate 109-2 is formed in the second recess 147-2 of the first region using a deposition process and a Chemical Mechanical Planarization (CMP) process, a gate 157 is formed in the second region, and a plurality of gates 159 are formed in the third region using the same deposition process and another etching process, and the first gate 109-1, the second gate 109-2, the gate 157, and the plurality of gates 159 are all formed from the same conductive material layer, such as a polysilicon layer formed by the same deposition process to form the first gate 109-1, the second gate 109-2, the gate 157, and the plurality of gates 159.
Thereafter, referring to fig. 16, in step S115, a source region 111S and a drain region 113D are formed in the first region and a source region 165S and a drain region 165D are formed in the third region by using the same ion implantation process of the second conductivity type, and the source region 111S, the drain region 113D, the source region 165S and the drain region 165D are all n-type heavily doped regions, for example, and a desired doped region of the second conductivity type (for example, n-type heavily doped region) may be formed in the second region. The source region 161S and the drain region 161D are formed in the second region and the source region 163S and the drain region 163D are formed in the third region by the same ion implantation process of the first conductivity type, and the source region 161S, the drain region 161D, the source region 163S and the drain region 163D are, for example, p-type heavily doped regions, and a desired doped region of the first conductivity type (for example, p-type heavily doped region) may be formed in the first region at the same time.
With continued reference to fig. 16, at step S117, an interlayer dielectric layer 120 is simultaneously formed over the first, second and third regions, and contact openings (contact openings) are simultaneously formed in the interlayer dielectric layer 120 of the first, second and third regions by photolithography and etching processes, and then a deposition process and a Chemical Mechanical Planarization (CMP) process are simultaneously performed to form a source electrode 111, a gate contact 119, a field plate contact 115 and a drain electrode 113 in the first region, and a source electrode 171, a gate contact 179 and a drain electrode 173 in the second region, and source electrodes 181 and 191, gate contacts 189 and 199 and drain electrodes 183 and 193 in the third region. In addition, other contacts (contacts) may be simultaneously formed in the interlayer dielectric 120 of the first, second and third regions to simultaneously complete the fabrication of the semiconductor devices 100, 200 and 300. In accordance with an embodiment of the present invention, it is advantageous to use a Bipolar-CMOS-DMOS (BCD) technology to fabricate an integrated circuit structure including semiconductor device 100, semiconductor device 200, and semiconductor device 300 simultaneously.
According to an embodiment of the present invention, before performing step S101 illustrated in fig. 12, a self-aligned doping process may be additionally performed to form doped regions having the second conductivity type under the trenches 105-1 to 105-3, thereby forming a structure similar to that shown in fig. 17, 18 and 19.
As shown in fig. 17, the cross-sectional structure 400-3 of fig. 17 generally corresponds to the first region 1000 of the cross-sectional structure 400-1 of fig. 12, and the main difference therebetween is that the cross-sectional structure 400-3 further includes a fifth trench 105-5 disposed between the first trench 105-1 and the second trench 105-2. Furthermore, the first doped regions 202a-1, 202a-2, 202a-5 and the second doped regions 204a-1, 204a-2, 204a-5 are formed under the first trench 105-1, the second trench 105-2 and the fifth trench 105-5, wherein the first doped regions 202a-1, 202a-2, 202a-5 have the second conductivity type (e.g., n-type), the second doped regions 204a-1, 204a-2, 204a-5 have the first conductivity type (e.g., p-type), and the first doped regions 204a-1, 204a-2, 204a-5 are projected to overlap each other in the first direction (e.g., X-direction), and the second doped regions 204a-1, 204a-2, 204a-5 are projected to overlap each other in the first direction (e.g., X-direction). According to one embodiment, the first doped regions 202a-3, 202a-4 and the second doped regions 204a-3, 204a-4 are further formed under the third trench 105-3 and the fourth trench 105-4.
For the cross-sectional structure 400-3 shown in fig. 17, the processing time is before the step of filling the conductive layer 107 on the dielectric layer 106 as shown in fig. 12, and the process is exemplified as follows. First, referring to fig. 17, a fifth trench 105-5 is formed in the well region 102, which is located between the first trench 105-1 and the second trench 105-2. Thereafter, a self-aligned (self-aligned) doping process is performed to form first doped regions 202a-1, 202a-2, 202a-5 and second doped regions 204a-1, 204a-2, 204a-5 under the first trench 105-1, the second trench 105-2 and the fifth trench 105-5. According to an embodiment, the second doped regions 204a-1, 204a-2, 204a-5 may be formed first, followed by the formation of the first doped regions 202a-1, 202a-2, 202a-5, but is not limited thereto. Because the doped region under each trench is formed by implementing the self-aligned doping process, the photolithography process can be omitted, and the process cost can be effectively reduced.
As shown in fig. 18, the cross-sectional structure 400-4 of fig. 18 is similar to the cross-sectional structure 400-3 of fig. 17, and the main difference between the two is that the cross-sectional structure 400-4 includes not only the first row 202a formed by arranging the first doped regions 202a-1 to 202a-5, but also the third row 202b formed by arranging the first doped regions 202b-1 to 202b-5, or the 2n-1 row formed by arranging other first doped regions, where n is an integer greater than 2, for example, the fifth row (not shown), the seventh row (not shown) …, the 2n-1 row, and so on. In addition, the cross-sectional structure 400-4 includes not only the second row 204a formed by the second doped regions 204a-1 to 204a-5, but also the fourth row 204b formed by the second doped regions 204b-1 to 204b-5 or the 2n row formed by the other second doped regions, where n is an integer greater than 2, for example, including the sixth row (not shown), the eighth row (not shown) …, the 2n row, and so on. According to an embodiment, the first doped 202a-1 to 202a-5, 202b-1 to 202b-5 rows 202a, 202b and the second doped regions 204a-1 to 204a-5, 204b-1 to 204b-5 rows 204a, 204b are alternately arranged along the depth direction (Z direction) of each trench.
For the cross-sectional structure 400-4 shown in fig. 18, the process time is before the step of filling the conductive layer 107 on the dielectric layer 106 shown in fig. 12, and the process includes performing a plurality of self-aligned doping processes to sequentially form the 2 n-th row, the 2n-1 st row.
As shown in fig. 19, the cross-sectional structure 400-5 of fig. 19 is similar to the cross-sectional structure 400-4 of fig. 18, the main difference between the two is that the third trench 105-3 and the fourth trench 105-4 of the cross-sectional structure 400-5 are devoid of the second doped region below, and adjacent doped regions in the same row 202a, 202b, 204a, 204b are in contact with each other. For the cross-sectional structure 400-5 shown in fig. 19, the process time is before the step of filling the conductive layer 107 on the dielectric layer 106 as shown in fig. 12, and the process includes performing at least one heat treatment process in addition to performing a plurality of self-aligned doping processes to sequentially form each row, such that adjacent first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, 202b-5 in the same row are in contact with each other, and such that adjacent second doped regions 204a-1, 204a-2, 204a-5, 204b-1, 204b-2, 204b-5 in the same row are in contact with each other, wherein after performing the heat treatment process, the first doped regions 202a-1, 202a-2, 202a-5, 202b-1, 202b-2, 202b-5 and the second doped regions 204a-1, 204a-2, 204b-5 have the same average doping concentration.
Fig. 20 is a schematic diagram showing the distribution of voltage equipotential lines in the off state and the on state of a semiconductor device according to an embodiment of the present invention. For example, as shown in fig. 20, when the semiconductor device is turned off, the voltage equipotential distribution 100-off of the semiconductor device according to the embodiment of fig. 1 shows that the first field plate 107-1 and the second field plate 107-2 can be used to disperse the voltage across each trench, so as to generate a relatively uniform voltage drop, and avoid generating a high-intensity electric field in a local area. In addition, when the number of trenches and field plates is further increased, the breakdown voltage can be further increased. As also shown in fig. 20, when the semiconductor device is in an on state, the first gate 109-1 is applied with an on potential (e.g., positive potential), and the first field plate 107-1 and the second field plate 107-2 are also applied with a field plate potential (e.g., positive potential), the voltage equipotential distribution 100-on of which shows a higher voltage near the drain electrode 113 (e.g., near HV), a lower voltage near the source electrode 111 (e.g., near 0V), and the current path 110 flows from the drain electrode 113 down the second trench 105-2 along the second side 20 of the second trench 105-2, then down the first trench 105-1, and then up the channel region (not shown) and the source electrode 111 along the first side 10 of the first trench 105-1, thereby presenting a U-shaped current path. Therefore, the current path can be reduced on the premise of not reducing the voltage endurance capacity, the depth of the groove can be reduced (about 30 to 50 percent compared with the depth of the traditional groove), the process difficulty is further reduced, and meanwhile, the on-resistance of the semiconductor component can be also reduced. In addition, according to the embodiment of the invention, the output power capacitance (Coss) of the semiconductor device can be reduced by using the arrangement of the plurality of trench field plates, the breakdown voltage (about 100V to 150V) of the semiconductor device can be increased, and the gate-drain charge quantity (Qgd) and the gate-drain capacitance (Cgd) of the semiconductor device can be reduced by using the arrangement of the plurality of gates, thereby improving the switching speed of the semiconductor device and meeting various electrical requirements.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (34)
1. A semiconductor assembly, comprising:
a substrate having a first conductivity type;
a well region having a second conductivity type and disposed on the substrate;
a first trench disposed in the well region, wherein a first field plate and a first dielectric layer are disposed in the first trench and surround the first field plate;
a second trench disposed in the well region, wherein a second field plate and a second dielectric layer are disposed in the second trench and surround the second field plate;
the first grid electrode is arranged above the first field plate;
a source electrode arranged on a first side of the first trench; and
the drain electrode is arranged on a second side of the second groove, and the source electrode, the first groove, the second groove and the drain electrode are sequentially arranged along a first direction.
2. The semiconductor device of claim 1, wherein when said first gate is biased to an on-state, a current is allowed to flow from said drain electrode, down said second side of said second trench to below said second trench, then under said first trench, and then up said first side of said first trench to said source electrode.
3. The semiconductor device of claim 1, wherein the first gate is disposed in the first trench and separated from the first field plate by a first dielectric spacer disposed on the first field plate.
4. The semiconductor assembly of claim 1, further comprising:
a third trench disposed in the well region, wherein a third field plate and a third dielectric layer are disposed in the third trench and surround the third field plate; and
the second grid electrode is arranged in the third groove and is separated from the third field plate by a third dielectric isolation part, the third dielectric isolation part is arranged on the third field plate, and the source electrode is arranged between the first groove and the third groove.
5. The semiconductor device according to claim 4, wherein the third trench, the source electrode, the first trench, the second trench, and the drain electrode are sequentially arranged along the first direction.
6. The semiconductor device of claim 1, further comprising a first body region of said first conductivity type disposed on said first side of said first trench, a bottom surface of said first body region being higher than a top surface of said first field plate.
7. The semiconductor device of claim 1, further comprising a second body region of the first conductivity type disposed between the first trench and the second trench, a bottom surface of the second body region being higher than a top surface of the first field plate.
8. The semiconductor device of claim 1, further comprising a fourth trench disposed in the well region, a fourth field plate and a fourth dielectric layer disposed within the fourth trench surrounding the fourth field plate, the drain electrode disposed between the fourth trench and the second trench, the source electrode, the first trench, the second trench, the drain electrode, and the fourth trench being sequentially aligned along the first direction.
9. The semiconductor assembly of claim 8, wherein a top surface of the fourth field plate is higher than or at the same level as a top surface of the first field plate.
10. The semiconductor device according to claim 1, wherein a potential of the first field plate is the same as a potential of the first gate electrode or the source electrode.
11. The semiconductor device of claim 1, wherein the first gate and the first field plate are interconnected and each consist of a different region of the same conductive layer within the first trench.
12. The semiconductor device of claim 11, further comprising a first body region and a second body region of the first conductivity type disposed in the well region along two opposite sides of the first trench and extending downward from a top surface height of the first trench to 3% to 60% of a depth of the first trench.
13. The semiconductor assembly of claim 1, further comprising:
a gate connecting portion extending from a sidewall of the first gate along the first direction, protruding out of the sidewall of the first gate, and disposed on the well region; and
and a substrate region having the first conductivity type and disposed below the gate connection portion.
14. The semiconductor assembly of claim 13, further comprising:
a third trench disposed in the well region, wherein a third field plate, a third dielectric layer surrounding the third field plate, and a third dielectric isolation portion are disposed in the third trench to cover the third field plate;
a second gate disposed on the top surface of the third dielectric isolation portion and on the well region; and
A source region located between the first trench, the third trench and the gate connection portion, wherein two sides of the source region are respectively adjacent to the first trench and the gate connection portion,
the grid connection part is arranged between the first grid and the second grid, and the substrate region extends to the lower part of the source region.
15. The semiconductor device of claim 14, wherein the first gate and the second gate extend along a second direction, the first direction having a non-zero included angle with the second direction.
16. The semiconductor device of claim 13, further comprising a first dielectric spacer disposed within the first trench and overlying the first field plate, wherein the first gate is disposed on a top surface of the first dielectric spacer and on the well region.
17. The semiconductor device of claim 1, further comprising an epitaxial layer of the first conductivity type disposed on the substrate, wherein the well region is disposed in the epitaxial layer.
18. The semiconductor device of claim 1, further comprising a buried layer of the second conductivity type disposed below the well region, and the first trench and the second trench extend into the buried layer.
19. The semiconductor assembly of claim 2, further comprising:
a fifth groove arranged in the well region and between the first groove and the second groove;
a plurality of first doped regions respectively arranged below the first groove, the second groove and the fifth groove, wherein the first doped regions have the second conductivity type; and
a plurality of second doped regions respectively arranged below the first doped regions, wherein the second doped regions have the first conductivity type,
wherein, along the depth direction of each groove, the projection of the first doping region is respectively overlapped with the projections of the first groove, the second groove and the fifth groove,
wherein, along the depth direction of each groove, the projection of the second doping region is respectively overlapped with the projections of the first groove, the second groove and the fifth groove,
wherein the current flows through the first doped region when the first gate is applied with the turn-on bias.
20. The semiconductor device of claim 19, wherein the first doped regions are arranged in a first row and a third row, the second doped regions are arranged in a second row and a fourth row, the rows in which the first doped regions are arranged and the rows in which the second doped regions are arranged alternate along the depth of each trench, the first doped regions arranged in the same row have substantially similar depths, and the second doped regions arranged in the same row have substantially similar depths.
21. The semiconductor package of claim 20, wherein,
the ratio between the average doping concentration of the first doped region and the average doping concentration of the second doped region is between 0.1 and 10,
along the depth direction of each trench, each adjacent first doped region and each second doped region are in contact with each other.
22. The semiconductor package of claim 19, wherein,
the second doped region arranged below the first groove and the second groove has a first average width, and the second doped region arranged below the fifth groove has a second average width, and the first average width is smaller than the second average width.
23. The semiconductor assembly of claim 2, further comprising:
a fifth groove arranged in the well region and between the first groove and the second groove;
a first doped region disposed below the fifth trench, the first doped region having the second conductivity type; and
a second doped region disposed under the first doped region, the second doped region having the first conductivity type,
Wherein, along the depth direction of the fifth groove, the projection of the first doped region and the projection of the second doped region are partially overlapped with each other,
wherein the current flows through the first doped region when the first gate is applied with the turn-on bias.
24. The semiconductor assembly of claim 23, further comprising:
a first starting region arranged below the first groove; and
a second initial region disposed below the second trench,
wherein the overall conductivity type of the first and second start regions is the second conductivity type.
25. The semiconductor assembly of claim 23, further comprising:
a further first doped region disposed below the second doped region, the further first doped region 202b-5 having the second conductivity type; and
a second doped region disposed below the third doped region, the first doped region having the first conductivity type,
wherein, along the depth direction of the fifth groove, the projection of the first doped region, the projection of the second doped region, the projection of the other first doped region and the projection of the other second doped region are partially overlapped with each other,
When the first gate is applied with the on bias, the current flows through the first doped region and the other first doped region.
26. A method of manufacturing a semiconductor device, comprising:
providing a substrate with a first conductive type;
forming a well region on the substrate, wherein the well region has a second conductivity type;
forming a first trench and a second trench in the well region;
depositing a dielectric layer in the first groove and the second groove in a forward direction, and filling a conductive layer on the dielectric layer;
etching the conductive layers in the first trench and the second trench to form a first recess on a first field plate and a second recess on a second field plate respectively;
filling a dielectric material in the first recess and the second recess to form a first dielectric isolation part and a second dielectric isolation part respectively;
etching the dielectric layer and the first dielectric isolation part in the first groove to form a first groove;
forming a first grid in the first groove; and
a source region and a drain region are formed in the well region, wherein the source region is located on a first side of the first trench, and the drain region is located on a second side of the second trench.
27. The method of manufacturing a semiconductor device according to claim 26, further comprising:
and forming a third groove and a fourth groove in the well region, wherein the third groove, the first groove, the second groove and the fourth groove are sequentially arranged along a first direction.
28. The method of manufacturing a semiconductor device according to claim 27, further comprising:
depositing the dielectric layer and filling the conductive layer on the dielectric layer in the third trench and the fourth trench in a forward direction, wherein the conductive layer in the fourth trench forms a fourth field plate;
etching the conductive layer in the third trench to form a third recess on a third field plate;
filling the third recess with the dielectric material to form a third dielectric isolation portion;
etching the third dielectric isolation portion and the dielectric layer to form a second groove; and
and forming a second grid electrode in the second groove.
29. The method of claim 26, further comprising forming a first body region and a second body region in the well region on opposite sides of the first trench, respectively.
30. The method of claim 26, wherein a power integrated circuit process integration technique is used to simultaneously form a laterally diffused metal oxide semiconductor device and a complementary metal oxide semiconductor device on the substrate.
31. The method of manufacturing a semiconductor device according to claim 26, further comprising, prior to filling the conductive layer over the dielectric layer:
forming a fifth groove in the well region, which is positioned between the first groove and the second groove;
performing a self-aligned doping process to form a plurality of first doped regions and a plurality of second doped regions under the first, second and fifth trenches, the first doped regions having the second conductivity type, the second doped regions having the first conductivity type,
wherein the first doped regions overlap each other in the first direction and the second doped regions overlap each other in the first direction.
32. The method of manufacturing a semiconductor device according to claim 31, wherein the first doped regions are arranged in a first row and a second row, the second doped regions are arranged in a second row and a fourth row, and each row in which the first doped regions are arranged and each row in which the second doped regions are arranged are alternately arranged along a depth direction of each trench.
33. The method of manufacturing a semiconductor device according to claim 32, wherein each of the first doped regions and each of the second doped regions which are adjacent to each other are in contact with each other along a depth direction of each trench.
34. The method of manufacturing a semiconductor device according to claim 32, further comprising:
performing at least one heat treatment process such that adjacent first doped regions in each row are in contact with each other and such that adjacent second doped regions in each row are in contact with each other,
wherein the first doped region and the second doped region have the same average doping concentration after the at least one heat treatment process is performed.
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