CN116893338A - Forced commutation test circuit and method for controllable commutation valve - Google Patents
Forced commutation test circuit and method for controllable commutation valve Download PDFInfo
- Publication number
- CN116893338A CN116893338A CN202310891724.9A CN202310891724A CN116893338A CN 116893338 A CN116893338 A CN 116893338A CN 202310891724 A CN202310891724 A CN 202310891724A CN 116893338 A CN116893338 A CN 116893338A
- Authority
- CN
- China
- Prior art keywords
- controllable
- converter valve
- valve
- main branch
- branch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims description 25
- 238000010998 test method Methods 0.000 claims abstract description 12
- 230000015654 memory Effects 0.000 claims description 26
- 239000003990 capacitor Substances 0.000 claims description 5
- 238000004891 communication Methods 0.000 claims description 4
- 230000000737 periodic effect Effects 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000005540 biological transmission Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 6
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
- G01R31/3271—Testing of circuit interrupters, switches or circuit-breakers of high voltage or medium voltage devices
- G01R31/3272—Apparatus, systems or circuits therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/60—Arrangements for transfer of electric power between AC networks or generators via a high voltage DC link [HVCD]
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Inverter Devices (AREA)
Abstract
The invention relates to the technical field of direct current transmission, and discloses a forced commutation test circuit and a forced commutation test method for a controllable commutation valve.
Description
Technical Field
The invention relates to the technical field of direct current transmission, in particular to a controllable converter valve forced converter test circuit and a controllable converter valve forced converter test method.
Background
The DC transmission system in China is characterized in that the receiving end of the power grid in the middle and eastern regions is fed into the DC system in a plurality of modes, the coupling between stations is tight, the commutation failure fault caused by the multi-station linkage is more serious, and more serious challenges are brought to the safe and stable operation of the power grid. Therefore, controllable commutated valves that resist commutation failure are now becoming a research hotspot.
Because the direct current transmission device generally has the characteristics of high voltage, large current and large capacity, it is difficult to construct a full-load circuit which is the same as the actual operation condition in the test environment for test, so that an equivalent test circuit is constructed, and the test which is equivalent to the actual operation condition in strength becomes a necessary choice.
In order to verify the capability of the controllable commutation valve to resist the commutation failure caused by the alternating current fault, the controllable turn-off capability of the alternating current fault current flowing in the commutation valve needs to be tested, so that the converter can turn off the fault current to complete forced commutation. Therefore, the controllable turn-off test is an important test means for ensuring the design and manufacturing level of the controllable topological converter and ensuring the capability of resisting commutation failure faults, and the test is required to verify the voltage, current and thermal stress born by each component in the forced commutation process of the converter valve and also required to prove that the component can bear transient stress with high di/dt and du/dt when the current is turned off.
Disclosure of Invention
In view of the above, the invention provides a forced commutation test circuit and a forced commutation test method for a controllable commutation valve, so as to solve the problem of how to construct an equivalent test circuit for the controllable commutation valve.
In a first aspect, the present invention provides a controllable converter valve forced commutation test circuit, comprising: the device comprises a steady-state power supply and a multi-wave harmonic current source, wherein the steady-state power supply is connected with a controllable converter valve in parallel and is used for providing voltage and current which accord with the actual steady operation working condition of the converter valve; the multi-wave subharmonic current source is connected with the controllable commutation valve in parallel and is used for periodically injecting fault current into the controllable commutation valve when a main branch and an auxiliary branch in the controllable commutation valve are continuously and alternately switched on and off in multiple cycles so as to perform a periodic forced commutation test on the controllable commutation valve.
The invention adopts a test method of composite multi-source injection, and adopts a multi-wave harmonic current source to inject adjustable half-wave multi-wave current, and the adjustable half-wave multi-wave current is overlapped with the test current of a steady-state power supply to form the test current capable of verifying the controllable turn-off function of the converter valve, thereby truly simulating the operation of the converter valve under the alternating current fault operation working condition of the system, and effectively verifying the voltage, current and thermal stress born by each component of the converter valve under the actual working condition and the transient stress of high di/dt and du/dt caused by high turn-off current in the turn-off process.
In an alternative embodiment, the multi-wave subharmonic current source comprises: a plurality of resonant branches connected in parallel; in one period, one resonant branch is conducted to inject fault current into the controllable converter valve.
In an alternative embodiment, the resonant circuit comprises: and the resonant inductor, the resonant capacitor and the thyristor are sequentially connected in series.
In an alternative embodiment, the controllable converter valve forced commutation test circuit further comprises: and the charging circuit is connected with the multi-wave subharmonic current source and is used for charging the multi-wave subharmonic current source.
In an alternative embodiment, the controllable converter valve forced commutation test circuit further comprises: the control background is connected with the controllable converter valve, the steady-state power supply and the multi-wave harmonic current source and is used for controlling the steady-state power supply to provide voltage and current which meet the actual steady-state operation working condition of the converter valve, controlling the main branch and the auxiliary branch of the controllable converter valve to be alternately switched on and switched off in multiple cycles and controlling the multi-wave harmonic current source to periodically inject fault current into the controllable converter valve.
In a second aspect, the present invention provides a method for testing a controllable converter valve for forced commutation, based on the test circuit of the first aspect and any optional embodiment thereof, the method comprising: controlling a steady-state power supply to provide voltage and current which meet the actual steady operation working condition of the converter valve; the main branch and the auxiliary branch of the controllable converter valve are controlled to be alternately switched on and off in multiple cycles, and the multi-wave harmonic current source is controlled to periodically inject fault current into the controllable converter valve so as to carry out periodic forced converter test on the controllable converter valve.
In an alternative embodiment, when the single valve of the controllable converter valve is formed by connecting two main branches and a plurality of auxiliary branches in parallel, the process of periodically injecting fault current into the controllable converter valve includes: controlling the first main branch to be conducted; when a logic time sequence on instruction is received, the first main branch is controlled to be turned off, and the second main branch is controlled to be turned on; when the first main branch is conducted for a first preset time, one resonance branch of the multi-wave subharmonic current source is controlled to be continuously conducted for a second preset time; when a logic time sequence turn-off instruction is received, the second main branch is controlled to be turned off; and returning to the step of controlling the first main branch to be conducted after the third preset time.
In an alternative embodiment, when the single valve of the controllable converter valve is formed by connecting a main branch and a plurality of auxiliary branches in parallel, the process of periodically injecting fault current into the controllable converter valve includes: controlling the first main branch to be conducted; when the first main branch is conducted for a first preset time, one resonance branch of the multi-wave subharmonic current source is controlled to be continuously conducted for a second preset time; when a logic time sequence turn-off instruction is received, the first main branch is controlled to be turned off; and returning to the step of controlling the first main branch to be conducted after the third preset time.
In a third aspect, the present invention provides a computer device comprising: the device comprises a memory and a processor, wherein the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions so as to execute the controllable converter valve forced conversion test method according to the second aspect or any corresponding implementation mode.
In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to execute the controllable converter valve forced commutation test method according to the second aspect or any one of the embodiments thereof.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a test circuit according to an embodiment of the invention;
FIG. 2 is a block diagram of another test circuit according to an embodiment of the invention;
FIG. 3 is a specific circuit topology of a test circuit according to an embodiment of the invention;
FIG. 4 is a flow chart of a test method according to an embodiment of the invention;
FIG. 5 is a single valve configuration of a controllable converter valve according to an embodiment of the invention;
fig. 6 is a control timing diagram when the current turn-off leg a has two legs according to an embodiment of the present invention;
fig. 7 is a control timing diagram when the current turn-off leg a has one leg according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals refer to the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary only for explaining the present invention and are not to be construed as limiting the present invention.
The embodiment provides a controllable converter valve forced converter test circuit, as shown in fig. 1, including: steady state power supply and multi-wave subharmonic current source.
As shown in fig. 1, a steady-state power supply is connected in parallel with the controllable converter valve and is configured to provide a voltage current consistent with the actual steady-state operating test conditions of the converter valve.
As shown in fig. 1, the multi-wave subharmonic current source is connected in parallel with the controllable converter valve and is used for periodically injecting fault current into the controllable converter valve when the main branch and the auxiliary branch in the controllable converter valve are continuously and alternately switched on and off in multiple cycles so as to perform forced converter test on the controllable converter valve.
Specifically, the embodiment adopts a test method of composite multi-source injection, and adopts a multi-wave harmonic current source to inject adjustable half-wave multi-wave current, and the adjustable half-wave multi-wave current is overlapped with a test current of a steady-state power supply to form a test current capable of verifying the controllable turn-off function of the converter valve. The test is completed by matching the time sequence of each power electronic device in the controllable commutation valve with the time sequence of the injection current of the multi-wave harmonic current source, and the test requirements of forced commutation required by different direct current transmission system projects can be met.
In some alternative embodiments, as shown in fig. 2, the multi-wave subharmonic current source includes: a plurality of resonant branches connected in parallel; in one period, one resonant branch is conducted to inject fault current into the controllable converter valve.
Optionally, the resonant circuit includes: and the resonant inductor, the resonant capacitor and the thyristor are sequentially connected in series. As shown in fig. 3, the resonant inductance is L 61 ～L 6n The resonance capacitance is C 61 ～C 6n The thyristor is V 61 ～V 6n Wherein the ratio of the number of the groups for k (k=1, 2,…, n) sets of parallel loop capacitors, each set of capacitors C 6k And reactor L 6k By means of thyristors V 6k Under the corresponding logic time sequence, the controllable additional fault current is formed by matching with triggering and switching off, and the controllable additional fault current is overlapped with the basic current to form fault current of k cycles capable of simulating alternating current faults.
In some alternative embodiments, as shown in fig. 3, the controllable converter valve forced commutation test circuit further includes: and the charging circuit is connected with the multi-wave subharmonic current source and is used for charging the multi-wave subharmonic current source. Wherein the charging circuit charges the k (k=1, 2, …, n) sets of parallel loop capacitances.
In some alternative embodiments, as shown in fig. 3, the controllable converter valve forced commutation test circuit further includes: the control background is connected with the controllable converter valve, the steady-state power supply and the multi-wave harmonic current source and is used for controlling the steady-state power supply to provide voltage and current which meet the actual steady operation working condition of the converter valve, controlling the main branch and the auxiliary branch of the controllable converter valve to be alternately switched on and switched off in multiple cycles and controlling the multi-wave harmonic current source to periodically inject fault current into the controllable converter valve.
The embodiment provides a method for testing forced commutation of a controllable commutating valve, which is based on the test circuit of any one of the above embodiments and optional implementation manners thereof, as shown in fig. 4, and includes:
step S11: controlling a steady-state power supply to provide voltage and current which meet the actual steady operation working condition of the converter valve;
step S12: the main branch and the auxiliary branch of the controllable converter valve are controlled to be alternately switched on and off in multiple cycles, and the multi-wave harmonic current source is controlled to periodically inject fault current into the controllable converter valve so as to perform forced converter test on the controllable converter valve.
Specifically, a test method of composite multi-source injection is adopted, and an adjustable half-wave multi-wave current is injected by adopting a multi-wave harmonic current source and is overlapped with a test current of a steady-state power supply to form a test current capable of verifying the controllable turn-off function of the converter valve.
Specifically, the embodiment controls the on and off of the power electronic device in the converter valve according to the forced commutation time sequence of the controllable commutation valve, and injects adjustable half-wave multi-wave current in the process of the on of the power electronic device.
In some alternative embodiments, when the single valve of the controllable converter valve is formed by connecting two main branches and a plurality of auxiliary branches in parallel, the process of periodically injecting fault current into the controllable converter valve includes:
(1) Controlling the first main branch to be conducted;
(2) When a logic time sequence on instruction is received, the first main branch is controlled to be turned off, and the second main branch is controlled to be turned on; when the first main branch is conducted for a first preset time, one resonance branch of the multi-wave subharmonic current source is controlled to be continuously conducted for a second preset time;
(3) When a logic time sequence turn-off instruction is received, the second main branch is controlled to be turned off;
(4) And returning to the step of controlling the first main branch to be conducted after the third preset time.
Specifically, as shown in fig. 5, the controllable converter valve is formed by parallel connection of a+b branches, wherein the current cut-off branch a (a=1, 2, …, p) comprises one or more power electronic devices with current cut-off and forward and reverse voltage blocking capabilities, such as IGBT, IGCT, IEGT, GTO or MOSFET, and the auxiliary converter branch b (b=1, 2, …, q) is used for establishing a converter valve converter voltage, and does not comprise the power electronic devices.
Specifically, the control logic time sequence of the converter valve with controllable turn-off capability or controllable commutation capability needs to meet the alternating fault current flowing through the bridge arm when the analog bridge arm commutates in the test process, and the commutation voltage is established through the turn-off current, so that the forced commutation function of the bridge arm is realized. The forced commutation test is performed under the stable operation condition of the converter valve. The current-off branch a includes two branches a1, a2, respectively:
the steady-state power supply is required to provide the controllable converter valve with voltage and current which meet the actual steady operation condition of the converter valve, and on the basis:
(1) the branch a1 power electronics is in a first period t 11 The moment is first turned on,
(2) after receiving the control background, sending out logic time sequence instruction, t 12 The controllable power electronic device of the branch a1 is turned off, the power electronic device of the branch a2 is turned on, the current is transferred from the branch 1 to the branch 2,
③t 13 and the controllable power electronic device of the moment branch 2 receives a logic time sequence instruction sent by the control background to turn off, current is transferred to the auxiliary commutation branch b, and VT valve turn-off voltage is established to realize forced commutation.
Trigger pulse ft of multi-wave subharmonic current source in the process n At t 1n -t 2n And injecting harmonic current with corresponding wave band and width according to test requirements at any time in the middle, and superposing the harmonic current and current provided by a steady-state power supply to form fault current required by the converter valve VT. The power electronic trigger pulse in the multi-wave harmonic current source and the converter valve VT is shown in fig. 6.
In some alternative embodiments, when the single valve of the controllable converter valve is formed by connecting one main branch and a plurality of auxiliary branches in parallel, the process of periodically injecting fault current into the controllable converter valve includes:
(1) Controlling the first main branch to be conducted;
(2) When the first main branch is conducted for a first preset time, one resonance branch of the multi-wave subharmonic current source is controlled to be continuously conducted for a second preset time;
(3) When a logic time sequence turn-off instruction is received, the first main branch is controlled to be turned off;
(4) And returning to the step of controlling the first main branch to be conducted after the third preset time.
The steady-state power supply is required to provide the controllable converter valve with voltage and current which meet the actual steady operation condition of the converter valve, and on the basis:
(1) converter valve power electronics is at t 11 The switch-on is performed at the moment,
(2) receiving control background to send out logic time sequence instruction t 12 Time-to-time shutdown, ac fault current diversionAnd (5) completing forced commutation to the branch without power electronic devices.
Trigger pulse ft of multi-wave subharmonic current source in the process n At t 1n -t 2n And injecting harmonic current with corresponding wave band and width according to test requirements at any time in the middle, and superposing the harmonic current and current provided by a steady-state power supply to form fault current required by the converter valve. The power electronics trigger pulse within the converter valve is shown in fig. 7.
Alternatively, in general, the multiple wave subharmonic current source auxiliary valve V 6k The trigger pulses being equidistant pulses, i.e. ft 1 ＝ft 2 ＝ft 3 ＝···＝ft n However, when there is a specific demand, the auxiliary valve V 6k The trigger pulses may be set to be unequal, i.e., ft 1 ≠ft 2 ≠ft 3 ≠···≠ft n 。
In addition, the fault current half-wave width of the multi-wave subharmonic current source is as follows:
the embodiment of the invention also provides computer equipment, which is provided with the control background shown in the figure 3.
Referring to fig. 8, fig. 8 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 8, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.
Claims (10)
1. The utility model provides a controllable commutation valve test circuit that forces that commutates which characterized in that includes: a steady state power supply and a multi-wave harmonic current source, wherein,
the steady-state power supply is connected with the controllable converter valve in parallel and is used for providing voltage and current which accord with the actual steady operation condition of the converter valve;
the multi-wave harmonic current source is connected with the controllable converter valve in parallel and is used for periodically injecting fault current into the controllable converter valve when a main branch and an auxiliary branch in the controllable converter valve are continuously and alternately switched on and off in multiple cycles so as to perform a periodic forced converter test on the controllable converter valve.
2. The controllable converter valve forced commutation test circuit of claim 1, wherein the multi-wave harmonic current source comprises:
a plurality of resonant branches connected in parallel;
in one period, one resonant branch is conducted to inject fault current into the controllable converter valve.
3. The controllable converter valve forced commutation test circuit of claim 2, wherein the resonant circuit comprises: and the resonant inductor, the resonant capacitor and the thyristor are sequentially connected in series.
4. The controllable converter valve forced commutation test circuit of claim 1, further comprising:
and the charging circuit is connected with the multi-wave subharmonic current source and is used for charging the multi-wave subharmonic current source.
5. The controllable converter valve forced commutation test circuit of claim 1, further comprising:
the control background is connected with the controllable converter valve, the steady-state power supply and the multi-wave harmonic current source and is used for controlling the steady-state power supply to provide voltage and current under test working conditions which accord with actual steady operation working conditions of the converter valve, controlling a main branch and an auxiliary branch of the controllable converter valve to be alternately switched on and switched off in multiple cycles, and controlling the multi-wave harmonic current source to periodically inject fault current into the controllable converter valve.
6. A method of testing a controllable converter valve for forced commutation, the method comprising, based on the test circuit of any one of claims 1-5:
controlling the steady-state power supply to provide voltage and current which meet the actual steady operation working condition of the converter valve;
and controlling the main branch and the auxiliary branch of the controllable converter valve to be alternately switched on and off in multiple cycles, and controlling the multi-wave harmonic current source to periodically inject fault current into the controllable converter valve so as to perform periodic forced converter test on the controllable converter valve.
7. The method for forced commutation test of a controllable commutated valve of claim 6, wherein when the single valve of the controllable commutated valve is formed by connecting two main branches and a plurality of auxiliary branches in parallel, the process of periodically injecting fault current into the controllable commutated valve comprises:
controlling the first main branch to be conducted;
when a logic time sequence on instruction is received, the first main branch is controlled to be turned off, and the second main branch is controlled to be turned on; when the first main branch is conducted for a first preset time, one resonance branch of the multi-wave subharmonic current source is controlled to be continuously conducted for a second preset time;
when a logic time sequence turn-off instruction is received, the second main branch is controlled to be turned off;
and returning to the step of controlling the first main branch to conduct after the third preset time.
8. The method for forced commutation testing of a controllable commutated valve of claim 6, wherein when the single valve of the controllable commutated valve is formed by connecting a main branch and a plurality of auxiliary branches in parallel, the process of periodically injecting fault current into the controllable commutated valve comprises:
controlling the first main branch to be conducted;
when the first main branch is conducted for a first preset time, one resonance branch of the multi-wave subharmonic current source is controlled to be continuously conducted for a second preset time;
when a logic time sequence turn-off instruction is received, the first main branch is controlled to be turned off;
and returning to the step of controlling the first main branch to conduct after the third preset time.
9. A computer device, comprising:
a memory and a processor, the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, thereby executing the controllable converter valve forced conversion test method according to any one of claims 6 to 8.
10. A computer readable storage medium having stored thereon computer instructions for causing a computer to perform the controllable converter valve forced commutation test method of any one of claims 6 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310891724.9A CN116893338A (en) | 2023-07-19 | 2023-07-19 | Forced commutation test circuit and method for controllable commutation valve |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310891724.9A CN116893338A (en) | 2023-07-19 | 2023-07-19 | Forced commutation test circuit and method for controllable commutation valve |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116893338A true CN116893338A (en) | 2023-10-17 |
Family
ID=88310512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310891724.9A Pending CN116893338A (en) | 2023-07-19 | 2023-07-19 | Forced commutation test circuit and method for controllable commutation valve |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116893338A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104977480A (en) * | 2014-04-02 | 2015-10-14 | 国家电网公司 | High-voltage DC power transmission converter valve fault current testing device and testing method thereof |
| CN112803795A (en) * | 2021-02-01 | 2021-05-14 | 全球能源互联网研究院有限公司 | Active commutation unit, hybrid converter topology structure and method for forced commutation |
| CN112803798A (en) * | 2021-02-01 | 2021-05-14 | 全球能源互联网研究院有限公司 | Active commutation unit, hybrid converter topology structure and method for forced commutation |
| CN114024452A (en) * | 2021-11-16 | 2022-02-08 | 全球能源互联网研究院有限公司 | Commutation control method and device of converter, converter and readable storage medium |
| CN218886082U (en) * | 2022-10-21 | 2023-04-18 | 国网智能电网研究院有限公司 | Test circuit and test system |
| CN116207997A (en) * | 2023-03-22 | 2023-06-02 | 国网智能电网研究院有限公司 | Method and system for controlling turn-off of main branch full control valve of controllable commutation converter |
-
2023
- 2023-07-19 CN CN202310891724.9A patent/CN116893338A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104977480A (en) * | 2014-04-02 | 2015-10-14 | 国家电网公司 | High-voltage DC power transmission converter valve fault current testing device and testing method thereof |
| CN112803795A (en) * | 2021-02-01 | 2021-05-14 | 全球能源互联网研究院有限公司 | Active commutation unit, hybrid converter topology structure and method for forced commutation |
| CN112803798A (en) * | 2021-02-01 | 2021-05-14 | 全球能源互联网研究院有限公司 | Active commutation unit, hybrid converter topology structure and method for forced commutation |
| WO2022160929A1 (en) * | 2021-02-01 | 2022-08-04 | 全球能源互联网研究院有限公司 | Active commutation unit, forced commutation hybrid converter topological structure, and method |
| CN114024452A (en) * | 2021-11-16 | 2022-02-08 | 全球能源互联网研究院有限公司 | Commutation control method and device of converter, converter and readable storage medium |
| CN218886082U (en) * | 2022-10-21 | 2023-04-18 | 国网智能电网研究院有限公司 | Test circuit and test system |
| CN116207997A (en) * | 2023-03-22 | 2023-06-02 | 国网智能电网研究院有限公司 | Method and system for controlling turn-off of main branch full control valve of controllable commutation converter |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| RU2706020C1 (en) | Output method of high-voltage direct current switch | |
| CN102323546B (en) | Back-to-back test method of VSC-HVDC MMC valve stable state operation test | |
| Mandrek et al. | Quasi-resonant DC-link inverter with a reduced number of active elements | |
| Baradar et al. | The modeling multi-terminal VSC-HVDC in power flow calculation using unified methodology | |
| CN102129034B (en) | Fault current operation test method of flexible DC (Direct Current) transmission MMC (Modular Multilevel Converter) valve | |
| CN102780384A (en) | High-performance low-cost IGBT (Insulated Gate Bipolar Translator) negative pressure bootstrap drive circuit | |
| CN202066942U (en) | Fault current operation test device for flexible direct current power transmission MMC (modular multi-level converter) valve | |
| CN110870191A (en) | Three-level and two-stage decoupling active NPC converter | |
| CN103944436A (en) | Three-phase fault-tolerant inverter circuit and control method thereof | |
| CN102692542A (en) | Trigger method of auxiliary valve in a short circuit current test apparatus | |
| CN112803798A (en) | Active commutation unit, hybrid converter topology structure and method for forced commutation | |
| Maguire et al. | Predicting switch ON/OFF statuses in real time electromagnetic transients simulations with voltage source converters | |
| CN114024452B (en) | Converter commutation control method and device, converter and readable storage medium | |
| Cho et al. | Three phase sine wave voltage source inverter using the soft switched resonant poles | |
| CN114188913A (en) | Control method and device of direct-current ice melting device and controller | |
| CN116893338A (en) | Forced commutation test circuit and method for controllable commutation valve | |
| CN112329235B (en) | Power electronic system real-time simulation method based on hybrid modeling | |
| CN103336163A (en) | Converter-valve AC/DC voltage test circuit of flexible high-voltage DC transmission system | |
| Zhou et al. | Current oscillation phenomenon of MMC based on IGCT and fast recovery diode with high surge current capability for HVDC application | |
| CN110427660B (en) | Simulation method of high-voltage direct-current circuit breaker | |
| CN218886082U (en) | Test circuit and test system | |
| CN214380680U (en) | Hybrid converter topology structure with active phase change unit and forced phase change | |
| US11789047B2 (en) | Steady state fault current calculation method for modular multilevel converter | |
| Liqiang et al. | The IGCT test platform for voltage source inverters | |
| Lu et al. | Sub-module fault analysis and fault-tolerant control strategy for modular multilevel converter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |