CN116888914A - Introduction and detection of parity errors for self-test of UART - Google Patents

Abstract

The UART includes a transmit register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate the contents of the receive register against parity errors, and control logic to determine the contents of the transmit register. The content includes base data and parity bits based on the base data. The control logic means routes the content to the receive register via the first virtual remappable pin. The control logic means causes the modified content to be provided to the receiving register before the full content is received at the receiving register. The modified content results in parity errors. The modified content includes different underlying data or different parity bits than the content of the transmit registers. The control logic unit determines whether the parity error is detected by the parity error checking circuit.

Description

Introduction and detection of parity errors for self-test of UART

Priority

The present application claims priority from indian application 202111030809 filed on 7.9 of 2021. The present application relates to electronic communications, and more particularly to the introduction and detection of parity errors in a single universal asynchronous receiver/transmitter (UART).

Technical Field

The present application relates to electronic communications, and more particularly to the introduction and detection of parity errors in a single universal asynchronous receiver/transmitter (UART).

Background

UARTs are used to implement a variety of communication protocols between electronic devices. UARTs may be used for serial communications. The data transmission by the UART may be framed by start and stop bits to facilitate timing between UARTs on different devices.

Different errors may occur in the data transmission between UARTs. Such errors may occur due to, for example, noise in the transmitting device, the transmission medium, the receiving device, or a misconfiguration of one of these elements. One such error may include a parity error. Parity errors may be caused by a data bit changing its value during transmission. Parity errors may be detected by parity checking. Parity checking may be performed in part by evaluating the parity bits. The parity bits may be an indication of whether the total count of bits in a given frame having a given value (such as 0 or 1) is even or odd. The parity bits may be set by the transmitting UART based on the data to be transmitted and included in or appended to the data frame. The receiving UART may calculate what the parity bit should be based on the actually received data and then compare the calculated parity bit with the parity bit received from the transmitting UART. If the calculated parity bit does not match the received parity bit, a parity error has occurred.

The inventors of the examples of the present disclosure have discovered that testing of UART circuits, devices, and modules often uses two or more such UART circuits, devices, or modules. Data is generated by one such UART and received by other such UARTs. To test the correctness of the operation, such as the detection of parity errors, parity errors may be created artificially. However, by using a separate UART circuit, device or module (which may in turn be located on a separate microcontroller or system from the original UART circuit, device or module), the inventors of the present disclosure have discovered that such reliance on another UART circuit, device or module may result in additional errors. Such additional errors may include positive or negative false recognition results resulting from testing the UART's parity error capability. For example, data may be transmitted from a transmitting UART to a receiving UART. The test mechanism in the transmitting UART may introduce parity errors by, for example, switching bits of data to be transmitted. However, if noise in the transmission medium or in the receiving UART switches another bit of data to be transmitted, for example, the error may not be detected. In UART testing or validation, even if such parity errors do not work properly, it may occur that the parity errors work properly. Further, it may not be clear whether the parity error check of the transmitting UART is not working properly or the parity error check of the receiving UART is not working properly, or whether there is noise in the transmitting UART, the transmission medium, or the receiving UART. The inventors of the examples of the present disclosure have discovered that the examples of the present disclosure solve one or more of these problems.

Disclosure of Invention

The UART includes a transmit register, a receive register, a virtual remappable pin, a parity error check circuit to evaluate the contents of the receive register against parity errors, and control logic to determine the contents of the transmit register. The content includes base data and parity bits based on the base data. The control logic routes the contents of the transmit register to the receive register through the virtual remappable pin. The control logic means causes the modified content to be provided to the receive register before the full content of the transmit register is received at the receive register. The modified content results in parity errors. The modified content includes different underlying data or different parity bits than the content of the transmit registers. The control logic unit determines whether the parity error is detected by the parity error checking circuit.

Drawings

FIG. 1 is an illustration of an exemplary system for introducing and detecting parity errors in a UART according to examples of the present disclosure.

Fig. 2 is a timing diagram of generation of parity information according to an example of the present disclosure.

Fig. 3 is a timing diagram of introducing parity errors into the generation of parity information according to an example of the present disclosure.

FIG. 4 is an illustration of an exemplary method for introducing and detecting parity errors in a UART according to examples of the present disclosure.

Detailed Description

Examples of the present disclosure may include a UART. The UART may include a transmit register, a receive register, a virtual remappable pin, a parity error check circuit, and control logic. UARTs may operate in a normal mode and a test mode. In the normal mode, the UART may transmit or receive data on behalf of other components that use the UART for communication, such as a system or microcontroller into which the UART is included or integrated. In test mode, the UART may perform a self-test to verify that the parity error check circuit is functioning properly. The mode of operation may be controlled by the control logic.

The transmit and receive registers may include any suitable mechanism for storing information, such as hardware registers, volatile memory, or non-volatile memory. In contrast to the general purpose registers of the larger microcontroller into which the UART is integrated or implemented, both the transmit and receive registers may be local to the UART. The transmit register may include information to be transmitted by the UART. The data for the transmit register may be provided by, for example, elements of the system that use UART for communication in the normal mode. Such data may be provided by the control logic in test mode, for example. The receive register may include information received by the UART. The data for the receive register may be provided by, for example, other elements of the system (such as a different UART) that communicate with the UART in normal mode. Such data may be provided by a test circuit in a test mode, for example, as described below.

The virtual remappable pins may be implemented in any suitable manner. In one example, the virtual remappable pins may be implemented by a software-controlled interconnect matrix. The matrix may be implemented entirely within the UART or within the UART and a larger system (such as a microcontroller) on which the UART resides. The virtual remappable pins may be programmable by the control logic. The control logic may then make programming calls to other parts of the system to set the virtual remappable pins. The virtual remappable pin may be programmable to bind together two ports of a UART or a system in which the UART is implemented. The virtual remappable pin may be used to bind, for example, a TX port and an RX port together, or to bind an RX port to a ready-to-transmit port.

The parity error checking circuit may evaluate the contents of the receive registers for parity errors. The parity error checking circuit may evaluate the parity of the contents of the receive registers against the expected parity. The parity error checking circuit may calculate the expected parity based on the data content. In the normal mode, the parity bit may be set correctly when the content is placed in the transmit register and sent to another UART. The transmitted content may be corrupted during transmission and thus the received content at the receive register may fail to parity error check. In the test mode, the control logic may artificially cause parity errors that should be detected by the parity error checking circuit, as described below. The test mode may thus test whether the parity error check circuit is functioning properly.

In test mode, the control logic may determine or set the contents of the transmit registers. The content may include base data and parity bits based on the base data. In test mode, the control logic may route the contents of the transmit register to the receive register through the virtual remappable pin. In the test mode, the control logic may cause the modified content to be provided to the receive register before the entire content of the transmit register is received at the receive register. The modified content may result in parity errors. The modified content may include different underlying data or different parity bits than the content of the transmit registers. In the test mode, the control logic may determine whether the parity error is detected by the parity error check circuit.

The control logic and parity error checking circuitry may be implemented in any suitable manner, such as by analog circuitry, digital circuitry, application specific integrated circuitry, field programmable gate arrays, reconfigurable or programmable hardware, instructions for execution by a processor, or any suitable combination thereof.

In combination with any of the above examples, the control logic may cause the modified content to be provided to the receive register by routing a known signal to the receive register via the virtual remappable pin before receiving the entire content of the transmit register at the receive register.

In combination with any of the above examples, the known signal may be a constant value.

In combination with any of the above examples, the constant value may be equal to an expected value of the stop bit.

In combination with any of the above examples, the content may include a stop bit, and the control logic may cause the modified content to be provided to the receive register. The modification may include setting different underlying data or different parity bits of the transmit register and setting an expected value of the stop bit by applying a known signal.

In combination with any of the above examples, the known signal may be a ready-to-transmit signal.

In combination with any of the above examples, the known signal may be a data terminal ready signal.

In combination with any of the above examples, the control logic may cause the modified content to be provided to the receive register by switching the input signal to the receive register from the content of the transmit register to a known signal.

In combination with any of the above examples, the control logic may cause the modified content to be provided to the receive register by remapping the virtual remappable pin from the content of the transmit register to a known signal.

In combination with any of the above examples, the control logic may cause the modified content to be provided to the receive register by selectively routing the input to the receive register.

In combination with any of the above examples, the control logic may issue an error signal indicating a failure to detect a parity error based on a determination that the parity error is not detected by the parity error checking circuit. Any suitable error signal may be used.

Examples of the present disclosure may include a microcontroller. The microcontroller may include any of the UARTs of the examples described above.

FIG. 1 is an illustration of an exemplary system 100 for introducing and detecting parity errors in a UART, such as a single UART, according to examples of the present disclosure. The system 100 may be implemented within any suitable environment, such as within a controller, microcontroller, die, integrated circuit, system on a chip, application specific integrated circuit, field programmable gate array, computer, mobile device, or any other suitable electronic device. In the example of fig. 1, the system 100 may be implemented by a microcontroller.

The system 100 may include a UART 116.UART 116 may be implemented by analog circuitry, digital circuitry, instructions executed by a processor, or any suitable combination thereof. The system 100 may include more instances of UARTs 116 than shown. However, a single such UART 116 may be configured to introduce and detect parity errors. In the case of multiple instances of UART 116, each of the multiple instances of UART 116 may introduce and detect a respective parity error.

The system 100 may include any suitable external ports for providing communication to and from the UART 116, such as a TX port 130, an RX port 118, and a Ready To Send (RTS) port 134.RTS port 134 may be a logic low port such that the RTS signal is "true" when it is 0 or other logic low value. Such ports 130, 118, 134 may be implemented by any suitable electrical connection. In various examples, the ports 130, 118, 134 may be external connections of a die, board, chip, or other package of the UART 116. The ports 130, 118, 134 may be configured to provide communication between the UART 116 and other instances of UARTs on other devices.

The system 100 may include any other suitable variety and number of elements. For example, the system 100 may include a processor 102 communicatively coupled to a memory 104. Memory 104 may include instructions that, when loaded and executed by processor 102, may implement software for execution by system 100. The system 100 may include a system bus 106. The system bus 106 may be configured to provide communication between the processor 102 and other parts of the system 100, such as the UART 116.

In one example, UART 116 may be a peripheral to a microcontroller of system 100. Such peripheral devices may perform tasks on behalf of processor 102 and system 100. The task may be initiated by a command, user input, software, or other operation of the processor 102. Once initiated, such tasks may be performed by the peripheral device independent of the processor 102. Thus, the processor 102 may offload tasks to such peripherals. When a task is completed, or according to other suitable criteria in which the processor 102 or software executing thereon takes further action, the peripheral device may, for example, generate an interrupt to the processor 102. Other possible peripheral devices of the system 100 may include, for example, the counter 108, the digital-to-analog converter 110, the analog-to-digital converter 112, or the I2C communication circuit 114, however, in some examples, the counter 108, the digital-to-analog converter 110, the analog-to-digital converter 112, or the I2C communication circuit 114 may not be included.

UART 116 may include control logic 132. The control logic 132 may be implemented by analog circuitry, digital circuitry, application specific integrated circuitry, field programmable gate arrays, reconfigurable or programmable hardware, instructions for execution by a processor, or any suitable combination thereof. The control logic 132 may be configured to direct and control the operation of the UART 116 to introduce parity errors, as described in this disclosure.

UART 116 may include a receive register such as RXREG 126. The RXREG 126 may be configured to store one or more information bits received at the UART 116 through the RX port 118, including essential data to be received, frame information, or error information such as parity bits. Data received on RX port 118 may be received from another instance of UART. The data in the RXREG 126 may be read and used by any suitable portion of the system 100, such as by the control logic component 132.

UART 116 may include a transmit register, such as TXREG 128. The TXREG 128 may be configured to store one or more information bits to be transmitted by the UART 116 through the TX port 130, including essential data, frame information, or error information such as parity bits to be transmitted. The data to be stored in the TXREG 128 and transmitted through the TX port 130 may be generated by any suitable portion of the system 100, such as by the control logic 132, software executing on the processor 102, or another peripheral device of the system 100.

In one example, UART 116 may be configured to introduce parity errors using resources available within UART 116. UART 116 may be configured to introduce parity errors without using additional instances of UART.

In one example, UART 116 may include or have access to one or more virtual remappable pins. To simplify the discussion, a single virtual remappable pin is described herein, it being understood that more than one virtual remappable pin may be provided. Such virtual remappable pins may be configured to provide connectivity between or within a given peripheral device of system 100, such as UART 116. The virtual remappable pins may be implemented by, for example, a switching fabric within UART 116 or between UART 116 and other elements of system 100. In one example, the virtual remappable pins may be implemented by a software-controlled interconnect matrix. The matrix may be implemented entirely within UART 116 or within UART 116 and a larger system (such as a microcontroller) within which UART 116 resides. The virtual remappable pins may be programmable through the control logic 132. The control logic 132 may then make programming calls to other parts of the system to set the virtual remappable pins. The virtual remappable pin may be programmable to electrically bind (i.e., connect) the UART 116 or two ports of the system 100. The virtual remappable pin may be used to bind, for example, a TX port or register and an RX port or register together or to bind an RX port or register to a ready-to-send signal. For example, UART 116 may include remappable pin RP1 120.RP1120 is shown as being external to UART 116 as if these were physical pins for demonstration purposes. Furthermore, two representations of remappable pins RP1120 provided for readability are shown in fig. 1. The single instances of the remappable pin RP1120 are shown as separate instances to illustrate the equivalent routing of signals to and from the remappable pin, although these are single instances. The control logic 130 may be configured to route two or more signals to the same remappable pin. This may have the effect of connecting two or more signals. This may occur within UART 116 or within system 100. Routing signals through the remappable pin RP1120 may be programmatically performed by the control logic 130 by assigning and reassigning the remappable pin RP 1120. However, for purposes of illustration, the ability of control logic 130 to route signals through remappable pin RP1120 may be illustrated as switch 124.

Parity information for data to be transmitted to TX port 130 may be stored in TXREG 128. The parity information may be set according to a parity scheme designed for UART 116. Any suitable parity information may be used. For example, parity bits may be used. In another example, the parity bit may be set to 1 if there are an odd number of 1 values within the data to be transmitted, and may be set to 0 if there are an even number of 1 values within the data to be transmitted. The examples shown in this disclosure may follow this scheme. In other examples, the parity bit may be set to 0 if there are an odd number of 1 values within the data to be transmitted, and may be set to 1 if there are an even number of 1 values within the data to be transmitted.

The parity information may be set or checked by any suitable portion of UART 116. For example, UART 116 may include parity error checking circuitry 136. The parity error checking circuit 136 may be implemented by analog circuitry, digital circuitry, instructions for execution by a processor, or any suitable combination thereof. In one example, the parity error checking circuit 136 may be configured to check and evaluate the contents of the TXREGs 128 and set the parity bits in the TXREGs 128 based on the underlying data to be transmitted from the TXREGs 128. In another example, the parity bits may be alternatively set by other suitable portions of UART 116 (such as the source of the content of TXREG 128). In addition, the parity error checking circuit 136 may be configured to check and evaluate the content of the RXREG 126 and evaluate whether a parity error has occurred. The parity error checking circuit 136 may be configured to read the base data of the RXREG 126 upon actual receipt thereof, and calculate parity bits corresponding to such base data. The parity error check circuit 136 may be configured to compare such calculated parity bits with the parity bits actually received in the RXREG 126. If the parity bits do not match, a parity error may have occurred. UART 116 may take any suitable corrective action. If the parity bits do match, no parity error occurs and then the UART 116 may continue to process the information in the RXREG 126.

During the normal mode of operation, where the parity error checking capability of UART 116 is not tested, the remappable pin RP 1120 may not be used in the manner shown in fig. 1. The remappable pin RP 1120 may alternatively be unassigned or non-existent, and the UART 116 may be configured to route the contents of the TXREG 128 to the TX port 130. Parity information for data in the TXREG 128 to be transmitted to the TX port 130 may be calculated and stored in the TXREG 128 or otherwise transmitted to the TX port 130 along with the data. Data may be sent from TX port 130 to other entities (not shown) connected to TX port 130, such as another UART. Further, the UART 116 may be configured to route content from the RX port 118 to the RXREG 126. In one example, the RX port 118 is directly connected to an input of the RXREG 126. As described above, the parity error checking circuit 136 may calculate parity information for data received in the RXREG 126 and compare it with parity information arriving with data received in the RXREG 126. If the parity information matches, no parity error may be detected. If the parity information does not match, a parity error may be detected. If a parity error is detected, any suitable corrective action may be taken. These may include, for example, the sender requesting the information (such as another UART) resending the data or informing the user or a software entity of the system 100.

During the normal mode of operation, control logic 132 may route an RTS signal to RTS port 134. The RTS signal may be part of a handshake scheme (along with a Clear To Send (CTS) message). The RTS signal may signal other UART instances (not shown) that UART 116 is ready to transmit. In an example of the system 100, a logic low signal may indicate that the UART 116 is ready to transmit, while a logic high signal may indicate that the UART 116 is not ready to transmit.

The control logic 132 may be configured to switch the UART 116 between the test mode and the normal mode. During the test mode, the control logic 132 may be configured to determine exemplary test content to be used in the TXREG 128. The control logic 132 may make this determination by generating test content or evaluating content in the TXREG 128 that may have been provided by another entity.

During the test mode, the control logic 132 may be configured to selectively route the contents of the TXREG 128 to the RXREG 126 through the remappable pin RP1 120. The control logic 132 may be configured to perform such routing in any suitable manner. The control logic 132 may be configured to selectively route other content to the RXREG 126 to cause modified content to be provided to the RXREG 126 when compared to the original content of the TXREG 128. The modified content may be provided to the RXREG 126 before the entire original content of the TXREG 128 is provided to the RXREG 126, i.e., a portion of the entire original content of the TXREG 128 may not be provided to the RXREG 126, but may be replaced with the modified content. The modified content may be configured to cause parity errors in the RXREG 126. The modified content may include parity bits that are different from the parity bits originally in the TXREG 128, or base data that is different from the base data originally in the TXREG 128, or both.

In one example, the remappable pin RP1 120 may be reprogrammed during the transmission of the content of the TXREG 128 to route the RTS signal to the input of the RXREG 126 before providing all of the original content of the TXREG 128 to the RXREG 12. This operation is symbolically shown as switch 124 in fig. 1. The control logic 132 may be configured to selectively apply the RTS signal output to RXREG 126 through the remappable pin RP1 120 or apply the contents of TXREG 128 to RXREG 126 through the remappable pin RP1 120. The selective application may be performed by reprogramming RP1 120 from the RTS signal output connecting TXREG 128 and RXREG 126 to connect control logic component 130 and RXREG 126. Reprogramming RP1 120 to connect control logic 130 and the RTS signal output of RXREG 126 may cause bits to be toggled, inserted, or otherwise manipulated to artificially create parity errors in the contents of RXREG 126.

The control logic 132 may change any appropriate bit in the transmission of information in the frame between the TXREG 128 and the RXREG 126 to artificially create parity errors. For example, bits in the base data that are logical low values in the content of the TXREG 128 may be changed to logical high values. In another example, bits in the base data that are logical high values in the content of the TXREG 128 may be changed to logical low values. In these examples, the underlying data in the content of the TXREG 128 may have resulted in setting a certain parity bit, and the action of the control logic 132 artificially altering the bits of such underlying data should result in the parity calculation of the RXREG 126 not matching the transmitted parity bit. If operating properly, the parity error checking circuit 136 may detect the parity error. The control logic 132 may be configured to determine whether the parity error is properly determined by the parity error check circuit 136.

In yet another example, the control logic 132 may change the parity bit itself, which is a logical low value in the content of the TXREG 128, to a logical high value to verify the operation of the parity error check circuit 136. In yet another example, the control logic 132 may change the parity bit itself, which is a logical high value in the content of the TXREG 128, to a logical low value to verify the operation of the parity error check circuit 136. In these examples, the underlying data in the contents of the TXREG 128 may have resulted in setting a certain parity bit, and the action of the control logic 132 artificially changing the value should result in the parity computation of the parity error check circuit 136 not matching the transmitted parity bit. If operating properly, the parity error checking circuit 136 may detect the parity error. The control logic 132 may be configured to determine whether the parity error is properly determined by the parity error check circuit 136.

The control logic 132 may be configured to set an incorrect value for providing parity bits to the RXREG 126 via the remappable pin RP 1120 using any suitable source of information. In one example, the control logic 132 may be configured to provide an RTS signal as an information source to set an incorrect value for providing parity bits to the RXREG 126 through the remappable pin RP 1120. As described above, the RTS signal may be logic low when the UART 116 is read to send data. However, when UART 116 is set to test mode, the RTS signal may be logic high, indicating that UART 116 is not ready to transmit data. Thus, in test mode, the control logic 132 may utilize the state of the RTS signal to send a logic high value into the RXREG 126. Although the use of an RTS signal is described as being used to create parity errors in the content of RXREG 126, any suitable signal may be used.

When the data is not ready to be transmitted because the test mode is activated, the RT S signal may be used because its value is known to be a logic high value. The logic high value corresponds to a value for an expected stop bit, which would also be logic high. Thus, in test mode, the RTS signal may reliably be a logic high value and successfully applied to alter the parity bits of the underlying data or content of the TXREG 128 received by the RXREG 126. By aligning such a modified value (e.g., RTS signal) received by the RXREG 126 to the same value as expected for the stop bit, the second modification matches the modified value to the expected value of the stop bit. In the event that, for example, the RTS signal does not provide the expected value of the stop bit, the parity error checking circuit 136 may not attempt to check the parity of the contents of the RXREG 126, as different transmission errors may be caused by incorrect stop bit values and preempt parity. As described above, when an RTS signal is used, any suitable known signal may be used. Instead of the content transmitted from the TXREG 128 and the value matching the expected value of the stop bit, the appropriate known signal may be a constant value for the duration of the application of the known signal to the RXREG 126. For example, a data terminal ready signal may be used instead of the RTS signal. The known signal may be inverted, if necessary, to conform to the expected value of the stop bit.

The test pattern may be used based on any suitable criteria. For example, the test mode may be performed at system 100 start-up, periodically, as part of a larger diagnostic test, or upon request of a user or system software.

Fig. 2 is a timing diagram of generation of parity information according to an example of the present disclosure. The chart of fig. 2 may reflect a correct information frame with correct parity bits tested during test mode. The data shown in fig. 2 may reflect the content of the TXREG 128, which may be generated by, for example, the control logic 132 or any other suitable portion of the system 100.

A known data sequence may be used. For example, the sequence "00110000" can be used. In this data sequence, there may be an even number of "1" values. Thus and for the purposes of this example, the parity bit "1" may be applied to the data sequence. The data content is shown in graph 202. The contents of the TXREG 128 may be routed to the remappable pin RP1 120 according to the timing shown. Both the parity bit and the stop bit may be "1" values.

Graph 204 may show values for an RTS signal. Control logic 132 may generate an RTS signal. In other examples, a Data Terminal Ready (DTR) signal may be used.

The graph 206 may show values received by the RXREG 126. These may be the content of the initial transmission of graph 202.

The graph 208 may show the timing of when data is sampled at the RXREG 126. As shown, the data may be sampled every 2 microseconds.

The test mode may begin at 0 microseconds. At about 1 microsecond, the RTS signal may be logic high, indicating that UART 116 is not ready to send data in normal mode. The RXREG 126 may be reset. The test sample may begin at 2 microseconds.

At 4 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 6 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 8 microseconds, a value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 10 microseconds, a value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 12 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 14 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 16 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 18 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

If the control logic 132 does not change the value of the parity bit (as is the case in FIG. 2), at 20 microseconds, a value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 22 microseconds, a stop bit with a logic high value may be received, ending the data frame received at RXREG 126. The parity bits may then be checked against the content received by the parity error checking circuit 136. In the example of fig. 2, the parity bits are correct. The control logic 132 may verify the results of the parity error check circuit 136.

Fig. 3 is a timing diagram of introducing parity errors into the generation of parity information according to an example of the present disclosure.

A known data sequence may be used. For example, the sequence "00110000" can be used. In this data sequence there may be an even number of "1" values, and thus, for the purposes of this example, parity bits of "1" may be applied to the data sequence. The data content is shown in graph 302. Both the parity bit and the stop bit may be "1" values.

Graph 304 may show values for the RTS signal. Control logic 132 may generate an RTS signal.

The graph 306 may show values received by the RXREG 126. These may be the content of graph 302 that was interrupted by applying an RTS signal that replaced a portion of the content of TXREG 128.

The graph 308 may show the timing of when data is sampled at the RXREG 126. As shown, the data may be sampled every 2 microseconds.

The test mode may begin at 0 microseconds. At about 1 microsecond, the RTS signal may be logic high, indicating that UART 116 is not ready to send data. The RXREG 126 may be reset. The test sample may begin at 2 microseconds.

At 4 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 6 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 8 microseconds, a value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 10 microseconds, a value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 12 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 14 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 16 microseconds, a value of 0 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126.

At 18 microseconds, the control logic 132 may be configured to cause the modified content to be provided to the RXREG 126. The control logic 132 may perform this operation by remapping the remappable pin RP1 120 to connect the RXREG 126 and the RTS signal shown in graph 304. Thus, at 18 microseconds, a value of 1 may be transmitted from the RTS signal to the input of RXREG 126 through the remappable pin RP1 120. This may replace the value 0 of TXREG 128. In one example, as shown, the remappable pin RP1 120 may be remapped to the TXRED 128 and RXREG 126 after the bit samples 308 have been sampled for 18 microsecond slots. At 20 microseconds, a value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126. At 22 microseconds, a stop bit value of 1 may be read from TXREG 128, output to remappable pin RP1 120, and input to RXREG 126, ending the data frame received at RXREG 126. The parity bits may then be checked against the content received by the parity error checking circuit 136. In the example of fig. 3, the parity bits are incorrect. The control logic 132 may check the result of the parity error check circuit 136 and confirm that the parity error check circuit 136 has detected a parity error.

At 22 microseconds, a stop bit with a high logic value may be received, ending the data frame received at RXREG 126. The parity bits may then be checked against the content received by the parity error checking circuit 136. In the example of fig. 2, the parity bits are incorrect. The parity bit has a value of 1, but the data at 18 microseconds is flipped, changing the parity of the data received at RXREG 126. The control logic 132 may check the results of the parity error check circuit 136 to see if the parity error has been properly identified.

In another example, the RTS signal may continue to be mapped to the remappable pin RP1120 (and thus to the RXREG 126) at 20 microseconds and 22 microseconds, which, similar to the example data and parity information, may result in the RXREG 126 receiving incorrect parity bits for the actual received data. The control logic 132 may check the result of the parity error check circuit 136 and confirm that the parity error check circuit 136 has detected a parity error. In another example, the RTS signal may continue to be mapped to the remappable pin RP1120 (and thus to RXREG 126) at 20 microseconds, but at 22 microseconds the remappable pin RP1120 may be remapped to the TXREG 128 and RXREG 126, which, for the information actually received, may result in the RXREG 126 receiving incorrect parity bits similar to the exemplary data and parity information. The control logic 132 may check the result of the parity error check circuit 136 and confirm that the parity error check circuit 136 has detected a parity error.

FIG. 4 is an illustration of an exemplary method 400 for introducing and detecting parity errors at a UART (i.e., in a single UART) according to examples of the present disclosure.

The method 400 may be performed by any suitable mechanism, such as the systems of fig. 1-3, and in particular the control logic 132 and the parity error checking circuit 136. Method 400 may include more or fewer steps than those shown in fig. 4. Further, various steps of method 400 may be repeated, omitted, skipped, performed in a different order, performed in parallel, or performed recursively.

At 405, a UART may be initialized.

At 410, it may be determined whether to operate the UART in a normal mode or in a test mode. The decision to enter the test mode may be made by the user of the UART on demand, periodically, at start-up, or on any other suitable basis. If the UART is operating in normal mode, the method 400 may proceed to 415. Otherwise, if the UART is operating in test mode, the method 400 may proceed to 430.

At 415, data may be transmitted from the UART to another UART or data from another UART may be received at the UART. The data to be transmitted may be stored in the TXREG. The received data may be stored in RXREG. The parity of the received data may be checked. The parity bits received in RXREG may be evaluated from the underlying data frame also received in RXREG.

At 420, it may be determined whether a parity bit error exists. If not, the method 400 may return to 410. If so, method 40 may proceed to 425.

At 425, any suitable corrective action may be taken on the parity bits, such as generating an error signal, generating an alarm, or requesting retransmission of the frame by the transmitting UART. The method 400 may return to 410.

At 430, the remappable pins may be mapped between the TXREGs and RXREGs such that the output of the TXREGs will propagate to the RXREGs. The countdown may begin until the appropriate time to apply the TXREG to the RXREG switches to apply a known signal (such as an RTS signal) to the RXREG. The countdown may be monitored by a timer, such as a clock signal, or a software counter. The switch that causes the modified content to propagate to the RXREG may be performed before the entire content of the TXREG is received at the RXREG.

At 435, it may be determined whether the application of the remappable pin is to be switched in order to cause the modified content to be propagated to the RXREG. If so, the method 400 may proceed to 440. Otherwise, the method 400 may repeat 435 for one or more additional clock cycles.

At 440, the remappable pins may be remapped to apply a known signal to RXREG, which may match the expected value of the stop bit (e.g., RTS signal or DTR signal).

At 445, the system may wait for the stop bit to propagate to RXREG.

At 450, the content of the RXREG may be evaluated according to the parity bits of the RXREG. The parity of the received data may be calculated and compared to the received parity information. It may be determined whether a parity error has been detected. If so, the method 400 may proceed to 460. Otherwise, the method 400 may proceed to 455.

At 455, it may be determined that the parity error checking circuit of execution 450 is not functioning properly. Any suitable corrective action may be performed, such as an alert to a user of the UART. The method 400 may return to 410.

At 460, it may be determined that the parity error checking circuitry of execution 450 is operating properly. The method 400 may return to 410.

Although examples have been described above, the present disclosure may have other modifications and examples without departing from the spirit and scope of these examples.

Claims (23)

1. A universal asynchronous receiver/transmitter (UART), comprising:

a transmit register including information to be transmitted by the UART;

a receive register including information received by the UART;

virtual remappable pins;

a parity error checking circuit that evaluates the contents of the receive register for parity errors; and

A control logic for:

determining content of the transmit register, the content comprising base data and parity bits based on the base data;

routing the contents of the transmit register to the receive register through the virtual remappable pin;

causing modified content to be provided to the receive register prior to receipt of the entire content of the transmit register at the receive register, the modified content resulting in a parity error, the modified content comprising different base data or different parity bits than the content of the transmit register; and

it is determined whether the parity error is detected by the parity error checking circuit.

2. The UART of claim 1, wherein the control logic means causes modified content to be provided to the receive register by routing a known signal to the receive register via the virtual remappable pin before the full content of the transmit register is received at the receive register.

3. The UART of claim 2, wherein the known signal is a constant value.

4. The UART according to claim 3, wherein the constant value is equal to an expected value of a stop bit.

5. The UART of claim 4, wherein:

the content includes the stop bit; and is also provided with

The control logic means causes, by application of the known signal, a modified content to be provided to the receive register, including setting a different base data or a different parity bit of the transmit register and setting the expected value of the stop bit.

6. The UART according to any one of claims 2 to 5, wherein the known signal is a ready-to-transmit signal.

7. The UART according to any one of claims 2 to 5, wherein the known signal is a data terminal ready signal.

8. The UART according to any one of claims 2 to 7, wherein the control logic means causes modified content to be provided to the receive register by switching an input signal to the receive register from the content of the transmit register to the known signal.

9. The UART according to any one of claims 2 to 7, wherein the control logic means causes modified content to be provided to the receive register by remapping the virtual remappable pin from the content of the transmit register to a known signal.

10. The UART according to any one of claims 1 to 9, wherein the control logic means causes modified content to be provided to the receive register by selectively routing inputs to the receive register.

11. The UART according to any one of claims 1 to 10, wherein the control logic component issues an error signal indicating a failure to detect the parity error based on a determination that the parity error is not detected by the parity error checking circuit.

12. A microcontroller comprising a universal asynchronous receiver/transmitter (UART) according to any of claims 1 to 11.

13. A method, in a universal asynchronous receiver/transmitter (UART), comprising:

determining content of a transmit register, the transmit register including information to be transmitted by the UART, the content including base data and parity bits based on the base data;

routing the contents of the transmit register to a receive register through a virtual remappable pin;

causing modified content to be provided to the receive register prior to receipt of the entire contents of the transmit register at the receive register, the modified content comprising different base data or different parity bits than the contents of the transmit register, the modified content causing a parity error; and

It is determined whether parity error checking circuitry detects a parity error in the receive register.

14. The method of claim 13, comprising causing modified content to be provided to the receive register by routing a known signal to the receive register via the virtual remappable pin before the entire content of the transmit register is received at the receive register.

15. The method of claim 14, wherein the known signal is a constant value.

16. The method of claim 15, wherein the constant value is equal to an expected value of a stop bit.

17. The method according to claim 16, wherein:

the content includes the stop bit; and is also provided with

The method includes causing, by applying the known signal, providing modified content to the receive register and setting the expected value of the stop bit.

18. The method of any of claims 14 to 17, wherein the known signal is a ready-to-send signal.

19. A method according to any of claims 14 to 17, wherein the known signal is a data terminal ready signal.

20. A method according to any of claims 14 to 19, comprising causing modified content to be provided to the receive register by switching an input signal to the receive register from the content of the transmit register to the known signal.

21. The method of any of claims 13 to 20, comprising causing modified content to be provided to the receive register by remapping the virtual remappable pin from the content of the transmit register to a known signal.

22. A method according to any of claims 13 to 20, comprising causing modified content to be provided to the receive register by selectively routing inputs to the receive register.

23. The method of any of claims 13 to 22, comprising issuing an error signal indicating a failure to detect the parity error based on a determination that the parity error is not detected by the parity error checking circuit.