CN116885556A

CN116885556A - VCSEL wafer and VCSEL integrated chip thereof

Info

Publication number: CN116885556A
Application number: CN202310811948.4A
Authority: CN
Inventors: 林珊珊; 李念宜; 刘赤宇
Original assignee: Zhejiang Ruixi Technology Co ltd
Current assignee: Zhejiang Ruixi Technology Co ltd
Priority date: 2023-07-04
Filing date: 2023-07-04
Publication date: 2023-10-13

Abstract

A VCSEL wafer and VCSEL integrated chip thereof are disclosed. The VCSEL integrated chip includes: at least one VCSEL light emitting point, a light modulating portion integrated at the VCSEL light emitting point at a wafer level, at least one photodiode spaced from the VCSEL light emitting point, and a thermoelectric refrigeration structure integrated at the VCSEL light emitting point at a wafer level, the VCSEL light emitting point and the photodiode sharing a substrate layer; the thermoelectric refrigeration structure comprises a plurality of thermocouple pairs, and each thermocouple pair comprises a P-type structure and an N-type structure which are electrically connected with each other.

Description

VCSEL wafer and VCSEL integrated chip thereof

Technical Field

The present application relates to the field of semiconductor lasers, and more particularly to VCSEL wafers and VCSEL integrated chips thereof.

Background

VCSEL (Vertical-Cavity Surface Emitting Laser) has great application potential in the fields of communication, daily consumption and vehicle-mounted as a semiconductor Laser with low cost and excellent performance. Currently, VCSEL products are widely applied to application scenes such as short-distance optical fiber communication, face recognition and 3D sensing.

In the actual industry, VCSEL lasers are often used as basic elements (e.g., as light sources) and assembled with other devices as modules. For example, when the VCSEL laser is applied to the depth camera module, the VCSEL laser is assembled with devices such as a circuit board, a bracket, an optical diffraction element, a metal shield, a photodiode, an optical lens, and an optical filter to form the depth camera module, wherein the VCSEL laser is assembled with devices such as the circuit board, the bracket, the optical diffraction element, and the metal shield to form a laser projection unit of the depth camera module, and devices such as the photodiode, the optical lens, and the optical filter are assembled to form a camera unit of the depth camera module.

There are problems of assembly stability and mounting accuracy in assembling the VCSEL laser with other devices. For example, during assembly of a VCSEL laser with an optical diffraction element, the accuracy of the mounting of the optical diffraction element relative to the VCSEL laser will greatly affect the performance of the laser projection unit. The relative positional relationship between the VCSEL laser and the optical diffraction element is currently determined mainly by physical positioning, and the element is fixed by a bracket and/or an adhesive, so that the relative positional relationship between the VCSEL laser and the optical diffraction element is maintained. In the process of assembling the laser projection unit and the camera unit, component fixation is also mainly performed by the bracket and/or the adhesive.

However, the positioning accuracy that can be achieved by physical positioning is limited, and physical positioning may not meet the application requirements when the accuracy requirements of the relative positional relationship between the VCSEL laser and the optical element are high. The fixation of the components by means of brackets and/or adhesives presents assembly stability problems, and when accidental collisions occur, the individual components may come off. Even if no unexpected collision occurs, the accuracy of the fit between the individual elements may decrease over time.

As another example, as VCSEL technology is gradually matured, more high power and high power density applications are gradually developed, and more recently, the gradually matured multi-junction technology can meet the requirement of vehicle-mounted lidar application, however, the VCSEL applied to the vehicle-mounted lidar is in a severe working environment, and the optical power is rapidly reduced when the temperature of the working environment where the VCSEL is located is 85 ℃ to 105 ℃, as shown in fig. 1, based on the thermal sensitivity, the performance of the VCSEL is deteriorated with the increase of temperature. To reduce the operating temperature of a VCSEL laser, a semiconductor refrigerator may be mounted to the VCSEL laser. Currently, semiconductor refrigerators are mounted to packaged VCSEL lasers mainly by way of mounting.

However, when the semiconductor refrigerator is mounted on the packaged VCSEL laser by means of mounting, the bonding stability between the semiconductor refrigerator and the VCSEL laser is poor, and the semiconductor refrigerator is liable to fall off.

It should be noted that in the practical industry, VCSEL lasers are usually provided by a chip manufacturer, and the assembly of VCSEL packages is performed by a packaging manufacturer. I.e. two nodes of the industry chain from the VCSEL laser to the VCSEL packaged product. Moreover, in the actual industry, the packaging factories may purchase VCSEL lasers provided by different manufacturers, and at the same time, there may occur problems such as different assembly accuracy during the assembly process, resulting in difficulty in ensuring the consistency of the final molded VCSEL package products.

Disclosure of Invention

An advantage of the present application is that it provides a VCSEL wafer and a VCSEL integrated chip thereof, in which the VCSEL integrated chip integrates, on a wafer level, a VCSEL light emitting point, a light modulating section for modulating laser light emitted from the VCSEL light emitting point, a thermoelectric cooling structure for adjusting temperature, and a photodiode for realizing photoelectric conversion.

Another advantage of the present application is to provide a VCSEL wafer and a VCSEL integrated chip thereof, in which, in the VCSEL integrated chip, a VCSEL light emitting point and a light modulating portion are integrated together at a wafer level, so that relatively precise positioning can be achieved at the wafer level, and further, the combination stability of the VCSEL light emitting point and the light modulating portion can be improved, and a thermoelectric refrigeration structure is integrated at the wafer level at the VCSEL light emitting point and/or the photodiode, and further, the combination stability of the thermoelectric refrigeration structure and the VCSEL light emitting point and/or the photodiode can be improved.

Still another advantage of the present application is to provide a VCSEL wafer and a VCSEL integrated chip thereof, wherein the VCSEL integrated chip can realize fabrication and assembly of a VCSEL light emitting point and a light modulating section, assembly of a thermoelectric refrigeration structure and a VCSEL light emitting point and/or a photodiode at a chip fabrication factory, and improve industrial efficiency.

Still another advantage of the present application is to provide a VCSEL wafer and a VCSEL integrated chip thereof, in which a VCSEL light emitting point, a light modulating section, a thermoelectric refrigeration structure, and a photodiode in the VCSEL integrated chip are completed in the same chip manufacturing factory, and structural uniformity between the respective VCSEL light emitting points, structural uniformity between the respective photodiodes, assembly accuracy uniformity between the VCSEL light emitting point and the light modulating section, and assembly accuracy uniformity between the VCSEL light emitting point and/or the photodiode and the thermoelectric refrigeration structure can be improved.

To achieve at least one of the above or other advantages and objects, according to one aspect of the present application, there is provided a VCSEL integrated chip comprising:

at least one VCSEL light emitting point;

a light modulation section integrated at the wafer level at the VCSEL emission point;

at least one photodiode spaced from the VCSEL emission point, the VCSEL emission point and the photodiode sharing a substrate layer; the method comprises the steps of,

and the thermoelectric refrigeration structure is integrated at the wafer level at the VCSEL luminous point and comprises a plurality of thermocouple pairs, and each thermocouple pair comprises a P-type structure and an N-type structure which are electrically connected with each other.

In the VCSEL integrated chip according to the present application, each of the VCSEL light emitting points includes a VCSEL body, and a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, each of the VCSEL bodies includes the substrate layer, a first reflective layer, an active region, a confinement layer having a confinement hole, and a second reflective layer, the light modulation section corresponds to the confinement hole, each of the photodiodes includes a diode body, a diode positive electrode and a diode negative electrode electrically connected to the diode body, and each of the diode bodies includes the substrate layer, a first type doped semiconductor layer, an inner depletion layer, a second type doped semiconductor layer, and an anti-reflection layer.

In the VCSEL integrated chip according to the present application, the thermoelectric refrigeration structure is located on a backlight side of an active region of the VCSEL emission point, and the light modulation section is located on a light exit side of the active region of the VCSEL emission point.

In the VCSEL integrated chip according to the present application, the substrate layer of the VCSEL light emitting point, the first reflective layer, the active region and the second reflective layer are sequentially arranged from bottom to top, the confinement layer is located on the upper side of the active region and/or the lower side of the active region, the substrate layer of the photodiode, the first doped semiconductor layer, the inner depletion layer, the second doped semiconductor layer and the anti-reflective layer are sequentially arranged from bottom to top, the thermoelectric refrigeration structure is located below the substrate layer, and the light modulation section is located above the second reflective layer.

In the VCSEL integrated chip according to the present application, the substrate layer of the VCSEL light emitting point, the first reflective layer, the active region and the second reflective layer are sequentially arranged from bottom to top, the confinement layer is located on the upper side of the active region and/or the lower side of the active region, the substrate layer of the photodiode, the first doped semiconductor layer, the inner depletion layer, the second doped semiconductor layer and the anti-reflective layer are sequentially arranged from bottom to top, the thermoelectric refrigeration structure is located between the substrate layer and the first reflective layer, and the light modulation section is located above the second reflective layer.

In the VCSEL integrated chip according to the present application, the substrate layer of the VCSEL light emitting point, the first reflective layer, the active region and the second reflective layer are sequentially arranged from bottom to top, the confinement layer is located at an upper side of the active region and/or a lower side of the active region, the substrate layer of the photodiode, the first doped semiconductor layer, the inner depletion layer, the second doped semiconductor layer and the anti-reflective layer are sequentially arranged from bottom to top, the thermoelectric refrigeration structure is located above the second reflective layer, and the light modulation section is located between the substrate layer and the first reflective layer.

In the VCSEL integrated chip according to the present application, the first reflective layer is an N-DBR layer, the second reflective layer is a P-DBR layer, the first type doped semiconductor layer is an N-type doped semiconductor layer, and the second type doped semiconductor layer is a P-type doped semiconductor layer.

In the VCSEL integrated chip according to the present application, the first reflective layer is a P-DBR layer, the second reflective layer is an N-DBR layer, the first type doped semiconductor layer is a P-type doped semiconductor layer, and the second type doped semiconductor layer is an N-type doped semiconductor layer.

According to another aspect of the present application, there is provided a VCSEL wafer comprising:

at least one VCSEL integrated chip as described above.

Further objects and advantages of the present application will become fully apparent from the following description and the accompanying drawings.

These and other objects, features and advantages of the present application will become more fully apparent from the following detailed description, the accompanying drawings and the appended claims.

Drawings

These and/or other aspects and advantages of the present application will become more apparent and more readily appreciated from the following detailed description of the embodiments of the application, taken in conjunction with the accompanying drawings, wherein:

fig. 1 illustrates a schematic diagram of the relationship between the operating temperature of a VCSEL chip and its optical power.

Fig. 2 illustrates a schematic diagram of a VCSEL wafer according to an embodiment of the present application.

Fig. 3 illustrates a schematic partial cross-sectional view of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 4 illustrates another partial cross-sectional schematic view of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 5 illustrates yet another partial cross-sectional schematic of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 6 illustrates yet another partial cross-sectional schematic of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 7 illustrates yet another partial cross-sectional schematic of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 8 illustrates yet another partial cross-sectional schematic of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 9 illustrates a flow diagram of a method of fabricating a VCSEL integrated chip according to an embodiment of the present application.

Fig. 10 illustrates one of schematic diagrams of a fabrication process of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 11 illustrates a second schematic diagram of a fabrication process of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 12 illustrates another flow diagram of a method of fabricating a VCSEL integrated chip according to an embodiment of the present application.

Fig. 13 illustrates one of the schematic diagrams of another fabrication process of a VCSEL integrated chip according to an embodiment of the present application.

Figure 14 illustrates a second schematic diagram of another fabrication process of a VCSEL integrated chip according to an embodiment of the present application.

Fig. 15 illustrates yet another flow diagram of a method of fabricating a VCSEL integrated chip according to an embodiment of the present application.

Fig. 16 illustrates one of the schematic diagrams of yet another fabrication process of a VCSEL integrated chip according to an embodiment of the present application.

Figure 17 illustrates a second schematic diagram of yet another fabrication process of a VCSEL integrated chip in accordance with an embodiment of the present application.

Detailed Description

The terms and words used in the following description and claims are not limited to literal meanings, but are used only by the inventors to enable a clear and consistent understanding of the application. It will be apparent to those skilled in the art, therefore, that the following description of the various embodiments of the application is provided for illustration only and not for the purpose of limiting the application as defined by the appended claims and their equivalents.

It will be understood that the terms "a" and "an" should be interpreted as referring to "at least one" or "one or more," i.e., in one embodiment, the number of elements may be one, while in another embodiment, the number of elements may be plural, and the term "a" should not be interpreted as limiting the number.

Although ordinal numbers such as "first," "second," etc., will be used to describe various components, those components are not limited herein. The term is used merely to distinguish one component from another. For example, a first component may be referred to as a second component, and likewise, a second component may be referred to as a first component, without departing from the teachings of the present inventive concept. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing various embodiments only and is not intended to be limiting. As used herein, the singular is intended to include the plural as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, or groups thereof.

Summary of the application: as described above, there are problems of assembly stability and mounting accuracy in assembling the VCSEL laser with other devices. For example, during assembly of a VCSEL laser with an optical diffraction element, the accuracy of the mounting of the optical diffraction element relative to the VCSEL laser will greatly affect the performance of the laser projection unit. The relative positional relationship between the VCSEL laser and the optical diffraction element is currently determined mainly by physical positioning, and the element is fixed by a bracket and/or an adhesive, so that the relative positional relationship between the VCSEL laser and the optical diffraction element is maintained. In the process of assembling the laser projection unit and the camera unit, component fixation is also mainly performed by the bracket and/or the adhesive.

In the actual industry, VCSEL lasers are typically provided by a chip manufacturer, and the assembly of the VCSEL package is performed by a packaging manufacturer. I.e. two nodes of the industry chain from the VCSEL laser to the VCSEL packaged product. Moreover, in the actual industry, the packaging factories may purchase VCSEL lasers provided by different manufacturers, and at the same time, there may occur problems such as different assembly accuracy during the assembly process, resulting in difficulty in ensuring the consistency of the final molded VCSEL package products.

Based on this, the inventors of the present application propose to integrate VCSEL laser structures, optical modulation structures, thermoelectric refrigeration structures and photodiode structures at the wafer level, starting from semiconductor product design and manufacturing processes. In this way, a relatively precise positioning and relatively stable coupling between the VCSEL laser structure and the optical modulation structure, and a relatively stable coupling between the thermoelectric refrigeration structure and the VCSEL laser structure and/or the photodiode structure, is achieved.

Accordingly, according to one aspect of the present application, the present application proposes a VCSEL integrated chip comprising:

having described the basic principles of the present application, various non-limiting embodiments of the present application will now be described in detail with reference to the accompanying drawings.

Schematic VCSEL integrated chip: as shown in fig. 1 to 8, a VCSEL wafer according to an embodiment of the present application is illustrated, wherein, as shown in fig. 1, the VCSEL wafer includes at least one VCSEL integrated chip 10, and when the VCSEL wafer includes a plurality of VCSEL integrated chips 10, the plurality of VCSEL integrated chips 10 form a VCSEL integrated chip array, the VCSEL wafer has a scribe line 105 formed between at least two of the VCSEL integrated chips 10, and the VCSEL wafer may be diced along the scribe line 105 in a subsequent process to separate the plurality of VCSEL integrated chips 10. The VCSEL integrated chip 10 includes at least one VCSEL emission point 60 and at least one photodiode 90. The VCSEL light emitting point 60 may be used as a light source for a laser projection unit in a depth camera module, and the photodiode 90 may be used as a photosensor for a camera unit in a depth camera module. That is, the VCSEL integrated chip integrates a part of the laser projection unit of the depth camera module and a part of the camera unit of the depth camera module. The depth camera module can be a structured light camera module or a TOF camera module.

In particular, as shown in fig. 2 to 8, in the embodiment of the present application, the VCSEL integrated chip 10 includes at least one VCSEL emission point 60, i.e., a single VCSEL laser structure, and an optical modulation section 70 integrated at the wafer level at the VCSEL emission point 60. The VCSEL luminous point 60 and the light modulation part 70 are integrated together on the wafer level, so that relatively accurate positioning can be realized on the wafer level, the combination stability of the VCSEL luminous point 60 and the light modulation part 70 can be improved, the assembly of the VCSEL luminous point 60 and the light modulation part 70 can be realized in a chip manufacturing factory, and the industrial efficiency is improved. The VCSEL light emitting point 60 and the light modulating section 70 in the VCSEL integrated chip 10 are completed in the same chip manufacturing factory, and structural uniformity between the respective VCSEL integrated chips 10 in which the VCSEL light emitting point 60 and the light modulating section 70 are integrated, and assembly accuracy uniformity between the VCSEL light emitting point 60 and the light modulating section 70 can be improved.

Each VCSEL emission point 60 includes a VCSEL body 61, and a VCSEL positive electrode 62 and a VCSEL negative electrode 63 electrically connected to the VCSEL body 61. Each of the VCSEL bodies 61 includes a substrate layer 611, a first reflective layer 612, an active region 613, a confinement layer 614 having a confinement aperture 601, and a second reflective layer 615 stacked on top of each other, the substrate layer 611, the first reflective layer 612, the active region 613, and the second reflective layer 615 of the VCSEL light emitting point 60 being sequentially arranged from bottom to top. The confinement layer 614 is located on the upper side of the active region 613 and/or on the lower side of the active region 613. The light modulation section 70 corresponds to the restriction hole 601.

Alternatively, the first reflective layer 612 is an N-DBR layer, and the second reflective layer 615 is a P-DBR layer, that is, the substrate layer 611 of the VCSEL light emitting point 60, the N-DBR layer, the active region 613, and the P-DBR layer are sequentially arranged from bottom to top; alternatively, the first reflective layer 612 is a P-DBR layer, and the second reflective layer 615 is an N-DBR layer, that is, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top.

In an embodiment of the present application, the material of the substrate layer 611 may be a doping type material such as InP, gaN, gaAs. When the first reflective layer 612 is an N-DBR layer, the substrate layer 611 is made of an N-type doping material, and when the first reflective layer 612 is a P-DBR layer, the substrate layer 611 is made of a P-type doping material.

The N-DBR layer is made of N-type doped Al with high aluminum content _x Ga _1-x As (x= 1~0) and N-doped low aluminum content Al _x Ga _1-x Alternate layers of As (x= 1~0) are formed. The P-DBR layer is made of P-type doped Al with high aluminum content _x Ga _1-x As (x=10) and P-doped Al with low aluminum content _x Ga _1-x Alternate layers of As (x= 1~0) are formed. In some examples of the application, the N-DBR layer and the P-DBR layer may even be made of materials that do not include aluminum, i.e., aluminum. It is worth mentioning that the material selection of the alternating layers depends on the operating wavelength of the laser light emitted by the VCSEL emission point 60, and that the optical thickness of each alternating layer is equal to or approximately equal to 1/4 of the operating wavelength of the laser light.

The active region 613 is sandwiched between the first reflective layer 612 and the second reflective layer 615 to form a resonant cavity, in which photons are repeatedly amplified by back and forth reflection within the resonant cavity after being excited to form laser oscillation, thereby forming laser light. It will be appreciated by those of ordinary skill in the art that the direction of the laser light exiting the first reflective layer 612 or the second reflective layer 615 can be selectively controlled by configuring and designing the first reflective layer 612 and the second reflective layer 615, for example. Accordingly, the first and second reflective layers 612 and 615 are configured such that, after the VCSEL light emitting point 60 is turned on, laser light generated by the active region 613 is reflected multiple times in a resonant cavity formed between the first and second reflective layers 612 and 615 and then exits the second reflective layer 615, or the first reflective layer 612.

Preferably, the light modulation part 70 is located at the light emitting side of the VCSEL light emitting point 60, so that the light emitted from the VCSEL light emitting point 60 is projected after being modulated by the light modulation part 70. The light emitting side of the VCSEL emission point 30 is a light emitting side of the VCSEL emission point 60, for example, when the substrate layer 611, the first reflective layer 612, the active region 613 and the second reflective layer 615 are sequentially arranged from bottom to top, and the light emitting direction is from the active region 613 to the second reflective layer 615, the upper side of the active region 613 is the light emitting side of the VCSEL emission point 60, and the second reflective layer 615 is located on the light emitting side of the VCSEL emission point 60; when the substrate layer 611, the first reflective layer 612, the active region 613 and the second reflective layer 615 are sequentially arranged from bottom to top, and the light emitting direction is from the active region 613 to the first reflective layer 612, the lower side of the active region 613 is the light emitting side of the VCSEL light emitting point 60, and the first reflective layer 612 and the substrate layer 611 are located on the light emitting side of the VCSEL light emitting point 60.

Accordingly, in some embodiments of the present application, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the second reflective layer 615 (i.e., P-DBR layer). The light modulation section 70 is formed above the second reflection layer 615 (i.e., P-DBR layer) and corresponds to the limiting aperture 601 (as shown in fig. 3 and 4), so that the light emitted from the second reflection layer 615 (i.e., P-DBR layer) by the VCSEL light emitting point 60 is projected after being modulated by the light modulation section 70.

In other embodiments of the present application, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the N-DBR layer, the active region 613, and the P-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the first reflective layer 612 (i.e., the N-DBR layer). The light modulation part 70 is formed below the first reflective layer 612 (i.e., the N-DBR layer) and corresponds to the limiting hole 601, and may be formed between the substrate layer 611 and the first reflective layer 612 (as shown in fig. 5), such that the light emitted from the first reflective layer 612 by the VCSEL light emitting point 60 passes through the substrate layer 611 (i.e., the N-DBR layer) after being modulated by the light modulation part 70 and then is projected. Preferably, the substrate layer 611 is made of a light transmissive material and has a light transmissive structure so that light is projected through the substrate layer 611. It should be understood that the light modulating portion 70 may be formed at other locations, for example, under the substrate layer 611.

In still other embodiments of the present application, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the second reflective layer 615 (i.e., N-DBR layer). The light modulation section 70 is formed above the second reflection layer 615 (i.e., N-DBR layer) and corresponds to the confinement holes 601 (as shown in fig. 6 and 7). So that the light emitted from the second reflection layer 615 (i.e., the N-DBR layer) by the VCSEL light emitting point 60 is projected after being modulated by the light modulation section 70.

In still other embodiments of the present application, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the first reflective layer 612 (i.e., the P-DBR layer) of the first reflective layer 612. The light modulation section 70 is formed below the first reflective layer 612 (i.e., P-DBR layer) and corresponds to the limiting aperture 601 (as shown in fig. 8), and may be formed between the substrate layer 611 and the first reflective layer 612 (i.e., P-DBR layer), such that the light emitted from the first reflective layer 612 (i.e., P-DBR layer) by the VCSEL light emission point 60 is modulated by the light modulation section 70 and then projected through the substrate layer 611. It should be understood that the light modulating portion 70 may be formed at other locations, for example, under the substrate layer 611.

After the VCSEL emission point 60 is turned on, a current is limited in flow direction by the confinement layer 614, which is finally introduced into the middle region of the VCSEL emission point 60, so that the middle region of the active region 613 generates laser light. More specifically, in the embodiment of the present application, the confinement layer 614 has a confinement region surrounding the confinement holes 601, the confinement region having a higher resistivity to confine carriers flowing into the middle region of the VCSEL emission point 60, and a lower refractive index of the confinement region to laterally confine photons, the carriers and optical lateral confinement increasing the density of carriers and photons within the active region 613, increasing the efficiency of light generation within the active region 613.

In an embodiment of the present application, the confinement layer 614 may be implemented as an oxidation confinement layer 614 formed on the upper side and/or the lower side of the active region 613 by an oxidation process. The confinement layer 614 may be implemented as other types, for example, as an ion confinement layer 614 formed on the upper side or the lower side of the active region 613 by an ion implantation process, which is not limited to the present application.

The formation positions of the VCSEL positive electrode 62 and the VCSEL negative electrode 63 are not limited to the present application. In some embodiments of the present application, as shown in fig. 3 to 4, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the P-DBR layer is located above the active region 613, the N-DBR layer is located below the active region 613, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, i.e., the body upper surface 602, the upper surface of the substrate layer 611 is partially exposed, and the VCSEL negative electrode 63 is formed on the exposed portion of the upper surface of the substrate layer 611. Alternatively, the VCSEL negative electrode 63 may be formed at other locations, for example, the upper surface of the first reflective layer 612 (i.e., the N-DBR layer) is partially exposed, and the VCSEL negative electrode 63 is formed at an exposed portion of the upper surface of the first reflective layer 612 (i.e., the N-DBR layer); as another example, the lower surface of the substrate layer 611 (as shown in fig. 5). When the second reflection layer 615 (i.e., P-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on, the VCSEL positive electrode 62 may be implemented as a ring-shaped positive electrode having a light emitting hole 604 corresponding to the limiting hole 601 formed at the middle thereof to allow light to pass out when laser light generated from the active region 613 exits from the second reflection layer 615 (i.e., P-DBR layer). When the second reflection layer 615 (i.e., P-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on and laser light generated by the active region 613 is emitted from the first reflection layer 612 (i.e., N-DBR layer), the VCSEL negative electrode 63 may be implemented as a ring-shaped negative electrode, a light emitting hole 604 corresponding to the confinement hole 601 being formed at a middle portion thereof to allow light to pass out.

In other embodiments of the present application, as shown in fig. 6 to 7, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the N-DBR layer is located above the active region 613, the P-DBR layer is located below the active region 613, the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL body 61, i.e., the body upper surface 602, the upper surface of the substrate layer 611 is partially exposed, and the VCSEL positive electrode 62 is formed on the exposed portion of the upper surface of the substrate layer 611. Alternatively, the VCSEL positive electrode 62 may be formed at other locations, for example, the upper surface of the first reflective layer 612 (i.e., the P-DBR layer) is partially exposed, and the VCSEL positive electrode 62 is formed at the exposed portion of the upper surface of the first reflective layer 612 (i.e., the P-DBR layer); as another example, the lower surface of the substrate layer 611 (as shown in fig. 8). When the second reflection layer 615 (i.e., the N-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on, the laser light generated by the active region 613 is emitted from the second reflection layer 615 (i.e., the N-DBR layer), the VCSEL negative electrode 63 may be implemented as a ring-shaped negative electrode, a light emitting hole 604 corresponding to the confinement hole 601 being formed at a middle portion thereof to allow light to pass out. When the second reflection layer 615 (i.e., N-DBR layer) is located above the active region 613 and the VCSEL light emitting point 60 is turned on and laser light generated by the active region 613 is emitted from the first reflection layer 6122 (i.e., P-DBR layer), the VCSEL positive electrode 62 may be implemented as a ring-shaped negative electrode, a light emitting hole 604 corresponding to the limiting hole 601 being formed at a center thereof to allow light to pass out.

In an embodiment of the present application, the light modulation part 70 includes at least one convex lens structure and/or at least one concave lens structure and/or a grating structure. The structure type of the light modulation section 70 may be designed according to actual requirements.

When the light modulation section 70 has a convex lens structure, the convex lens structure of the light modulation section 70 can reduce the beam divergence angle of the laser light emitted from the laser light emitting surface. When the light modulation section 70 has a concave lens structure, the concave lens structure of the light modulation section 70 can increase the beam divergence angle of the light beam emitted from the laser light emitting surface.

It should be noted that, compared with the conventional technology that the optical modulation element is assembled on the VCSEL light emitting point 60 by means of other element supporting or by means of adhesive mounting, the present application integrates the optical modulation part 70 on the wafer level on the VCSEL light emitting point 60, and there is no redundant component affecting the laser between the optical modulation part 70 and the VCSEL light emitting point 60, so that the accuracy of modulating the light can be improved, and the laser emitted from the VCSEL light emitting point 60 is modulated according to the expected modulation mode.

It should be noted that in some embodiments of the present application, the VCSEL integrated chip 10 further includes a protection portion 80 covering the entire outer surface of the light modulation portion 70.

In the embodiment of the present application, the VCSEL light emitting point 60 and the photodiode 90 are formed on the same wafer, and are completed in the same chip manufacturer, or may be assembled in the chip manufacturer, so as to improve the industrial efficiency. The VCSEL emission point 60 and the photodiode 90 are completed in the same chip manufacturing facility, which can improve structural uniformity between the respective photodiodes 90, and assembly uniformity between the VCSEL emission point 60 and the photodiode 90.

The VCSEL emission point 60 is spaced apart from the photodiode 90. Each of the photodiodes 90 includes a diode body 91, a diode positive electrode 92 and a diode negative electrode 93 electrically connected to the diode body 91, each of the diode bodies 91 includes the substrate layer 611, a first doped semiconductor layer 911, an inner depletion layer 912, a second doped semiconductor layer 913, and an anti-reflection layer 914, and the VCSEL body 61 and the diode body 91 share the substrate layer 611. That is, the substrate layer 611 of the VCSEL body 61 of the VCSEL emission point 60 and the substrate layer 611 of the diode body 91 are common substrate layers.

In an embodiment of the present application, the first type doped semiconductor layer 911 is an N type doped semiconductor layer, and the second type doped semiconductor layer 913 is a P type doped semiconductor layer. In other embodiments of the present application, the first type doped semiconductor layer 911 is a P type doped semiconductor layer, and the second type doped semiconductor layer 913 is an N type doped semiconductor layer.

The N-type doped semiconductor layer may be made of N-type doped GaAs, and the N-type doped semiconductor layer may be made of P-type doped GaAs. It should be appreciated that the N-doped semiconductor layer may be made of other semiconductor materials that are N-doped and the P-doped semiconductor layer may be made of other semiconductor materials that are P-doped.

The inner depletion layer 912 may be made of undoped GaAs or low concentration N-doped GaAs, and the inner depletion layer 912 may also be made of undoped other semiconductor material or low concentration N-doped other material. The anti-reflection layer 914 may be made of silicon dioxide material and located on the light receiving surface of the photodiode 90, and the anti-reflection layer 914 may be made of other anti-reflection materials.

In the embodiment of the present application, the substrate layer 611, the first type doped semiconductor layer 911, the inner depletion layer 912, the second type doped semiconductor layer 913, and the anti-reflection layer 914 are sequentially arranged from bottom to top. When the first doped semiconductor layer 911 is an N-type doped semiconductor layer and the second doped semiconductor layer 913 is a P-type doped semiconductor layer, the substrate layer 611, the N-type doped semiconductor layer, the inner depletion layer 912, the P-type doped semiconductor layer and the anti-reflection layer 914 are sequentially arranged from bottom to top. The diode positive electrode 92 is formed over the second type doped semiconductor layer 913 (i.e., a P-type doped semiconductor layer), the upper surface of the substrate layer 611 is partially exposed, and the diode negative electrode 93 is formed on the exposed portion of the upper surface of the substrate layer 611. The diode negative electrode 93 may be formed at other locations, for example, the upper surface of the first type doped semiconductor layer 911 (i.e., N-type doped semiconductor layer) is partially exposed, and the diode negative electrode 93 is formed at the exposed portion of the upper surface of the first type doped semiconductor layer 911 (i.e., N-type doped semiconductor layer).

When the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer, the substrate layer 611, the P-type doped semiconductor layer, the inner depletion layer 912, the N-type doped semiconductor layer and the anti-reflection layer 914 are sequentially arranged from bottom to top. The diode negative electrode 93 is formed over the second type doped semiconductor (i.e., N-type doped semiconductor layer), the upper surface of the substrate layer 611 is partially exposed, and the diode positive electrode 92 is formed at the exposed portion of the upper surface of the substrate layer 611. The diode positive electrode 92 may be formed at other locations, for example, the upper surface of the first type doped semiconductor layer 911 (i.e., P-type doped semiconductor layer) is partially exposed, and the diode positive electrode 92 is formed at the exposed portion of the upper surface of the first type doped semiconductor layer 911 (i.e., P-type doped semiconductor layer).

When the substrate layer 611, the N-doped semiconductor layer, the inner depletion layer 912, the P-doped semiconductor layer and the anti-reflection layer 914 of the photodiode 90 are sequentially arranged from bottom to top, the photodiode 90 further includes a guard ring (not illustrated) surrounding the N-doped semiconductor layer.

In the embodiment of the present application, the VCSEL integrated chip 10 further includes a thermoelectric refrigeration structure 30 to reduce the operating temperature of the VCSEL integrated chip 10, and the thermoelectric refrigeration structure 30 is integrated at the VCSEL light emitting point 60 and/or the photodiode 90 on a wafer level, so that the bonding strength between the thermoelectric refrigeration structure 30 and the VCSEL light emitting point 60 and/or the photodiode 90 can be improved.

The thermoelectric refrigeration structure 30 utilizes the peltier effect to reduce the operating temperature of the VCSEL integrated chip 10. The Peltier effect refers to that when current passes through loops formed by different conductors, irreversible Joule heat is generated, and the joints of the different conductors can be separated according to the different directions of the currentAnd the phenomena of heat absorption and heat release are generated. Accordingly, the thermoelectric refrigeration structure 30 includes a plurality of thermocouple pairs 31, each thermocouple pair 31 including two different types of conductor structures, namely a P-type structure 311 and an N-type structure 312, to form a hot side and a cold side. The P-type structure 311 may be implemented as an alloy of P-type material doped Bi or Te (e.g., bi ₂ Te ₃ Or BiSb), pbTe, siGe, mgSi, P-doped elements Sb, B, etc.; the N-type structure 312 may be implemented as an alloy of N-type material doped Bi or Te (e.g., bi2Te3 or BiSb), pbTe, siGe, mgSi, N-type doping elements Se, P, etc.

The thermoelectric refrigeration structure 30 further includes a thermoelectric positive electrode 32 electrically connected to one of the thermocouple pairs 31 and a thermoelectric negative electrode 33 electrically connected to the other of the thermocouple pairs 31. The thermoelectric positive electrode 32 is formed at the N-type structure 312 of one of the thermocouple pairs, and the thermoelectric negative electrode 33 is formed at the P-type structure 311 of one of the thermocouple pairs 31. The hot side of the thermoelectric refrigeration structure 30, i.e., the heat-emitting side, and the cold side of the thermoelectric refrigeration structure 30, i.e., the heat-absorbing side, may be controlled by controlling the electrical connection of the thermoelectric refrigeration structure 30. Optionally, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control a hot end of the thermoelectric refrigeration structure 30 to be formed at a bottom of the thermoelectric refrigeration structure 30; alternatively, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control the hot side of the thermoelectric refrigeration structure 30 to be formed on top of the thermoelectric refrigeration structure 30.

Optionally, a plurality of said thermocouple pairs 31 are connected in electrical series, thermal parallel. Accordingly, the thermoelectric cooling structure 31 includes a plurality of first electrical connection lines 341 and a plurality of second electrical connection lines 351, one first electrical connection line 341 is formed between one P-type structure 311 and one N-type structure 312 of each thermocouple pair 31, and one second electrical connection line 351 is formed between the P-type structure 311 of each thermocouple pair 31 and the N-type structure 312 of the other thermocouple pair 31 in each two adjacent thermocouple pairs 31. Accordingly, each of the first electrical connection lines 341 is formed between the P-type structure 311 and the N-type structure 312 of each of the thermocouple pairs 31, and each of the second electrical connection lines 432 is formed between the P-type structure 311 of one of the thermocouple pairs 31 and the N-type structure 312 of the adjacent thermocouple pair 31. The plurality of first electrical connection lines 341 form a first electrical connection layer 34, and the plurality of second electrical connection lines 351 form a second electrical connection layer 35.

The thermoelectric refrigeration structure 30 also includes an insulating filler 36. At least part of the insulating filler 36 is filled between the P-type structure 311 and the N-type structure 312 of the two adjacent thermocouple pairs 31; at least a portion of the insulating filler 36 is filled between the P-type structure 311 and the N-type structure 312 of each of the thermocouple ends 31.

The thermoelectric cooling structure 30 further comprises an insulating layer 37 formed between the VCSEL body 61 and/or the diode body 91 to electrically isolate the VCSEL emission point 60 and/or the photodiode 90 from the thermoelectric cooling structure 30.

Alternatively, the thermoelectric cooling structure 30 may be formed on the surface of the VCSEL body 61 and/or the photodiode body 91 (as shown in fig. 3 and 5 and fig. 6 to 8), and may also be formed in the VCSEL body 61 and/or the photodiode body 91 (as shown in fig. 4 and 7). When the thermoelectric refrigeration structure 30 is formed on the surface of the VCSEL main body 61, the thermoelectric refrigeration structure 30 is convenient to be attached to a heat sink structure during packaging, so that heat dissipation is accelerated. The heat sink structure refers to a structure in which the temperature is not substantially changed with the change of heat transferred thereto.

Preferably, the thermoelectric refrigeration structure 30 is formed on the backlight side of the VCSEL emission point 60 to avoid affecting the light extraction performance of the VCSEL emission point 60. The backlight side of the VCSEL emission point 30 refers to a side of the active region 613 that emits light away from the light emitting direction, for example, when the substrate layer 611, the first reflective layer 612, the active region 613, and the second reflective layer 615 are sequentially arranged from bottom to top, and the light emitting direction is from the active region 613 to the second reflective layer 615, the lower side of the active region 613 is the backlight side of the VCSEL emission point 60, and the first reflective layer 612 and the substrate layer are located on the backlight side of the VCSEL emission point; the substrate layer 611, the first reflective layer 612, the active region 613 and the second reflective layer 615 are sequentially arranged from bottom to top, and when the light emitting direction is from the active region 613 to the first reflective layer 612, the side of the active region 613 is the backlight side of the VCSEL light emitting point 60, and the second reflective layer 615 is located on the backlight side of the VCSEL light emitting point 60.

Accordingly, in some embodiments of the present application, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the second reflective layer 615 (i.e., P-DBR layer). The thermoelectric cooling structure 30 is formed below the substrate layer 611. In a specific example of the present application, the lower surface of the substrate layer 611 forms the lower surface of the VCSEL light emitting body 61, that is, the thermoelectric refrigeration structure 30 is formed on the lower surface of the VCSEL light emitting body 61.

When the thermoelectric refrigeration structure 30 is formed on the substrate layer 611, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control a hot side of the thermoelectric refrigeration structure 30 to be formed at a bottom of the thermoelectric refrigeration structure 30. The top of the thermoelectric refrigeration structure 30 absorbs heat from the VCSEL emission point 60 and/or the photodiode 90, and the thermoelectric refrigeration structure 30 dissipates heat through the heat sink structure, so that the VCSEL body 10 operates at a lower temperature, guaranteeing its performance, e.g., its optical power. The thermoelectric cooling structure 30 includes an insulating layer 37 formed between the substrate layer 611 and the thermocouple pair 31.

In other embodiments of the present application, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the second reflective layer 615 (i.e., P-DBR layer). The thermoelectric cooling structure 30 is formed between the substrate layer 611 and the first reflective layer 612 (i.e., the N-DBR layer).

When the thermoelectric refrigeration structure 30 is formed between the substrate layer 611 and the first reflective layer 612, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control a hot side of the thermoelectric refrigeration structure 30 to be formed at a bottom of the thermoelectric refrigeration structure 30. The top of the thermoelectric cooling structure 30 absorbs heat from the VCSEL emission point 60 and/or the photodiode 90, and the bottom of the thermoelectric cooling structure 30 dissipates heat through the substrate layer 611. Optionally, a heat sink structure may be provided at the substrate layer 611 to further dissipate heat through the heat sink structure. The thermoelectric cooling structure 30 includes an insulating layer 37 formed between the substrate layer 611 and the thermocouple pair 31 and an insulating layer 37 formed between the substrate layer 611 and the first reflective layer 612.

In still other embodiments of the present application, the first reflective layer 612 is an N-DBR layer, the second reflective layer 615 is a P-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the first reflective layer 612 (i.e., N-DBR layer). The thermoelectric cooling structure 30 is formed over the second reflective layer 615 (i.e., P-DBR layer).

When the thermoelectric refrigeration structure 30 is formed over the thermoelectric refrigeration structure 30 formed over the second reflective layer 615, the thermoelectric positive electrode 32 and the thermoelectric negative electrode 33 are configured to control a hot side of the thermoelectric refrigeration structure 30 to be formed on a bottom top side of the thermoelectric refrigeration structure 30. The bottom of the thermoelectric cooling structure 30 absorbs heat from the VCSEL emission point 60 and/or the photodiode 90, and the top of the thermoelectric cooling structure 30 dissipates heat through the substrate layer 611. The thermoelectric refrigeration structure 30 includes an insulating layer 37 formed between the second reflective layer 615 and the thermocouple pair 31.

In still other embodiments of the present application, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the second reflective layer 615 (i.e., N-DBR layer). The thermoelectric cooling structure 30 is formed below the substrate layer 611. In a specific example of the present application, the lower surface of the substrate layer 611 forms the lower surface of the VCSEL light emitting body 61, that is, the thermoelectric refrigeration structure 30 is formed on the lower surface of the VCSEL light emitting body 61.

In still other embodiments of the present application, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the second reflective layer 615 (i.e., N-DBR layer). The thermoelectric cooling structure 30 is formed between the substrate layer 611 and the first reflective layer 612 (i.e., the P-DBR layer).

In still other embodiments of the present application, the first reflective layer 612 is a P-DBR layer, the second reflective layer 615 is an N-DBR layer, the substrate layer 611 of the VCSEL light emitting point 60, the P-DBR layer, the active region 613, and the N-DBR layer are sequentially arranged from bottom to top, and the light emitting direction of the VCSEL light emitting point 60 is directed from the active region 613 toward the first reflective layer 612 (i.e., P-DBR layer). The thermoelectric cooling structure 30 is formed over the second reflective layer 615 (i.e., the N-DBR layer).

The manufacturing method of the schematic VCSEL integrated chip comprises the following steps: accordingly, in an embodiment of the present application, a method for manufacturing a VCSEL integrated chip is provided, as shown in fig. 9 to 11, which includes: s110, forming at least one VCSEL body 61 by an epitaxial growth process, wherein the VCSEL body 61 comprises: a substrate layer 611, a first reflective layer 612, an active region 613, a confinement layer 614 having a confinement aperture 601, and a second reflective layer 615; s120 of forming an optical modulation section 70 on the upper surface of the VCSEL main body 61; s130, growing a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 over the substrate layer 611 to form a diode body 91; s140 of forming a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61, and forming a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91; and S150, forming a thermoelectric cooling structure 30 under the substrate layer 611.

In step S110, at least one VCSEL body 61 is formed by an epitaxial growth process. In particular, the specific embodiment of forming the VCSEL body 61 is not limiting of the application. In one specific example of the present application, first, a substrate layer 611 is provided, and then, first, alternating layers of semiconductor of a first doping type, an active region forming layer, and alternating layers of semiconductor of a second doping type stacked on the substrate layer 611 are grown on the substrate layer 611 through an epitaxial growth process to form an epitaxial body structure including the first alternating layers of semiconductor of a first doping type, the active region forming layer, and the alternating layers of semiconductor of a second doping type stacked on the substrate layer 611. The first doping type semiconductor alternating layers, the active region forming layer and the second doping type semiconductor alternating layers are arranged from bottom to top. The first doping type semiconductor alternating layer is implemented as an N type semiconductor alternating layer, the second doping type semiconductor alternating layer is implemented as a P type semiconductor alternating layer, or the first doping type semiconductor alternating layer is implemented as a P type semiconductor alternating layer, and the second doping type semiconductor alternating layer is implemented as an N type semiconductor alternating layer. Next, a VCSEL emission point forming region is defined, and a portion outside the VCSEL emission point forming region of the epitaxial body is removed by an etching process so that the epitaxial body structure is partitioned into a plurality of cell structures for forming the VCSEL emission point 60. Specifically, each layer structure of the epitaxial body structure (i.e., the N-type semiconductor alternating layer, the active region forming layer, and the P-type semiconductor alternating layer) is divided into a plurality of sub-unit regions, respectively. Each unit structure comprises: at least one first doping type semiconductor alternating layer subunit region, at least one active region forming layer subunit region and at least one second doping type semiconductor alternating layer subunit region. The unit structure is subjected to oxidation treatment, so that part of alternating layers of each first doping type semiconductor alternating layer subunit region and/or part of alternating layers of the second doping type semiconductor alternating layer subunit region near the outer edge of the unit structure are oxidized to form a limiting region, part near the center of the unit structure is not oxidized to form a limiting hole 601 in the limiting region, and part of alternating layers of the first doping type semiconductor alternating layer subunit region and/or part of alternating layers of the second doping type semiconductor alternating layer subunit region in the unit structure form a limiting layer 614 with the limiting hole 601. The confinement layer 614 may also be formed by other means, such as, for example, ion implantation processes to form the confinement layer 614. In this way, each oxidized cell structure and the substrate layer 611 form the VCSEL body 61, wherein the portion of the first-doped semiconductor alternating layer sub-cell region where the confinement layer is not formed forms the first reflective layer 612, the portion of the second-doped semiconductor alternating layer sub-cell region where the confinement layer is not formed forms the second reflective layer 615, and the active region forming layer sub-cell region forms the active region of the VCSEL body 61. In an embodiment of the present application, the substrate layer 611 may be thinned.

In step S120, an optical modulation section 70 is formed on the upper surface of the VCSEL main body 61. Specifically, the manner of forming the light modulation section 70 is not limited to the present application. In one embodiment of the present application, the light modulation part 70 is formed through an over-etching process. First, a modulation section forming layer may be formed on the second doping type semiconductor alternating layer. Then, in a process of removing a portion other than the VCSEL light emitting point forming region of the epitaxial body by an etching process so that the epitaxial body structure is partitioned into a plurality of unit structures for forming the VCSEL light emitting point 60, the modulation section forming layer is also partitioned into a plurality of sub-unit regions so that the modulation section forming layer is partitioned into a plurality of modulation section forming sub-unit regions which are spaced apart from each other and respectively correspond to the plurality of unit structures. Next, a plurality of the modulation section forming sub-unit regions are respectively removed by etching the plurality of the modulation section forming sub-unit regions, respectively, and the remaining portions form a plurality of the light modulation sections 70 having a predetermined shape.

In another embodiment of the present application, the light modulation part 70 is formed by an oxidation process. First, a modulation section forming layer may be formed on the second doping type semiconductor alternating layer. The modulation section forming layer includes at least two semiconductor layer structure layers made of semiconductor materials doped with metal atoms having different concentrations. Then, in a process of removing a portion other than the VCSEL light emitting point forming region of the epitaxial body by an etching process so that the epitaxial body structure is partitioned into a plurality of unit structures for forming the VCSEL light emitting point 60, the modulation section forming layer is also partitioned into a plurality of sub-unit regions so that the modulation section forming layer is partitioned into a plurality of modulation section forming sub-unit regions which are spaced apart from each other and respectively correspond to the plurality of unit structures. Next, the modulation portion forming layer sub-unit region is subjected to oxidation treatment, a predetermined region of the semiconductor layer structure layer of the modulation portion forming layer sub-unit region is close to an outer edge of the modulation portion forming layer sub-unit region, and is oxidized to form a protection portion 80, a region of the modulation portion forming layer sub-unit region which is not oxidized forms the light modulation portion 70, and the protection portion 80 covers an entire outer surface of the light modulation portion 70. Alternatively, oxidizing the unit structure and oxidizing the modulation portion formation layer may be performed simultaneously or separately.

In step S130, a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 are grown over the substrate layer 611 to form a diode body 91. Specifically, a photodiode formation region is defined, which is spaced apart from the VCSEL light emission point formation region. A first type doped semiconductor layer 911, an inner depletion layer 912, and an anti-reflection layer 914, a second type doped semiconductor layer 913 stacked on the substrate layer 611 are formed on the substrate layer 611 by an epitaxial growth process to form the diode body 91. When the first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, the first doped semiconductor layer 911 is an N-type doped semiconductor layer and the second doped semiconductor layer 913 is a P-type doped semiconductor layer. When the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer.

In step S140, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91 are formed. Specifically, the formation manner and the formation position of the VCSEL positive electrode 62 and the VCSEL negative electrode 63, and the diode positive electrode 92 and the diode negative electrode 93 are not limited by the present application. In an embodiment of the present application, when the N-type semiconductor alternating layers, the active region forming layer, and the P-type semiconductor alternating layers are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61 by electroplating, that is, the body upper surface 602, and the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating; forming the diode positive electrode 92 on the upper surface of the diode body 91 by electroplating; the diode negative electrode 93 is formed on the upper surface of the VCSEL substrate layer 611 by electroplating.

Forming the VCSEL positive electrode 62 on the upper surface of the VCSEL substrate layer 611 by electroplating when the P-type semiconductor alternating layers, the active region forming layers, and the N-type semiconductor alternating layers are arranged from bottom to top; forming the VCSEL negative electrode 63 on the upper surface of the VCSEL body 61, i.e., body upper surface 602, by electroplating; forming the diode positive electrode 92 on the upper surface of the VCSEL substrate layer 611 by electroplating; the diode negative electrode 93 is formed on the upper surface of the diode body 91 by electroplating.

In step S150, a thermoelectric cooling structure 30 is formed under the substrate layer 611. Specifically, first, an insulating layer 37 is formed on the lower surface of the substrate layer 611. Then, a first electrical connection layer 34 is formed on the lower surface of the insulating layer 37, and the first electrical connection layer 34 includes a plurality of first electrical connection lines 341 spaced apart from each other. Next, a plurality of thermocouple pairs 31 may be grown on the lower surface of the first electrical connection line 341 through a semiconductor growth process, each thermocouple pair 31 including a P-type structure 311 and an N-type structure 312, the P-type structure 311 and the N-type structure 312 of one thermocouple pair 31 being formed on one of the first electrical connection line 341. Subsequently, a second electric connection layer 35, a thermoelectric positive electrode 32, and a thermoelectric negative electrode 33 may be formed on the lower surface of the thermocouple pair 31, wherein the second electric connection layer 35 includes a plurality of second electric connection lines 351 spaced apart from each other, one of the second electric connection lines 351 being formed between one P-type structure 311 of one of the thermocouple pairs 31 and an N-type structure 312 of the thermocouple pair 31 adjacent thereto; the thermoelectric positive electrode 32 is formed on the N-type structure 312 of one thermocouple pair 31, and the thermoelectric negative electrode 33 is formed on the P-type structure 311 of one thermocouple pair 31.

In an embodiment of the present application, another method for manufacturing a VCSEL integrated chip is proposed, as shown in fig. 12 to 14, which includes: s210, providing a substrate layer 611; s220, forming a thermoelectric refrigeration structure 30 over the substrate layer; s230, forming a first reflective layer 612, an active region 613, a confinement layer 614 having a confinement aperture 601, and a second reflective layer 615 over the thermoelectric refrigeration structure 30 to form an integrated unit of the thermoelectric refrigeration structure 30 and the VCSEL body 61; s240 forming an optical modulation section 70 on the upper surface of the VCSEL main body 61; s250, growing a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 on the thermoelectric cooling structure 30 to form a diode body 91; s260, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91 are formed.

In step S210, a substrate layer 611 is provided. Specifically, the material of the substrate layer 611 may be a doping type material such as InP, gaN, gaAs.

In step S220, a thermoelectric cooling structure 30 is formed on the substrate layer to form an integrated unit of the thermoelectric cooling structure 30 and the VCSEL body 61. Specifically, first, an insulating layer 37 is formed on the substrate layer 611. Then, an electrical connection layer including a plurality of electrical connection lines spaced apart from each other, a thermoelectric positive electrode 32, and a thermoelectric negative electrode 33 are formed on the insulating layer 37. Next, a plurality of thermocouple pairs 31 may be grown over the electrical connection lines by a semiconductor growth process, each thermocouple pair 31 including a P-type structure 311 and an N-type structure 312, the P-type structure 311 and the N-type structure 312 of one thermocouple pair 31 being formed on one of the electrical connection lines; an N-type structure 312 is formed on the thermoelectric positive electrode 32 and a P-type structure 311 is formed on the thermoelectric negative electrode 33. Subsequently, another electrical connection layer including a plurality of electrical connection lines spaced apart from each other may be formed over the thermocouple pair 31, each electrical connection line over the thermocouple pair 31 being formed between one P-type structure 311 of one of the thermocouple pairs 31 and an N-type structure 312 of the thermocouple pair 31 adjacent thereto. Then, another insulating layer 37 is formed on the second electrical connection line 351.

In step S230, a first reflective layer 612, an active region 613, a confinement layer 614 with a confinement aperture 601 and a second reflective layer 615 are formed over the insulating layer 37 of the thermoelectric refrigeration structure 30 on the second electrical connection line 351 to form an integrated unit of the thermoelectric refrigeration structure 30 and the VCSEL body 61. Specifically, a first doping type semiconductor alternating layer, an active region forming layer, and a second doping type semiconductor alternating layer are grown on the thermoelectric cooling structure 30 through an epitaxial growth process to form an epitaxial body structure including the first doping type semiconductor alternating layer, the active region forming layer, and the second doping type semiconductor alternating layer. The first doping type semiconductor alternating layers, the active region forming layer and the second doping type semiconductor alternating layers are arranged from bottom to top. The first doping type semiconductor alternating layer is implemented as an N type semiconductor alternating layer, the second doping type semiconductor alternating layer is implemented as a P type semiconductor alternating layer, or the first doping type semiconductor alternating layer is implemented as a P type semiconductor alternating layer, and the second doping type semiconductor alternating layer is implemented as an N type semiconductor alternating layer. Next, a VCSEL emission point forming region is defined, and a portion outside the VCSEL emission point forming region of the epitaxial body is removed by an etching process so that the epitaxial body structure is partitioned into a plurality of cell structures for forming the VCSEL emission point 60. Specifically, each layer structure of the epitaxial body structure (i.e., the N-type semiconductor alternating layer, the active region forming layer, and the P-type semiconductor alternating layer) is divided into a plurality of sub-unit regions, respectively. Each unit structure comprises: at least one first doping type semiconductor alternating layer subunit region, at least one active region forming layer subunit region and at least one second doping type semiconductor alternating layer subunit region. The unit structure is subjected to oxidation treatment, so that part of alternating layers of each first doping type semiconductor alternating layer subunit region and/or part of alternating layers of the second doping type semiconductor alternating layer subunit region near the outer edge of the unit structure are oxidized to form a limiting region, part near the center of the unit structure is not oxidized to form a limiting hole 601 in the limiting region, and part of alternating layers of the first doping type semiconductor alternating layer subunit region and/or part of alternating layers of the second doping type semiconductor alternating layer subunit region in the unit structure form a limiting layer 614 with the limiting hole 601. The confinement layer 614 may also be formed by other means, such as, for example, ion implantation processes to form the confinement layer 614. In this way, each oxidized cell structure and the substrate layer 611 form the VCSEL body 61, wherein the portion of the first-doped semiconductor alternating layer sub-cell region where the confinement layer is not formed forms the first reflective layer 612, the portion of the second-doped semiconductor alternating layer sub-cell region where the confinement layer is not formed forms the second reflective layer 615, and the active region forming layer sub-cell region forms the active region of the VCSEL body 61. In an embodiment of the present application, the substrate layer 611 may be thinned.

In step S240, an optical modulation section 70 is formed on the upper surface of the VCSEL main body 61. Specifically, the manner of forming the light modulation section 70 is not limited to the present application. In one embodiment of the present application, the light modulation part 70 is formed through an over-etching process. First, a modulation section forming layer may be formed on the second doping type semiconductor alternating layer. Then, in a process of removing a portion other than the VCSEL light emitting point forming region of the epitaxial body by an etching process so that the epitaxial body structure is partitioned into a plurality of unit structures for forming the VCSEL light emitting point 60, the modulation section forming layer is also partitioned into a plurality of sub-unit regions so that the modulation section forming layer is partitioned into a plurality of modulation section forming sub-unit regions which are spaced apart from each other and respectively correspond to the plurality of unit structures. Next, a plurality of the modulation section forming sub-unit regions are respectively removed by etching the plurality of the modulation section forming sub-unit regions, respectively, and the remaining portions form a plurality of the light modulation sections 70 having a predetermined shape.

In step S250, a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 are grown on the thermoelectric cooling structure 30 to form a diode body 91. Specifically, a photodiode formation region is defined, which is spaced apart from the VCSEL light emission point formation region. A first type doped semiconductor layer 911, an internal depletion layer 912, and an anti-reflection layer 914, a second type doped semiconductor layer 913 stacked on the thermoelectric cooling structure 30 are formed on the thermoelectric cooling structure 30 by an epitaxial growth process to form a diode body 91. When the first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, the first doped semiconductor layer 911 is an N-type doped semiconductor layer and the second doped semiconductor layer 913 is a P-type doped semiconductor layer. When the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer.

In step S260, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL main body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode main body 91 are formed. Specifically, the formation manner and the formation position of the VCSEL positive electrode 62 and the VCSEL negative electrode 63, and the diode positive electrode 92 and the diode negative electrode 93 are not limited by the present application. In an embodiment of the present application, when the N-type semiconductor alternating layers, the active region forming layer, and the P-type semiconductor alternating layers are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61 by electroplating, that is, the body upper surface 602, and the VCSEL negative electrode 63 is formed on the N-type semiconductor alternating layers by electroplating; forming the diode positive electrode 92 on the upper surface of the diode body 91 by electroplating; the diode negative electrode 93 is formed on the N-type doped semiconductor layer by electroplating.

Forming the VCSEL positive electrode 62 on the P-type semiconductor alternating layer by electroplating when the P-type semiconductor alternating layer, the active region forming layer, and the N-type semiconductor alternating layer are arranged from bottom to top; forming the VCSEL negative electrode 63 on the upper surface of the VCSEL body 61, i.e., body upper surface 602, by electroplating; forming the diode positive electrode 92 on the P-type doped semiconductor layer by electroplating; the diode negative electrode 93 is formed on the upper surface of the diode body 91 by electroplating.

In an embodiment of the present application, there is provided a method for manufacturing a VCSEL integrated chip, as shown in fig. 15 to 17, including: s310, providing a substrate layer 611; s320 of forming a light modulation section 70 on the substrate layer 611; s330 forming a first reflective layer 612, an active region 613, a confinement layer 614 having a confinement hole 601, and a second reflective layer 615 over the light modulation section 70 to form an integrated unit of the light modulation section 70 and the VCSEL body 61; s340 growing a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 on the substrate layer 611 to form a diode body 91; s350 of forming a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61, and forming a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91; and S360 forming a thermoelectric cooling structure 30 over the VCSEL body 61 and/or over the diode body 91.

In step S310, a substrate layer 611 is provided. Specifically, the material of the substrate layer 611 may be a doping type material such as InP, gaN, gaAs.

In step S320, the light modulation section 70 is formed on the substrate layer 611. Specifically, the manner of forming the light modulation section 70 is not limited to the present application. In one embodiment of the present application, the light modulation part 70 is formed by an oxidation process. First, a modulation section forming layer including at least two semiconductor layer structure layers made of semiconductor materials doped with metal atoms having different concentrations may be formed on the substrate layer 611. Then, the modulation section forming layer is divided into a plurality of sub-unit regions, so that the modulation section forming layer is divided into a plurality of modulation section forming sub-unit regions spaced apart from each other. Next, the modulation portion forming layer sub-unit region is subjected to oxidation treatment, a predetermined region of the semiconductor layer structure layer of the modulation portion forming layer sub-unit region is close to an outer edge of the modulation portion forming layer sub-unit region, and is oxidized to form a protection portion 80, a region of the modulation portion forming layer sub-unit region which is not oxidized forms the light modulation portion 70, and the protection portion 80 covers an entire outer surface of the light modulation portion 70.

In step S330, a first reflective layer 612, an active region 613, a confinement layer 614 having a confinement hole 601, and a second reflective layer 615 are formed over a plurality of the light modulation sections 70 to form an integrated unit of the light modulation sections 70 and the VCSEL main body 61. Specifically, a first doping type semiconductor alternating layer, an active region forming layer, and a second doping type semiconductor alternating layer are grown on the modulation section forming layer or the light modulation section 70 and the protection section 80 by an epitaxial growth process to form an epitaxial body structure including the first doping type semiconductor alternating layer, the active region forming layer, and the second doping type semiconductor alternating layer. The first doping type semiconductor alternating layers, the active region forming layer and the second doping type semiconductor alternating layers are arranged from bottom to top. The first doping type semiconductor alternating layer is implemented as an N type semiconductor alternating layer, the second doping type semiconductor alternating layer is implemented as a P type semiconductor alternating layer, or the first doping type semiconductor alternating layer is implemented as a P type semiconductor alternating layer, and the second doping type semiconductor alternating layer is implemented as an N type semiconductor alternating layer. Next, a VCSEL emission point forming region is defined, and a portion outside the VCSEL emission point forming region of the epitaxial body is removed by an etching process so that the epitaxial body structure is partitioned into a plurality of cell structures for forming the VCSEL emission point 60. Specifically, each layer structure of the epitaxial body structure (i.e., the N-type semiconductor alternating layer, the active region forming layer, and the P-type semiconductor alternating layer) is divided into a plurality of sub-unit regions, respectively. Each unit structure comprises: at least one first doping type semiconductor alternating layer subunit region, at least one active region forming layer subunit region and at least one second doping type semiconductor alternating layer subunit region. The unit structure is subjected to oxidation treatment, so that part of alternating layers of each first doping type semiconductor alternating layer subunit region and/or part of alternating layers of the second doping type semiconductor alternating layer subunit region near the outer edge of the unit structure are oxidized to form a limiting region, part near the center of the unit structure is not oxidized to form a limiting hole 601 in the limiting region, and part of alternating layers of the first doping type semiconductor alternating layer subunit region and/or part of alternating layers of the second doping type semiconductor alternating layer subunit region in the unit structure form a limiting layer 614 with the limiting hole 601. The confinement layer 614 may also be formed by other means, such as, for example, ion implantation processes to form the confinement layer 614. In this way, each oxidized cell structure and the substrate layer 611 form the VCSEL body 61, wherein the portion of the first-doped semiconductor alternating layer sub-cell region where the confinement layer is not formed forms the first reflective layer 612, the portion of the second-doped semiconductor alternating layer sub-cell region where the confinement layer is not formed forms the second reflective layer 615, and the active region forming layer sub-cell region forms the active region of the VCSEL body 61. In an embodiment of the present application, the substrate layer 611 may be thinned.

In step S340, a first type doped semiconductor layer 911, an inner depletion layer 912, a second type doped semiconductor layer 913, and an anti-reflection layer 914 are grown on the substrate layer 611 to form a diode body 91. Specifically, a photodiode formation region is defined, which is spaced apart from the VCSEL light emission point formation region. A first type doped semiconductor layer 911, an inner depletion layer 912, and an anti-reflection layer 914, a second type doped semiconductor layer 913 stacked on the substrate layer 611 are formed on the substrate layer 611 by an epitaxial growth process to form the diode body 91. When the first doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer, the first doped semiconductor layer 911 is an N-type doped semiconductor layer and the second doped semiconductor layer 913 is a P-type doped semiconductor layer. When the first doped semiconductor alternating layer is implemented as a P-type semiconductor alternating layer and the second doped semiconductor alternating layer is implemented as an N-type semiconductor alternating layer, the first doped semiconductor layer 911 is a P-type doped semiconductor layer and the second doped semiconductor layer 913 is an N-type doped semiconductor layer.

In step S350, a VCSEL positive electrode 62 and a VCSEL negative electrode 63 connected to the VCSEL body 61 are formed, and a diode positive electrode 92 and a diode negative electrode 93 connected to the diode body 91 are formed. Specifically, the formation manner and the formation position of the VCSEL positive electrode 62 and the VCSEL negative electrode 63, and the diode positive electrode 92 and the diode negative electrode 93 are not limited by the present application. In an embodiment of the present application, when the N-type semiconductor alternating layers, the active region forming layer, and the P-type semiconductor alternating layers are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, that is, the body upper surface 602, by electroplating, that is, the VCSEL positive electrode 62 is formed on the body upper surface 602; forming the diode positive electrode 92 on the upper surface of the diode body 91 by electroplating; forming the VCSEL negative electrode 63 on the lower surface of the VCSEL substrate layer 611 by electroplating; the diode negative electrode 93 is formed on the lower surface of the VCSEL substrate layer 611 by electroplating.

Forming the VCSEL positive electrode 62 on the lower surface of the VCSEL substrate layer 611 by electroplating when the P-type semiconductor alternating layers, the active region forming layers, and the N-type semiconductor alternating layers are arranged from bottom to top; the VCSEL negative electrode 63 is formed on the upper surface of the VCSEL body 61, i.e., body upper surface 602, by electroplating: forming the diode negative electrode 93 on the upper surface of the diode body 91 by electroplating; forming the VCSEL positive electrode 62 on the lower surface of the VCSEL substrate layer 611 by electroplating; the diode positive electrode 92 is formed on the lower surface of the VCSEL substrate layer 611 by electroplating.

In step S360, a thermoelectric cooling structure 30 is formed over the VCSEL body 61 and/or over the diode body 91. Specifically, when the N-type semiconductor alternating layers, the active region forming layers, and the P-type semiconductor alternating layers are arranged from bottom to top, the VCSEL positive electrode 62 is formed on the upper surface of the VCSEL body 61, and the diode positive electrode 92 is formed on the upper surface of the diode body 91, first, the insulating layer 37 is formed on the upper surface of the VCSEL positive electrode 62 and/or the diode positive electrode 92. Then, an electrical connection layer including a plurality of electrical connection lines spaced apart from each other, a thermoelectric positive electrode 32, and a thermoelectric negative electrode 33 are formed on the insulating layer 37. Next, a plurality of thermocouple pairs 31 may be grown over the electrical connection lines by a semiconductor growth process, each thermocouple pair 31 including a P-type structure 311 and an N-type structure 312, the P-type structure 311 and the N-type structure 312 of one thermocouple pair 31 being formed on one of the electrical connection lines; an N-type structure 312 is formed on the thermoelectric positive electrode 32 and a P-type structure 311 is formed on the thermoelectric negative electrode 33. Subsequently, another electrical connection layer including a plurality of electrical connection lines spaced apart from each other may be formed over the thermocouple pair 31, each electrical connection line over the thermocouple pair 31 being formed between one P-type structure 311 of one of the thermocouple pairs 31 and an N-type structure 312 of the thermocouple pair 31 adjacent thereto.

In summary, the VCSEL wafer and the VCSEL integrated chip 10 according to the embodiments of the present application are illustrated, and in the VCSEL integrated chip 10, the thermoelectric refrigeration structure is integrated at the VCSEL light emitting point and/or the photodiode on the wafer level, so that the bonding stability of the thermoelectric refrigeration structure and the VCSEL light emitting point and/or the photodiode can be improved.

The basic principles of the present application have been described above in connection with specific embodiments, however, it should be noted that the advantages, benefits, effects, etc. mentioned in the present application are merely examples and not intended to be limiting, and these advantages, benefits, effects, etc. are not to be considered as essential to the various embodiments of the present application. Furthermore, the specific details disclosed herein are for purposes of illustration and understanding only, and are not intended to be limiting, as the application is not necessarily limited to practice with the above described specific details.

Claims

1. A VCSEL integrated chip, comprising:

at least one VCSEL light emitting point;

2. The VCSEL integrated chip of claim 1, wherein each of the VCSEL light emitting points comprises a VCSEL body, and a VCSEL positive electrode and a VCSEL negative electrode electrically connected to the VCSEL body, each of the VCSEL bodies comprising the substrate layer, a first reflective layer, an active region, a confinement layer having a confinement aperture, and a second reflective layer, the light modulating portion corresponding to the confinement aperture, each of the photodiodes comprising a diode body, a diode positive electrode and a diode negative electrode electrically connected to the diode body, each of the diode bodies comprising the substrate layer, a first-type doped semiconductor layer, an inner depletion layer, a second-type doped semiconductor layer, and an anti-reflective layer.

3. The VCSEL integrated chip of claim 2, wherein the thermoelectric refrigeration structure is located on a backlight side of an active region of the VCSEL emission point and the light modulation section is located on a light exit side of the active region of the VCSEL emission point.

4. A VCSEL integrated chip as claimed in claim 3, wherein the substrate layer of the VCSEL emission point, the first reflective layer, the active region and the second reflective layer are arranged in sequence from bottom to top, the confinement layer is located on the upper side of the active region and/or on the lower side of the active region, the substrate layer of the photodiode, the first type doped semiconductor layer, the inner depletion layer, the second type doped semiconductor layer and the anti-reflective layer are arranged in sequence from bottom to top, the thermoelectric cooling structure is located below the substrate layer, and the light modulating section is located above the second reflective layer.

5. A VCSEL integrated chip as claimed in claim 3, wherein the substrate layer of the VCSEL emission point, the first reflective layer, the active region and the second reflective layer are arranged in sequence from bottom to top, the confinement layer is located on the upper side of the active region and/or on the lower side of the active region, the substrate layer of the photodiode, the first type doped semiconductor layer, the inner depletion layer, the second type doped semiconductor layer and the anti-reflective layer are arranged in sequence from bottom to top, the thermoelectric cooling structure is located between the substrate layer and the first reflective layer, and the light modulating portion is located above the second reflective layer.

6. A VCSEL integrated chip as claimed in claim 3, wherein a substrate layer of the VCSEL emission point, the first reflective layer, the active region and the second reflective layer are arranged in sequence from bottom to top, the confinement layer is located on an upper side of the active region and/or on a lower side of the active region, a substrate layer of the photodiode, the first doped semiconductor layer, the inner depletion layer, the second doped semiconductor layer and the anti-reflective layer are arranged in sequence from bottom to top, the thermoelectric refrigeration structure is located above the second reflective layer, and the light modulating section is located between the substrate layer and the first reflective layer.

7. The VCSEL-integrated chip of claim 3, wherein the first reflective layer is an N-DBR layer, the second reflective layer is a P-DBR layer, the first type doped semiconductor layer is an N-type doped semiconductor layer, and the second type doped semiconductor layer is a P-type doped semiconductor layer.

8. The VCSEL-integrated chip of claim 3, wherein the first reflective layer is a P-DBR layer, the second reflective layer is an N-DBR layer, the first type doped semiconductor layer is a P-type doped semiconductor layer, and the second type doped semiconductor layer is an N-type doped semiconductor layer.

9. The VCSEL integrated chip of claim 1, wherein the VCSEL emission point is electrically isolated from the thermoelectric cooling structure.

10. A VCSEL wafer, comprising:

at least one VCSEL integrated chip according to any of claims 1-9.