CN116884945A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
- Publication number
- CN116884945A CN116884945A CN202310643682.7A CN202310643682A CN116884945A CN 116884945 A CN116884945 A CN 116884945A CN 202310643682 A CN202310643682 A CN 202310643682A CN 116884945 A CN116884945 A CN 116884945A
- Authority
- CN
- China
- Prior art keywords
- plug
- layer
- metal silicide
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 55
- 238000000034 method Methods 0.000 title claims description 72
- 229910052751 metal Inorganic materials 0.000 claims abstract description 150
- 239000002184 metal Substances 0.000 claims abstract description 150
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 123
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 123
- 239000000758 substrate Substances 0.000 claims abstract description 90
- 125000006850 spacer group Chemical group 0.000 claims abstract description 70
- 239000000463 material Substances 0.000 claims description 54
- 230000008569 process Effects 0.000 claims description 45
- 229910017052 cobalt Inorganic materials 0.000 claims description 12
- 239000010941 cobalt Substances 0.000 claims description 12
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 12
- 230000007423 decrease Effects 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 3
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 4
- 239000010410 layer Substances 0.000 description 171
- 239000003989 dielectric material Substances 0.000 description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 15
- 229910052710 silicon Inorganic materials 0.000 description 15
- 239000010703 silicon Substances 0.000 description 15
- 230000004888 barrier function Effects 0.000 description 11
- 238000005530 etching Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- 239000002131 composite material Substances 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000002210 silicon-based material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910001936 tantalum oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- UGACIEPFGXRWCH-UHFFFAOYSA-N [Si].[Ti] Chemical compound [Si].[Ti] UGACIEPFGXRWCH-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- RJCRUVXAWQRZKQ-UHFFFAOYSA-N oxosilicon;silicon Chemical compound [Si].[Si]=O RJCRUVXAWQRZKQ-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a semiconductor device and a manufacturing method thereof. The gate structure is disposed on the substrate, and the plug hole is disposed in the dielectric layer and partially protrudes into the substrate. The plug spacer is disposed on the sidewall of the plug hole and exposes the substrate. The metal silicide layer is arranged at the bottom of the plug hole, wherein a part of the substrate is clamped between the metal silicide layer and the plug gap wall. The plug is disposed within the plug hole and physically contacts a portion of the substrate. Therefore, the forming position and depth of the metal silicide layer are accurately positioned through the arrangement of the plug gap wall, and the effect of improving the performance of the semiconductor device is achieved.
Description
Technical Field
The present invention relates generally to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a plug structure and a method of fabricating the same.
Background
In the conventional process of manufacturing a metal-oxide-semiconductor transistor (MOS), a contact plug (contact plug) is usually required to be formed for conducting in order to electrically connect the gate and the source/drain of the transistor to a circuit. The contact plugs are generally made of a metal material such as tungsten, aluminum, copper, etc., and the gate electrode, the source electrode and the drain electrode are made of a material such as polysilicon or monocrystalline silicon, however, the conduction effect between the metal material and the polysilicon material or monocrystalline silicon material is not ideal. In order to improve Ohmic contact between the contact plug and the gate, and between the contact plug and the source/drain, it has been proposed to additionally form a metal silicide (silicide) between the contact plug and the gate, and between the contact plug and the source/drain, but the related manufacturing process and design have yet to be further improved to effectively improve the structural reliability and operation performance of the related semiconductor device.
Disclosure of Invention
The invention aims to provide a semiconductor device and a manufacturing method thereof, wherein a plug gap wall is additionally arranged on the side wall of a plug hole so as to accurately position the forming position and depth of a metal silicide layer and achieve the effect of improving the performance of the semiconductor device.
In order to achieve the above object, one embodiment of the present invention provides a semiconductor device including a substrate, a gate structure, a dielectric layer, a plug hole, a plug spacer, a metal silicide layer, and a plug. The gate structure is disposed on the substrate. The dielectric layer is disposed on the substrate and covers the gate structure. The plug holes are disposed within the dielectric layer and extend partially into the substrate. The plug spacer is disposed on a sidewall of the plug hole and exposes a portion of the substrate. The metal silicide layer is arranged at the bottom of the plug hole, wherein the part of the substrate is clamped between the metal silicide layer and the plug gap wall. The plug is disposed within the plug aperture and physically contacts the portion of the substrate.
Optionally, the sidewall of the metal silicide layer is aligned with the sidewall of the plug spacer.
Optionally, the metal silicide layer includes a discontinuous structure.
Optionally, the dimension of the metal silicide layer in the horizontal direction gradually decreases with increasing depth.
Optionally, the plug spacers do not directly contact the metal silicide layer.
Optionally, the vertical sidewalls of the plug physically contact both the portion of the substrate and the plug spacer.
Optionally, the gate structure includes: a stacked layer structure; and the grid gap wall is arranged on the side wall of the stacked layer structure and is positioned at one side of the plug gap wall.
Optionally, the metal silicide layer includes cobalt silicide, cobalt disilicide, titanium silicide, or nickel silicide.
Optionally, the method further comprises: and the doped region is arranged in the substrate and positioned at two opposite sides of the grid structure, and the plug physically contacts the doped region.
In order to achieve the above object, one embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. A substrate is provided, and a gate structure is formed on the substrate. A dielectric layer is formed over the substrate covering the gate structure. Plug holes are formed in the dielectric layer, the plug hole portions extending into the substrate. Plug spacers are formed on sidewalls of the plug holes and expose portions of the substrate. A metal silicide layer is formed at the bottom of the plug hole, wherein the portion of the substrate is sandwiched between the metal silicide layer and the plug spacer. A plug is formed within the plug aperture.
Optionally, before forming the metal silicide layer, the method further includes: forming doped regions in the substrate on opposite sides of the gate structure; and forming a perforation in the dielectric layer, exposing a portion of the doped region.
Optionally, forming the metal silicide layer includes: and performing a metal silicide manufacturing process to form a metal silicide material layer.
Optionally, the metal silicide manufacturing process includes: performing a selective epitaxial growth manufacturing process to form a metal layer in the through hole; and reacting the metal layer to generate the metal silicide material layer.
Optionally, the metal silicide manufacturing process includes: performing a deposition manufacturing process to form a metal layer; reacting the metal layer to generate the metal silicide material layer; and removing unreacted metal layer after the metal silicide material layer is formed.
Optionally, the method further comprises: and after the metal silicide manufacturing process, partially removing the metal silicide material layer to form the plug hole and the metal silicide layer positioned at the bottom of the plug hole, wherein the upper half part of the plug hole is overlapped with the through hole.
Optionally, the method further comprises: depositing a layer of material within the via prior to performing the metal silicide fabrication process; and partially removing the material layer to form the plug spacer on the sidewall of the through hole.
Optionally, the plug spacers do not directly contact the metal silicide layer.
Optionally, forming the gate structure on the substrate includes: forming a stacked layer structure on the substrate; and forming a gate spacer on the sidewall of the stacked layer structure and on one side of the plug spacer.
Optionally, the dimension of the metal silicide layer in the horizontal direction gradually decreases with increasing depth.
Optionally, the sidewall of the metal silicide layer is aligned with the sidewall of the plug spacer.
Drawings
The accompanying drawings are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.
Fig. 1 is a schematic cross-sectional view of a semiconductor device according to an embodiment of the invention.
Fig. 2 to 7 are schematic views illustrating a method for fabricating a semiconductor device according to an embodiment of the invention; wherein:
fig. 2 is a schematic cross-sectional view of the semiconductor device after formation of a dielectric layer;
fig. 3 is a schematic cross-sectional view of the semiconductor device after forming plug holes;
fig. 4 is a schematic cross-sectional view of the semiconductor device after forming a material layer;
FIG. 5 is a schematic cross-sectional view of a semiconductor device after performing an etch-back process;
fig. 6 is a schematic cross-sectional view of the semiconductor device after performing a metal silicide fabrication process; and
fig. 7 is a schematic cross-sectional view of the semiconductor device after an etching process is performed.
Fig. 8 is a schematic diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the invention.
Fig. 9 to 10 are schematic views illustrating a method for fabricating a semiconductor device according to another embodiment of the invention; wherein:
fig. 9 is a schematic cross-sectional view of a semiconductor device after performing a metal silicide fabrication process; and
fig. 10 is a schematic cross-sectional view of the semiconductor device after an etching process is performed.
Wherein reference numerals are as follows:
100. substrate and method for manufacturing the same
101. 103 semiconductor device
102. Shallow trench isolation
110. Insulating layer
112. Semiconductor layer
114. Barrier layer
116. Conductive layer
118. Cover layer
120. Gate spacer
122. First spacer
124. Second spacer
126. Third spacer
128. Lightly doped source/drain regions
130. Doped region
132. Gate structure
134. Dielectric layer
136. Plug hole
136a perforation
137. Bottom side wall
138. Plug spacer
138a material layer
139. Bottom surface
140. 244 metal silicide layer
140a, 242 metal silicide material layer
142. Plug-in connector
244a first portion
244b second portion
P1 back etching process
P2, P21 metal silicide making process
P3 and P31 etching manufacturing process
Maximum width of W
Detailed Description
In order to enable those skilled in the art to which the invention pertains, a few preferred embodiments of the invention are described below in detail, together with the accompanying drawings, in order to further explain the principles of the invention and its advantages. Those skilled in the art to which the invention pertains will be able to replace, reorganize, and mix features in several different embodiments with reference to the following examples to complete other embodiments without departing from the spirit of the invention.
Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a semiconductor device 101 according to an embodiment of the invention. As shown in fig. 1, semiconductor device 101 includes a substrate 100, a gate structure 132, a dielectric layer 134, plug holes 136, plug spacers 138, a metal silicide layer 140, and plugs 142. The substrate 100 may include, but is not limited to, a silicon substrate (silicon substrate), a silicon-containing substrate (silicon-containing substrate), an epitaxial silicon substrate (epitaxial silicon substrate), a silicon-on-insulator substrate (silicon-on-insulator substrate), or other suitable materials. The gate structure 132 is disposed on the substrate 100, and is covered by the dielectric layer 134, and the top surface of the dielectric layer 134 and the top surface of the gate structure 132 may be substantially on the same plane, but not limited thereto. The plug hole 136 penetrates the dielectric layer 134 in a vertical direction (not shown) perpendicular to the surface of the substrate 100 and partially protrudes into the substrate 100, and a portion of the substrate 100 is exposed from the sidewall 137 and the bottom 139 of the bottom of the plug hole 136, respectively. Plug 142 is disposed in plug hole 136 to electrically connect doped region 130 in substrate 100. It should be noted that, the plug spacer 138 is disposed on the sidewall of the plug hole 136 to define the location of the metal silicide layer 140 at the bottom of the plug hole 136, and the portion of the doped region 130 in the substrate 100 is sandwiched between the metal silicide layer 140 and the plug spacer 138 and physically contacts the plug 142. In other words, the sidewalls of the plugs 142 in the vertical direction physically contact the portion of the doped regions 130 and the plug spacers 138 in the substrate 100 at the same time, and the bottom surfaces of the plugs 142 physically contact the portion of the doped regions 130 and the metal silicide layer 140 in the substrate 100 at the same time. Thus, the location and depth of the metal silicide layer 140 are precisely defined by the plug spacers 138, so that the sidewalls of the plugs 142 are aligned with the sidewalls of the metal silicide layer 140. In addition, the plug 142 can simultaneously contact the metal silicide layer 140 and a portion of the substrate 100 (i.e., the doped region 130), which can provide an optimized ohmic contact while generating a relatively large lateral contact resistance at the bottom and bottom of the sidewall of the plug 142, thereby improving the electrical performance of the semiconductor device 101.
The metal silicide layer 140 includes, for example, cobalt silicide (CoSi x ) Titanium silicide (TiSi) 2 ) Or nickel silicide (Ni 2 Si), preferably comprising cobalt disilicide (CoSi) 2 ) But is not limited thereto. The plug spacer 138 may comprise a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a conductive barrier material such as titanium or tantalum, but is not limited thereto. Since the plug spacers 138 disposed on the sidewalls of the plug holes 136 limit the lateral development of the metal silicide layer 140, the metal silicide layer 140 is precisely defined at the bottom of the plug holes 136, and the dimension of the metal silicide layer 140 in a horizontal direction (not shown) parallel to the surface of the substrate 100 gradually decreases with increasing depth within the substrate 100, having an inverted triangular cross section. That is, the cross section of the metal silicide layer 140 has a maximum width W on its topmost surface and gradually decreases downward as shown in fig. 1. In one embodiment, the top surface of metal silicide layer 140 is lower than the top surface of substrate 100 without physically contacting plug spacers 138.
In detail, the gate structure 132 is, for example, a polysilicon gate structure, a metal gate structure, or a gate structure formed by an integrated memory manufacturing process. The gate structure 132 includes a stacked layer structure and a gate spacer 120 disposed on a sidewall of the stacked layer structure, wherein the stacked layer structure is composed of a semiconductor layer 112, a barrier layer 114, a conductive layer 116 and a cap layer 118 sequentially stacked on a substrate 100 from bottom to top. In one embodiment, the semiconductor layer 112 comprises a semiconductor material such as doped polysilicon, doped amorphous silicon, etc., the barrier layer 114 comprises a conductive barrier material such as titanium and/or titanium nitride, tantalum and/or tantalum oxide, the conductive layer 116 comprises copper, aluminum, tungsten or other suitable low resistivity conductive material, and the cap layer 118 comprises an insulating material such as silicon oxide, silicon nitride or silicon oxynitride, but is not limited thereto. Gate spacer 120 is located between the stacked layer structure and dielectric layer 134 and on one side of plug spacer 138. The gate spacer 120 has a composite layer structure, for example, including, but not limited to, a first spacer 122, a second spacer 124 and a third spacer 126 sequentially disposed on the sidewalls of the stacked structure in the horizontal direction. In one embodiment, the first spacer 122 and the third spacer 126 include the same insulating material, such as silicon nitride, silicon carbonitride, etc., and the second spacer 124 includes an insulating material, such as silicon oxide, silicon oxynitride, etc., which is different from the insulating material of the first spacer 122 and the third spacer 126, but not limited thereto. In other embodiments, the spacer may have a single layer structure, such as an insulating material including silicon oxide, silicon nitride or silicon oxynitride, but not limited thereto.
The semiconductor device 101 further includes a shallow trench isolation 102 disposed within the substrate 100, an insulating layer 110 disposed over the substrate 100, and lightly doped source/drain regions 128 and doped regions 130 also disposed within the substrate 100. In this embodiment, the top surface of the shallow trench isolation 102 is coplanar with the top surface of the substrate 100 to surround and define a plurality of active regions (not shown) in the substrate 100. The shallow trench isolation 102 is formed by a patterning process of the substrate 100, which includes, but is not limited to, the following steps. First, a block substrate (not shown) is patterned through a mask layer (not shown) to form at least one trench (not shown), and then a deposition process is performed to fill the trench with an insulating material to serve as the shallow trench isolation 102. In other embodiments, the top surface of the shallow trench isolation 102 may alternatively not be coplanar with the top surface of the substrate 100 to surround and define a portion of the substrate protruding from the top surface of the shallow trench isolation 102 as fins (fins). An insulating layer 110 is integrally overlying the top surface of the substrate 100 and is located between the gate structure 132 and the substrate 100 to act as a gate dielectric layer for the gate structure 132 while isolating other components disposed within the substrate 100 or on the substrate 100. In one embodiment, the insulating layer 110 may include a nitride dielectric material (such as silicon nitride), an oxide dielectric material (such as silicon oxide), a high-k dielectric material (such as a dielectric material with a k higher than 3.9 or a dielectric material with a k higher than 4.52), or other suitable dielectric materials, and may optionally include a composite layer structure composed of the nitride dielectric material and the oxide dielectric material, for example, but not limited to, a silicon oxide-silicon nitride-oxide (ONO) structure.
On the other hand, lightly doped source/drain regions 128 and doped regions 130 are disposed in the substrate 100 on opposite sides of the gate structure 132. Lightly doped source/drain region 128 and doped region 130 have, for example, the same conductivity type and dopant, and the dopant concentration in lightly doped source/drain region 128 is less than the dopant concentration in doped region 130, such that doped region 130 serves as the source/drain of gate structure 132. For example, if the gate structure 132 is intended to form a P-type transistor (PMOS) in a subsequent process, the lightly doped source/drain regions 128 and the doped regions 130 may include P-type dopants such as boron, for example, and if the gate structure 132 is intended to form an N-type transistor (NMOS) in a subsequent process, the lightly doped source/drain regions 128 and the doped regions 130 may include N-type dopants such as phosphorus, but are not limited thereto.
In this arrangement, the plug 142 disposed within the dielectric layer 134 may be electrically connected to the source/drain (i.e., the doped region 130) of the gate structure 132 by means of the metal silicide layer 140 at the bottom of the plug hole 136, providing an optimized ohmic contact through the top surface of the metal silicide layer 140 having the maximum width W, while avoiding shorting by pulling away from surrounding components by the gradually decreasing dimension of the metal silicide layer 140 with increasing depth (i.e., having an inverted triangular cross-section). On the other hand, since the metal silicide layer 140 is not formed between the bottom and bottom of the sidewall of the plug 142 and the source/drain, but directly contacts a portion of the source/drain (i.e., the doped region 130), a relatively large sheet resistance (sheet resistance) is generated in lateral contact, so that the current is more effectively directed in a specific direction (downward). Thus, the semiconductor device 101 of the present embodiment has a reliable structure and optimized performance, and can be electrically connected to other active devices and/or passive devices downward and/or upward through other connection devices in the subsequent manufacturing process, so as to achieve more optimized operation performance.
In order to enable those skilled in the art to easily understand the semiconductor device of the present invention, the method for manufacturing the semiconductor device of the present invention will be further described below.
Fig. 2 to 7 are schematic views illustrating a method for manufacturing a semiconductor device 101 according to an embodiment of the invention. First, as shown in fig. 2, a gate structure 132 is formed on an insulating layer 110, and lightly doped source/drain regions 128 and doped regions 130 are formed in a substrate 100 on opposite sides of the gate structure 132. The gate structure 132 is formed, for example, by a process of forming an integrated memory (e.g., DRAM), and is not limited thereto, when a process of forming a bit line is performed. In other embodiments, the gate structure may be formed by a common gate fabrication process, such as a gate-last (gate-last) fabrication process and a high-k dielectric layer (high-k last) fabrication process. In one embodiment, the lightly doped source/drain regions 128 are formed, for example, by using the stacked layer structure of the gate structure 132 as a doping mask after the stacked layer structure is formed, such that the sidewalls of the lightly doped source/drain regions 128 are aligned with the sidewalls of the stacked layer structure in the vertical direction, but not limited thereto. In addition, the doped region 130 is formed by using the gate spacer 120 as a doping mask after the gate spacer 120 is formed, so that the sidewall of the doped region 130 is cut Ji Shanji from the sidewall of the spacer 120 in the vertical direction, but not limited thereto.
Next, as further shown in fig. 2, a dielectric layer 134 is formed over the substrate 100, covering the gate structure 132. Dielectric layer 134 is formed, for example, by sequentially performing a deposition process and an etching-back process of a dielectric material, such that the top surface of dielectric layer 134 and the top surface of gate structure 132 are on the same plane. In one embodiment, the dielectric material includes a nitride dielectric material (such as silicon nitride), an oxide dielectric material (such as silicon oxide), or other suitable dielectric materials, preferably including the same material as the second spacer 124, such as silicon oxide, silicon oxynitride, etc., but not limited thereto.
As shown in fig. 3, a through hole 136a is formed in the dielectric layer 134, and the through hole 136a penetrates the dielectric layer 134 and the insulating layer 110 in the vertical direction and partially protrudes into the substrate 100. The bottom surface of the perforation 136a is lower than the top surface of the substrate 100 and exposes a portion of the doped region 130.
As shown in fig. 4, a layer of material 138a is formed conformally overlying the top surface of dielectric layer 134 and the bottom surfaces and sidewalls of perforations 136a. That is, the material layer 138a is partially formed within the perforations 136a and partially formed outside the perforations 136a. In one embodiment, the material layer 138a includes a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, or a high-k dielectric material, preferably including a material having an etching selectivity with respect to the dielectric layer 134 and the gate spacers 120, but is not limited thereto. In other embodiments, the material layer 138a may alternatively include conductive barrier materials such as titanium, tantalum, etc., but is not limited thereto. The material layer 138a may be formed by a film forming process, such as a chemical vapor deposition process, a physical vapor deposition process, or other suitable methods, but is not limited thereto. In another embodiment, the material layer 138a may alternatively comprise a single film layer or a composite film layer according to the actual device requirements.
As shown in fig. 5, an etching back process P1 is performed to remove the material layer 138a outside the via 136a and remove the material layer 138a on the bottom surface of the via 136a, thereby forming the plug spacer 138 only on the sidewall of the via 136a. And, after the etching back process P1, a portion of the doped region 130 is exposed again from the bottom surface of the through hole 136a.
As shown in fig. 6, a metal silicide process P2 is performed to form a metal silicide material layer 140a at the bottom of the via 136a, and the metal silicide process P2 includes, but is not limited to, the following steps. First, a selective deposition process is performed, a selective epitaxial growth process is performed on the bottom of the via 136a or a metal plasma gas is selectively introduced, and a metal layer (not shown), such as a metal material suitable for reacting with a silicon material, including cobalt, titanium, nickel, and the like, preferably cobalt, is formed only on the bottom of the via 136a. Then, a heat treatment process is performed such that the metal layer reacts with the exposed portion of the doped region 130 (i.e., the substrate 100) to form a metal silicide material layer 140a. In one embodiment, the metal silicide material layer 140a includes, for example, cobalt silicide, titanium silicide, nickel silicide, and other metal silicide materials, preferably cobalt disilicide, but is not limited thereto.
In detail, since the plug spacers 138 disposed on the sidewalls of the through-holes 136a define the formation range of the metal layer, the metal layer is precisely formed at the bottom of the through-holes 136a. Under this operation, the metal layer can be completely reacted into the metal silicide material layer 140a in the heat treatment manufacturing process, and the subsequent step of removing the unreacted metal layer can be omitted. On the other hand, the reaction range of the heat treatment process is also correspondingly limited by the plug spacers 138, and the metal silicide material layer 140a whose dimension in the horizontal direction gradually decreases with the increase of the depth in the substrate 100 is formed. That is, the top surface of the metal silicide layer 140a extends to a range not exceeding the aperture extension of the through hole 136a, and the lateral reaction of the metal silicide layer 140a is limited by the plug spacer 138, so that the metal silicide layer has an inverted triangle cross-section structure. The opposite sides of the cross-sectional structure of the metal silicide layer 140a are just aligned with the inner sidewalls of the plug spacers 138, as shown in fig. 6, but not limited thereto.
Then, as shown in fig. 7, an etching process P3, such as a dry etching process, is performed to remove a portion of the metal silicide material layer 140a vertically downward, and simultaneously, the extension of the metal silicide material layer 140a in the horizontal direction is reduced integrally, so as to form the metal silicide layer 140. The metal silicide layer 140 has an inverted triangle cross section, and has a maximum width W on the top surface thereof, and gradually decreases downward. Meanwhile, after removing the portion of the metal silicide material layer 140a, a portion of the doped region 130 (i.e., the substrate 100) is again exposed, forming plug holes 136 of the portion of the doped region 130 exposed by both the bottom sidewall 137 and the bottom surface 139. The aperture extension of the plug hole 136 is significantly larger than the maximum width W of the metal silicide layer 140, so that the metal silicide layer 140 is located just under the center of the plug hole 136, and the topmost surface of the metal silicide layer 140 having the maximum width W is exposed, as shown in fig. 7. Note that the plug hole 136 has an overall vertical sidewall, and the upper half of the plug hole 136 completely overlaps the through hole 136a as shown in fig. 6.
Subsequently, the plug 142 shown in fig. 1 is continuously formed in the plug hole 136, and the semiconductor device 101 shown in fig. 1 can be formed. In one embodiment, the plug 142 includes, but is not limited to, a barrier layer (not shown) formed on the sidewall and bottom of the plug hole 136 and a contact metal layer (contact metal layer, not shown) filling the plug hole 136. In the present embodiment, the semiconductor device 101 can accurately define the location and depth of the metal silicide layer 140 by the arrangement of the plug spacer 138, so that the vertical sidewall of the plug 142 formed later can contact the plug spacer 138 and the doped region 130 (i.e. the substrate 100) at the same time, and the bottom surface of the plug 142 can physically contact the metal silicide layer 140 and the doped region 130 at the same time, thereby improving the structure and performance of the semiconductor device 101. Thus, the fabrication of the semiconductor device 101 in this embodiment is completed. In addition, the semiconductor device 101 has reliable structure and optimized performance, and can be electrically connected to other active components and/or passive components downwards and/or upwards through other connecting components in the subsequent manufacturing process, so as to achieve more optimized operation performance.
It should be readily understood by those skilled in the art that the semiconductor device and the method for manufacturing the same may have other aspects or may be achieved by other means, and are not limited to the foregoing, so as to meet the needs of actual products. Further embodiments or variations of the semiconductor device of the present invention and its method of fabrication are described below. In order to simplify the description, the following description mainly aims at the differences of the embodiments, and the details of the differences will not be repeated. In addition, like elements in the various embodiments of the present invention are labeled with like reference numerals to facilitate cross-reference between the various embodiments.
Referring to fig. 8, fig. 8 is a schematic diagram illustrating a method for fabricating a semiconductor device according to another embodiment of the invention. The fabrication method of the present embodiment is substantially the same as that of the foregoing embodiment, with the main difference that the metal silicide fabrication process of the present embodiment includes forming the metal layer 240 by a deposition fabrication process or a sputtering fabrication process, and a heat treatment fabrication process.
In detail, after forming the structure as shown in fig. 5, the deposition process or the sputtering process is performed to form the metal layer 240. A metal layer 240 is conformally formed on the top surface of the dielectric layer 134 and the bottom and sidewalls of the via 136a, and covers the plug spacers 138. As such, the metal layer 240 may be formed partially within the perforation 136a and partially outside the perforation 136a. In one embodiment, the metal layer 240 includes a metal material suitable for reacting with a silicon material, such as cobalt, titanium, nickel, etc., preferably includes cobalt, but is not limited thereto. A barrier layer (not shown), such as a conductive barrier material including titanium and/or titanium nitride, tantalum and/or tantalum oxide, is then conformally formed on the metal layer 240, and the thermal treatment process is performed. The barrier layer can prevent the metal material from being diffused during the heat treatment manufacturing process, and can uniformly heat and react the metal layer 240 to form the metal silicide material layer 140a as shown in fig. 6.
Subsequently, another etching process is performed to remove the barrier layer and the unreacted metal layer 240, and then an etching process is performed as shown in fig. 7, so that the plug hole 136 shown in fig. 7 can be formed, and the plug 142 shown in fig. 1 can be formed in the plug hole 136, so that the semiconductor device 101 shown in fig. 1 can be formed. Thus, the fabrication of the semiconductor device 101 in this embodiment is completed. Under this operation, the semiconductor device 101 manufactured by the manufacturing method of the present embodiment also has a reliable structure and optimized performance, and can be electrically connected to other active devices and/or passive devices downward and/or upward through other connection devices in the subsequent manufacturing process, so as to achieve more optimized operation performance. Fig. 9 to 10 are schematic views illustrating a method for fabricating a semiconductor device 103 according to another embodiment of the invention. The fabrication method of this embodiment is substantially the same as that of the previous embodiment, and the main difference is that the metal silicide fabrication process P21 of this embodiment controls the operation parameters or operation conditions of the selective epitaxial growth process or the selective metal plasma gas to form the metal silicide material layer 242 with the top surface extending beyond the aperture extending range of the through hole 136a.
In detail, as shown in fig. 9, when the selective epitaxial growth process is performed or the metal plasma gas is selectively introduced, the operation time, the operation temperature, or the flow rate or the ratio of the metal plasma gas are synchronously adjusted, so that the metal silicide material layer 242 also forms an inverted triangle cross-section structure, wherein two opposite sides of the cross-section structure of the metal silicide material layer 242 are located, for example, between an inner side wall and an outer side wall of the plug spacer 138 in a direction parallel to the substrate 100, as shown in fig. 9, but not limited thereto. Alternatively, in another embodiment, the operation time, the operation temperature, the flow rate or the ratio of the metal plasma gas, or the like may be adjusted according to the actual device requirement, so that two opposite sides of the cross-sectional structure of the metal silicide material layer (not shown) are located between the outer side wall of the plug spacer 138 and the outer side wall of the gate spacer 120 in the direction parallel to the substrate 100.
Subsequently, as shown in fig. 10, an etching process P31, such as a dry etching process, is performed to remove a portion of the metal silicide material layer 242 vertically downward, and simultaneously, to reduce the extension of the metal silicide material layer 242 in the horizontal direction as a whole, so as to form a metal silicide layer 244. And, after removing the portion of the metal silicide material layer 242, a portion of the doped region 130 (i.e., the substrate 100) is again exposed, forming a plug hole 136 of the doped region 130 with both the bottom sidewall 137 and the bottom surface 139. It should be noted that, since the top surface of the metal silicide material layer 242 extends beyond the aperture extension of the through hole 136a as shown in fig. 9, the metal silicide material layer 242 is cut into two parts when being etched vertically downward, so that the metal silicide layer 244 has a discontinuous structure. The first portion 244a of the metal silicide layer 244 is formed directly under the plug spacer 138, physically contacts the bottom surface of the plug spacer 138 and the bottom sidewall 137 of the plug hole 136, and the second portion 244b has an inverted triangle cross-section and is located directly under the center of the plug hole 136. It should be noted that, in the present embodiment, the top surface of the second portion 244b of the metal silicide layer 244 also has the maximum width W, and gradually decreases downwards, and the top surface of the second portion 244b is also exposed from the plug hole 136, as shown in fig. 10.
Then, the plug 142 shown in fig. 1 continues to be formed in the plug hole 136. In this embodiment, the metal silicide layer 244 has a discontinuous structure, the first portion 244a of which is located directly under the plug spacer 138, and the second portion 244b of which has an inverted triangular cross-section and is located just under the center of the plug hole 136, to provide a more optimized ohmic contact. Thus, the fabrication of the semiconductor device 103 in this embodiment is completed. Under this operation, the semiconductor device 103 manufactured by the manufacturing method of the present embodiment also has a reliable structure and optimized performance, and can be electrically connected to other active devices and/or passive devices downward and/or upward through other connection devices in the subsequent manufacturing process, so as to achieve more optimized operation performance.
In the semiconductor device and the manufacturing method, the plug gap wall is additionally arranged on the side wall of the plug hole so as to accurately position the forming position and the forming depth of the metal silicide layer, thereby achieving the effect of improving the performance of the semiconductor device.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (20)
1. A semiconductor device characterized by comprising:
a substrate;
a gate structure disposed on the substrate;
a dielectric layer disposed on the substrate and covering the gate structure;
plug holes disposed within the dielectric layer and extending partially into the substrate;
plug spacers disposed on sidewalls of the plug holes and exposing a portion of the substrate; a metal silicide layer disposed at the bottom of the plug hole, wherein the portion of the substrate is sandwiched between the metal silicide layer and the plug spacer; and
a plug disposed within the plug aperture and physically contacting the portion of the substrate.
2. The semiconductor device of claim 1, wherein sidewalls of the metal silicide layer are aligned with sidewalls of the plug spacers.
3. The semiconductor device of claim 1, wherein the metal silicide layer comprises a discontinuous structure.
4. The semiconductor device according to claim 1, wherein a dimension of the metal silicide layer in a horizontal direction gradually decreases with an increase in depth.
5. The semiconductor device of claim 1, wherein the plug spacers do not directly contact the metal silicide layer.
6. The semiconductor device of claim 1, wherein vertical sidewalls of the plug physically contact both the portion of the substrate and the plug spacer.
7. The semiconductor device of claim 1, wherein the gate structure comprises:
a stacked layer structure; and
the grid gap wall is arranged on the side wall of the stacked layer structure and is positioned on one side of the plug gap wall.
8. The semiconductor device of claim 1, wherein the metal silicide layer comprises cobalt silicide, cobalt disilicide, titanium silicide, or nickel silicide.
9. The semiconductor device according to claim 1, further comprising:
and the doped region is arranged in the substrate and positioned at two opposite sides of the grid structure, and the plug physically contacts the doped region.
10. A method of fabricating a semiconductor device, comprising:
providing a substrate;
forming a gate structure on the substrate;
forming a dielectric layer on the substrate and covering the gate structure;
forming a plug hole in the dielectric layer, the plug hole portion extending into the substrate;
forming plug spacers on sidewalls of the plug holes and exposing a portion of the substrate;
forming a metal silicide layer at the bottom of the plug hole, wherein the part of the substrate is clamped between the metal silicide layer and the plug spacer; and
a plug is formed within the plug aperture.
11. The method of claim 10, further comprising, prior to forming the metal silicide layer:
forming doped regions in the substrate on opposite sides of the gate structure; and
perforations are formed in the dielectric layer exposing portions of the doped regions.
12. The method of claim 11, wherein forming the metal silicide layer comprises:
and performing a metal silicide manufacturing process to form a metal silicide material layer.
13. The method of claim 12, wherein the metal silicide process comprises:
performing a selective epitaxial growth manufacturing process to form a metal layer in the through hole; and
the metal layer is reacted into the metal silicide material layer.
14. The method of claim 12, wherein the metal silicide process comprises:
performing a deposition manufacturing process to form a metal layer;
reacting the metal layer to generate the metal silicide material layer; and
after the metal silicide material layer is formed, the unreacted metal layer is removed.
15. The method of manufacturing a semiconductor device according to claim 12, further comprising:
and after the metal silicide manufacturing process, partially removing the metal silicide material layer to form the plug hole and the metal silicide layer positioned at the bottom of the plug hole, wherein the upper half part of the plug hole is overlapped with the through hole.
16. The method of manufacturing a semiconductor device according to claim 12, further comprising:
depositing a layer of material within the via prior to performing the metal silicide fabrication process; and
and partially removing the material layer to form the plug gap wall on the side wall of the through hole.
17. The method of claim 10, wherein the plug spacer does not directly contact the metal silicide layer.
18. The method of claim 10, wherein forming a gate structure on the substrate comprises:
forming a stacked layer structure on the substrate; and
and forming a gate spacer, wherein the gate spacer is positioned on the side wall of the stacked layer structure and is positioned on one side of the plug spacer.
19. The method of claim 10, wherein the dimension of the metal silicide layer in the horizontal direction gradually decreases with increasing depth.
20. The method of claim 10, wherein the sidewall of the metal silicide layer is aligned with the sidewall of the plug spacer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310643682.7A CN116884945A (en) | 2023-06-01 | 2023-06-01 | Semiconductor device and method for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310643682.7A CN116884945A (en) | 2023-06-01 | 2023-06-01 | Semiconductor device and method for manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN116884945A true CN116884945A (en) | 2023-10-13 |
Family
ID=88263280
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310643682.7A Pending CN116884945A (en) | 2023-06-01 | 2023-06-01 | Semiconductor device and method for manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116884945A (en) |
-
2023
- 2023-06-01 CN CN202310643682.7A patent/CN116884945A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI713121B (en) | Vertical fin field effect transistor, method of fabricating the same and semiconductor device having the same | |
| KR100714401B1 (en) | Semiconductor device having stacked transistors and method of forming the same | |
| US6852597B2 (en) | Method for fabricating power semiconductor device having trench gate structure | |
| US6228730B1 (en) | Method of fabricating field effect transistor | |
| CN107393960B (en) | Vertical field effect transistor and method of manufacturing the same | |
| CN114420644A (en) | Semiconductor structure and manufacturing method thereof | |
| US6171954B1 (en) | Method of manufacturing self-aligned contact | |
| US11757015B2 (en) | Semiconductor devices | |
| KR20150068084A (en) | Semiconductor devices and methods of manufacturing the same | |
| US20230020711A1 (en) | Semiconductor structure and method for manufacturing same | |
| KR20160142803A (en) | Vertical channel transistors and methods for fabricating vertical channel transistors | |
| US7843014B2 (en) | Small size transistor semiconductor device capable of withstanding high voltage | |
| KR20140086670A (en) | Nonvolatile memory device and method for fabricating the same | |
| CN220106519U (en) | Semiconductor device with a semiconductor layer having a plurality of semiconductor layers | |
| KR20170109422A (en) | Semiconductor device and method for manufacturing the same | |
| KR20040088376A (en) | Method for fabricating transistors of different conduction types and having different packing densities in a semiconductor substrate | |
| US10304839B2 (en) | Metal strap for DRAM/FinFET combination | |
| US20080173924A1 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| CN213401190U (en) | Semiconductor device with a plurality of transistors | |
| CN116884945A (en) | Semiconductor device and method for manufacturing the same | |
| KR100684906B1 (en) | Semiconductor devices having bipolar transistor and methods of forming the same | |
| EP4080557A1 (en) | Semiconductor devices and methods of manufacturing the same | |
| US20240023319A1 (en) | Semiconductor device | |
| US20240074155A1 (en) | Semiconductor device | |
| US20230133763A1 (en) | Semiconductor devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |