CN116882331A - Chip test equipment and register data read-write method - Google Patents

Chip test equipment and register data read-write method Download PDF

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Publication number
CN116882331A
CN116882331A CN202310871350.4A CN202310871350A CN116882331A CN 116882331 A CN116882331 A CN 116882331A CN 202310871350 A CN202310871350 A CN 202310871350A CN 116882331 A CN116882331 A CN 116882331A
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China
Prior art keywords
register
register module
rgm
data
write
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CN202310871350.4A
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Chinese (zh)
Inventor
喻志伟
银磊
王�锋
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New H3C Semiconductor Technology Co Ltd
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New H3C Semiconductor Technology Co Ltd
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Priority to CN202310871350.4A priority Critical patent/CN116882331A/en
Publication of CN116882331A publication Critical patent/CN116882331A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/333—Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]

Abstract

The embodiment of the invention provides chip test equipment and a register data read-write method, which relate to the technical field of chip verification and comprise the following steps: when RGM receives a writing instruction for writing data into a virtual register, RGM determines the identification of a writing register module indicated by the writing instruction and a target transmission variable; RGM determines a write address corresponding to the combination of the identification of the write register module and the target transmission variable based on the corresponding relation; RGM sends target transmission variable and write address to DUT through bus, wherein the value of target transmission variable is data to be written; the DUT writes the value of the target transport variable to the location indicated by the write address. By applying the scheme provided by the embodiment of the invention, the pipeline operation of writing data into the register can be conveniently performed.

Description

Chip test equipment and register data read-write method
Technical Field
The embodiment of the invention relates to the technical field of chip verification, in particular to chip test equipment and a register data reading and writing method.
Background
Registers are often configured in the chip, and in the chip verification process, the functions of the registers in the chip need to be verified. With the increase in the size and complexity of chips, the number and size of registers are also increasing, and thus a large number of registers need to be verified in the chip verification process. When Register data is written in the existing UVM (Universal Verification Methodology, general verification method), a Register program execution unit in the RGM (Register Model) generates a variable storing a read-write type and an operation address, and performs type conversion on the variable through an adaptive function from a bus to a Register, the converted variable is sent to a bus sequencer, the bus sequencer processes the received variable, the processed variable is sent to a bus driver, and finally the bus driver realizes writing operation on the Register data based on the received variable.
In the existing UVM register model, for a write operation of a front gate access, a mirror value and an expected value are updated to the same value as a bus after a bus transaction is completed, and the write operation involves the above-described series of processes for performing variable processing and response/item_done of a component, resulting in poor support of pipeline operation.
Disclosure of Invention
The embodiment of the invention aims to provide chip test equipment and a register data reading and writing method so as to facilitate the pipeline operation of writing data into a register. The specific technical scheme is as follows:
in a first aspect, an embodiment of the present invention provides a chip testing device, where the chip testing device includes a module to be tested DUT and a register model RGM, where the DUT and the RGM are connected through a bus;
the DUT comprises a register module, wherein the register module comprises a virtual register, the RGM comprises a resource pool, and the resource pool corresponds to the register module one by one;
each resource pool is recorded with the identification and transmission variable of the corresponding register module of the resource pool, the transmission variable is in one-to-one correspondence with the virtual register contained in the register module, and the RGM is recorded with the corresponding relation between the combination of the identification and transmission variable of the register module and the virtual register address corresponding to the transmission variable;
The RGM is used for determining the identification of a write register module indicated by the write instruction and a target transmission variable under the condition that the write instruction for writing data into the virtual register is received; determining a write address corresponding to a combination of the identification of the write register module and a target transmission variable based on the corresponding relation; transmitting the target transmission variable and write address to the DUT via the bus; the value of the target transmission variable is data to be written;
the DUT is used for writing the value of the target transmission variable into the position indicated by the write address.
In one embodiment of the present invention, the RGM is further configured to determine, when a read instruction for reading data from a virtual register is received, an identification of a read register module indicated by the read instruction and a target transmission variable; based on the corresponding relation, determining a read address corresponding to the combination of the identification of the read register module and the target transmission variable; transmitting the read address to the DUT via the bus;
the DUT is also used for reading the data at the read address and sending the read data to the RGM through the bus;
The RGM is further used for setting the value of the target transmission variable as the read data.
In one embodiment of the present invention, different resource pools are connected to the corresponding register modules by using different buses, and the RGM is specifically configured to send the target transmission variable and the write address to the DUT through the bus between the write register module and the resource pool.
In one embodiment of the invention, the resource pool is constructed in the following manner:
scanning a register description file describing a register module in the DUT and virtual registers contained in the register module;
extracting text for describing a register module and a virtual register contained in the register module from the register description file;
extracting information of the register module and an identification of the register module from the text;
generating resource pools respectively corresponding to the identifications of each register module;
for each register module, extracting information of a virtual register contained in the register module from the text, generating a transmission variable corresponding to the virtual register, and recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module.
In one embodiment of the present invention, the signal transmitted by the bus includes at least one of the following information: the data writing device comprises a clock signal, an address line for recording an address, data to be written, read data, a read-write signal for representing whether the data writing device is in a read state or a write state currently, a write valid indication for representing whether the data writing device is in a write state currently, and a read valid indication for representing whether the data writing device is in a read state currently.
In a second aspect, an embodiment of the present invention provides a method for reading and writing register data, which is applied to a chip test device, where the chip test device includes a module DUT to be tested and a register model RGM, and the DUT and the RGM are connected through a bus;
the DUT comprises a register module, wherein the register module comprises a virtual register, the RGM comprises a resource pool, and the resource pool corresponds to the register module one by one;
each resource pool is recorded with the identification and transmission variable of the corresponding register module of the resource pool, the transmission variable is in one-to-one correspondence with the virtual register contained in the register module, and the RGM is recorded with the corresponding relation between the combination of the identification and transmission variable of the register module and the virtual register address corresponding to the transmission variable;
The method comprises the following steps:
when the RGM receives a writing instruction for writing data into a virtual register, the RGM determines an identification of a writing register module indicated by the writing instruction and a target transmission variable, wherein the value of the target transmission variable is the data to be written;
the RGM determines a write address corresponding to the combination of the identification of the write register module and the target transmission variable based on the corresponding relation;
the RGM sends the target transfer variable and a write address to the DUT over the bus;
the DUT writes the value of the target transport variable to the location indicated by the write address.
In one embodiment of the present invention, the method further comprises:
when the RGM receives a reading instruction for reading data from a virtual register, the RGM determines the identification of a reading register module indicated by the reading instruction and a target transmission variable;
the RGM determines a read address corresponding to the combination of the identification of the read register module and the target transmission variable based on the corresponding relation;
the RGM sends the read address to the DUT over the bus;
the DUT reads the data at the read address and sends the read data to the RGM through the bus;
The RGM sets the value of the target transmission variable as the read data.
In one embodiment of the present invention, different resource pools are connected to corresponding register modules by using different buses, and the RGM sends the target transmission variable and the write address to the DUT through the buses, including:
RGM sends the target transfer variable and write address to the DUT via a bus between the write register module and a resource pool.
In one embodiment of the invention, the resource pool is constructed in the following manner:
scanning a register description file describing a register module in the DUT and virtual registers contained in the register module;
extracting text for describing a register module and a virtual register contained in the register module from the register description file;
extracting information of the register module and an identification of the register module from the text;
generating resource pools respectively corresponding to the identifications of each register module;
for each register module, extracting information of a virtual register contained in the register module from the text, generating a transmission variable corresponding to the virtual register, and recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module.
In one embodiment of the present invention, the signal transmitted by the bus includes at least one of the following information: the data writing device comprises a clock signal, an address line for recording an address, data to be written, read data, a read-write signal for representing whether the data writing device is in a read state or a write state currently, a write valid indication for representing whether the data writing device is in a write state currently, and a read valid indication for representing whether the data writing device is in a read state currently.
In a third aspect, embodiments of the present invention provide a computer-readable storage medium having a computer program stored therein, which when executed by a processor, implements the method steps of any of the second aspects.
The embodiment of the invention has the beneficial effects that:
the embodiment of the invention provides chip testing equipment, which comprises a DUT (Design Under Test, a module to be tested) and RGM, wherein the DUT and the RGM are connected through a bus; the DUT comprises a register module, wherein the register module comprises a virtual register, the RGM comprises a resource pool, and the resource pool corresponds to the register module one by one; each resource pool is recorded with the identification and transmission variable of the register module corresponding to the resource pool, the transmission variable is in one-to-one correspondence with the virtual register contained in the register module, and the RGM is recorded with the correspondence between the combination of the identification and transmission variable of the register module and the virtual register address corresponding to the transmission variable; the RGM is used for determining the identification of a write register module indicated by the write instruction and a target transmission variable when receiving the write instruction for writing data into the virtual register; determining a write address corresponding to a combination of the identification of the write register module and a target transmission variable based on the correspondence; transmitting the target transmission variable and the write address to the DUT through the bus, wherein the value of the target transmission variable is data to be written; the DUT is used for writing the value of the target transmission variable into the position indicated by the write address.
In the above-mentioned scheme provided by the embodiment of the present invention, because the correspondence between the combination of the identifier of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after determining the identifier of the write register module indicated by the write instruction and the target transmission variable, the RGM may determine the address of the virtual register corresponding to the combination of the identifier of the write register module and the target transmission variable based on the correspondence; then, RGM can send the address of the virtual register and the target transmission variable to DUT directly, DUT writes the value of the target transmission variable into the virtual register based on the received address of the virtual register. Compared with the mode of writing data into a register in the prior UVM, the process of writing data into the register in the embodiment of the invention does not involve a series of variable processing processes, and the speed of writing data into the register is improved, so that the pipeline operation of writing data into the register can be more conveniently performed, and the efficiency of the pipeline operation is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other embodiments may be obtained according to these drawings to those skilled in the art.
FIG. 1 is a schematic diagram of a RAL-based RGM-DUT connection architecture in a conventional general verification method;
fig. 2 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present invention;
FIG. 3 is a timing diagram of writing data via a bus according to an embodiment of the present invention;
FIG. 4 is a timing chart of reading data through a bus according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a first method for reading and writing register data according to an embodiment of the present invention;
FIG. 6 is a flowchart illustrating a second method for reading and writing register data according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a third method for reading and writing register data according to an embodiment of the present invention;
fig. 8 is a flow chart of a resource pool construction method according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by the person skilled in the art based on the present invention are included in the scope of protection of the present invention.
In existing UVMs, RGM is built based on RAL (Register Abstract Layer, register abstraction layer) which is based on modeling registers and memories with address mapping in DUTs by building a set of high level abstract classes.
Referring to fig. 1, a schematic diagram of an RGM-DUT connection based on RAL in the conventional general verification method is shown.
In fig. 1, uvm _reg_0 (general verification method_register_0), uvm _reg_1 (general verification method_register_1), uvm _reg_2 (general verification method_register_2) to uvm _reg_n (general verification method_register_n) respectively represent different high-level abstract classes, map represents a mobile application part, adapter represents an adaptation module, predictor represents a prediction module, and Bus agent represents a Bus agent. The bus_agent contains a bus_sequencer, which represents a Bus sequencer; bus_driver, which represents a Bus driver; bus_monitor represents a Bus monitor. In the DUT, reg_0, reg_1, reg_2 through reg_N represent different registers 0-N, respectively. In the RGM structure shown in fig. 1, in the process of data reading and writing, the RGM generates a variable storing a read-write type and an operation address, then performs type conversion on the variable through a register-to-Bus adapting function (reg 2 Bus), sends the converted variable to a bus_sequencer, processes the received variable, sends the processed variable to a bus_driver, and finally realizes the read-write operation on register data based on the received variable by the bus_driver, and before the variable is fed back to the RGM by the Bus, the variable needs to be processed through the Bus-to-register adapting function (Bus 2 reg).
In the above process of writing data, a series of processes of variable processing and response/item_done of components are involved, resulting in a pipeline operation that cannot support data writing well.
In order to solve the above problems, the embodiments of the present invention provide a chip test apparatus and a register data read/write method, which are specifically described below.
In the embodiment of the invention, the chip test equipment comprises a DUT and an RGM, and the DUT and the RGM are connected through a bus; the DUT comprises a register module, wherein the register module comprises a virtual register, the RGM comprises a resource pool, and the resource pool corresponds to the register module one by one; each resource pool is recorded with the identification and the transmission variable of the register module corresponding to the resource pool, the transmission variable is in one-to-one correspondence with the virtual register contained in the register module, and the RGM is recorded with the correspondence between the combination of the identification and the transmission variable of the register module and the virtual register address corresponding to the transmission variable.
Fig. 2 is a schematic structural diagram of a chip testing apparatus according to an embodiment of the present invention. As can be seen in fig. 2, the chip test apparatus includes an RGM201 and a DUT202. In FIG. 2, DUT202 includes register module 0, register module 1, register module 2, and so on, up to register module N. For each register module, the register module includes a positive integer number of virtual registers. Illustratively, for register module 1, virtual register 1-0, virtual register 1-1, virtual register 1-2, and so on are included in the register module, up to virtual register 1-M. In fig. 2, virtual registers 1-M represent the m+1th virtual register of register module 1, virtual registers 2-P represent the p+1th virtual register of register module 2, and so on.
In fig. 2, the resource pool 0 corresponds to the register module 0, the resource pool 1 corresponds to the register module 1, the resource pool 2 corresponds to the register module 2, and so on, and the resource pool N corresponds to the register module N, that is, the number of the resource pools is the same as the number of the register modules, and corresponds to one.
Illustratively, the identity of the register module corresponding to the resource pool 1 is recorded in the resource pool 1: the register module 1 is also recorded with a transmission variable 1-0 in the resource pool 1 and corresponds to the virtual register 1-0; a transmission variable 1-1 is recorded and corresponds to the virtual register 1-1; a transmission variable 1-2 is recorded and corresponds to the virtual register 1-2; similarly, the transfer variables 1-M are recorded, corresponding to the virtual registers 1-M. The identification and transmission variable of the register module recorded in the other resource pool and the corresponding relation setting of the transmission variable and the virtual register can refer to the description of the resource pool 1.
Specifically, the number of resource pools and register modules in fig. 2 is not limited in the embodiment of the present invention, that is, in the above description, N may be valued as needed in a natural number starting from 0.
In fig. 2, a LUT (Look-Up Table) records a correspondence between a combination of an identification of a register module and a transmission variable and a virtual register address corresponding to the transmission variable, and the LUT is one way of recording the correspondence, and the way of recording the correspondence is not limited in this embodiment. The write operation in fig. 2 indicates that RGM201 writes data into the virtual register, and the read operation indicates that RGM201 reads data from the virtual register.
In addition, the number of virtual registers in each register module is not required to be completely consistent, that is, the number of virtual registers in each register module can be set as required, so that the number of transmission variables in each resource pool is set according to actual conditions, and only one-to-one correspondence between the transmission variables and the virtual registers is ensured.
In the embodiment of the present invention, the RGM201 is configured to determine, when receiving a write instruction for writing data into a virtual register, an identifier of a write register module indicated by the write instruction and a target transmission variable.
After the RGM201 receives the write instruction, the RGM201 determines, according to information in the write instruction, the target transmission variable and the identifier of the write register module, that is, the RGM201 needs to write data into the register module corresponding to the identifier, where the value of the target transmission variable is to be written, that is, the RGM201 needs to write the value of the target transmission variable into the write register module.
The RGM201 determines a write address corresponding to a combination of the identification of the write register module and the target transfer variable based on the correspondence relationship.
After determining the target transfer variable and the identifier of the write register module, the RGM201 searches the correspondence for the address of the virtual register corresponding to the combination of the identifier of the write register module and the target transfer variable, that is, the write address. After determining the write address, the RGM201 determines that the value of the target transport variable needs to be written into the virtual register indicated by the write address.
The RGM201 sends the target transfer variable and write address to the DUT202 via the bus.
Specifically, the RGM201 transmits the target transfer variable and the write address to the DUT202, so that the DUT202 writes the value of the target transfer variable into a virtual register indicated by the write address.
The DUT202 is configured to write the value of the target transmission variable to the location indicated by the write address.
Specifically, the DUT202, upon receiving the write address, writes the received value of the target transport variable into the virtual register indicated by the write address according to the write address, thereby completing the process of writing the data indicated by the write instruction.
In one embodiment of the present invention, the signal transmitted by the bus includes at least one of the following information: the data writing device comprises a clock signal, an address line for recording an address, data to be written, read data, a read-write signal for representing whether the data writing device is in a read state or a write state currently, a write valid indication for representing whether the data writing device is in a write state currently, and a read valid indication for representing whether the data writing device is in a read state currently.
Referring to table 1, a table is defined for information in signals transmitted by the bus in an embodiment of the present invention.
TABLE 1
In table 1, the naming of each information name is only an example, and the bit width of each information is also an example, and can be adjusted as needed.
Referring to fig. 3, a timing diagram of writing data through a bus according to an embodiment of the present invention is provided. As can be seen from fig. 3, the clock signal is formed by a combination of alternately occurring high and low levels, wherein successive ones of the high and low levels constitute one clock cycle. In fig. 3, the read-write signal being high indicates that the chip test apparatus is currently in a write state, in which case the write-active indication is high indicating that the chip test apparatus is currently in a write state. As can be seen from fig. 3, since the RGM201 sends the data to be written, that is, the target transmission variable and the write address, to the DUT202 through the bus at one time, the DUT202 directly writes the value of the target transmission variable into the virtual register indicated by the write address, and as can be seen from fig. 3, the time duration of the vaill in the high level state in the embodiment of the present invention is only one clock cycle, that is, the whole process of writing data can be completed only one clock cycle, and the time consumption of the process of writing data in the embodiment of the present invention is shorter.
Specifically, the fact that the read-write signal is high level indicates that the chip test device is currently in the writing state is only an example, and the fact that the chip test device is currently in the writing state can also be specified according to the requirement that the chip test device is low level indicates that the chip test device is currently in the writing state, and for the writing effective indication and the reading effective indication, reference is made to the description of the read-write signal.
In the above-mentioned scheme provided by the embodiment of the present invention, because the correspondence between the combination of the identifier of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after determining the identifier of the write register module indicated by the write instruction and the target transmission variable, the RGM may determine the address of the virtual register corresponding to the combination of the identifier of the write register module and the target transmission variable based on the correspondence; then, RGM can send the address of the virtual register and the target transmission variable to DUT directly, DUT writes the value of the target transmission variable into the virtual register based on the received address of the virtual register. Compared with the mode of writing data into a register in the prior UVM, the process of writing data into the register in the embodiment of the invention does not involve a series of variable processing processes, and the speed of writing data into the register is improved, so that the pipeline operation of writing data into the register can be more conveniently performed, and the efficiency of the pipeline operation is improved.
During chip verification, RGM201 not only writes data to the virtual registers of DUT202, but also reads data from the virtual registers of DUT 202.
In one embodiment of the present invention, the RGM201 is further configured to determine, when a read instruction for reading data from the virtual register is received, an identification of a read register module indicated by the read instruction and a target transmission variable.
After the RGM201 receives the read instruction, the RGM201 determines the target transmission variable and the identifier of the read register module according to the information in the read instruction, that is, the RGM201 needs to read data from the register module corresponding to the identifier, and finally gives the value of the read data to the target transmission variable.
The RGM201 determines a read address corresponding to a combination of the identification of the read register module and the target transfer variable based on the correspondence relationship.
After determining the target transmission variable and the identifier of the read register module, the RGM201 searches the corresponding relationship for the address of the virtual register corresponding to the combination of the identifier of the read register module and the target transmission variable, that is, the read address. After determining the read address, the RGM201 also determines that data needs to be read from the virtual register indicated by the read address.
The RGM201 sends the read address to the DUT202 via the bus.
Specifically, the RGM201 transmits the read address to the DUT202 so that the DUT202 reads data from the virtual register indicated by the read address.
The DUT202 is also configured to read data at the read address and send the read data to the RGM201 via the bus.
Specifically, the DUT202, after receiving the read address, reads the data in the virtual register indicated by the read address according to the read address, and sends the read data to the RGM201.
The RGM201 is further configured to set the value of the target transmission variable to the read data.
Upon receiving the read data sent from the DUT202, the RGM201 sets the value of the target transmission variable to the read data, thereby completing the process of reading the data indicated by the read command.
Referring to fig. 4, a timing diagram of reading data through a bus according to an embodiment of the present invention is provided. In fig. 4, the read/write signal is low to indicate that the chip test apparatus is currently in a read state, in which case the read valid indication is high to indicate that the chip test apparatus is currently in a read state, as compared with the aforementioned timing chart of writing data through the bus shown in fig. 3. As can be seen from fig. 4, the RGM201 sends a read address to the DUT202 through the bus, the DUT202 reads data according to the read address, and sends the read data to the RGM201, and as can be seen from fig. 4, the rvaild is in the high state for two clock cycles in the embodiment of the present invention, that is, two clock cycles are required for completing the whole process of reading data.
Specifically, the above-described process of writing data and the process of reading data have no sequence in actual implementation.
In the solution provided in the embodiment of the present invention, because the correspondence between the combination of the identifier of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after determining the identifier of the read register module indicated by the read instruction and the target transmission variable, the RGM may determine, based on the correspondence, the address of the virtual register corresponding to the combination of the identifier of the read register module and the target transmission variable, that is, the read address; and then, the RGM sends the read address to the DUT, the DUT reads the data in the virtual register indicated by the read address and sends the read data to the RGM, and the RGM sets the value of the target transmission variable to the read data, so that the process of reading the data indicated by the read instruction is completed.
With the increasing size and complexity of chips, the number and size of registers is increasing, requiring a large number of registers to be verified during chip verification, in which case the RGM is required to write data into the virtual registers of the DUT as quickly as possible.
In another embodiment of the present invention, different buses are used to connect different resource pools with their corresponding register modules, so that all the different buses can be packaged together, which is called a Hbus. The RGM201 is specifically configured to send the target transmission variable and the write address to the DUT202 through a bus between the write register module and the resource pool.
In the embodiment of the present invention, different buses are adopted between different resource pools and corresponding register modules, and according to the description of fig. 2, a bus exists between the resource pool 0 and the register module 0, which may be referred to as bus 0, where the resource pool 0 corresponds to the register module 0, the resource pool 1 corresponds to the register module 1, the resource pool 2 corresponds to the register module 2, and so on, and the resource pool N corresponds to the register module N; a bus exists between the resource pool 1 and the register module 1, which may be called a bus 1; a bus exists between the resource pool 2 and the register module 2, which may be called a bus 2; similarly, there is a bus, which may be referred to as bus N, between the resource pool N and the register module N. Therefore, the RGM201 includes n+1 resource pools, and then n+1 different buses exist, and the different resource pools and the register modules corresponding to the resource pools are connected through the different buses.
For example, if the write register module is register module N and the corresponding resource pool is resource pool N, RGM201 sends the target transmission variable and the write address to DUT202 via bus N between register module N and resource pool N. In addition, RGM201 may send not only the target transfer variable and the write address to DUT202 via bus N between register module N and resource pool N, RGM201 may also send the read address to DUT202 via bus N between register module N and resource pool N, and DUT202 may send the read data to RGM201 via bus N.
In one embodiment of the present invention, in the process of writing data to the virtual register in the register module N by the RGM201 and the DUT202 through the bus N between the register module N and the resource pool N, the RGM201 and the DUT202 may also write data to the virtual register in the register module 2 or read data from the virtual register in the register module 2 through the bus 2 between the register module 2 and the resource pool 2, so as to implement parallel operations of writing data and reading data in different register modules.
In the prior art, only one bus is connected between the RGM and the DUT, and the next data writing or data reading process can be performed after the last data writing or data reading process is completed, so that the pipeline operation efficiency is low. In another embodiment of the present invention, the starting time of writing data into and reading data from different register modules and resource pools may be controlled, for example, in the case that the process of writing data into the virtual register in the register module N by the RGM201 and the DUT202 through the bus N between the register module N and the resource pool N is not completed yet, the RGM201 and the DUT202 may write data into the virtual register in the register module 2 or read data from the virtual register in the register module 2 through the bus 2 between the register module 2 and the resource pool 2, so as to implement the pipeline operation of writing data into and reading data.
From the above, in the scheme provided by the embodiment of the invention, since different resource pools are connected with the corresponding register modules by adopting different buses, the RGM can simultaneously send the target transmission variable and the write address of each of the plurality of register modules to the plurality of register modules, thereby realizing parallel writing of data and further improving the data writing rate of the RGM to the virtual register of the DUT. In addition, in the embodiment of the invention, after the last process of writing data or reading data is completed, the next process of writing data or reading data is performed, so that the efficiency of pipeline operation is further improved.
In one embodiment of the invention, the resource pool is constructed in the following manner:
a register description file describing the register modules in the DUT202 and virtual registers contained in the register modules is scanned.
Specifically, after the register description file is obtained, whether the content in the register description file is empty or not is judged first, and if so, the flow is ended; and if the register description file is not empty, scanning the content in the register description file to acquire related information.
The register description file is used to describe the register modules in the DUT202 and virtual registers included in the register modules, and the contents of the register description file are described in the following by way of example. As shown in table 2, is a table of register information in DUT 202.
TABLE 2
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In table 2, two modules are shown, each containing four registers therein. In table 2, setting of the module address and the register address is an example, naming of the names of the module and the register is an example, and setting of the address and the name can be adjusted according to actual needs.
In addition, the modules in table 2 refer to the register modules in the foregoing, and the registers in table 2 may refer to virtual registers in the foregoing.
Specifically, the contents of the above-described register description file contain all the information in table 2.
In one embodiment of the present invention, the register description file is an xml file, and the name of the register description file is: reg_db (register_Descriibe, register_description).
The format of the register description file can be other common document formats, such as a doc format or a docx format, and the names of the register description file can be set as required.
Text describing the register module and virtual registers included in the register module is extracted from the register description file.
After the register description file is scanned, information describing the register module and the virtual register in the register description file is extracted to form a text containing the register module and the virtual register information.
In one embodiment of the present invention, the register description file is an xml file, and the name of the register description file is: the REG_DB.xml, firstly, calling a related function to convert the REG_DB.xml file, wherein the name of the related function can be named as etre.XML, and the object obtained after the object conversion can be named as an Element object; and then, calling a related expression processing_element object to obtain a text containing the register module and the virtual register information, wherein the name of the related expression can be named as an xpath expression.
And extracting the information of the register module and the identification of the register module from the text.
After a text containing the register module and the virtual register information is obtained, the information of the register module and the identification of the register module are extracted from the text.
A resource pool is generated that corresponds to the identity of each register module, respectively.
After the identifiers of the register modules are obtained, the register modules with different identifiers are classified into different classes, and resource pools corresponding to each class of register modules respectively are generated, namely, the register modules with different identifiers correspond to different resource pools. In addition, the name of each different class is generated by the name of the virtual register in the class; for each different class, a structure of the class is generated based on information contained in the class, the structure containing information of the register module and the virtual register.
For each register module, extracting information of a virtual register included in the register module from the text, generating a transmission variable corresponding to the virtual register, and recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module.
For each register module, information of a virtual register of the register module is extracted from a text containing the register module and the virtual register information, and the information can be an address of the virtual register, and a virtual register can be uniquely determined through the information. Based on the extracted information of the virtual register, a transmission variable corresponding to the virtual register is generated, so that the transmission variable corresponds to the virtual register one by one. And recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module, thereby completing the construction of the resource pool.
From the above, in the scheme provided by the embodiment of the present invention, information of a register module and a virtual register is extracted from a register description file for describing the register module in a DUT and the virtual register included in the register module, a resource pool corresponding to an identification of each register module is generated, and a transmission variable corresponding to the virtual register is generated. And for each register module, recording the obtained information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module, and completing the construction of the resource pool.
Corresponding to the chip test equipment, the embodiment of the invention also provides a register data reading and writing method. Referring to fig. 5, a flowchart of a first register data reading and writing method according to an embodiment of the present invention is provided, and the method is applied to a chip test device, and includes the following steps S501 to S504.
Step S501: when the RGM receives a write instruction for writing data into the virtual register, the RGM determines the identification of the write register module indicated by the write instruction and the target transfer variable.
Step S502: the RGM determines a write address corresponding to a combination of the identification of the write register module and a target transfer variable based on the correspondence.
Step S503: the RGM sends the target transfer variable and write address to the DUT via the bus.
Step S504: the DUT writes the value of the target transmission variable to the location indicated by the write address.
In the above-mentioned scheme provided by the embodiment of the present invention, because the correspondence between the combination of the identifier of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after determining the identifier of the write register module indicated by the write instruction and the target transmission variable, the RGM may determine the address of the virtual register corresponding to the combination of the identifier of the write register module and the target transmission variable based on the correspondence; then, RGM can send the address of the virtual register and the target transmission variable to DUT directly, DUT writes the value of the target transmission variable into the virtual register based on the received address of the virtual register. Compared with the mode of writing data into a register in the prior UVM, the process of writing data into the register in the embodiment of the invention does not involve a series of variable processing processes, and the speed of writing data into the register is improved, so that the pipeline operation of writing data into the register can be more conveniently performed, and the efficiency of the pipeline operation is improved.
During chip verification, the RGM not only writes data to the virtual registers of the DUT, but also reads data from the virtual registers of the DUT. The embodiment of the invention provides the embodiment shown in fig. 6, and a process of reading data from a virtual register by using the RGM is described.
Referring to fig. 6, a flowchart of a second register data reading and writing method according to an embodiment of the present invention is shown, and compared with the embodiment shown in fig. 5, the method further includes the following steps S505 to S509.
Step S505: when the RGM receives a read instruction for reading data from the virtual register, the RGM determines the identification of the read register module indicated by the read instruction and a target transmission variable.
Step S506: and the RGM determines a read address corresponding to the combination of the identification of the read register module and the target transmission variable based on the corresponding relation.
Step S507: the RGM sends the read address to the DUT via the bus.
Step S508: the DUT reads the data at the read address and transmits the read data to the RGM via the bus.
Step S509: the RGM sets the value of the target transmission variable as the read data.
In the solution provided in the embodiment of the present invention, because the correspondence between the combination of the identifier of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after determining the identifier of the read register module indicated by the read instruction and the target transmission variable, the RGM may determine, based on the correspondence, the address of the virtual register corresponding to the combination of the identifier of the read register module and the target transmission variable, that is, the read address; and then, the RGM sends the read address to the DUT, the DUT reads the data in the virtual register indicated by the read address and sends the read data to the RGM, and the RGM sets the value of the target transmission variable to the read data, so that the process of reading the data indicated by the read instruction is completed.
With the increasing size and complexity of chips, the number and size of registers is increasing, and a large number of registers need to be verified during chip verification, in which case the RGM is required to write data into the virtual registers of the DUT as fast as possible, for which purpose the embodiment of the invention provides the embodiment shown in fig. 7.
Referring to fig. 7, a flow chart of a third method for reading and writing register data according to an embodiment of the present invention is shown, and compared with the embodiment shown in fig. 5, different buses are used to connect different resource pools with corresponding register modules, so that all the different buses can be uniformly packaged together, which is called a Hbus, and the above step S503 can be implemented by the following step S503A.
Step S503A: the RGM sends the target transfer variable and write address to the DUT via a bus between the write register module and a resource pool.
From the above, in the scheme provided by the embodiment of the invention, since different resource pools are connected with the corresponding register modules by adopting different buses, the RGM can simultaneously send the target transmission variable and the write address of each of the plurality of register modules to the plurality of register modules, thereby realizing parallel writing of data and further improving the data writing rate of the RGM to the virtual register of the DUT. In addition, in the embodiment of the invention, after the last process of writing data or reading data is completed, the next process of writing data or reading data is performed, so that the efficiency of pipeline operation is further improved.
Referring to fig. 8, a flow chart of a resource pool construction method according to an embodiment of the present invention is provided, and the method is applied to a chip test device, and the method includes the following steps S801 to S805.
Step S801: a register description file describing a register module in the DUT and virtual registers contained in the register module is scanned.
Step S802: text describing the register module and virtual registers included in the register module is extracted from the register description file.
Step S803: and extracting the information of the register module and the identification of the register module from the text.
Step S804: a resource pool is generated that corresponds to the identity of each register module, respectively.
Step S805: for each register module, extracting information of a virtual register included in the register module from the text, generating a transmission variable corresponding to the virtual register, and recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module.
From the above, in the scheme provided by the embodiment of the present invention, information of a register module and a virtual register is extracted from a register description file for describing the register module in a DUT and the virtual register included in the register module, a resource pool corresponding to an identification of each register module is generated, and a transmission variable corresponding to the virtual register is generated. And for each register module, recording the obtained information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module, and completing the construction of the resource pool.
In yet another embodiment of the present invention, a computer readable storage medium is provided, in which a computer program is stored, the computer program implementing the steps of any of the above-mentioned register data read-write methods when executed by a processor.
When the computer program stored in the computer readable storage medium provided by the embodiment of the invention is used for reading and writing register data, because the corresponding relation between the combination of the identification of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after the identification of the write register module indicated by the write instruction and the target transmission variable are determined, the address of the virtual register corresponding to the combination of the identification of the write register module and the target transmission variable can be determined based on the corresponding relation by the RGM; then, RGM can send the address of the virtual register and the target transmission variable to DUT directly, DUT writes the value of the target transmission variable into the virtual register based on the received address of the virtual register. Compared with the mode of writing data into a register in the prior UVM, the process of writing data into the register in the embodiment of the invention does not involve a series of variable processing processes, and the speed of writing data into the register is improved, so that the pipeline operation of writing data into the register can be more conveniently performed, and the efficiency of the pipeline operation is improved.
In yet another embodiment of the present invention, a computer program product containing instructions that, when run on a computer, cause the computer to perform the method of reading and writing register data of any of the above embodiments is also provided.
When the computer program product provided by the embodiment of the invention is applied to register data reading and writing, because the corresponding relation between the combination of the identifier of the register module and the transmission variable and the virtual register address corresponding to the transmission variable is recorded in the RGM, after the identifier of the write register module indicated by the write instruction and the target transmission variable are determined, the RGM can determine the address of the virtual register corresponding to the combination of the identifier of the write register module and the target transmission variable based on the corresponding relation; then, RGM can send the address of the virtual register and the target transmission variable to DUT directly, DUT writes the value of the target transmission variable into the virtual register based on the received address of the virtual register. Compared with the mode of writing data into a register in the prior UVM, the process of writing data into the register in the embodiment of the invention does not involve a series of variable processing processes, and the speed of writing data into the register is improved, so that the pipeline operation of writing data into the register can be more conveniently performed, and the efficiency of the pipeline operation is improved.
In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present invention, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in or transmitted from one computer-readable storage medium to another, for example, by wired (e.g., coaxial cable, optical fiber, digital Subscriber Line (DSL)), or wireless (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the apparatus, chip test device, computer readable storage medium and computer program product embodiments, the description is relatively simple, as it is substantially similar to the method embodiments, and relevant places are referred to in the section of the method embodiments.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (11)

1. The chip testing equipment is characterized by comprising a module DUT to be tested and a register model RGM, wherein the DUT is connected with the RGM through a bus;
the DUT comprises a register module, wherein the register module comprises a virtual register, the RGM comprises a resource pool, and the resource pool corresponds to the register module one by one;
each resource pool is recorded with the identification and transmission variable of the corresponding register module of the resource pool, the transmission variable is in one-to-one correspondence with the virtual register contained in the register module, and the RGM is recorded with the corresponding relation between the combination of the identification and transmission variable of the register module and the virtual register address corresponding to the transmission variable;
the RGM is used for determining the identification of a write register module indicated by the write instruction and a target transmission variable under the condition that the write instruction for writing data into the virtual register is received; determining a write address corresponding to a combination of the identification of the write register module and a target transmission variable based on the corresponding relation; transmitting the target transmission variable and write address to the DUT via the bus; the value of the target transmission variable is data to be written;
The DUT is used for writing the value of the target transmission variable into the position indicated by the write address.
2. The chip test apparatus according to claim 1, wherein the RGM is further configured to, in a case where a read instruction to read data from a virtual register is received, determine an identification of a read register module indicated by the read instruction and a target transmission variable; based on the corresponding relation, determining a read address corresponding to the combination of the identification of the read register module and the target transmission variable; transmitting the read address to the DUT via the bus;
the DUT is also used for reading the data at the read address and sending the read data to the RGM through the bus;
the RGM is further used for setting the value of the target transmission variable as the read data.
3. The chip test apparatus of claim 1, wherein different resource pools are connected to corresponding register modules by different buses, and wherein the RGM is specifically configured to send the target transmission variable and the write address to the DUT through the bus between the write register module and the resource pool.
4. A chip testing apparatus according to any one of claims 1-3, characterized in that the resource pool is constructed in the following way:
Scanning a register description file describing a register module in the DUT and virtual registers contained in the register module;
extracting text for describing a register module and a virtual register contained in the register module from the register description file;
extracting information of the register module and an identification of the register module from the text;
generating resource pools respectively corresponding to the identifications of each register module;
for each register module, extracting information of a virtual register contained in the register module from the text, generating a transmission variable corresponding to the virtual register, and recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module.
5. A chip testing apparatus according to any one of claims 1-3, wherein the signal transmitted by the bus comprises at least one of the following information: the data writing device comprises a clock signal, an address line for recording an address, data to be written, read data, a read-write signal for representing whether the data writing device is in a read state or a write state currently, a write valid indication for representing whether the data writing device is in a write state currently, and a read valid indication for representing whether the data writing device is in a read state currently.
6. The register data reading and writing method is characterized by being applied to chip test equipment, wherein the chip test equipment comprises a module DUT to be tested and a register model RGM, and the DUT and the RGM are connected through a bus;
the DUT comprises a register module, wherein the register module comprises a virtual register, the RGM comprises a resource pool, and the resource pool corresponds to the register module one by one;
each resource pool is recorded with the identification and transmission variable of the corresponding register module of the resource pool, the transmission variable is in one-to-one correspondence with the virtual register contained in the register module, and the RGM is recorded with the corresponding relation between the combination of the identification and transmission variable of the register module and the virtual register address corresponding to the transmission variable;
the method comprises the following steps:
when the RGM receives a writing instruction for writing data into a virtual register, the RGM determines an identification of a writing register module indicated by the writing instruction and a target transmission variable, wherein the value of the target transmission variable is the data to be written;
the RGM determines a write address corresponding to the combination of the identification of the write register module and the target transmission variable based on the corresponding relation;
The RGM sends the target transfer variable and a write address to the DUT over the bus;
the DUT writes the value of the target transport variable to the location indicated by the write address.
7. The method of claim 6, wherein the method further comprises:
when the RGM receives a reading instruction for reading data from a virtual register, the RGM determines the identification of a reading register module indicated by the reading instruction and a target transmission variable;
the RGM determines a read address corresponding to the combination of the identification of the read register module and the target transmission variable based on the corresponding relation;
the RGM sends the read address to the DUT over the bus;
the DUT reads the data at the read address and sends the read data to the RGM through the bus;
the RGM sets the value of the target transmission variable as the read data.
8. The method of claim 6, wherein different resource pools are coupled to their corresponding register modules using different buses, wherein the RGM sends the target transfer variable and write address to the DUT via the buses, comprising:
RGM sends the target transfer variable and write address to the DUT via a bus between the write register module and a resource pool.
9. The method according to any of claims 6-8, characterized in that the resource pool is constructed in the following way:
scanning a register description file describing a register module in the DUT and virtual registers contained in the register module;
extracting text for describing a register module and a virtual register contained in the register module from the register description file;
extracting information of the register module and an identification of the register module from the text;
generating resource pools respectively corresponding to the identifications of each register module;
for each register module, extracting information of a virtual register contained in the register module from the text, generating a transmission variable corresponding to the virtual register, and recording the extracted information of the register module, the information of the virtual register and the generated transmission variable in a resource pool corresponding to the register module.
10. The method according to any one of claims 6 to 8, wherein,
The signal transmitted by the bus comprises at least one of the following information: the data writing device comprises a clock signal, an address line for recording an address, data to be written, read data, a read-write signal for representing whether the data writing device is in a read state or a write state currently, a write valid indication for representing whether the data writing device is in a write state currently, and a read valid indication for representing whether the data writing device is in a read state currently.
11. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 6-10.
CN202310871350.4A 2023-07-14 2023-07-14 Chip test equipment and register data read-write method Pending CN116882331A (en)

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