CN116880986A - Task scheduling method and device, vehicle-mounted controller, electronic equipment and storage medium - Google Patents

Task scheduling method and device, vehicle-mounted controller, electronic equipment and storage medium Download PDF

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Publication number
CN116880986A
CN116880986A CN202310922005.9A CN202310922005A CN116880986A CN 116880986 A CN116880986 A CN 116880986A CN 202310922005 A CN202310922005 A CN 202310922005A CN 116880986 A CN116880986 A CN 116880986A
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China
Prior art keywords
executed
task
tasks
processor core
processor
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CN202310922005.9A
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Chinese (zh)
Inventor
柳宜芳
韩元飞
柏永圣
周光强
姚芳菲
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Zero Beam Technology Co ltd
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Zero Beam Technology Co ltd
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Priority to CN202310922005.9A priority Critical patent/CN116880986A/en
Publication of CN116880986A publication Critical patent/CN116880986A/en
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4843Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485Task life-cycle, e.g. stopping, restarting, resuming execution

Abstract

The application provides a task scheduling method, a task scheduling device, electronic equipment and a storage medium, wherein the task scheduling method comprises the following steps: acquiring running periods and worst execution time of a plurality of tasks to be executed, determining the utilization rate of the tasks to be executed to processor cores according to the running periods and worst execution time of the tasks to be executed, respectively determining the processor cores for executing each task to be executed according to the utilization rate of the tasks to be executed to the processor cores, determining the execution time sequence of each task to be executed by the processor core according to the running periods of the tasks to be executed by the same processor core, and sequentially scheduling each task to be executed by the corresponding processor core according to the execution time sequence so as to sequentially execute the scheduled tasks to be executed by the corresponding processor cores. The scheme can improve the certainty of task scheduling.

Description

Task scheduling method and device, vehicle-mounted controller, electronic equipment and storage medium
Technical Field
The embodiment of the application relates to the technical field of information, in particular to a task scheduling method and device, a vehicle-mounted controller, electronic equipment and a storage medium.
Background
With the explosive development of information technology, more and more industries use processors to process information, and for some scenes with high safety requirements, it is very necessary to ensure that tasks can be completed within a specified time.
Currently, in order to solve the above problem, a general method is that a processor schedules tasks according to task priorities and task maximum execution times.
However, since it is checked whether there is a task trigger of higher priority within the maximum execution time of the task before executing the low priority task each time, if there is a task trigger, the current task is suspended, so there may be a case that the low priority task cannot be executed each time, resulting in uncertainty of the result.
Disclosure of Invention
In view of the above, embodiments of the present application provide a task scheduling method, device, vehicle-mounted controller, electronic device, and storage medium, so as to at least solve some of the above problems.
According to a first aspect of an embodiment of the present application, there is provided a task scheduling method, including: and acquiring running periods and worst execution time of a plurality of tasks to be executed. And determining the utilization rate of the task to be executed to the processor core according to the running period and the worst execution time of the task to be executed. And respectively determining the processor cores for executing each task to be executed according to the utilization rate of the processor cores by the tasks to be executed. And determining the execution time sequence of each task to be executed, which is executed by the same processor core, according to the running period of the task to be executed, which is executed by the same processor core. And sequentially scheduling each task to be executed by the corresponding processor core according to the execution time sequence, so as to sequentially execute the scheduled tasks to be executed by the corresponding processor core.
According to a second aspect of an embodiment of the present application, there is provided a task scheduling device, including: and the acquisition module is used for acquiring the running periods and the worst execution time of the tasks to be executed. And the calculation module is used for determining the utilization rate of the task to be executed to the processor core according to the running period and the worst execution time of the task to be executed. And the distribution module is used for respectively determining the processor cores for executing each task to be executed according to the utilization rate of the plurality of tasks to be executed on the processor cores. And the arrangement module is used for determining the execution time sequence of each task to be executed, which is executed by the processor core, according to the running period of the task to be executed, which is executed by the same processor core. And the scheduling module is used for sequentially scheduling each task to be executed, which is executed by the corresponding processor core, according to the execution time sequence so as to sequentially execute the scheduled task to be executed through the corresponding processor core.
According to a third aspect of the embodiment of the present application, there is provided an in-vehicle controller deployed on a vehicle, including: the vehicle-mounted controller is used for executing the task scheduling method according to the first aspect.
According to a fourth aspect of an embodiment of the present application, there is provided an electronic device including: the device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the memory and the communication interface are communicated with each other through the communication bus. The memory is configured to store at least one executable instruction, where the executable instruction causes the processor to perform operations corresponding to the task scheduling method according to the first aspect.
According to a fifth aspect of embodiments of the present application, there is provided a computer storage medium having stored thereon a computer program which, when executed by a processor, implements a task scheduling method as described in the first aspect above.
According to the technical scheme, the running period and the worst execution time of a plurality of tasks to be executed are obtained, then the utilization rate of the tasks to be executed to the processor core is determined according to the running period and the worst execution time of the tasks to be executed, the processor core for executing each task to be executed is determined according to the utilization rate of the tasks to be executed to the processor core, then the execution time sequence of each task to be executed by the processor core is determined according to the running period of the tasks to be executed by the same processor core, and then each task to be executed by the corresponding processor core is sequentially scheduled according to the execution time sequence, so that the scheduled tasks to be executed are sequentially executed by the corresponding processor core, the processor core of the tasks to be executed is determined according to the utilization rate of the processor core, the execution time sequence of each task to be executed is determined according to the running period of the tasks to be executed, and the certainty of the task scheduling result is improved.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of task scheduling provided by one embodiment of the present application;
FIG. 2 is a schematic diagram of a task scheduler according to one embodiment of the present application;
fig. 3 is a schematic diagram of an electronic device according to an embodiment of the present application.
Detailed Description
The present application is described below based on examples, but the present application is not limited to these examples. In the following detailed description of the present application, certain specific details are set forth in detail. The present application will be fully understood by those skilled in the art without the details described herein. Well-known methods, procedures, and flows have not been described in detail so as not to obscure the nature of the application. The figures are not necessarily drawn to scale.
Task scheduling method
The embodiment of the application provides a task scheduling method, and the task scheduling method is described in detail through a plurality of embodiments.
FIG. 1 is a flow chart of a task scheduling method of one embodiment of the present application. As shown in fig. 1, the task scheduling method includes the steps of:
step S102: and acquiring running periods and worst execution time of a plurality of tasks to be executed.
Under the condition of multitasking, some tasks have a dependency relationship before and after, for example, the execution of task A depends on the execution result of task B, and if task C is arranged between task A and task B, the timely execution of task A may be affected, so that in order to ensure that a plurality of tasks to be executed can be executed, a plurality of tasks to be executed need to be reasonably scheduled.
The task to be executed may be a thread, which is executed in cycles according to its run-time period.
The worst execution time refers to the maximum length of time required for task execution.
Step S104: and determining the utilization rate of the task to be executed to the processor core according to the running period and the worst execution time of the task to be executed.
The running period of the task to be executed may be regarded as that the processor runs for a period of time, the worst execution time represents the longest execution time of the task to be executed, and the utilization rate of the task to be executed to the processor core in a period of time may be determined according to the running period of the task and the worst execution time.
The processor cores may be single or multiple, as the application is not limited in this regard.
Step S106: and respectively determining the processor cores for executing each task to be executed according to the utilization rate of the processor cores by the tasks to be executed.
The utilization rate of the processor cores by each task to be executed can be used for judging whether the current processor cores are occupied or not, and further determining whether the task to be executed is distributed on one or a plurality of processor cores.
Step S108: and determining the execution time sequence of each task to be executed by the same processor core according to the running period of the task to be executed by the same processor core.
For a task to be executed on the same processor core, the execution timing of the execution task is determined according to the running period of the task to be executed, for example, the start time of the task 1, the start time of the task 2, and the like are determined.
The least common multiple of task periods to be executed on the same processor core is calculated, and when tasks are scheduled, the tasks on the same processor core are ensured not to run simultaneously within the least common multiple time, so that all the tasks can be ensured not to run simultaneously in the whole running process.
Step S110: and sequentially scheduling each task to be executed by the corresponding processor core according to the execution time sequence so as to sequentially execute the scheduled task to be executed by the corresponding processor core.
After the execution time sequence of the tasks to be executed is determined, the tasks to be executed on the processor cores are sequentially scheduled according to the execution time sequence, so that each task to be executed on the corresponding processor core can be executed.
In the embodiment of the application, the running period and the worst executing time of a plurality of tasks to be executed are acquired, then the utilization rate of the tasks to be executed to the processor core is determined according to the running period and the worst executing time of the tasks to be executed, the processor core for executing each task to be executed is respectively determined according to the utilization rate of the tasks to be executed to the processor core, then the executing time sequence of each task to be executed by the processor core is determined according to the running period of the tasks to be executed by the same processor core, and then each task to be executed by the corresponding processor core is sequentially scheduled according to the executing time sequence, so that the scheduled tasks to be executed are sequentially executed by the corresponding processor core, the processor core of the tasks to be executed is determined according to the utilization rate of the processor core in the process, the executing time sequence of each task to be executed is determined according to the running period of the tasks to be executed, and the certainty of the task scheduling result is improved.
In one possible implementation manner, determining the utilization rate of the task to be executed to the processor core according to the running period and the worst execution time of the task to be executed includes: and calculating the ratio of the worst execution time to the running period of the task to be executed, and determining the calculation result as the utilization rate of the task to be executed to the processor core.
The processor performs tasks in a cyclic manner according to the operation cycle of the tasks to be performed, for example, the operation cycle of the tasks to be performed is 10ms, the processor performs the tasks to be performed once every 10ms, the worst execution time is the worst execution time of the tasks to be performed, the execution time of the tasks to be performed is usually very short, for example, 0.5ms, and then the utilization rate of the tasks to be performed to the processor core is 0.5/10.
In the embodiment of the application, the core of the task to be executed to the processor is obtained by calculating the ratio of the worst execution time to the running period of the task to be executed, so that a basis is provided for judging whether the core of the processor is occupied.
In one possible implementation manner, according to the utilization rate of the processor cores by the plurality of tasks to be executed, determining the processor core for executing each task to be executed respectively includes: and summing the utilization rates of the processor cores for a plurality of tasks to be executed to obtain a utilization rate sum. If the sum of the utilization rates is smaller than 1, a plurality of tasks to be executed are distributed to one processor core for execution. If the sum of the utilization rates is greater than or equal to 1, a plurality of tasks to be executed are distributed to at least two processor cores for execution, so that the sum of the utilization rates of the processor cores by the tasks to be executed by each processor core is smaller than 1.
The utilization rates of the processor cores are summed up for a plurality of tasks to be executed to obtain a utilization rate sum, and the utilization rate sum reflects whether the current processor core is occupied by the tasks.
If the sum of the utilization rates is less than 1, which indicates that the current processor core is not fully occupied, a plurality of tasks to be executed may be allocated to the processor core for execution.
If the sum of the utilization rates is greater than or equal to 1, it indicates that at least 2 tasks on the current processor core will run simultaneously, and the situation that the tasks cannot be executed due to insufficient computing resources easily occurs, so that a plurality of tasks to be executed are distributed to at least two processor cores, so that each processor core cannot be occupied by the tasks.
In the embodiment of the application, the sum is used for obtaining the utilization rate sum of the processor cores, and the task to be executed is distributed to one or more processor cores by judging whether the utilization rate sum is larger than 1, so that each processor core is not occupied by the task, each task to be executed can be executed, and the certainty of task scheduling is improved.
In one possible implementation manner, a maximum memory usage amount of each task to be executed in a plurality of tasks to be executed is obtained, and memory is allocated to the task to be executed according to the maximum memory usage amount of the task to be executed.
And before the task is scheduled, memory is allocated for the task to be executed according to the maximum memory usage amount of the task to be executed, so that the task to be executed has enough resources in running.
In the embodiment of the application, the memory is allocated for the task to be executed according to the maximum memory usage amount of the task to be executed, so that the task to be executed has enough resources in running, and the certainty of task execution is improved.
In one possible implementation, determining execution timing of each task to be executed by the same processor core according to a running period of the task to be executed by the processor core includes: and sequencing the tasks to be executed by the processor cores according to the order of the corresponding running periods from small to large according to the running periods of the tasks to be executed by the same processor core, so as to obtain task sequencing. And determining the execution time sequence of each task to be executed in sequence according to the resource mutex lock and the task sequence, so that the resources with the mutex lock cannot be called by different tasks to be executed at the same time.
When the tasks are scheduled, the tasks to be executed, which are executed by the processor cores, are ordered according to the sequence from small to large corresponding operation periods, and the tasks with small operation periods do not cause resource waste caused by excessively long waiting time of the tasks to be executed after the tasks are scheduled even if the interrupt condition of the execution tasks occurs due to the small period, so that the task ordering can maximize the utilization of the processor cores.
A mutex lock is a marker of a resource that is used to ensure that only one task can access the resource at any one time.
In the embodiment of the application, the tasks to be executed by the processor cores are ordered according to the sequence from small to large of the corresponding running period, so that the processor cores can be utilized to the maximum extent, the sufficiency of computing resources is ensured, the resources are ensured not to be simultaneously called by different tasks to be executed through the mutual exclusion lock, and the certainty of task scheduling is further improved.
In one possible implementation manner, a starting time of the task to be executed is obtained, and according to the starting time, if an execution completion message of the task to be executed is not received within the worst execution time of the task to be executed, an abnormal operation is executed.
The abnormal operation may be a predefined operation including executing the remaining tasks to be executed of the current cycle, terminating the current tasks to be executed, or restarting the system when the processor is idle before the next cycle.
In the embodiment of the application, the starting time of the task to be executed is acquired, and if the execution completion message of the task to be executed is not received in the worst execution time of the task to be executed according to the starting time, the abnormal operation is executed, so that the influence of the abnormal execution timeout of a certain task on the subsequent task to be executed is avoided, and the task scheduling certainty is further improved.
Task scheduling device
Fig. 2 is a schematic diagram of a task scheduling device according to an embodiment of the present application, and as shown in fig. 2, a task scheduling device 200 may include: an acquisition module 202, a calculation module 204, an allocation module 206, an orchestration module 208, and a scheduling module 210.
The acquiring module 202 is configured to acquire a running period and a worst execution time of a plurality of tasks to be executed.
Under the condition of multitasking, some tasks have a dependency relationship before and after, for example, the execution of task A depends on the execution result of task B, and if task C is arranged between task A and task B, the timely execution of task A may be affected, so that in order to ensure that a plurality of tasks to be executed can be executed, a plurality of tasks to be executed need to be reasonably scheduled.
The task to be executed may be a thread, which is executed in cycles according to its run-time period.
The worst execution time refers to the maximum length of time required for task execution.
The calculating module 204 is configured to determine a utilization rate of the to-be-executed task to the processor core according to the running period and the worst execution time of the to-be-executed task.
The running period of the task to be executed may be regarded as that the processor runs for a period of time, the worst execution time represents the longest execution time of the task to be executed, and the utilization rate of the task to be executed to the processor core in a period of time may be determined according to the running period of the task and the worst execution time.
The processor cores may be single or multiple, as the application is not limited in this regard.
And the allocation module 206 is configured to determine the processor cores that execute each task to be executed according to the utilization rates of the multiple tasks to be executed on the processor cores.
The utilization rate of the processor cores by each task to be executed can be used for judging whether the current processor cores are occupied or not, and further determining whether the task to be executed is distributed on one or a plurality of processor cores.
An orchestration module 208, configured to determine execution timing of each task to be executed by the same processor core according to execution cycles of the tasks to be executed by the processor core.
For a task to be executed on the same processor core, the execution timing of the execution task is determined according to the running period of the task to be executed, for example, the start time of the task 1, the start time of the task 2, and the like are determined.
The least common multiple of task periods to be executed on the same processor core is calculated, and when tasks are scheduled, the tasks on the same processor core are ensured not to run simultaneously within the least common multiple time, so that all the tasks can be ensured not to run simultaneously in the whole running process.
The scheduling module 210 is configured to schedule each of the tasks to be executed by the corresponding processor core in turn according to the execution timing, so as to sequentially execute the scheduled tasks to be executed by the corresponding processor core.
After the execution time sequence of the tasks to be executed is determined, the tasks to be executed on the processor cores are sequentially scheduled according to the execution time sequence, so that each task to be executed on the corresponding processor core can be executed.
In the embodiment of the present application, the acquiring module 202 acquires the running periods and the worst execution times of the plurality of tasks to be executed, then the calculating module 204 determines the utilization rate of the tasks to be executed to the processor cores according to the running periods and the worst execution times of the tasks to be executed, the distributing module 206 determines the processor cores for executing each task to be executed according to the utilization rate of the tasks to be executed to the processor cores, then the arranging module 208 determines the execution time sequence of each task to be executed by the processor cores according to the running periods of the tasks to be executed by the same processor core, and the scheduling module 210 sequentially schedules each task to be executed by the corresponding processor core according to the execution time sequence, so as to sequentially execute the scheduled tasks to be executed by the corresponding processor cores, determine the processor cores of the tasks to be executed according to the utilization rate of the processor cores in the process, and determine the execution time sequence of each task to be executed according to the running periods of the tasks to be executed, thereby improving the certainty of the task scheduling results.
Vehicle-mounted controller
The embodiment of the application also provides a vehicle-mounted controller which is deployed on the vehicle and is used for executing the relevant steps in any task scheduling method embodiment.
Electronic equipment
Fig. 3 is a schematic block diagram of an electronic device according to an embodiment of the present application, which is not limited to the specific implementation of the electronic device. As shown in fig. 3, the electronic device 300 may include: a processor (processor) 302, a communication interface (Communications Interface) 304, a memory (memory) 306, and a communication bus 308. Wherein:
processor 302, communication interface 304, and memory 306 perform communication with each other via communication bus 308.
Communication interface 304 for communicating with other electronic devices or servers.
The processor 302 is configured to execute the program 310, and may specifically perform relevant steps in any of the foregoing task scheduling method embodiments.
In particular, program 310 may include program code including computer-operating instructions.
The processor 302 may be a CPU or a specific integrated circuit ASIC (Application Specific Integrated Circuit) or one or more integrated circuits configured to implement embodiments of the present application. The one or more processors comprised by the smart device may be the same type of processor, such as one or more CPUs; but may also be different types of processors such as one or more CPUs and one or more ASICs.
Memory 306 for storing programs 310. Memory 306 may comprise high-speed RAM memory or may also include non-volatile memory (non-volatile memory), such as at least one disk memory.
Program 310 may be specifically configured to cause processor 302 to perform the task scheduling method of any of the foregoing embodiments.
The specific implementation of each step in the procedure 310 may refer to corresponding steps and corresponding descriptions in units in any of the foregoing task scheduling method embodiments, which are not described herein. It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and modules described above may refer to corresponding procedure descriptions in the foregoing method embodiments, which are not repeated herein.
According to the electronic device, the running period and the worst executing time of a plurality of tasks to be executed are obtained, then the utilization rate of the tasks to be executed to the processor cores is determined according to the running period and the worst executing time of the tasks to be executed, the processor cores for executing each task to be executed are respectively determined according to the utilization rate of the tasks to be executed to the processor cores, then the executing time sequence of each task to be executed by the processor cores is determined according to the running period of the tasks to be executed by the same processor core, and then each task to be executed by the corresponding processor cores is sequentially scheduled according to the executing time sequence, so that the scheduled tasks to be executed are sequentially executed by the corresponding processor cores, the processor cores of the tasks to be executed are determined according to the utilization rate of the processor cores in the process, the executing time sequence of each task to be executed is determined according to the running period of the tasks to be executed, and therefore the certainty of a task scheduling result is improved.
Storage medium
In this embodiment, a computer-readable storage medium is provided storing instructions for causing a machine to perform a task scheduling method as herein. Specifically, a system or apparatus provided with a storage medium on which a software program code realizing the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or apparatus may be caused to read out and execute the program code stored in the storage medium.
In this case, the program code itself read from the storage medium may realize the functions of any of the above-described embodiments, and thus the program code and the storage medium storing the program code form part of the present application.
Examples of the storage medium for providing the program code include a floppy disk, a hard disk, a magneto-optical disk, an optical disk (e.g., CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RAM, DVD-RW, DVD+RW), a magnetic tape, a nonvolatile memory card, and a ROM. Alternatively, the program code may be downloaded from a server computer by a communication network.
It should be noted that in the description of the present application, the terms "first," "second," and the like are merely used for convenience in describing the various components or names and are not to be construed as indicating or implying a sequential relationship, relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It should be noted that, although specific embodiments of the present application have been described in detail with reference to the accompanying drawings, the present application should not be construed as limiting the scope of the present application. Various modifications and variations which may be made by those skilled in the art without the creative effort are within the scope of the present application as described in the claims.
Examples of embodiments of the present application are intended to briefly illustrate technical features of embodiments of the present application so that those skilled in the art may intuitively understand the technical features of the embodiments of the present application, and are not meant to be undue limitations of the embodiments of the present application.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting; although the application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (10)

1. A method of task scheduling, the method comprising:
acquiring running periods and worst execution time of a plurality of tasks to be executed;
determining the utilization rate of the task to be executed to the processor core according to the running period and the worst execution time of the task to be executed;
respectively determining the processor cores for executing each task to be executed according to the utilization rate of the processor cores by the tasks to be executed;
determining the execution time sequence of each task to be executed by the same processor core according to the running period of the task to be executed by the same processor core;
and sequentially scheduling each task to be executed by the corresponding processor core according to the execution time sequence, so as to sequentially execute the scheduled tasks to be executed by the corresponding processor core.
2. The method of claim 1, wherein determining the utilization of the processor core by the task to be executed based on the run period and the worst execution time of the task to be executed comprises:
and calculating the ratio of the worst execution time to the running period of the task to be executed, and determining the calculation result as the utilization rate of the task to be executed to the processor core.
3. The method of claim 2, wherein determining the processor core to execute each of the tasks to be executed based on the utilization of the processor cores by the plurality of tasks to be executed, respectively, comprises:
summing the utilization rates of the processor cores by the tasks to be executed to obtain a utilization rate sum;
if the sum of the utilization rates is smaller than 1, distributing the tasks to be executed to a processor core for execution;
and if the sum of the utilization rates is greater than or equal to 1, distributing the tasks to be executed to at least two processor cores for execution, so that the sum of the utilization rates of the processor cores by the tasks to be executed by each processor core is smaller than 1.
4. The method according to claim 1, wherein the method further comprises:
obtaining the maximum memory usage of each task to be executed in the plurality of tasks to be executed;
and distributing memory for the task to be executed according to the maximum memory usage of the task to be executed.
5. The method of claim 1, wherein determining execution timing of each of the tasks to be executed by the same processor core based on execution cycles of the tasks to be executed by the same processor core comprises:
according to the running period of each task to be executed by the same processor core, sequencing each task to be executed by the processor core according to the sequence from small to large of the corresponding running period to obtain task sequencing;
and determining the execution time sequence of each task to be executed in sequence according to the task sequencing according to the resource mutex locks, so that the resources with the mutex locks cannot be called by different tasks to be executed at the same time.
6. The method according to any one of claims 1-5, further comprising:
acquiring the starting time of the task to be executed;
and according to the starting time, if the execution completion message of the task to be executed is not received in the worst execution time of the task to be executed, executing abnormal operation, wherein the abnormal operation comprises executing the residual task to be executed in the current period, stopping the current task to be executed or restarting the system when the processor is idle before the next period.
7. A task scheduling device, the device comprising:
the acquisition module is used for acquiring running periods and worst execution time of a plurality of tasks to be executed;
the computing module is used for determining the utilization rate of the task to be executed to the processor core according to the running period and the worst execution time of the task to be executed;
the distribution module is used for respectively determining the processor cores for executing each task to be executed according to the utilization rate of the plurality of tasks to be executed on the processor cores;
the scheduling module is used for determining the execution time sequence of each task to be executed, which is executed by the processor core, according to the running period of the task to be executed, which is executed by the same processor core;
and the scheduling module is used for sequentially scheduling each task to be executed, which is executed by the corresponding processor core, according to the execution time sequence so as to sequentially execute the scheduled task to be executed through the corresponding processor core.
8. An in-vehicle controller deployed on a vehicle for performing the task scheduling method of any one of claims 1-6.
9. An electronic device, comprising: the device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the memory and the communication interface are communicated with each other through the communication bus;
the memory is configured to store at least one executable instruction, where the executable instruction causes the processor to perform operations corresponding to the task scheduling method according to any one of claims 1 to 6.
10. A computer storage medium having stored thereon a computer program which when executed by a processor implements the task scheduling method of any one of claims 1-6.
CN202310922005.9A 2023-07-25 2023-07-25 Task scheduling method and device, vehicle-mounted controller, electronic equipment and storage medium Pending CN116880986A (en)

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CN117234696A (en) * 2023-11-13 2023-12-15 北京控制工程研究所 Determination method and device for multitasking execution strategy of high-frequency GNC system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117234696A (en) * 2023-11-13 2023-12-15 北京控制工程研究所 Determination method and device for multitasking execution strategy of high-frequency GNC system
CN117234696B (en) * 2023-11-13 2024-01-19 北京控制工程研究所 Determination method and device for multitasking execution strategy of high-frequency GNC system

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