CN116866447A

CN116866447A - Conversion device, chip and electronic equipment between four-phase binding and two-phase double-track protocol

Info

Publication number: CN116866447A
Application number: CN202311130249.XA
Authority: CN
Inventors: 张华秋; 刘震; 白鑫; 乔宁
Original assignee: Shi Shi Ruidi Qingdao Technology Co ltd; Shenzhen Shizhi Technology Co ltd
Current assignee: Shi Shi Ruidi Qingdao Technology Co ltd; Shenzhen Shizhi Technology Co ltd
Priority date: 2023-09-04
Filing date: 2023-09-04
Publication date: 2023-10-10
Anticipated expiration: 2043-09-04
Also published as: CN116866447B

Abstract

The application discloses a conversion device, a chip and electronic equipment between four-phase binding and two-phase double-track protocols. In order to realize data exchange or transmission between circuit modules adopting a four-phase binding data protocol and a two-phase double-track protocol in an asynchronous circuit, the application realizes cross-protocol information exchange through a protocol conversion circuit. The application realizes protocol conversion by using only logic gate and C unit, has low comprehensive and verification difficulty, does not need strict and complex time sequence constraint, and has the technical effects of high efficiency and low difficulty. The application is suitable for the fields of asynchronous circuit design, nerve form chips and Internet of things.

Description

Conversion device, chip and electronic equipment between four-phase binding and two-phase double-track protocol

Technical Field

The application relates to a conversion device between a four-phase binding data protocol and a two-phase double-track protocol, in particular to a conversion device, a chip and electronic equipment for realizing the conversion between the four-phase binding data protocol and the two-phase double-track protocol.

Background

Asynchronous circuits use handshake protocols to ensure reliability and synchronicity of data transmission to avoid problems such as loss, confusion, or desynchronization of data. Based on the handshake protocol, it can be ensured that the sender and the receiver exchange data at the proper timing.

The four-phase bundled data protocol highlights the timing relationship between the data signal (data) and the handshake signals (req, ack), and the timing of the transmit and receive end signal changes is consistent, thus it relies on delay matching. The req line and the ack line adopt Boolean values, four steps are needed to complete the transmission of single data, and the handshake process is as follows: a. the sender sends data and pulls the req signal high; b. the receiver receives the data and pulls the ack signal high; c. the sender responds to the ack signal and pulls req low; d. the receiver pulls ack low. The asynchronous protocol is easy to implement, most similar to synchronous circuits, and often allows for optimal performance of the circuit due to the widely used timing assumptions. However, the protocol is sensitive to wire delay, has poor robustness and stability, has redundant zero-resetting action, and increases the cost of the circuit in terms of speed and power consumption.

The two-phase dual-track protocol encodes a request signal (req) together with a data signal (data) and uses 2 lines d.t, d.f to represent 1 bit of information, forming a signal for communication, the information on the ack line being represented by signal transitions, and either 0 to 1 or 1 to 0 representing the same information, only two steps being required to complete the transmission of a single data. Therefore, the transmission speed is low, the power consumption is low, and the robustness and the stability are strong and the influence of wire delay is avoided because 2 lines are used for representing 1 bit of information. But the response circuit is complex and the implementation difficulty is high.

The choice of whether to use the four-phase bundled data protocol or the two-phase dual-track protocol circuit depends on the asynchronous circuit design requirements, performance goals, complexity, and the like.

How to efficiently realize the conversion between the four-phase binding data protocol and the two-phase double-track protocol is a problem to be solved in the design of an asynchronous circuit.

Disclosure of Invention

In order to solve or alleviate some or all of the above technical problems, the present application is implemented by the following technical solutions:

a first class of conversion means for converting two-phase dual-track protocol data into four-phase bundled data protocol data, comprising at least: a first edge detector, a second edge detector, and a first logic unit (101), and a third C unit (109); the true value signal (d0. T) and the false value signal (d0. F) in the two-phase double-track protocol data are respectively processed by a first edge detector and a second edge detector and then used as a first input and a second input of a first logic part; the first logic part at least comprises a first C unit (103) and a second C unit (104), wherein the first C unit is used for generating a request signal (Req) in four-phase binding Data protocol Data, and the second C unit outputs a Data signal (Data [0 ]) in the four-phase binding Data protocol Data corresponding to the true value signal (d0.t) and the false value signal (d0.f); the acknowledgement signal (Ack) and the request signal (Req) in the four-phase bundled data protocol data are used as inputs of the third C-unit for generating an acknowledgement signal in the two-phase double track protocol data.

In certain embodiments, the output of the third C cell is inverted by a NOT gate (106) and then used as one of the inputs to the first C cell and the second C cell.

In some embodiments, the output of the third C unit is connected to the CK terminal of the D flip-flop, the output of the Q terminal of the D flip-flop is used as a response signal in the two-phase dual-track protocol data, and the output of the Q terminal of the D flip-flop is connected to the D terminal of the D flip-flop after being subjected to non-gate inversion.

In some class of embodiments, if the two-phase dual-track protocol data includes only one pair of true and false signals, then the output of the first C unit is used as a request signal (Req) in the four-phase bundled data protocol data;

if the two-phase dual-track protocol data includes at least two pairs of true signals (d0.t, d 1.t) and false signals (d 0.f, d 1.f), the outputs of the first C units corresponding to each pair of true signals and false signals are input into a logic unit (108) which outputs a request signal (Req) in the four-phase bundled data protocol data.

In some types of embodiments, the output of the logic cell is provided as one of the inputs to the multiplexer, the other input to the multiplexer is low, and the output signal is selected by the multiplexer as the input to the third C cell.

In certain classes of embodiments, the logic unit: a first stage C unit comprising a plurality of C units; the output of the first stage C unit is processed by a second stage C unit comprising a plurality of C units until the last stage C unit has only one C unit; the output of every two C units in the former stage C unit is used as the input of one C unit in the latter stage C unit; the output of only one C cell included in the C cell of the last stage serves as the output of the logic cell.

In certain classes of embodiments, the or gate is replaced with an exclusive or gate.

A second class of conversion means for converting four-phase bundled data protocol data into two-phase double-track protocol data, comprising at least: a logic unit (201), an edge detector, and a C unit (207); after the response signal in the two-phase double-track protocol data is processed by the edge detector, the response signal is used as one of the inputs of the C unit, and the other input of the C unit is a request signal in the four-phase binding data protocol data; the C unit outputs a response signal in the four-phase binding data protocol data; the logic part at least comprises a first AND gate (203), a second AND gate (204), a first D trigger (205) and a second D trigger (206); the logic receives the Data signal (Data [0 ]) and the request signal in the four-phase bundled Data protocol Data and converts them into a true value signal (d0. T) and a false value signal (d0. F) in the two-phase double-track protocol Data.

In certain classes of embodiments, the first AND gate receives the data signals and the request signals in the four-phase bundled data protocol data, and the second AND gate receives the request signals and the inverted data signals in the four-phase bundled data protocol data; the output of the first AND gate is connected with the CK end of the first trigger, and the output of the second AND gate is connected with the CK end of the second trigger; the Q end output signal of the first trigger is connected to the D end of the first trigger after the NOT gate inversion, and the Q end output signal of the second trigger is connected to the D end of the second trigger after the NOT gate inversion; the Q end of the first trigger outputs a true value signal in the two-phase double-track protocol data, and the Q end of the second trigger outputs a false value signal in the two-phase double-track protocol data.

A chip comprising any one of the first class of conversion devices described above; or/and, comprise any of the preceding second class of conversion means.

An electronic device comprising a chip as described above.

In certain classes of embodiments, the electronic device is an animal ear tag.

Some or all embodiments of the present application have the following beneficial technical effects:

1) The application realizes flexible conversion between four-phase binding data protocol and two-phase double-track protocol data.

2) The circuit has a simple structure and is easy to realize, and commercial design can be carried out based on EDA tools.

3) The conversion circuit provided by the application is modularized and outstanding, and has universality and expansibility.

4) The application realizes protocol conversion by using only logic gate and C unit, and has low comprehensive and verification difficulty, and no need of strict and complex time sequence constraint.

5) The conversion circuit has the characteristics of event driving and low power consumption, and can be applied to the field of nerve morphology, such as event imaging devices, pulse neural network processors and the like.

Further advantageous effects will be further described in the preferred embodiments.

The above-described technical solutions/features are intended to summarize the technical solutions and technical features described in the detailed description section, and thus the ranges described may not be exactly the same. However, these new solutions disclosed in this section are also part of the numerous solutions disclosed in this document, and the technical features disclosed in this section and the technical features disclosed in the following detailed description section, and some contents in the drawings not explicitly described in the specification disclose more solutions in a reasonable combination with each other.

The technical scheme combined by all the technical features disclosed in any position of the application is used for supporting the generalization of the technical scheme, the modification of the patent document and the disclosure of the technical scheme.

Drawings

FIG. 1 is a device for converting two-phase dual-track protocol data into four-phase bundled data protocol data;

FIG. 2 is a schematic diagram of a logic unit in some embodiments of the application;

FIG. 3 is a diagram of a device for converting four-phase bundled data protocol data into two-phase double-track protocol data;

fig. 4 is a schematic diagram of a chip structure including a conversion device.

Detailed Description

Since various alternatives are not exhaustive, the gist of the technical solution in the embodiment of the present application will be clearly and completely described below with reference to the drawings in the embodiment of the present application. Other technical solutions and details not disclosed in detail below, which generally belong to technical objects or technical features that can be achieved by conventional means in the art, are limited in space and the present application is not described in detail.

Except where division is used, any position "/" in this disclosure means a logical "or". The ordinal numbers "first", "second", etc., in any position of the present application are used merely for distinguishing between the labels in the description and do not imply an absolute order in time or space, nor do they imply that the terms preceded by such ordinal numbers are necessarily different from the same terms preceded by other ordinal terms.

The present application will be described in terms of various elements for use in various combinations of embodiments, which elements are to be combined in various methods, products. In the present application, even if only the gist described in introducing a method/product scheme means that the corresponding product/method scheme explicitly includes the technical feature.

The description of a step, module, or feature in any location in the disclosure does not imply that the step, module, or feature is the only step or feature present, but that other embodiments may be implemented by those skilled in the art with the aid of other technical means according to the disclosed technical solutions. The embodiments of the present application are generally disclosed for the purpose of disclosing preferred embodiments, but it is not meant to imply that the contrary embodiments of the preferred embodiments are not intended to cover all embodiments of the application as long as such contrary embodiments are at least one technical problem addressed by the present application. Based on the gist of the specific embodiments of the present application, a person skilled in the art can apply means of substitution, deletion, addition, combination, exchange of sequences, etc. to certain technical features, so as to obtain a technical solution still following the inventive concept. Such solutions without departing from the technical idea of the application are also within the scope of protection of the application.

The four-phase binding data protocol is most similar to the synchronous circuit, the realization is simple, and the four-phase binding data protocol data (called four-phase binding data protocol for short) is matched with two-phase double-track protocol data (called two-phase double-track protocol for short) to have better robustness and more application scenes. The present application is therefore focused on the conversion between the four-phase bundled data protocol and the two-phase dual-track protocol.

Referring to fig. 1, taking 2-way data d0 and d1 as an example, a schematic diagram of a two-phase dual-track protocol data to four-phase binding data protocol data conversion device (2-phase dual-track to 4-phase binding conversion device for short) 100 is shown. In the present application, "switching" means a switching direction of data to be transmitted, and is generally opposite to the direction of a response signal.

The 2-way data d0 and d1 include a d0.t true value signal and a d0.f false value signal, and a d1.t true value signal and a d1.f false value signal, respectively, which are all data signals transmitted in a 2-phase dual-track protocol. These true and false signals are processed by edge (edge) detectors, respectively. With respect to edge detectors, reference may be made in particular to prior art CN116582113a, which is incorporated by reference in its entirety.

The d0.T signal and the d0.F signal processed by the first edge detector and the second edge detector, respectively, are fed to the first logic unit 101 as a first input signal and a second input signal. The d1.T signal and the d1.F signal processed by the edge detector are fed to the second logic 102. The first logic unit 101 and the second logic unit 102 preferably have the same circuit logic structure.

The first logic unit 101 includes one not gate 105, and gate, or gate, and first and second C units 103 and 104. The preferred second logic 102 is the same as this.

The information processing logic of the first logic portion 101 is described by taking d0 data as an example, and the d 1-way data processing manner is similar and reference is made to fig. 1, which is not repeated here. The d0.t signal and the d0.f signal processed by the edge detector are fed into the or gate, the output of which is used as a first input of the first C-unit. The d0.T signal processed by the edge detector is used as input to the and gate with the d0.F signal inverted by the not gate 105. The output of the and gate is taken as a first input of the second C-cell. The output of the second C unit is Data [0] in the four-phase bundled Data protocol Data.

The other inputs (i.e., the second inputs) of the first C-cell 103 and the second C-cell 104 are both the same signal, i.e., the output of the not gate 106.

As an embodiment having two-way data d0, d1, the outputs of the respective first C units (103, 107) in the first logic unit 101 and the second logic unit 102 serve as inputs to the logic unit 108, and the logic unit 108 outputs the request signal Req in the four-phase bundled data protocol data. The second C unit in the second logic 102 outputs Data [1] in the four-phase bundled Data protocol Data.

In some embodiments, when more than two paths of data (n is equal to or greater than 3) are included, the similar processing is adopted, and the output of the first C unit corresponding to each path of data is processed by the n-input and gate to output the request signal Req in the four-phase binding data protocol data.

In some embodiments, when there is only one path of data (assuming d 0), the logic unit 108 may be omitted, and the output signal of the first C unit 103 is directly used as the request signal Req in the four-phase bundled data protocol data.

The request signal Req in the four-phase bundled data protocol data outputted from the logic unit 108 and the response signal Ack in the four-phase bundled data protocol data are inputted to the third C unit 109. The output of the third C cell 109 is used as an input to the aforementioned not gate 106 and is connected to the CK input of the D flip-flop. The Q end of the D trigger is accessed to the D end of the D trigger after the NOT gate is reversed, and the Q end of the D trigger outputs a response signal Ack in the two-phase double-track protocol data.

By the preferred embodiment, two-phase double-track protocol data of 2-way data are converted into four-phase binding data protocol data.

FIG. 2 is a schematic diagram of a logic unit 108 according to some embodiments of the application. Fig. 2 (a) to (d) correspond to the case where the conversion device 100 converts 2-way to 5-way data, respectively.

As an example, as shown in fig. 1, it includes only two logic sections 101, 102 whose outputs y0 and y1, and referring to part (a) in fig. 2, the logic unit 108 includes only one C unit whose inputs are the aforementioned y0 and y1, and whose output out is the request signal Req in the four-phase bundled data protocol data.

The logic unit 108 includes a plurality of C cells including a number of C cells that is the number of bits of the data signal to be converted minus 1.

In general, logic unit 108: a first stage C unit comprising a plurality of C units; the output of the first stage C unit is processed by a second stage C unit comprising a plurality of C units until the last stage C unit has only one C unit; the output of every two C units in the former stage C unit is used as the input of one C unit in the latter stage C unit; the output of only one C cell included in the C cells of the last stage serves as the output of the logic unit 108.

Optionally, the output of logic unit 108 is provided as one of the inputs to a multiplexer, the other input of which is low, and one of the outputs is selected by the multiplexer.

The output of logic unit 108 is coupled to the input of C unit 109 via multiplexer MUX. One input of the multiplexer MUX is connected to the output of the logic unit 108 and the other input may be connected to a low level (0), the output of the MUX being connected to one input of the C unit 109. The C-cell has a memory effect where the MUX can be used for power-on reset purposes.

Referring to FIG. 3, there is shown a preferred embodiment of a Data conversion device 200 that will bind Data protocol Data for four phases to two-phase dual-track protocol Data (4-phase to 2-phase dual-track conversion device for short), which still takes 2-way Data [0], data [1] as an example.

The four-phase binding to two-phase double-track conversion device includes a third logic portion 201 and a fourth logic portion 202 for converting into d0.t, d0.f (2-phase double track), and d1.t, d1.f (2-phase double track) according to the request signals Req, data [0] (4-phase binding), and the request signals Req, data [1] (4-phase binding), respectively. The third logic unit 201 and the fourth logic unit 202 preferably have the same circuit configuration logic.

The request signal Req in the four-phase bundled Data protocol Data, bundled with Data 0 (4) is input to and gate 203, and the output of and gate 203 is coupled to the CK terminal of D flip-flop 205.

The request signal Req in the four-phase bundled Data protocol Data, bundled with Data 0 (4) after the NOT phase inversion, is used as the input of the AND gate 204, and the output of the AND gate 204 is connected to the CK end of the D flip-flop 206.

The Q-terminal of the D flip-flop 205 outputs a D0.t (2-phase dual rail) signal, and the Q-terminal of the D flip-flop 205 is connected to the D-terminal of the D flip-flop 205 after being not-gate inverted.

The Q-terminal of the D flip-flop 206 outputs a D0.F (2-phase dual rail) signal, and the Q-terminal of the D flip-flop 206 is coupled to the D-terminal of the D flip-flop 206 after being not-gate inverted.

For the preferred fourth logic portion 202, the circuit structure is shown in fig. 3, and the structure and circuit logic are similar to those of the third logic portion 201, and will not be described here again.

The request signal Req in the four-phase bundled data protocol data and the Ack (2-phase double track) processed by the edge detector are used as inputs of the C unit 207, and the output of the C unit 207 is the acknowledgement signal Ack in the four-phase bundled data protocol data.

Referring to fig. 4, a schematic diagram of a chip structure with an asynchronous circuit protocol conversion function is shown. The chip comprises the 2-phase double-track to 4-phase binding conversion device, or/and the 4-phase binding to 2-phase double-track conversion device. These conversion means are embodied, for example, as protocol conversion circuits.

The chip can be used in electronic equipment, such as Internet of things equipment (animal ear tags and the like).

Alternatively, in any of the foregoing embodiments, in the protocol conversion circuit of the present application, the buffer unit or the delay unit may be inserted at any position as required.

In some embodiments, the protocol conversion circuit described in the previous embodiments of the present application is applied to an interface.

In some embodiments, the protocol conversion circuit described in the previous embodiments of the present application is applied to a chip. Optionally, the chip is a chip implemented based on an asynchronous circuit.

Because the asynchronous circuit is more attached to a biological reaction mechanism, more and more AI chips adopt asynchronous circuit designs, such as bionic visual sensors, rapidly feel dynamic information based on the change of light intensity in a visual field, and asynchronously output sparse event streams, such as event imaging devices; and the neuromorphic processor realizes neuron dynamics based on an asynchronous and event-driven mechanism, breaks through the traditional von neumann architecture, and has the characteristics of ultra-low power consumption and ultra-low delay.

Alternatively, the aforementioned chip is a neuromorphic chip or a chip designed based on event driving.

Preferably, the chip is a neuromorphic sensor or neuromorphic processor.

For the OR gate at any position in the application, at least one OR gate can be replaced by an exclusive OR gate, and compared with the OR gate, the OR gate has lower complexity, smaller area and lower power consumption.

Although the present application has been described with reference to specific features and embodiments thereof, various modifications, combinations, substitutions can be made thereto without departing from the application. The scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification, but rather, the methods and modules may be practiced in one or more products, methods, and systems of the associated, interdependent, inter-working, pre/post stages.

The specification and drawings are, accordingly, to be regarded in an abbreviated manner as an introduction to some embodiments of the technical solutions defined by the appended claims and are thus to be construed in accordance with the doctrine of greatest reasonable interpretation and are intended to cover as much as possible all modifications, changes, combinations or equivalents within the scope of the disclosure of the application while also avoiding unreasonable interpretation.

Further improvements in the technical solutions may be made by those skilled in the art on the basis of the present application in order to achieve better technical results or for the needs of certain applications. However, even if the partial improvement/design has creative or/and progressive characteristics, the technical idea of the present application is relied on to cover the technical features defined in the claims, and the technical scheme shall fall within the protection scope of the present application.

The features recited in the appended claims may be presented in the form of alternative features or in the order of some of the technical processes or the sequence of organization of materials may be combined. Those skilled in the art will readily recognize that such modifications, changes, and substitutions can be made herein after with the understanding of the present application, by changing the sequence of the process steps and the organization of the materials, and then by employing substantially the same means to solve substantially the same technical problem and achieve substantially the same technical result, and therefore such modifications, changes, and substitutions should be made herein by the equivalency of the claims even though they are specifically defined in the appended claims.

The steps and components of the embodiments have been described generally in terms of functions in the foregoing description to clearly illustrate this interchangeability of hardware and software, and in terms of various steps or modules described in connection with the embodiments disclosed herein, may be implemented in hardware, software, or a combination of both. Whether such functionality is implemented as hardware or software depends upon the particular application or design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different approaches for each particular application, but such implementation is not intended to be beyond the scope of the claimed application.

Claims

1. A conversion device characterized in that:

the conversion device is used for converting two-phase double-track protocol data into four-phase binding data protocol data, and at least comprises: a first edge detector, a second edge detector, and a first logic unit (101), and a third C unit (109);

the true value signal (d0. T) and the false value signal (d0. F) in the two-phase double-track protocol data are respectively processed by a first edge detector and a second edge detector and then used as a first input and a second input of a first logic part;

the first logic part at least comprises a first C unit (103) and a second C unit (104), wherein the first C unit is used for generating a request signal (Req) in four-phase binding Data protocol Data, and the second C unit outputs a Data signal (Data [0 ]) in the four-phase binding Data protocol Data corresponding to the true value signal (d0.t) and the false value signal (d0.f);

the acknowledgement signal (Ack) and the request signal (Req) in the four-phase bundled data protocol data are used as inputs of the third C-unit for generating an acknowledgement signal in the two-phase double track protocol data.

2. The conversion device according to claim 1, wherein:

the output of the third C cell is inverted by a NOT gate (106) and then used as one of the inputs of the first C cell and the second C cell.

3. The conversion device according to claim 2, wherein:

the output of the third C unit is connected to the CK end of the D trigger, the output of the Q end of the D trigger is used as a response signal in the two-phase double-track protocol data, and the output of the Q end of the D trigger is connected to the D end of the D trigger after being subjected to NOT gate inversion.

4. A conversion device according to any one of claims 1 to 3, characterized in that:

the first logic part further comprises an OR gate, an AND gate and an NOT gate;

the or gate receives the first input and the second input, and an output of the or gate is one of the inputs of the first C-cell;

the AND gate receives the first input and the inverted second input, and an output of the AND gate is one of the inputs of the second C cell.

5. The conversion device according to claim 4, wherein:

if the two-phase dual-track protocol data only includes a pair of true signal and false signal, the output of the first C unit is used as a request signal (Req) in the four-phase bundled data protocol data;

if the two-phase dual-track protocol data includes at least two pairs of true signals (d0.t, d 1.t) and false signals (d 0.f, d 1.f), the outputs of the first C units corresponding to each pair of true signals and false signals are input into an AND gate (108) which outputs a request signal (Req) in the four-phase bundled data protocol data.

6. The switching device of claim 5, wherein:

the or gate is replaced by an exclusive or gate.

7. A conversion device characterized in that:

the conversion device is used for converting four-phase binding data protocol data into two-phase double-track protocol data, and at least comprises:

a logic unit (201), an edge detector, and a C unit (207);

after the response signal in the two-phase double-track protocol data is processed by the edge detector, the response signal is used as one of the inputs of the C unit, and the other input of the C unit is a request signal in the four-phase binding data protocol data; the C unit outputs a response signal in the four-phase binding data protocol data;

the logic part at least comprises a first AND gate (203), a second AND gate (204), a first D trigger (205) and a second D trigger (206);

the logic receives the Data signal (Data [0 ]) and the request signal in the four-phase bundled Data protocol Data and converts them into a true value signal (d0. T) and a false value signal (d0. F) in the two-phase double-track protocol Data.

8. The conversion device according to claim 7, wherein:

the first AND gate receives the data signal and the request signal in the four-phase binding data protocol data, and the second AND gate receives the request signal and the inverted data signal in the four-phase binding data protocol data;

the output of the first AND gate is connected with the CK end of the first trigger, and the output of the second AND gate is connected with the CK end of the second trigger;

the Q end output signal of the first trigger is connected to the D end of the first trigger after the NOT gate inversion, and the Q end output signal of the second trigger is connected to the D end of the second trigger after the NOT gate inversion;

the Q end of the first trigger outputs a true value signal in the two-phase double-track protocol data, and the Q end of the second trigger outputs a false value signal in the two-phase double-track protocol data.

9. A chip, characterized in that:

the chip comprising the conversion device of any one of claims 1-6; or/and the combination of the two,

comprising a conversion device according to any one of claims 7-8.

10. An electronic device, characterized in that:

the electronic device comprising the chip of claim 9.