CN116865743A - Level shift circuit with wide voltage range - Google Patents

Level shift circuit with wide voltage range Download PDF

Info

Publication number
CN116865743A
CN116865743A CN202310851726.5A CN202310851726A CN116865743A CN 116865743 A CN116865743 A CN 116865743A CN 202310851726 A CN202310851726 A CN 202310851726A CN 116865743 A CN116865743 A CN 116865743A
Authority
CN
China
Prior art keywords
transistor
voltage
low
voltage signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202310851726.5A
Other languages
Chinese (zh)
Other versions
CN116865743B (en
Inventor
周仁杰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Gaotuoxunda Beijing Microelectronics Co ltd
Original Assignee
Gaotuoxunda Beijing Microelectronics Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gaotuoxunda Beijing Microelectronics Co ltd filed Critical Gaotuoxunda Beijing Microelectronics Co ltd
Priority to CN202310851726.5A priority Critical patent/CN116865743B/en
Publication of CN116865743A publication Critical patent/CN116865743A/en
Application granted granted Critical
Publication of CN116865743B publication Critical patent/CN116865743B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

The application provides a level shift circuit with a wide voltage range, which relates to the technical field of integrated circuits, and comprises a low-voltage inverter, a differential input module, a voltage clamping module, a latch and a high-voltage inverter; the low-voltage inverter inverts the phase of the first low-voltage signal to obtain a second low-voltage signal; the output end of the low-voltage inverter is connected with the input end of the differential input module, and the differential input module inverts the phase of the low-voltage signal to obtain a medium-low voltage signal; the output end of the differential input module is connected with the input end of the voltage clamping module, the voltage clamping module converts the medium-low voltage signal into a high-voltage signal, and the output end of the differential input module is connected with the input end of the high-voltage inverter to input the medium-low voltage signal into the high-voltage inverter; the output end of the voltage clamping module is connected with the input end of the latch; the latch output is connected to the high voltage inverter input. By adopting the level shift circuit with the wide voltage range, the problem that the voltage range of the low voltage in the level shift circuit is limited is solved.

Description

Level shift circuit with wide voltage range
Technical Field
The application relates to the technical field of integrated circuits, in particular to a level shift circuit with a wide voltage range.
Background
The level shift circuit can convert an input low voltage signal into a high voltage signal and output the high voltage signal, and is widely used in integrated circuits. In digital circuits, as process nodes decrease, for example: the process node is reduced from 14 nm to 7 nm, and the voltage of the Core transistor (VDDL) is reduced, and the voltage of the high voltage supply (VDDH) is still required to be kept at a higher voltage of 3.3V, which poses a design challenge for the level shift circuit.
In the prior art, the level shift circuit is limited by the contradiction between the higher threshold voltage and the lower supply voltage of the 3.3V Input Output (IO) transistor, so that the application scenario requirement that VDDL is smaller than 0.7V is difficult to support, and the problem that the voltage range of the low voltage is limited is caused.
Disclosure of Invention
Accordingly, the present application is directed to a level shift circuit with a wide voltage range, so as to solve the problem of limited voltage range of the low voltage in the level shift circuit.
In a first aspect, an embodiment of the present application provides a level shift circuit with a wide voltage range, where the level shift circuit includes a low voltage inverter, a differential input module, a voltage clamping module, a latch, and a high voltage inverter;
the signal input end of the low-voltage inverter receives a first low-voltage signal input by an external circuit, performs phase inversion processing on the first low-voltage signal to obtain a second low-voltage signal with the opposite phase to the first low-voltage signal, and the power input end of the low-voltage inverter is connected with the low-voltage power supply;
the output end of the low-voltage inverter is connected with the input end of the differential input module, the first low-voltage signal and the second low-voltage signal are input into the differential input module, and the differential input module respectively performs phase inversion processing on the first low-voltage signal and the second low-voltage signal to obtain a first medium-low voltage signal and a second medium-low voltage signal;
the output end of the differential input module is connected with the input end of the voltage clamping module, the first medium-low voltage signal and the second medium-low voltage signal are input into the voltage clamping module, the voltage clamping module is connected with the high voltage power supply through the latch, the first medium-low voltage signal and the second medium-low voltage signal are respectively converted into a first high voltage signal and a second high voltage signal, the output end of the differential input module is also connected with the first input end of the high voltage inverter, and the first medium-low voltage signal is input into the high voltage inverter;
the output end of the voltage clamping module is connected with the input end of the latch, the first high-voltage signal and the second high-voltage signal are input into the latch, and the latch determines a level state value corresponding to the first high-voltage signal;
the output end of the latch is connected with the second input end of the high-voltage inverter, the level state value is input into the high-voltage inverter, and the high-voltage inverter outputs the high-voltage signal after the high-voltage inverter performs phase inversion processing on the first medium-low voltage signal and the level state value.
Optionally, the low-voltage inverter includes a first transistor and a second transistor, both of which are CMOS transistors; the grid electrode of the first transistor is used as a signal input end of the low-voltage inverter to be connected with an external circuit, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected with the drain electrode of the second transistor; the grid electrode of the second transistor is connected with the grid electrode of the first transistor, and the source electrode of the second transistor is used as a power input end to be connected with a low-voltage power supply; the grid electrode of the first transistor is also used as a first output end of the low-voltage inverter to be connected with a first input end of the differential input module, and the drain electrode of the first transistor is also used as a second output end of the low-voltage inverter to be connected with a second input end of the differential input module.
Optionally, the differential input module includes a third transistor and a fourth transistor, both of which are NMOS transistors; the grid electrode of the third transistor is used as a first input end of the differential input module to be connected with the first output end of the low-voltage inverter, the source electrode of the third transistor is grounded, and the drain electrode of the third transistor is used as a first output end of the differential input module to be connected with the first input end of the voltage clamping module; the drain electrode of the third transistor is used as the first output end of the differential input module and is also connected with the first input end of the high-voltage inverter; the grid electrode of the fourth transistor is used as a second input end of the differential input module to be connected with the second output end of the low-voltage inverter, the source electrode of the fourth transistor is grounded, and the drain electrode of the fourth transistor is used as a second output end of the differential input module to be connected with the second input end of the voltage clamping module.
Optionally, the voltage clamping module includes a fifth transistor and a sixth transistor, both of which are PMOS transistors; the drain electrode of the fifth transistor is used as a first input end of the voltage clamping module and is connected with the first output end of the differential input module, the grid electrode of the fifth transistor is connected with the drain electrode of the fifth transistor, and the source electrode of the fifth transistor is used as a first output end of the voltage clamping module and is connected with the first input end of the latch; the drain electrode of the sixth transistor is used as the second input end of the voltage clamping module to be connected with the second output end of the differential input module, the grid electrode of the sixth transistor is connected with the drain electrode of the sixth transistor, and the source electrode of the sixth transistor is used as the second output end of the voltage clamping module to be connected with the second input end of the latch.
Optionally, the latch includes a seventh transistor and an eighth transistor, each of the seventh transistor and the eighth transistor being a PMOS transistor; a drain electrode of the seventh transistor is used as a first input end of the latch and is connected with a first output end of the voltage clamping module, a grid electrode of the seventh transistor is connected with a drain electrode of the eighth transistor, and a source electrode of the seventh transistor is connected with the high-voltage power supply; a drain electrode of the eighth transistor is used as a second input end of the latch and is connected with a second output end of the voltage clamping module, a grid electrode of the eighth transistor is connected with a drain electrode of the seventh transistor, and a source electrode of the eighth transistor is connected with the high-voltage power supply; the drain of the seventh transistor is also connected as a first output of the latch to the second input of the high voltage inverter.
Optionally, the high-voltage inverter includes a ninth transistor and a tenth transistor, each of which is a CMOS transistor; a grid electrode of the ninth transistor is used as a first input end of the high-voltage inverter to be connected with a first output end of the differential input module, a source electrode of the ninth transistor is grounded, and a drain electrode of the ninth transistor is used as an output end of the high-voltage inverter to output a high-voltage signal; the gate of the tenth transistor is connected to the first output terminal of the latch as the second input terminal of the high voltage inverter, the source of the tenth transistor is connected to the high voltage power supply, and the drain of the tenth transistor is connected to the drain of the ninth transistor.
Optionally, the fifth transistor includes a plurality of fifth transistors, and the sixth transistor includes a plurality of sixth transistors; the number of the plurality of fifth transistors is equal to the number of the plurality of sixth transistors.
Optionally, the drain electrode of a first fifth transistor of the plurality of fifth transistors is connected as the first input end of the voltage clamping module to the first output end of the differential input module, the gate electrode of the first fifth transistor is connected with the drain electrode of the first fifth transistor, the source electrode of the first fifth transistor is connected with the drain electrode of the second fifth transistor, the gate electrode of the second fifth transistor is connected with the drain electrode of the second fifth transistor, the source electrode of the second fifth transistor is connected with the drain electrode of the third fifth transistor, and so on, and the source electrode of the last fifth transistor is connected as the first output end of the voltage clamping module to the first input end of the latch; the drain electrode of a first sixth transistor of the plurality of sixth transistors is connected as the second input end of the voltage clamping module to the second output end of the differential input module, the gate electrode of the first sixth transistor is connected with the drain electrode of the first sixth transistor, the source electrode of the first sixth transistor is connected with the drain electrode of the second sixth transistor, the gate electrode of the second sixth transistor is connected with the drain electrode of the second sixth transistor, the source electrode of the second sixth transistor is connected with the drain electrode of the third sixth transistor, and so on, the source electrode of the last sixth transistor is connected as the second output end of the voltage clamping module to the second input end of the latch.
Optionally, the fifth transistor and the sixth transistor are PMOS transistors of 3.3V.
Optionally, the ninth transistor and the tenth transistor are each 3.3V CMOS transistors.
The embodiment of the application has the following beneficial effects:
according to the level shift circuit with the wide voltage range, the voltage clamping module can be inserted between the differential input module and the latch, the voltage difference between the voltage of the output signal of the differential input module and the voltage of the output signal of the voltage clamping module is adjusted by the voltage clamping module, so that signals with two different voltages are input to the high-voltage inverter, the maximum voltage of the output end of the differential input module is reduced on the basis of VDDH, the differential input module can adopt a transistor with lower threshold voltage, the power supply range of a low-voltage power supply is expanded downwards, and compared with the level shift circuit with the wide voltage range in the prior art, the problem that the low-voltage power supply range is limited in the level shift circuit is solved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram showing a wide voltage range level shift circuit according to an embodiment of the present application;
fig. 2 is a circuit diagram of a level shift circuit of a single fifth transistor and a single sixth transistor according to an embodiment of the present application;
fig. 3 is a circuit diagram of a level shift circuit of a plurality of fifth transistors and a plurality of sixth transistors according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments of the present application, every other embodiment obtained by a person skilled in the art without making any inventive effort falls within the scope of protection of the present application.
It should be noted that, before the present application is proposed, the level shift circuit can convert the input low voltage signal into the high voltage signal and output the high voltage signal, and is widely used in integrated circuits. In digital circuits, as process nodes decrease, for example: the process node is reduced from 14 nm to 7 nm, and the voltage of the Core transistor (VDDL) is reduced, and the voltage of the high voltage supply (VDDH) is still required to be kept at a higher voltage of 3.3V, which poses a design challenge for the level shift circuit. In the prior art, the level shift circuit is limited by the contradiction between the higher threshold voltage and the lower supply voltage of the 3.3V Input Output (IO) transistor, so that the application scenario requirement that VDDL is smaller than 0.7V is difficult to support, and the problem that the voltage range of the low voltage is limited is caused. For example: when low voltage power is supplied with VDDL below 0.7V, the voltage of the high level signal input to the differential input module is close to or lower than the threshold voltage (typically about 0.7V) of the 3.3V IO transistor of the differential input module, so that the transistor of the differential input module cannot be normally turned on and output a low level, thereby causing an output error.
Based on the above, the embodiment of the application provides a level shift circuit with a wide voltage range so as to improve the voltage range of a low-voltage power supply in the level shift circuit.
Referring to fig. 1, fig. 1 is a schematic diagram of a level shift circuit with a wide voltage range according to an embodiment of the application. As shown in fig. 1, the level shift circuit with a wide voltage range provided by the embodiment of the application includes a low-voltage inverter 100, a differential input module 200, a voltage clamping module 300, a latch 400 and a high-voltage inverter 500;
the signal input end of the low-voltage inverter 100 receives a first low-voltage signal input by an external circuit, performs phase inversion processing on the first low-voltage signal to obtain a second low-voltage signal with the opposite phase to the first low-voltage signal, and the voltage input end of the low-voltage inverter 100 is connected with the low-voltage power supply VDDL, and the ground of the low-voltage inverter 100 is grounded to VSS.
The output end of the low-voltage inverter 100 is connected with the input end of the differential input module 200, the first low-voltage signal and the second low-voltage signal are input into the differential input module 200, the differential input module 200 performs phase inversion processing on the first low-voltage signal and the second low-voltage signal respectively to obtain a first middle low-voltage signal and a second middle low-voltage signal, and the grounding end of the differential input module 200 is grounded to the VSS.
The output end of the differential input module 200 is connected with the input end of the voltage clamping module 300, the first medium-low voltage signal and the second medium-low voltage signal are input into the voltage clamping module 300, the voltage clamping module 300 is connected with the high voltage power supply VDDH through the latch 400, the first medium-low voltage signal and the second medium-low voltage signal are respectively converted into a first high voltage signal and a second high voltage signal, the output end of the differential input module 200 is also connected with the first input end of the high voltage inverter 500, and the first medium-low voltage signal is input into the high voltage inverter 500.
The output terminal of the voltage clamping module 300 is connected to the input terminal of the latch 400, the first high voltage signal and the second high voltage signal are input to the latch 400, the latch 400 determines a level state value corresponding to the first high voltage signal, and the voltage input terminal of the latch 400 is connected to the high voltage power supply VDDH.
The output terminal of the latch 400 is connected to the second input terminal of the high-voltage inverter 500, the level state value is input to the high-voltage inverter 500, the high-voltage inverter 500 performs the phase inversion processing on the first medium-low voltage signal and the level state value, then outputs the high-voltage signal, the voltage input terminal of the high-voltage inverter 500 is connected to the high-voltage power supply VDDH, and the ground terminal of the high-voltage inverter 500 is grounded to VSS.
Here, the first low voltage signal may be a control signal, a communication signal, or a data signal.
The first low voltage signal may be a low voltage signal of a low level or a low voltage signal of a high level.
In the embodiment of the application, the chip of the low-process node comprises an external circuit and a potential translation circuit, the external circuit inputs a first low-voltage signal to the potential translation circuit, a low-voltage inverter in the potential translation circuit receives the first low-voltage signal, and the phase inversion processing is carried out on the first low-voltage signal to obtain a second low-voltage signal. Wherein if the first low voltage signal is a low level signal, the second low voltage signal is a high level signal, and if the first low voltage signal is a high level signal, the second low voltage signal is a low level signal. Here, since the low voltage inverter is powered by a low voltage power supply, both the input and output of the low voltage inverter are low voltage signals.
The low-voltage inverter is used for driving the differential input module, and after the low-voltage inverter obtains a first low-voltage signal and a second low-voltage signal, the first low-voltage signal and the second low-voltage signal are input into the differential input module, and the differential input module respectively performs phase inversion processing on the first low-voltage signal and the second low-voltage signal to obtain a first medium-low voltage signal after phase inversion of the first low-voltage signal and a second medium-low voltage signal after phase inversion of the second low-voltage signal. The differential input module is connected with the high-voltage power supply through the voltage clamping module and the latch, so that the voltage of the output signal of the differential input module is higher than that of the output signal of the low-voltage inverter, and the voltage of the output signal of the differential input module is lower than that of the output signal of the voltage clamping module, and therefore the differential input module is called as a medium-low voltage signal. The output end of the differential input module is connected with the first input end of the high-voltage inverter, and the first medium-low voltage signal is input into the high-voltage inverter.
The differential input module is used for carrying out high-low conversion of the level, is connected with the voltage clamping module, inputs the first medium-low voltage signal and the second medium-low voltage signal into the voltage clamping module, changes the first medium-low voltage signal into the first high voltage signal after passing through the voltage clamping module, changes the second medium-low voltage signal into the second high voltage signal, and inputs the first high voltage signal and the second high voltage signal into the latch. Here, the voltage clamping module is used for forming a voltage difference, and since the voltage clamping module can step down the high voltage of the high-voltage power supply, the voltage of the output end of the voltage clamping module is higher than the voltage of the input end of the voltage clamping module, that is, the voltage difference is formed between the voltage of the output end of the voltage clamping module and the voltage of the output end of the differential input module, and the voltage of the output end of the voltage clamping module is higher than the voltage of the differential input module.
The latch is used for accurately judging the level. The latch judges the first high-voltage signal, determines the level of the first high-voltage signal, outputs a level state value of 1 if the first high-voltage signal is at a high level, and outputs a level state value of 0 if the first high-voltage signal is at a low level.
The high voltage inverter acts as a phase inversion. The high-voltage inverter reads the level state value from the output end of the latch, performs phase inversion processing on the level state value and the first medium-low voltage signal, and outputs a high-voltage signal. Here, the phases of the first medium-low voltage signal and the level state value are the same, both are high level or both are low level, and if both the first medium-low voltage signal and the level state value are low level, the high-voltage inverter outputs a high-voltage signal of high level; if the first medium-low voltage signal and the level state value are both high level, the high-voltage inverter outputs a high-voltage signal with low level.
The individual blocks in the level shift circuit are described below with reference to fig. 2.
Fig. 2 is a circuit diagram of a level shift circuit of a single fifth transistor and a single sixth transistor according to an embodiment of the present application.
As shown in fig. 2, the low voltage inverter 100 includes a first transistorSecond transistor->A first transistorSecond transistor->CMOS (Complementary Metal Oxide Semiconductor) transistors; first transistor->The gate of the low-voltage inverter 100 is connected to an external circuit as a signal input terminal, and a first transistor +.>Source of (2) is grounded to VSS, a firstTransistor->Drain of (2) and second transistor->Is connected with the drain electrode of the transistor; second transistor->Gate of (c) and first transistor->Gate connection of the second transistor->Is connected with a low-voltage power supply VDDL as a power supply input end; first transistor->The gate of the (a) is also connected as the first output terminal of the low voltage inverter 100 to the first input terminal of the differential input module 200, the first transistor +.>And also as a second output of the low voltage inverter 100 to a second input of the differential input module 200.
Specifically, the second transistorA second transistor connected to the power supply voltage VDDL as a power supply input terminalDrain of (c) and first transistor->Drain connection of the first transistor +.>The source of (a) is grounded so that the entire low voltage inverter outputs a low voltage signal. In addition, the first transistor->The grid electrode of the low-voltage inverter is used as a signal input end of the low-voltage inverter to be connected with an external circuit, receives a first low-voltage signal input by the external circuit, and is a first transistor +>Gate of (2) and second transistor->Is connected to the gate of the second transistor for inputting the first low voltage signal>By a first transistor->And a second transistor->Forming a low-voltage inverter, performing phase inversion processing on the first low-voltage signal to obtain a second low-voltage signal, wherein the second low-voltage signal is formed by a first transistor +.>The first low voltage signal is outputted from the drain of the first transistor->Is provided.
The differential input module 200 includes a third transistorFourth transistor->Third transistor->Fourth transistor->Are NMOS transistors; third transistor->A third transistor, which is connected as a first input terminal of the differential input module 200 to the first output terminal of the low voltage inverter 100>Source ground VSS, third transistor +.>Is connected as a first output of the differential input module 200 with a first input of the voltage clamp module 300; third transistorThe drain electrode of the high-voltage inverter 500 is also connected with the first output end of the differential input module 200; fourth transistor->A fourth transistor as a second input terminal of the differential input module 200 connected to the second output terminal of the low voltage inverter 100>Source ground VSS, fourth transistor +.>Is connected as a second output of the differential input module 200 to a second input of the voltage clamp module 300.
Specifically, the third transistorThe gate of the (a) is used as a first input end of the differential input module 200 to receive a first low voltage signal, and a fourth transistor is +>The gate of the differential input module 200 receives the second low voltage signal as a second input terminal, the differential input module 200 performs phase inversion on the first low voltage signal to obtain a first medium low voltage signal,the differential input module 200 performs phase inversion on the second low voltage signal to obtain a second medium-low voltage signal.
Assuming that the first low voltage signal is low level, the second low voltage signal is high level, the first medium low voltage signal is high level, the second medium low voltage signal is low level, and simultaneously, due to the third transistorThe drain of the (d) is used as the first output terminal of the differential input module 200 to output the first medium-low voltage signal, and the signal input to the high voltage inverter 500 is also at the high level.
The voltage clamp module 300 includes a fifth transistorSixth transistor->Fifth transistor->Sixth transistor->Are PMOS transistors; fifth transistor->A fifth transistor, which is connected as a first input terminal of the voltage clamping module 300 to a first output terminal of the differential input module 200>Gate of (c) and fifth transistor->Drain connection of fifth transistor +.>Is connected as a first output of the voltage clamp block 300 to a first input of the latch 400; sixth transistor->A sixth transistor, which is connected as the second input terminal of the voltage clamping module 300 to the second output terminal of the differential input module 200>Gate of (c) and sixth transistor->Drain connection of (d) sixth transistor->Is connected as a second output of voltage clamp block 300 to a second input of latch 400.
Specifically, the fifth transistorGate of (c) and fifth transistor->Drain connection of (d) sixth transistor->Gate of (c) and sixth transistor->The connection between the gate and the drain of the transistor is called diode connection, so that the clamp voltage between the drain and the source of the transistor is about 0.7V. Fifth transistor->Voltage clamp corresponding to the first medium-low voltage signal, fifth transistor +.>The source of (a) is used as the first output end of the voltage clamping module 300 to output a first high voltage signal, and a sixth transistor is +>Corresponding to the second medium-low voltage signalVoltage clamp, sixth transistor->The source of (a) is used as the second output terminal of the voltage clamping module 300 to output the second high voltage signal. Taking the above example as an example, when the first low voltage signal is at a low level, the first high voltage signal is at a high level, and the second high voltage signal is at a low level.
It should be noted that if only a lower clamp voltage needs to be obtained, for example: 0.7V, i.e. the voltage at the output end of the voltage clamping module is higher than the voltage at the input end of the voltage clamping module by 0.7V, only one group of PMOS transistor clamping circuit units is needed, one group of clamping circuit units refers to a fifth transistorAnd a sixth transistor->。
Wherein, the fifth transistor and the sixth transistor are 3.3V PMOS transistors.
Specifically, the voltage clamping module can be a diode-connected 3.3V PMOS IO transistorAnd 3.3V PMOS IO transistor +.>Composition is prepared.
Latch 400 includes a seventh transistorEighth transistor->Seventh transistor->Eighth transistorAre PMOS transistors; seventh crystalBody tube->A seventh transistor +.>Gate and eighth transistor of (2)>Drain electrode connection of (a) seventh transistorIs connected with a high-voltage power supply VDDH; eighth transistor->Is connected as the second input of latch 400 to the second output of voltage clamp block 300, eighth transistor +.>Gate and seventh transistor->Drain connection of (a) eighth transistor->Is connected with a high-voltage power supply VDDH; seventh transistor->Also connected as a first output of latch 400 to a second input of high voltage inverter 500.
Specifically, the latch is formed of 3.3V PMOS IO transistorsAnd->Is formed by cross coupling of a gate and a drain. The first high voltage signal and the second high voltage signal are respectively transmitted through the first latchAn input end and a second input end enter a latch, and the latch judges the level of the first high-voltage signal. Taking the above example as an example, when the first high voltage signal is at a high level, the first output terminal of the latch outputs a value 1, and the value 1 is input to the high voltage inverter. Wherein the first input of the latch is also the first output.
The high voltage inverter 500 includes a ninth transistorTenth transistor->Ninth transistor->Tenth transistor->All are CMOS transistors; ninth transistor->A ninth transistor, which is connected as a first input terminal of the high voltage inverter 500 to the first output terminal of the differential input module 200>Source ground VSS, ninth transistor +.>The drain electrode of the high-voltage inverter 500 is used as the output end for outputting a high-voltage signal; tenth transistor->A tenth transistor, connected as a second input of the high voltage inverter 500 to the first output of the latch 400>A tenth transistor connected to the source of the high voltage power supply VDDH>Drain of (d) and ninth transistor->Is connected to the drain of the transistor.
Specifically, the ninth transistorA tenth transistor for receiving the first medium-low voltage signal as the first input terminal of the high voltage inverter 500>The gate of the high voltage inverter 500 receives a level state value corresponding to the first high voltage signal. Taking the above example as an example, when the first low-voltage signal is at a low level, the level state value and the first medium-low voltage signal are both at a high level, that is, both inputs of the high-voltage inverter are high-level signals, and the high-voltage low-level signal is obtained after the phase inversion process of the high-voltage inverter. The ninth transistor and the tenth transistor are 3.3V CMOS transistors, or may be higher-voltage CMOS transistors. The ninth transistor realizes a voltage pull-down function for the output signal, and the tenth transistor realizes a voltage pull-up function for the output signal.
In an alternative embodiment, the fifth transistor comprises a plurality of fifth transistors and the sixth transistor comprises a plurality of sixth transistors; the number of the plurality of fifth transistors is equal to the number of the plurality of sixth transistors.
Specifically, if a higher clamp voltage is required, for example: 1.4V, i.e. the voltage at the output end of the voltage clamping module is higher than the voltage at the input end of the voltage clamping module by 1.4V, two groups of PMOS transistor clamping circuit units, i.e. two fifth transistors, are neededAnd two sixth transistors->If a higher clamping voltage is required, for example: 2.1V, i.e. the voltage at the output of the voltage clamping module is higher than the input of the voltage clamping moduleThe voltage at the terminal is 2.1V, three groups of PMOS transistor clamp units are needed, namely three fifth transistors +>And three sixth transistors->。
In an alternative embodiment, the drain of a first fifth transistor of the plurality of fifth transistors is connected as a first input of the voltage clamp module to the first output of the differential input module, the gate of the first fifth transistor is connected to the drain of the first fifth transistor, the source of the first fifth transistor is connected to the drain of the second fifth transistor, the gate of the second fifth transistor is connected to the drain of the second fifth transistor, the source of the second fifth transistor is connected to the drain of the third fifth transistor, and so on, and the source of the last fifth transistor is connected as a first output of the voltage clamp module to the first input of the latch; the drain electrode of a first sixth transistor of the plurality of sixth transistors is connected as the second input end of the voltage clamping module to the second output end of the differential input module, the gate electrode of the first sixth transistor is connected with the drain electrode of the first sixth transistor, the source electrode of the first sixth transistor is connected with the drain electrode of the second sixth transistor, the gate electrode of the second sixth transistor is connected with the drain electrode of the second sixth transistor, the source electrode of the second sixth transistor is connected with the drain electrode of the third sixth transistor, and so on, the source electrode of the last sixth transistor is connected as the second output end of the voltage clamping module to the second input end of the latch.
A voltage clamping module including a plurality of fifth transistors and a plurality of sixth transistors is described below with reference to fig. 3.
Fig. 3 is a circuit diagram of a level shift circuit of a plurality of fifth transistors and a plurality of sixth transistors according to an embodiment of the present application.
As shown in fig. 3, the voltage clamping module 300 includes a plurality of fifth transistors and a plurality of sixth transistors,representing a first fifth transistor of the plurality of fifth transistors +.>Representing a first one of a plurality of sixth transistors,/one of the plurality of sixth transistors>Representing the last fifth transistor of the plurality of fifth transistors +.>Representing the last sixth transistor of the plurality of sixth transistors.
The first medium-low voltage signal is converted into a first high voltage signal via a plurality of fifth transistors, and the second medium-low voltage signal is converted into a second high voltage signal via a plurality of sixth transistors. The source electrode of the former fifth transistor is connected with the drain electrode of the latter fifth transistor, the source electrode of the last fifth transistor is used as a first output end of the voltage clamping module to be connected with the first input end of the latch, and a first high-voltage signal is output. The source electrode of the former sixth transistor is connected with the drain electrode of the latter sixth transistor, the source electrode of the last sixth transistor is used as a second output end of the voltage clamping module to be connected with the second input end of the latch, and a second high-voltage signal is output. For each fifth transistor, the gate of the fifth transistor is connected to the drain of the fifth transistor, and for each sixth transistor, the gate of the sixth transistor is connected to the drain of the sixth transistor.
Compared with the level shift circuit in the prior art, the self-bias voltage clamp module adopted by the application does not need to be added with a new bias circuit, and has the advantages of simple and reliable structure, small area and no static direct current power consumption. In the level shift circuit, the transistors used in the differential input module can adopt the transistors with the lower threshold voltage of 2.5V/1.8V, so that the power supply range of the VDDL is expanded downwards, the input transistors of the level shift circuit can use the IO transistors with the lower threshold voltage, the power supply range of the VDDL is expanded to be below 0.5V, the application requirement of low-voltage power supply is met, and the problem that the voltage range of the low-voltage power supply is limited in the level shift circuit is solved.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Finally, it should be noted that: the above examples are only specific embodiments of the present application, and are not intended to limit the scope of the present application, but it should be understood by those skilled in the art that the present application is not limited thereto, and that the present application is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application, and are intended to be included in the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims (10)

1. The level shift circuit with the wide voltage range is characterized by comprising a low-voltage inverter, a differential input module, a voltage clamping module, a latch and a high-voltage inverter;
the signal input end of the low-voltage inverter receives a first low-voltage signal input by an external circuit, performs phase inversion processing on the first low-voltage signal to obtain a second low-voltage signal with the opposite phase to the first low-voltage signal, and the power input end of the low-voltage inverter is connected with a low-voltage power supply;
the output end of the low-voltage inverter is connected with the input end of the differential input module, the first low-voltage signal and the second low-voltage signal are input into the differential input module, and the differential input module respectively performs phase inversion processing on the first low-voltage signal and the second low-voltage signal to obtain a first medium-low voltage signal and a second medium-low voltage signal;
the output end of the differential input module is connected with the input end of the voltage clamping module, the first medium-low voltage signal and the second medium-low voltage signal are input into the voltage clamping module, the voltage clamping module is connected with a high voltage source through the latch, the first medium-low voltage signal and the second medium-low voltage signal are respectively converted into a first high voltage signal and a second high voltage signal, the output end of the differential input module is also connected with the first input end of the high voltage inverter, and the first medium-low voltage signal is input into the high voltage inverter;
the output end of the voltage clamping module is connected with the input end of the latch, the first high-voltage signal and the second high-voltage signal are input into the latch, and the latch determines a level state value corresponding to the first high-voltage signal;
the output end of the latch is connected with the second input end of the high-voltage inverter, the level state value is input into the high-voltage inverter, and the high-voltage inverter outputs a high-voltage signal after performing phase inversion processing on the first medium-low voltage signal and the level state value.
2. The level shift circuit of claim 1, wherein the low voltage inverter comprises a first transistor and a second transistor, the first transistor and the second transistor each being CMOS transistors;
the grid electrode of the first transistor is used as a signal input end of the low-voltage inverter to be connected with an external circuit, the source electrode of the first transistor is grounded, and the drain electrode of the first transistor is connected with the drain electrode of the second transistor;
the grid electrode of the second transistor is connected with the grid electrode of the first transistor, and the source electrode of the second transistor is used as a power input end to be connected with a low-voltage power supply;
the grid electrode of the first transistor is further used as a first output end of the low-voltage inverter to be connected with a first input end of the differential input module, and the drain electrode of the first transistor is further used as a second output end of the low-voltage inverter to be connected with a second input end of the differential input module.
3. The level shift circuit of claim 1, wherein the differential input module comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor each being an NMOS transistor;
the grid electrode of the third transistor is used as a first input end of the differential input module and is connected with the first output end of the low-voltage inverter, the source electrode of the third transistor is grounded, and the drain electrode of the third transistor is used as a first output end of the differential input module and is connected with the first input end of the voltage clamping module;
the drain electrode of the third transistor is used as the first output end of the differential input module and is also connected with the first input end of the high-voltage inverter;
the grid electrode of the fourth transistor is used as the second input end of the differential input module to be connected with the second output end of the low-voltage inverter, the source electrode of the fourth transistor is grounded, and the drain electrode of the fourth transistor is used as the second output end of the differential input module to be connected with the second input end of the voltage clamping module.
4. The level shift circuit of claim 1, wherein the voltage clamp module comprises a fifth transistor and a sixth transistor, the fifth transistor and the sixth transistor each being PMOS transistors;
the drain electrode of the fifth transistor is used as a first input end of the voltage clamping module and is connected with the first output end of the differential input module, the grid electrode of the fifth transistor is connected with the drain electrode of the fifth transistor, and the source electrode of the fifth transistor is used as a first output end of the voltage clamping module and is connected with the first input end of the latch;
the drain electrode of the sixth transistor is used as the second input end of the voltage clamping module to be connected with the second output end of the differential input module, the grid electrode of the sixth transistor is connected with the drain electrode of the sixth transistor, and the source electrode of the sixth transistor is used as the second output end of the voltage clamping module to be connected with the second input end of the latch.
5. The level shift circuit of claim 1, wherein the latch comprises a seventh transistor and an eighth transistor, the seventh transistor and the eighth transistor each being PMOS transistors;
the drain electrode of the seventh transistor is used as a first input end of the latch and is connected with the first output end of the voltage clamping module, the grid electrode of the seventh transistor is connected with the drain electrode of the eighth transistor, and the source electrode of the seventh transistor is connected with a high-voltage power supply;
the drain electrode of the eighth transistor is used as a second input end of the latch and is connected with the second output end of the voltage clamping module, the grid electrode of the eighth transistor is connected with the drain electrode of the seventh transistor, and the source electrode of the eighth transistor is connected with a high-voltage power supply;
the drain of the seventh transistor is also connected as a first output of the latch to the second input of the high voltage inverter.
6. The level shift circuit of claim 1, wherein the high voltage inverter comprises a ninth transistor and a tenth transistor, both of which are CMOS transistors;
the grid electrode of the ninth transistor is used as a first input end of the high-voltage inverter and is connected with the first output end of the differential input module, the source electrode of the ninth transistor is grounded, and the drain electrode of the ninth transistor is used as an output end of the high-voltage inverter to output a high-voltage signal;
the gate of the tenth transistor is connected to the first output terminal of the latch as the second input terminal of the high voltage inverter, the source of the tenth transistor is connected to the high voltage power supply, and the drain of the tenth transistor is connected to the drain of the ninth transistor.
7. The level shift circuit of claim 4, wherein the fifth transistor comprises a plurality of fifth transistors, and the sixth transistor comprises a plurality of sixth transistors;
the number of the plurality of fifth transistors is equal to the number of the plurality of sixth transistors.
8. The level shifting circuit of claim 7, wherein a drain of a first fifth transistor of the plurality of fifth transistors is connected as a first input of the voltage clamp block to the first output of the differential input block, a gate of the first fifth transistor is connected to a drain of the first fifth transistor, a source of the first fifth transistor is connected to a drain of a second fifth transistor, a gate of the second fifth transistor is connected to a drain of the second fifth transistor, a source of the second fifth transistor is connected to a drain of a third fifth transistor, and so on, a source of a last fifth transistor is connected as a first output of the voltage clamp block to the first input of the latch;
the drain electrode of a first sixth transistor of the plurality of sixth transistors is connected as the second input end of the voltage clamping module and the second output end of the differential input module, the gate electrode of the first sixth transistor is connected with the drain electrode of the first sixth transistor, the source electrode of the first sixth transistor is connected with the drain electrode of a second sixth transistor, the gate electrode of the second sixth transistor is connected with the drain electrode of the second sixth transistor, the source electrode of the second sixth transistor is connected with the drain electrode of a third sixth transistor, and so on, and the source electrode of the last sixth transistor is connected as the second output end of the voltage clamping module and the second input end of the latch.
9. The level shift circuit of claim 4, wherein the fifth transistor and the sixth transistor are each 3.3V PMOS transistors.
10. The level shift circuit according to claim 6, wherein the ninth transistor and the tenth transistor are each 3.3V CMOS transistors.
CN202310851726.5A 2023-07-12 2023-07-12 Level shift circuit with wide voltage range Active CN116865743B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310851726.5A CN116865743B (en) 2023-07-12 2023-07-12 Level shift circuit with wide voltage range

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310851726.5A CN116865743B (en) 2023-07-12 2023-07-12 Level shift circuit with wide voltage range

Publications (2)

Publication Number Publication Date
CN116865743A true CN116865743A (en) 2023-10-10
CN116865743B CN116865743B (en) 2024-02-06

Family

ID=88235505

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310851726.5A Active CN116865743B (en) 2023-07-12 2023-07-12 Level shift circuit with wide voltage range

Country Status (1)

Country Link
CN (1) CN116865743B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1630194A (en) * 2003-12-18 2005-06-22 松下电器产业株式会社 Level shift circuit
US20070085566A1 (en) * 2005-10-19 2007-04-19 Masaaki Koto Level shift circuit
CN109391258A (en) * 2018-08-27 2019-02-26 浙江航芯源集成电路科技有限公司 Level displacement circuit based on low-voltage tube

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1630194A (en) * 2003-12-18 2005-06-22 松下电器产业株式会社 Level shift circuit
US20070085566A1 (en) * 2005-10-19 2007-04-19 Masaaki Koto Level shift circuit
CN109391258A (en) * 2018-08-27 2019-02-26 浙江航芯源集成电路科技有限公司 Level displacement circuit based on low-voltage tube

Also Published As

Publication number Publication date
CN116865743B (en) 2024-02-06

Similar Documents

Publication Publication Date Title
US6914462B2 (en) Power-on reset circuit and method
US8179160B1 (en) Input-output (I/O) circuit supporting multiple I/O logic-level swings
US20110316505A1 (en) Output Buffer With Improved Output Signal Quality
US11592856B2 (en) Switchable power supply
US6472920B1 (en) High speed latch circuit
US10367505B2 (en) Low power general purpose input/output level shifting driver
CN112929012A (en) Leakage compensation latch, data operation unit and chip
KR100211758B1 (en) Multi-power data buffer
US9203381B2 (en) Current mode logic latch
CN116865743B (en) Level shift circuit with wide voltage range
US8942053B2 (en) Generating and amplifying differential signals
KR19990009581A (en) Semiconductor circuit for generating high output voltage
US6998879B2 (en) Level determination circuit determining logic level of input signal
CN108255753B (en) I/O receiver and receiving circuit thereof
CN109861684B (en) Cross-potential level shift circuit
JP4469798B2 (en) Integrated circuit device and method for driving an output signal with the output of an inverter stage
JP4824304B2 (en) Input buffer and semiconductor device including the same
TWI840929B (en) Key storage device and key generation method
CN110739958A (en) Level conversion circuit
JP3804647B2 (en) Semiconductor integrated circuit
CN112349332B (en) Input buffer circuit and memory
US7403042B2 (en) Flip-flop, integrated circuit, and flip-flop resetting method
US20090243693A1 (en) Circuit for providing deterministic logic level in output circuit when a power supply is grounded
CN111835318B (en) Pulse generating circuit
US20230288950A1 (en) Switchable power supply

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant