CN116864582A - Method for preparing circuit on surface of solar silicon wafer - Google Patents
Method for preparing circuit on surface of solar silicon wafer Download PDFInfo
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- CN116864582A CN116864582A CN202311126757.0A CN202311126757A CN116864582A CN 116864582 A CN116864582 A CN 116864582A CN 202311126757 A CN202311126757 A CN 202311126757A CN 116864582 A CN116864582 A CN 116864582A
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- silicon wafer
- seed layer
- layer
- printing
- solar silicon
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 114
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 114
- 239000010703 silicon Substances 0.000 title claims abstract description 114
- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000000463 material Substances 0.000 claims abstract description 222
- 238000007639 printing Methods 0.000 claims abstract description 105
- 238000009713 electroplating Methods 0.000 claims abstract description 65
- 239000007788 liquid Substances 0.000 claims description 41
- 239000012943 hotmelt Substances 0.000 claims description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 17
- 239000010949 copper Substances 0.000 claims description 17
- 238000002844 melting Methods 0.000 claims description 17
- 239000007787 solid Substances 0.000 claims description 13
- 230000008018 melting Effects 0.000 claims description 11
- 238000004140 cleaning Methods 0.000 claims description 10
- 238000001816 cooling Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 239000011344 liquid material Substances 0.000 claims description 7
- 238000002791 soaking Methods 0.000 claims description 7
- 239000007921 spray Substances 0.000 claims description 7
- 238000004506 ultrasonic cleaning Methods 0.000 claims description 6
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 238000000016 photochemical curing Methods 0.000 claims description 5
- 239000011347 resin Substances 0.000 claims description 5
- 229920005989 resin Polymers 0.000 claims description 5
- 239000002904 solvent Substances 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 4
- 230000001678 irradiating effect Effects 0.000 claims description 4
- 239000002253 acid Substances 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims description 2
- 230000008023 solidification Effects 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 8
- 238000001259 photo etching Methods 0.000 abstract description 7
- 238000007747 plating Methods 0.000 description 26
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 14
- 229910052709 silver Inorganic materials 0.000 description 14
- 239000004332 silver Substances 0.000 description 14
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 9
- 238000005516 engineering process Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 238000007641 inkjet printing Methods 0.000 description 6
- 238000002360 preparation method Methods 0.000 description 6
- 239000003513 alkali Substances 0.000 description 5
- 238000001514 detection method Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 230000033001 locomotion Effects 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 4
- -1 acrylic compound Chemical class 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000003854 Surface Print Methods 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 2
- 239000007864 aqueous solution Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000031700 light absorption Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 238000005507 spraying Methods 0.000 description 2
- 229910000570 Cupronickel Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000002585 base Substances 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005868 electrolysis reaction Methods 0.000 description 1
- 238000010304 firing Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000006557 surface reaction Methods 0.000 description 1
- 238000011282 treatment Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic Table
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
- H01L31/022433—Particular geometry of the grid contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Sustainable Energy (AREA)
- Manufacturing & Machinery (AREA)
- Sustainable Development (AREA)
- Photovoltaic Devices (AREA)
Abstract
The application discloses a method for preparing a circuit on the surface of a solar silicon wafer, which comprises the following steps: setting a seed layer on the outer surface of the solar silicon wafer, printing a material A outside the seed layer to form a material A layer, and forming a circuit structure outline on the solar silicon wafer by the material A layer; printing a material B on the outer surface of the seed layer and forming a mask; the end part of the material A layer is at least partially exposed outside the mask; removing the material A layer to ensure that a growing area is reserved on the seed layer by the mask; electroplating operation is carried out on the seed layer, and electroplating materials grow in the growth area to form an electroplating line; and removing the mask and the seed layer on the seed layer to obtain the photovoltaic cell with the electroplating circuit. The application discloses a method for preparing a circuit on the surface of a solar silicon wafer, which is characterized in that an electroplating mask is manufactured in a non-photoetching mode, so that the process difficulty and the equipment cost are reduced; the circuit generated by electroplating has a comparatively ideal form, and can improve the electric energy efficiency of the photovoltaic cell.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for preparing a circuit on the surface of a solar silicon wafer.
Background
The current Heterojunction (HJT) battery preparation technology is that electrodes are printed on the surface of a silicon wafer by screen printing; the electrode material is silver electrode. The other is that the photoetching and electroplating technology are matched to realize the non-contact electrode preparation technology.
Among them, in the prior art, for example, patent application number: CN202011271814.0, patent name: a preparation method of a cast monocrystalline silicon heterojunction solar cell; the preparation process of cast monocrystalline silicon heterojunction solar cell is disclosed; the method comprises the following steps: s1, removing greasy dirt, metal particles and other impurities on the surface by using an acidic solution; s2, depositing an aluminum film on the cleaned silicon wafer by a physical vapor deposition technology; s3, depositing a layer of PSG on the surface of the silicon wafer after the aluminum film is deposited, and performing a series of annealing treatments; s4, removing the surface reaction layer and impurities from the treated silicon wafer by using a solvent; then, carrying out surface texturing on the treated silicon wafer; s5, carrying out amorphous silicon coating on the processed silicon wafer; s6, respectively generating transparent conductive film layers on the front side and the back side of the amorphous silicon film layer; and S7, forming grid line electrodes on the transparent conductive film layers on the two sides of the silicon wafer, thereby completing the manufacturing process of the heterojunction battery piece. In the prior art, the cost of silver paste for printing in a printing electrode on the surface of a silicon wafer by means of screen printing accounts for 16-24%, and the excessively high cost of silver paste becomes an important factor for limiting the industrialized popularization of the silver paste, so that the upgrading and optimizing of a metallization process are required to be explored.
The photoetching and electroplating technology is matched to realize the non-contact electrode preparation technology, namely, metal is deposited on the surface of the conductive layer by utilizing the electrolysis principle; the electroplating scheme adopted in the prior art is as follows: and (3) carrying out surface photoresist printing on HJT (heterojunction photovoltaic cell silicon wafer) with the seed layer, etching a photoresist groove (electroplating area) on HJT of the seed layer, etching the photoresist in the groove area, metallizing the etched product, removing the photoresist, and removing the seed layer to finish electroplating operation. However, the photolithographic method adopted in the prior art is used for manufacturing the copper plating mask, and the equipment cost is high.
Moreover, the heterojunction photovoltaic cell grid line is generally in a positive trapezoid shape, and the trapezoid shape can reduce the resistance between the grid lines to a certain extent, so that the efficiency of the cell is improved. In addition, the trapezoid shape can reduce reflection and improve the absorption of sunlight. In heterojunction photovoltaic cells, the gate line serves mainly two functions: firstly, the diffusion of charge carriers is limited, so that the service life of the carriers is prolonged, and the efficiency of a battery is improved; and secondly, the current is led out through the connection of the grid line with the anode and the cathode. In both of these effects, electrons are a critical factor. If the width of the gate lines is too narrow, the resistance between the gate lines increases, resulting in an increase in current flow resistance, affecting the output of the battery.
Therefore, the width of the grid line can be gradually widened from the top to the bottom by adopting the positive trapezoid shape, and the lower bottom of the positive trapezoid is tightly contacted with the battery piece, so that the contact resistance is reduced; the positive trapezoid shape can also reduce the reflection on the surface of the battery piece, enhance the light absorption efficiency and improve the efficiency of the battery. In addition, the patterned mask is directly manufactured, the grid line groove formed by the mask is used for electroplating, and the grid line is in an inverted trapezoid shape after electroplating, so that the requirement of a positive trapezoid shape of the grid line cannot be met.
Disclosure of Invention
The application overcomes the defects of the prior art, provides a method for preparing a circuit on the surface of a solar silicon wafer, and adopts a non-photoetching mode to manufacture an electroplating mask, thereby reducing the process difficulty and the equipment cost, reducing the contact resistance and improving the efficiency of a battery.
In order to achieve the above purpose, the application adopts the following technical scheme: a method for preparing a circuit on the surface of a solar silicon wafer comprises the following steps:
step S1, a solar silicon wafer is obtained, a seed layer is arranged on the outer surface of the solar silicon wafer, a material A is printed outside the seed layer to form a material A layer, and the material A layer forms a line structure outline on the solar silicon wafer;
step S2, printing a material B on the outer surface of the seed layer of the solar silicon wafer processed in the step S1 by using a jet printing method, and forming a mask on the outer surface of the seed layer of the solar silicon wafer while avoiding the material A layer; the mask is attached to the periphery of the outer peripheral surface of the material A layer, and the end part of the material A layer is at least partially exposed outside the mask;
step S3, removing the material A layer on the seed layer processed in the step S2, and reserving a growth area on the seed layer by using a mask;
step S4, electroplating operation is carried out on the seed layer processed in the step S3, electroplating materials grow on the seed layer uncovered by the mask, and an electroplating line is formed in the growth area;
and S5, removing the mask on the seed layer subjected to electroplating in the step S4 and the seed layer below the mask to obtain the photovoltaic cell with the electroplating circuit.
In a preferred scheme of the application, the material A adopted by the material A layer is a hot-melting material; material a is in a liquid state when printed, and is cooled to a solid state after being printed and deposited on the seed layer.
In a preferred scheme of the application, the material A is one of a mixture of resin and hot melt wax, the hot melt wax and the resin, the melting point of the hot melt material is 50-80 ℃, the viscosity range is 8.0-13 mPas when the temperature of the material A is 85-100 ℃, and the surface tension is 28-32 dyn/cm.
In a preferred scheme of the application, in the step S1, the solar silicon wafer and the silicon wafer carrier are cooled by using a cooling device, liquid drops of the hot-melt material printed on the seed layer on the outer surface of the solar silicon wafer are cooled, and the form of the material A sprayed on the seed layer of the solar silicon wafer is adjusted by adjusting the solidification speed of the liquid drops.
In a preferred scheme of the application, in the step S1, the surface temperature of a printing nozzle in a jet printing method is controlled to be 80-110 ℃, and the printing speed of the printing nozzle is controlled to be 30-80 mm/S; the printing width of the material A printed by the printing nozzle at one time is 10-50 mu m; the printing height of the material A layer printed by the printing nozzle is 10-30 mu m; and printing for a plurality of times through the printing spray head, and stacking hot-melting materials sprayed by the printing spray head to control and adjust the printing height of the material A layer.
Specifically, the material A layer is widest at the bottom of the profile substrate formed by the solar silicon wafer, and gradually narrows along with the increase of the thickness of the material, and is similar to a positive trapezoid shape.
Specifically, the low temperature control range of the surface of the solar silicon wafer is 0-20 ℃. The material A is printed in a graphical printing mode, namely, the printing pattern is an electroplating circuit pattern, and the area outside the electroplating circuit is not printed.
In a preferred scheme of the application, for the material B in the step S2 which is a liquid material during or before printing, the material B is printed on the surface of the seed layer to form a liquid film, and the thickness of the liquid film is 10-20 mu m; and the material B is an acrylic photo-curing compound, and the liquid film is cured by irradiating the liquid film with ultraviolet light to form a solid mask, wherein the thickness of the solid mask is 10-20 mu m.
Specifically, the material B adopts an acrylic compound, has photosensitive property, and is sprayed by an ink-jet printing mode to form a liquid film with the thickness of 10-20 mu m; for the already printed material a layer, the printing position of the material B is controlled such that the material B falls on both sides of the already printed material a layer without covering the top of the material a layer. The specific control mode is as follows: the material B is molded in a pattern printing mode; the printing area is an area except for an electroplating circuit on the surface of the solar silicon wafer, and the front surface of the solar silicon wafer is set as the printing area; the circuit pattern printed in the step S1 is overlapped on a printing area of the material B and is set as a non-printing area; by making a printed pattern of material B in this way, it can be ensured that material B does not cover the top of the layer of material a.
In a preferred scheme of the application, in the step S3, the material A layer is removed by blowing and cleaning with hot air at a temperature of more than 100 ℃ or soaking and cleaning with alkaline liquid or ultrasonic cleaning.
Specifically, in the multiple removal mode of the material A layer, hot air with the temperature of 200-400 ℃ is adopted, or alkali liquor with the concentration of 0.5-5% is selected for cleaning, or ultrasonic cleaning is adopted, so that the material A layer on the seed layer is removed, and a mask with a channel shape with a circuit structure outline is obtained.
In a preferred scheme of the application, in the step S5, a mask on the seed layer is removed by adopting an alkaline liquid soaking cleaning or ultrasonic cleaning mode; wherein the alkali concentration of the alkaline liquid is more than 10%.
In a preferred embodiment of the present application, the solar silicon wafer after electroplating in step S5 is etched to remove the seed layer on the surface of the solar silicon wafer.
In a preferred scheme of the application, the solar silicon wafer after being electroplated in the step S5 is etched by adopting an acid solvent; the electroplating circuit is etched to have the same thickness as the copper seed layer, so that the surface electroplating circuit of the heterojunction battery is obtained, and the electroplating circuit is in a positive trapezoid shape with narrow upper part and wide lower part.
In a preferred embodiment of the application, the melting point of the mask is higher than the melting point of material A;
or/and, the seed layer is a copper seed layer;
or/and, the electroplating line is a copper electroplating line;
alternatively or additionally, the mask is an insulating layer.
The application solves the defects existing in the background technology:
the non-photoetching method disclosed by the application is used for manufacturing the electroplating mask, so that the process difficulty and the equipment cost are reduced; the circuit electroplated by the method has a more ideal form, and can improve the efficiency of the photovoltaic cell.
The shape of the electroplating line is a positive trapezoid, so that the width of the grid line can be gradually widened from the top to the bottom, the lower bottom of the positive trapezoid is in close contact with the battery piece, and the contact resistance is reduced; the positive trapezoid shape can also reduce the reflection on the surface of the battery piece, enhance the light absorption efficiency and improve the efficiency of the battery.
Drawings
The application will be further described with reference to the drawings and examples.
FIG. 1 is a process flow diagram corresponding to a preferred embodiment of the present application;
FIG. 2 is a schematic diagram of a seed layer disposed on a solar wafer in step S1 according to a preferred embodiment of the present application;
FIG. 3 is a schematic view of a layer of material A corresponding to the outline of the circuit structure formed by spraying material A on the seed layer disposed on the solar silicon wafer in step S1 in the preferred embodiment of the present application;
FIG. 4 is a schematic diagram of spraying material B on the seed layer to mask the seed layer from the line structure profile in step S2 according to the preferred embodiment of the present application;
FIG. 5 is a schematic diagram of a mask with a channel shape having a line structure profile, which corresponds to a preferred embodiment of the present application, wherein a growth region is reserved on a seed layer after removing a layer A of material sprayed on the seed layer in step S3;
FIG. 6 is a schematic diagram of a plating line for electroplating growth in a trench with a line structure profile formed in a mask corresponding to the growth region reserved on the seed layer in step S4 in a preferred embodiment of the present application;
FIG. 7 is a schematic diagram of the preferred embodiment of the present application after removal of a mask corresponding to the outer periphery of the plated line on the seed layer in step S5;
FIG. 8 is a schematic diagram of the preferred embodiment of the present application after the seed layer is removed in step S5;
FIG. 9 is a photograph of profile generation and height measurement for lines of material A layer of a solar wafer surface using Olympus LEXT 3D MEASURING LASER MICROSCOPE OLS5000 in accordance with a preferred embodiment of the application;
FIG. 10 is a scan of local sample detection in layer A of material corresponding to the surface of a solar wafer in a preferred embodiment of the present application;
FIG. 11 is a detection scan corresponding to FIG. 10;
FIG. 12 is a cross-sectional view of the line of the corresponding material A layer of FIG. 10;
FIG. 13 is a photograph of a printed hot melt material line on the surface of a solar silicon wafer with a seed layer in accordance with a preferred embodiment of the present application;
FIG. 14 is a photomicrograph of lines corresponding to the formation of a layer of material A on the surface of a seed layer of a silicon wafer by a hot melt material in a preferred embodiment of the application;
FIG. 15 is a line width measurement plot of material A layer in a photomicrograph of lines corresponding to the formation of material A layer by hot melt material on the surface of a silicon wafer seed layer in a preferred embodiment of the present application;
FIG. 16 generates line width tests at different print speeds;
FIG. 17 generates line width tests for different stage surface temperatures;
FIG. 18 is a profile of a low viscosity material silicon wafer surface print interval of five minutes;
FIG. 19 is a profile view of a low viscosity material wafer surface after being left to stand for thirty minutes after being printed;
FIG. 20 is a table of parameter information for the formation of a low temperature silver paste of a higher viscosity liquid on the surface of a silicon wafer;
in the figure, 1-solar silicon wafer, 2-seed layer, 3-material A layer, 4-mask, 5-growth area and 6-electroplating line.
Detailed Description
The application will now be described in further detail with reference to the drawings and examples, which are simplified schematic illustrations of the basic structure of the application, which are presented only by way of illustration, and thus show only the structures that are relevant to the application.
Example 1
As shown in fig. 1-8, a method for preparing a circuit on the surface of a solar silicon wafer comprises the following steps:
step S1, a solar silicon wafer 1 is obtained, a seed layer 2 is arranged on the outer surface of the solar silicon wafer 1 as shown in FIG. 2, a material A layer 3 is formed by printing a material A on the outer surface of the seed layer 2 as shown in FIG. 3, and a line structure outline is formed on the solar silicon wafer 1 by the material A layer 3.
The material A adopted by the material A layer 3 is a hot-melting material; material a layer 3 is in a liquid state when printed, and material a is deposited on seed layer 2 in a solid state when printed. The melting point of the hot-melt material is 50-100 ℃; in this embodiment, the melting point of the preferred hot-melt material is 60-80 ℃. The hot-melt material is selected from hot-melt wax, but not limited thereto, and in other embodiments, other hot-melt materials meeting the melting point requirement in the prior art may be selected according to actual use requirements.
Further, the solar silicon wafer 1 is cooled by a cooling device, and the cooling speed of the material A layer 3 sprayed on the seed layer 2 of the solar silicon wafer 1 is controlled by low temperature. The temperature of a silicon wafer carrier in a jet printing method is controlled to be 10-15 ℃ through cooling equipment, the surface temperature of a printing spray head is controlled to be 80-110 ℃ in the preparation process, the temperature of the printing spray head is preferably 100 ℃ in the embodiment, and the printing speed of the printing spray head is 30-80 mm/s; the printing width of the material A printed by the printing nozzle is 10-50 mu m; the printing height of the material A printed by the printing nozzle is 10-30 mu m, and the profile of the material A layer 3 formed on the solar silicon wafer 1 is similar to a trapezoid shape. The printing speed (i.e. the speed of the printing movement of the printing head) and the physical spacing between adjacent material a drops ejected by the printing head have the following relationship: s=f x; where s is the speed of the printing movement, f is the firing frequency of the nozzle, and x is the physical spacing between adjacent material A drops ejected by the printing nozzle; the speed s of the printing movement is a device motion control system parameter, and x is a nozzle control system parameter; and adjusting the printing height and the printing width of the material A printed by the printing nozzle by carrying out the adaptive adjustment of the two parameters s and x within the maximum emission frequency range of the nozzle. FIG. 9 is a photograph of profile generation and height measurement for lines of material A layer of a solar wafer surface using Olympus LEXT 3D MEASURING LASER MICROSCOPE OLS5000 in accordance with a preferred embodiment of the application; as can be seen from the measurement graph, the line height is 17.9 micrometers, and the width is 20-24 micrometers (the unit micrometers of the bottom scale, and each cell is 8 micrometers); FIG. 10 is a scan of local sample detection in layer A of material corresponding to the surface of a solar wafer in a preferred embodiment of the present application; FIG. 11 is a detection scan corresponding to FIG. 10; fig. 12 is a cross-sectional view of a line of the material a layer corresponding to fig. 10, wherein the horizontal axis corresponds to the Y-axis direction in fig. 10, and the vertical axis corresponds to the Z-axis direction in fig. 10, and in order to facilitate the display of an image of the height of the cross section, a scale of the horizontal axis and a scale of the vertical axis having different scale units are selected in the scanning pattern during the detection. The height value of the detected Z axis was 17.933. Mu.m. FIG. 13 is a photograph of a printed hot melt material line on the surface of a solar silicon wafer with a seed layer in accordance with a preferred embodiment of the present application, wherein the arrow indicates the printed hot melt material line; FIG. 14 is a photomicrograph of lines corresponding to the formation of a layer of material A on the surface of a seed layer of a silicon wafer by a hot melt material in a preferred embodiment of the application; fig. 15 is a microscopic sample photograph of a line width measurement chart of a material a layer (the line width of the material a printed on the surface of the silicon seed layer is 21-22 μm) corresponding to the line of the material a layer formed by the hot-melt material on the surface of the silicon seed layer in the preferred embodiment of the present application.
The hot melt material may be one of a hot melt wax, a mixture of a hot melt wax and a resin. In this example, a hot melt wax was used. And the viscosity of the hot-melt material is within the temperature range of 85-100 ℃:8.0 to 13.0 mPas. Further, the surface tension is 28 to 32dyn/cm; the viscosity at 85 ℃ is: 8.0-10.5 mPas; the surface tension at 85 ℃ is: 28-32 dyn/cm.
The surface of the silicon wafer is an ITO conductive layer (Indium Tin Oxide), the surface shape is a micro pyramid structure with the height of 1 mu m, and when the ITO surface is treated by Plasma gas (Plasma), the surface energy is more than 72mN/cm. When the liquid material is printed on the surface of the silicon wafer, the surface energy of the silicon wafer is far greater than the surface tension of the liquid material, so that the diffusion phenomenon of the material is obvious, the line profile can not be maintained, and the following is the practical effect of printing on the surface of the silicon wafer by using high-viscosity liquid and low-viscosity liquid. Fig. 16 generates a line width test plot at different print speeds, and fig. 17 generates a line width test plot at different stage surface temperatures.
And under the condition that the peripheral printing environments are the same, using materials with different viscosities to perform post-printing contour forming effect test:
in comparative example one, the surface of a silicon wafer of low viscosity glue (acrylic optical glue) for ink-jet printing is actually represented as follows: viscosity 13 Centipoise (CP), width 0.5mm after printing on silicon wafer surface, gradual spreading glue profile cannot be maintained, and glue thickness cannot be measured for characterization; the conventional liquid ink jet printing material cannot be molded on the surface of a silicon wafer, and is actually shown in fig. 18 and 19. FIG. 18 is a profile view of a low viscosity material silicon wafer surface print interval of five minutes; fig. 19 is a profile view of a low viscosity material wafer surface printed and then left to stand for thirty minutes. It can be seen that the profile of the low viscosity material after printing to the surface of the solar wafer is not maintained.
In the second comparative example, the printing effect of high-viscosity fluid on the surface of a silicon wafer is compared by using an electrofluidic printing mode;
the printing material selected by the material A is low-temperature solidified silver paste with the viscosity of 10000CP at the temperature of 25 ℃, and the low-temperature silver paste of the liquid with higher viscosity is molded on the surface of the silicon wafer.
The printing material selected in comparative example two had a material viscosity of about 10000CP at 25 c, as shown in fig. 20, and the aspect ratio of the material could not be controlled effectively with a higher viscosity material, i.e., low temperature silver paste. It is also worth noting that the viscosity (room temperature) of the material for inkjet printing in the prior art is 7-15 cp. In this embodiment, when printing is performed, even if low-temperature silver paste with viscosity far higher than that of a common printing material is selected, the aspect ratio of the material cannot be effectively controlled.
The viscosity of the selected hot-melt material at the heating temperature is suitable for ink-jet printing, and when the hot-melt material contacts the surface of the silicon wafer, the liquid material is subjected to phase change and is converted into a solid state, so that the shape of the printing material on the surface of the silicon wafer is kept.
Step S2, printing a material B on the outer surface of the seed layer 2 of the solar silicon wafer 1 processed in the step S1 by using a jet printing method, wherein the material B is printed on the outer surface of the seed layer 2 of the solar silicon wafer 1 and forms a mask 4 avoiding the material A layer as shown in FIG. 4; the mask 4 is attached around the outer peripheral surface of the material a layer 3, and the end portion of the material a layer 3 is at least partially exposed outside the mask 4. Specifically, the melting point of the material of the mask 4 is higher than that of the material a.
Specifically, for the material B in the step S2 being a liquid material during or before printing, the material B forms a liquid film after being printed on the surface of the seed layer 2, and the thickness of the liquid film is 10-20 μm; the material B is an acrylic photo-curing compound, the liquid film is cured by irradiating the liquid film with ultraviolet light to form a solid mask 4, and the thickness of the solid mask 4 is 10-20 mu m.
Further, it is preferable that the width range after one printing of the material a is: width 20~40 mu m, high scope: 15-30 μm; the aspect ratio of the printed lines is typically 70-90%.
Further, it is preferable that the layer thickness of the material B ranges: setting according to the height of the material A layer 3, wherein the thickness is set to be 70% -85% of the height of the material A layer 3; after printing the material B, removing the material A by a chemical or physical means, wherein the depth of a formed groove is 49% -77% of the width of the material A (namely, the line height-width ratio of the material A layer is 70% -90%, the printing thickness of the material B is 70% -85% of the height of the material A layer 3, the depth of the groove is about 49% -77% of the width of the material A layer 3), and the internal contour form of the groove is the same as the contour form of the line after printing the hot-melt material. Through the electroplating process, the plating layer grows along the inner contour of the groove, the inner contour of the groove is consistent with the contour of the line printed by the material A, the thickness of the copper plating layer growing is controlled to be 35-50% of the width of the line of the material A, and the electroplating line with the aspect ratio of 35-50% can be obtained.
In step S3, the material a layer 3 on the seed layer 2 processed in step S2 is removed, and as shown in fig. 5, a growth area 5 is reserved on the seed layer 2 by the mask 4.
Further, the material A layer 3 is removed by selecting hot air at 200-400 ℃, or alkali liquor with concentration of 0.5-5% or ultrasonic cleaning, so that the material A on the seed layer is removed, and a mask with a channel shape with a line structure outline is obtained.
Specifically, in this embodiment, the material a layer 3 is removed by immersing the material a layer 3 on the seed layer 2 in a 4% aqueous solution of potassium hydroxide at 50 ℃ for 50s or more, and then cleaning the material a layer with ultrasonic waves for 10s or more, thereby obtaining the mask 4 having the channel shape with the outline of the circuit structure.
Step S4, performing an electroplating operation on the seed layer 2 processed in step S3, as shown in fig. 6, an electroplating material grows in a growth area 5 uncovered by the mask 4, and an electroplating line 6 is formed in the growth area 5.
Step S5, as shown in FIG. 7 and FIG. 8, the mask 4 on the solar silicon wafer 1 which is subjected to electroplating in the step S4 and the seed layer 2 below the mask are removed, and the photovoltaic cell with the electroplating line 6 shown in FIG. 8 is obtained.
Specifically, in this embodiment, the mask 4 on the seed layer 2 is removed by cleaning or soaking with an alkaline liquid. The concentration of the alkali liquor in the alkaline liquid is more than 10 percent.
Further, the solar silicon wafer 1 after electroplating in step S5 is etched to remove the seed layer 2 on the surface of the solar silicon wafer 1. In the embodiment, an acidic solvent is adopted to etch the solar silicon wafer 1 after electroplating in the step S5; the plated circuit 6 is etched to the same thickness as the copper seed layer 2, and the plated circuit 6 on the surface of the heterojunction cell (HJT) is obtained, so that the shape of the plated circuit 6 is a positive trapezoid shape with a narrow top and a wide bottom.
Example two
On the basis of the first embodiment, as shown in fig. 1 to 8, a method for forming a circuit on the surface of a solar silicon wafer 1 includes the following steps:
step S1, a solar silicon wafer 1 is obtained, a seed layer 2 is arranged on the outer surface of the solar silicon wafer 1, a material A is printed on the outer surface of the seed layer 2 to form a material A layer 3, and the material A layer 3 forms a line structure outline on the solar silicon wafer 1.
The material A adopted by the material A layer 3 is a hot-melting material; the material a is in a liquid state at the time of printing, and the material a is deposited on the seed layer 2 in a solid state at the time of printing. In the embodiment, the material A adopts hot melt wax, and the melting point of the hot melt wax is 50-80 ℃.
Further, the solar silicon wafer 1 is cooled by a cooling device, and the cooling speed of the material A layer 3 sprayed on the seed layer 2 of the solar silicon wafer 1 is controlled by the temperature difference between the silicon wafer and the drip liquid on the material A. Controlling the temperature and the surface temperature of a silicon wafer carrying platform in a jet printing method to be 10-15 ℃ through cooling equipment, wherein the temperature of a printing nozzle is 100 ℃, and the printing speed of the printing nozzle is 50mm/s; the printing width of the material A printed by the printing nozzle is 20-25 mu m; the printing height of the material A printed by the printing nozzle is 18-22 mu m, and the outline of the material A layer 3 formed on the solar silicon wafer 1 is similar to a trapezoid shape. Fig. 16 and 17 illustrate the trend of impact of different printing speeds and different wafer stage temperatures on the printed linewidth of the hot melt material.
Step S2, printing a material B on the outer surface of the seed layer 2 of the solar silicon wafer 1 processed in the step S1 by using a jet printing method, wherein the material B is printed on the outer surface of the seed layer 2 of the solar silicon wafer 1 and forms a mask 4 avoiding the material A layer; the mask 4 is attached around the outer peripheral surface of the material a layer 3, and the end portion of the material a layer 3 is at least partially exposed outside the mask 4. Specifically, the melting point of the material of the mask 4 is higher than that of the material a.
Specifically, for the material B in the step S2 that is a liquid material during or before printing, a liquid film is formed after the material B is printed on the surface of the seed layer 2, where the thickness of the liquid film is 12-15 μm; the material B is an acrylic photo-curing compound, the liquid film is cured by irradiating the liquid film with ultraviolet light to form a solid mask 4, the thickness of the solid mask 4 is 11-14 mu m, the photo-curing material generally has 3-8% curing shrinkage rate, and the thickness of the liquid film is controlled according to the actual shrinkage rate.
Specifically, the material B adopts an acrylic compound, has photosensitive property, and is sprayed by an ink-jet printing mode to form a liquid film with the thickness of 12-15 mu m; for the already printed material a layer 3, the printing position of the material B is controlled such that the material B falls on both sides of the already printed material a layer 3 without covering the top of the material a layer 3. The specific control mode is as follows: the material B is molded in a pattern printing mode; the printing area is an area except for an electroplating circuit on the surface of the silicon wafer, and the front surface of the solar silicon wafer 1 is set as the printing area; the circuit pattern printed in the step S1 is overlapped on a printing area of the material B and is set as a non-printing area; by making a printed pattern of material B in this way, it can be ensured that material B does not cover the top of material a layer 3.
And step S3, removing the material A layer 3 on the seed layer 2 processed in the step S2, so that a growth area 5 is reserved on the seed layer 2 by the mask 4.
Specifically, the material A layer 3 is removed by soaking in a KOH (potassium hydroxide) aqueous solution with a concentration of 2-4% at a temperature of 30-60 ℃ to obtain a channel-shaped mask 4 with a circuit structure profile.
And step S4, electroplating operation is carried out on the seed layer 2 processed in the step S3, electroplating material grows in the growth area 5 which is not covered by the mask 4, and an electroplating line 6 is formed in the growth area 5. When the thickness of the electroplating coating is smaller than that of the mask 4, the coating grows along the bottom of the groove of the mask 4 towards the surface of the mask 4; when the thickness of the plating layer exceeds the thickness of the mask 4 layer, the plating layer grows in the semicircular direction by taking the groove as the center of a circle, and the growth thickness of the plating layer needs to be controlled so that the thickness of the plating layer is smaller than or equal to the thickness of the mask 4 layer.
And S5, removing the mask 4 and the seed layer 2 below the mask on the solar silicon wafer 1 subjected to electroplating in the step S4 to obtain the photovoltaic cell with the electroplating circuit 6.
Specifically, in this embodiment, the mask 4 on the seed layer 2 is removed by cleaning with an alkaline liquid or soaking in an ultrasonic pool. The alkali concentration of the alkaline liquid is more than 10%.
Further, the solar silicon wafer 1 electroplated in step S5 is etched to remove the seed layer 2 on the surface of the solar silicon wafer 1. In the embodiment, etching the solar silicon wafer 1 electroplated in the step S5 by adopting an acid solvent; the seed layer 2 outside the plating area is etched away, the surface of the plating line 6 is also etched away to the same thickness, and the plating line 6 on the surface of the heterojunction battery (HJT) is obtained, and the shape of the plating line 6 is approximately trapezoidal. The width of the plating line 6 is 20 to 25 μm, the height is 10 to 15 μm, and the aspect ratio is 35 to 50%. The current collecting capacity of the grid line of the photovoltaic cell is strong in correlation with the resistance of the line, and the higher the height is, the larger the cross-sectional area is, and the smaller the resistance of the lead is; when the height-width ratio exceeds 50%, the supporting force of the lead is insufficient, and the lead is easy to deform or break after being pressed. The thickness of the plating layer growth is controlled, and the circuit with proper height-width ratio can be obtained.
Example III
On the basis of the second embodiment, the heterojunction battery (HJT) has a structure of a double-sided electroplating circuit, and the difference is that the second embodiment discloses a single-sided electroplating condition, and the second embodiment adopts the electroplating mode to perform double-sided electroplating operation.
Example IV
The difference is that the seed layer 2 is a copper seed layer based on the first embodiment; the plating line 6 is selected from copper plating lines which are grown by a plating material, i.e., copper plating material, in a growth region 5 on the copper seed layer not covered by the mask 4, and the plating line 6 is formed in the growth region 5. However, in other embodiments, the seed layer 2 may be made of pure copper or copper-nickel alloy, and the plating line 6 may be made of a material consistent with that of the seed layer 2.
Working principle:
according to the method for forming the circuit on the surface of the solar silicon wafer 1, the seed layer 2 is used as a base layer for electroplating growth, and the optimal state of the electroplated circuit 6 needs to be approximately in a regular trapezoid shape, so that the circuit structure cannot be ensured to be in an approximately trapezoid shape by adopting the screen printing low-temperature silver paste technology in the prior art for preparing the circuit. In the application, the material A layer 3 is printed on the seed layer 2 through the material A layer 3, then the material B is printed on the seed layer 2, the mask 4 is formed on the periphery of the material A layer 3 on the seed layer 2, and the mask 4 with the channel shape of the line structure outline is displayed through removing the material A layer 3. The plating line 6 on the surface of the heterojunction cell (HJT) is obtained by performing plating growth on the seed layer 2 where the material B is not covered, etching the seed layer 2 outside the plating region, and etching the same thickness on the surface of the plating line 6, whereby the shape of the plating line 6 is approximately trapezoidal. The application successfully realizes the change from silver to copper of the solar grid line, greatly reduces the forming cost of the grid line on the solar surface, and further reduces the cost of the solar silicon wafer 1; the simple physical process is used for replacing photoresist photoetching equipment, so that the electroplating cost of a silicon wafer circuit is reduced. The plating mask 4 is manufactured in a non-photoetching mode, so that the process difficulty and the equipment cost are reduced; the circuit electroplated by the method has a more ideal form, the aspect ratio can reach 35-45%, and the efficiency of the photovoltaic cell can be improved.
The circuit electroplated and generated by the method for realizing circuit forming on the surface of the solar silicon wafer 1 has a relatively ideal circuit shape, and compared with the existing screen printing low-temperature silver paste technology, the method can improve the electric energy efficiency of a photovoltaic cell. The resistivity of the current low-temperature silver paste cured circuit is 3-10 mu omega/cm. The resistivity of the electroplated pure copper grid line prepared by the method is 1.7 mu omega/cm. Compared with the grid lines with the same length in the lines prepared by the prior art, the resistance of the electroplated copper line is lower than that of the low-temperature silver paste line, and the current collecting capacity is enhanced.
In view of the foregoing, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the spirit and scope of the application. The technical scope of the present application is not limited to the description, but must be determined according to the scope of claims.
Claims (10)
1. The method for preparing the circuit on the surface of the solar silicon wafer is characterized by comprising the following steps of:
step S1, a solar silicon wafer is obtained, a seed layer is arranged on the outer surface of the solar silicon wafer, a material A layer is formed by printing a material A outside the seed layer, and a line structure outline is formed on the solar silicon wafer by the material A layer;
step S2, printing a material B on the outer surface of the seed layer of the solar silicon wafer processed in the step S1 by using a jet printing method, and forming a mask on the outer surface of the seed layer of the solar silicon wafer while avoiding the material A layer; the mask is attached to the periphery of the outer peripheral surface of the material A layer, and the end part of the material A layer is at least partially exposed outside the mask;
step S3, removing the material A layer on the seed layer processed in the step S2, and reserving a growth area on the seed layer by the mask;
step S4, electroplating operation is carried out on the seed layer processed in the step S3, electroplating materials are grown on the seed layer uncovered by the mask, and an electroplating line is formed in the growth area;
and S5, removing the mask on the seed layer subjected to electroplating in the step S4 and the seed layer below the mask to obtain the photovoltaic cell with the electroplating circuit.
2. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 1, wherein the method comprises the following steps: the material A is a hot-melting material; the material A is in a liquid state during printing, and is cooled to be solid after being deposited on the seed layer through printing.
3. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 2, wherein the method comprises the following steps: the material A is one of a mixture of resin and hot melt wax, the hot melt wax and the resin, the melting point of the hot melt material is 50-80 ℃, the viscosity range is 8.0-13 mPas when the temperature of the material A is 85-100 ℃, and the surface tension is 28-32 dyn/cm.
4. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 1, wherein the method comprises the following steps: in step S1, the solar silicon wafer and the silicon wafer carrier are cooled by using a cooling device, droplets of the hot-melt material printed on the seed layer on the outer surface of the solar silicon wafer are cooled, and the form of the material a sprayed on the seed layer of the solar silicon wafer is adjusted by adjusting the solidification speed of the droplets.
5. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 4, wherein the method comprises the following steps: in the step S1, controlling the surface temperature of a printing nozzle in the jet printing method to be 80-110 ℃, wherein the printing speed of the printing nozzle is 30-80 mm/S; the printing width of the material A printed by the printing nozzle at one time is 10-50 mu m; the printing height of the material A layer printed by the printing nozzle is 10-30 mu m;
and printing for a plurality of times through the printing spray head, and stacking hot-melting materials sprayed by the printing spray head to control and adjust the printing height of the material A layer.
6. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 1, wherein the method comprises the following steps: in the step S2, the material B is a liquid material during or before printing, a liquid film is formed after the material B is printed on the surface of the seed layer, and the thickness of the liquid film is 10-20 mu m;
and the material B is an acrylic photo-curing compound, the liquid film is cured by irradiating the liquid film with ultraviolet light, and a solid mask is formed, wherein the thickness of the solid mask is 10-20 mu m.
7. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 1, wherein the method comprises the following steps: in the step S3, the material layer a is removed by cleaning with hot air at a temperature above 100 ℃, or by soaking and cleaning with alkaline liquid or ultrasonic cleaning.
8. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 1, wherein the method comprises the following steps: in the step S5, removing the mask on the seed layer by using an alkaline liquid soaking cleaning or ultrasonic cleaning mode; wherein the concentration of the alkaline liquid adopted is more than 10 percent;
or/and etching the solar silicon wafer electroplated in the step S5 to remove the seed layer on the surface of the solar silicon wafer.
9. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 8, wherein the method comprises the following steps: etching the solar silicon wafer after electroplating in the step S5 by adopting an acid solvent; the electroplating circuit is etched to have the same thickness as the copper seed layer, so that the surface electroplating circuit of the heterojunction battery is obtained, and the electroplating circuit is in a positive trapezoid shape with narrow upper part and wide lower part.
10. The method for preparing a circuit on the surface of a solar silicon wafer according to claim 1, wherein the method comprises the following steps: the melting point of the mask is higher than that of the material A;
or/and, the seed layer is a copper seed layer;
or/and, the electroplating line is a copper electroplating line;
or/and, the mask is an insulating layer.
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| CN108257854A (en) * | 2017-09-27 | 2018-07-06 | 苏州太阳井新能源有限公司 | A kind of manufacturing method of patterned mask |
| CN113013295A (en) * | 2021-03-02 | 2021-06-22 | 苏州太阳井新能源有限公司 | Electrode manufacturing method for preventing edge short circuit of photovoltaic cell and photovoltaic cell formed by method |
| CN113130671A (en) * | 2019-12-30 | 2021-07-16 | 国家电投集团科学技术研究院有限公司 | Silicon heterojunction solar cell and preparation method thereof |
| WO2022184038A1 (en) * | 2021-03-02 | 2022-09-09 | 苏州太阳井新能源有限公司 | Manufacturing method for electrode of photovoltaic cell, and photovoltaic cell |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108257854A (en) * | 2017-09-27 | 2018-07-06 | 苏州太阳井新能源有限公司 | A kind of manufacturing method of patterned mask |
| CN113130671A (en) * | 2019-12-30 | 2021-07-16 | 国家电投集团科学技术研究院有限公司 | Silicon heterojunction solar cell and preparation method thereof |
| CN113013295A (en) * | 2021-03-02 | 2021-06-22 | 苏州太阳井新能源有限公司 | Electrode manufacturing method for preventing edge short circuit of photovoltaic cell and photovoltaic cell formed by method |
| WO2022184038A1 (en) * | 2021-03-02 | 2022-09-09 | 苏州太阳井新能源有限公司 | Manufacturing method for electrode of photovoltaic cell, and photovoltaic cell |
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