CN116863978A

CN116863978A - Controller, control method and related equipment for ferroelectric memory array

Info

Publication number: CN116863978A
Application number: CN202210304392.5A
Authority: CN
Inventors: 李�昊; 贾秀峰; 张敏; 杨喜超; 张恒; 吕杭炳; 许俊豪
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-03-26
Filing date: 2022-03-26
Publication date: 2023-10-10
Also published as: WO2023185254A1

Abstract

The application provides a controller, a control method and related equipment of a ferroelectric memory array, wherein the controller is used for controlling the ferroelectric memory array, and the ferroelectric memory array comprises a plurality of ferroelectric memory units deployed in an array; the controller is used for writing first data into each storage unit in the target row when a full selection conduction level is input to a first WL (WL) connected with each storage unit in the target row and a transmission level of a PL (programmable logic) input connected with each storage unit is smaller than 0; the controller is further configured to, when a WL input chip select power is turned on to each of the memory cells in the target row, input a transfer level to BL and PL connected to each of the memory cells in the target row, and write second data to the target memory cell. By adopting the method and the device, the data can be written into the storage unit when the transmission level is lower, the controller is prevented from interfering the data stored in the non-target storage unit when the data is written into the target storage unit, and the storage density of the data storage is improved.

Description

Controller, control method and related equipment for ferroelectric memory array

Technical Field

The present application relates to the field of power electronics, and in particular, to a controller, a control method, and related devices for a ferroelectric memory array.

Background

In the field of power electronics technology, the controller may apply a read-write voltage to the ferroelectric memory cell after turning on the ferroelectric memory cell so that the ferroelectric memory cell is polarized, and store different data by using different polarization directions of the ferroelectric memory cell. However, in the course of data storage, in order to change the polarization direction of the ferroelectric memory cell, a large read-write voltage needs to be applied to the ferroelectric memory cell. The inventors of the present application have found during research and practice that in the prior art, the read/write voltage in a ferroelectric memory cell is related to the transmission level that the ferroelectric memory cell can withstand, and that the smaller the size of the ferroelectric memory cell, the lower the transmission level that the ferroelectric memory cell can withstand, that is, the smaller the size of one ferroelectric memory cell, the smaller the transmission level of this ferroelectric memory cell cannot provide a sufficiently large read/write voltage. If the read-write voltage of the ferroelectric memory cell is high, the required ferroelectric memory cell size is large, and thus the storage density of the data storage will be reduced. If the read-write voltage of the ferroelectric memory cell is low, the polarization direction of the ferroelectric memory cell is not completely changed, and the reliability and stability of data storage are low.

Disclosure of Invention

The application provides a controller, a control method and related equipment of a ferroelectric memory array, which can write data into a ferroelectric memory cell when the transmission level is low, prevent the controller from interfering data stored in a non-target ferroelectric memory cell when writing the data into the target ferroelectric memory cell, and improve the reliability, stability and storage density of data storage.

In a first aspect, the present application provides a controller for a ferroelectric memory array for controlling a ferroelectric memory array comprising a plurality of ferroelectric memory cells arranged in an array, a plurality of word lines WL, a plurality of plate lines PL and a plurality of bit lines BL. Here, the control terminals of the ferroelectric memory cells located in the same row among the plurality of ferroelectric memory cells are connected to the same word line WL among the plurality of word lines WL, the first terminals of the ferroelectric memory cells located in the same column among the plurality of ferroelectric memory cells are connected to the same bit line BL among the plurality of bit lines BL, and the second terminals of the ferroelectric memory cells located in the same row among the plurality of ferroelectric memory cells are connected to the same plate line PL among the plurality of plate lines PL. Here, the plurality of word lines WL includes a first word line WL. The controller may be configured to input a transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data to each ferroelectric memory cell in the target row when the first word line WL connected to each ferroelectric memory cell in the target row is inputted with the full selection on level and the transfer level inputted to the plate line PL connected to each ferroelectric memory cell in the target row is less than 0. The controller is further configured to input a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row when a chip select on level is input to the first word line WL connected to each ferroelectric memory cell in the target row, so as to control the target ferroelectric memory cell in the target row to be turned on and control other non-target ferroelectric memory cells in the target row to be turned off, and write the second data into the target ferroelectric memory cell. Here, the chip select on level is smaller than the full select on level.

In the embodiments provided herein, the ferroelectric memory cell may be a ferroelectric memory or other memory element made of other materials that can generate polarization according to the direction and magnitude of an applied electric field. Here, one ferroelectric memory cell may be turned on or off according to the transmission level of the word line WL and the bit line BL to which the one ferroelectric memory cell is connected. It will be appreciated that when the transmission level of the word line WL to which one ferroelectric memory cell is connected by the controller is greater than the transmission level of the bit line BL to which that ferroelectric memory cell is connected, and the difference between the transmission level of the word line WL and the transmission level of the bit line BL is greater than or equal to the turn-on voltage of that ferroelectric memory cell (here, the turn-on voltage may be the minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell when turned on), that ferroelectric memory cell will be in the turned-on state. It will also be appreciated that a conductive ferroelectric memory cell may be polarized according to the transmission levels of the bit line BL and the plate line PL to which the ferroelectric memory cell is connected, and store different data according to the polarization direction. For example, when the transmission level of the bit line BL input to one ferroelectric memory cell is greater than the transmission level of the plate line PL input to the one ferroelectric memory cell, and the difference between the transmission level of the bit line BL and the transmission level of the plate line PL is greater than or equal to the read/write voltage of the one ferroelectric memory cell (here, the read/write voltage may be the minimum applied voltage that causes the ferroelectric memory cell to be polarized in the electric field direction of the applied voltage and still maintains the polarization after the applied voltage is removed), the controller may write the first data (for example, "1") to the one ferroelectric memory cell. For another example, when the transfer level of the bit line BL to which one ferroelectric memory cell is connected by the controller is smaller than the transfer level of the plate line PL to which the one ferroelectric memory cell is connected, and the difference between the transfer level of the plate line PL and the transfer level of the bit line BL is greater than or equal to the read/write voltage of the one ferroelectric memory cell, the controller may write second data (e.g., "0") to the one ferroelectric memory cell. Here, the transmission level of the word line WL to which one ferroelectric memory cell is connected is less than or equal to the maximum level that this ferroelectric memory cell can withstand, and the transmission level of the bit line BL to which one ferroelectric memory cell is connected is less than or equal to the maximum level that this ferroelectric memory cell can withstand minus the turn-on voltage of the ferroelectric memory cell (here, the turn-on voltage may be the minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell at the time of turn-on).

In the present application, the controller may input a transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data to each ferroelectric memory cell in the target row when the first word line WL connected to each ferroelectric memory cell in the target row is inputted with the full selection on level and the transfer level inputted to the plate line PLPL connected to each ferroelectric memory cell in the target row is less than 0. Here, the transmission level of the bit line BL to which each ferroelectric memory cell in the target row is connected is less than or equal to the all-selected on level minus the on voltage of the ferroelectric memory cell, and is greater than or equal to the transmission level of the plate line PL plus the read-write voltage of the ferroelectric memory cell. At this time, since the transfer level of the plate line PL is less than 0, the transfer level of the bit line BL can be not more than the maximum level that this ferroelectric memory cell can withstand minus the on-voltage of the ferroelectric memory cell while satisfying that the difference from the transfer level of the plate line PL is greater than or equal to the read-write voltage of the ferroelectric memory cell. Here, the controller may also input a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row when a chip select on level is input to the first word line WL connected to each ferroelectric memory cell in the target row to control the target ferroelectric memory cell in the target row to be turned on and control other non-target ferroelectric memory cells in the target row to be turned off, and write the second data into the target ferroelectric memory cell. The all-selected on level here is a level at which each ferroelectric memory cell in the target row can be turned on (here, the all-selected on level is less than or equal to the maximum level that the control terminal of the ferroelectric memory cell can withstand), and the chip-selected on level here is a level at which part of the ferroelectric memory cells (which may be one ferroelectric memory cell or a plurality of ferroelectric memory cells) in the target row can be turned on and part of the ferroelectric memory cells can be turned off. Here, the transmission level of the bit line BL connected to the target ferroelectric memory cell is less than or equal to the chip select on level minus the on voltage of the ferroelectric memory cell, and the transmission level of the bit line BL connected to the non-target ferroelectric memory cell is greater than the chip select on level minus the on voltage of the ferroelectric memory cell. By adopting the embodiment of the application, when the transmission level (for example, the transmission level of the bit line BL or the transmission level of the plate line PL connected with each ferroelectric memory cell in the target row) is low, data (for example, first data) can be written into the ferroelectric memory cell, the target ferroelectric memory cell is conducted and the non-target ferroelectric memory cell is turned off through controlling the transmission level of the bit line BL connected with the ferroelectric memory cell, further data (for example, second data) is written into the target ferroelectric memory cell, and the controller is prevented from writing data (for example, second data) into the target ferroelectric memory cell to interfere the data stored by the non-target ferroelectric memory cell, so that the reliability, stability and storage density of data storage are improved.

With reference to the first aspect, in a first possible implementation manner, the plurality of word lines WL further includes a second word line WL in addition to the first word line WL. The controller may be configured to input a full selection on level to a first word line WL connected to each ferroelectric memory cell in the target row, input an off level to a second word line WL connected to each ferroelectric memory cell in the non-target row, and input a first write level to a bit line BL connected to each ferroelectric memory cell in the target row as a transmission level of the bit line BL to turn on each ferroelectric memory cell in the target row. Here, the off level is smaller than the chip select on level, and the first write level is greater than 0 and smaller than the full select on level. The controller herein may also input the second write level to the plate line PL to which each ferroelectric memory cell in the target row is connected as a transfer level of the plate line PL to store the first data (e.g., "1") to each ferroelectric memory cell in the target row. Here, the second write level is less than 0.

It will be appreciated that the off level herein is a level (e.g., 0V) that causes each ferroelectric memory cell in the non-target row to be turned off, the fully selected on level herein is a level that causes each ferroelectric memory cell in the target row to be turned on (where the fully selected on level is less than or equal to the maximum level that the control terminal of the ferroelectric memory cell can withstand), and the first write level herein is less than or equal to the fully selected on level minus the on voltage of the ferroelectric memory cell (where the on voltage may be the minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell when turned on). That is, when the controller inputs the all-selected on level to the first word line WL to which each ferroelectric memory cell in the target row is connected and inputs the first write level to the bit line BL as the transfer level of the bit line BL, each ferroelectric memory cell in the target row is turned on. It is further understood that the first write level is greater than the second write level, and the difference between the first write level and the second write level is greater than or equal to the read-write voltage of the ferroelectric memory cell (here, the read-write voltage may be the minimum applied voltage that causes the ferroelectric memory cell to be polarized in the direction of the electric field of the applied voltage, and still maintain the polarization after the applied voltage is removed). That is, when each ferroelectric memory cell in the target row is in the on state, the controller inputs the second write level as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first write level), the first data can be written to each ferroelectric memory cell in the target row. By adopting the embodiment provided by the application, when the transmission level (for example, the first writing level or the second writing level) is lower, data (for example, the first data) can be written into the ferroelectric memory cells of the target row, so that the limitation of the size of the ferroelectric memory cells on the transmission level (for example, the smaller the size of the ferroelectric memory cells is, the smaller the maximum level which can be born by the control end or the first end of the ferroelectric memory cells is), and when the transmission level of the transmission lines connected with the ends of the ferroelectric memory cells is fixed, the size of the ferroelectric memory cells can be reduced, and the storage density of data storage is improved; when the size of the ferroelectric memory cell is fixed, the voltage between the transmission levels (for example, the voltage between the first write level and the second write level) of the transmission line to which each end of the ferroelectric memory cell is connected can be increased, and the sensitivity and stability of data storage can be improved.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, the controller may be further configured to input a third write level to a bit line BL connected to a target ferroelectric memory cell in the target row as a transmission level of the bit line BL, and input a first write level to a bit line BL connected to a non-target ferroelectric memory cell in the target row, and input a chip select on level to a first word line WL connected to each ferroelectric memory cell in the target row to turn on the target ferroelectric memory cell in the target row and turn off other non-target ferroelectric memory cells in the target row. Here, the third write level is less than the chip select on level and greater than or equal to the off level, the chip select on level being less than the first write level. The controller herein may also input a fourth write level as a transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected, to store the second data (e.g., "0") to the target ferroelectric memory cell in the target row. Here, the fourth write level is greater than the first write level.

It will be appreciated that the chip select on level herein is a level that may cause a portion of the ferroelectric memory cells in the target row (e.g., target ferroelectric memory cells) to be on and a portion of the ferroelectric memory cells to be off (e.g., non-target ferroelectric memory cells), and that the third write level herein is less than the chip select on level minus the on voltage of the ferroelectric memory cells and the first write level herein is greater than the chip select on level minus the on voltage of the ferroelectric memory cells. That is, when the controller inputs a chip select on level to the first word line WL connected to each ferroelectric memory cell in the target row and inputs a third write level as a transfer level of the bit line BL to the bit line BL connected to the target ferroelectric memory cell, the target ferroelectric memory cell is turned on. When the controller inputs a chip select on level to a first word line WL connected to each ferroelectric memory cell in the target row and inputs a first write level to a bit line BL connected to a non-target ferroelectric memory cell, the non-target ferroelectric memory cell is turned off. It is further understood that the fourth write level is greater than the third write level and the difference between the fourth write level and the third write level is greater than or equal to the read-write voltage of the ferroelectric memory cell. That is, when the target ferroelectric memory cell is in the on state, the controller inputs the fourth write level to the plate line PL to which the target ferroelectric memory cell is connected (at this time, the transfer level of the bit line BL to which the target ferroelectric memory cell is connected is the third write level), and the second data can be written to the target ferroelectric memory cell (i.e., the polarization direction of the target ferroelectric memory cell is reversed). Meanwhile, the level of the bit line BL connected with the non-target ferroelectric memory cell is the first writing level, the non-target ferroelectric memory cell is in an off state, and the process of writing second data into the target ferroelectric memory cell cannot interfere with the first data stored in the non-target ferroelectric memory cell. By adopting the implementation mode provided by the application, the controller can be prevented from interfering the data stored in the non-target ferroelectric memory unit when writing the data into the target ferroelectric memory unit, and the reliability and stability of data storage are improved.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the ferroelectric memory cell may include a switch tube and a capacitor. Here, the control terminal of the switching transistor of the ferroelectric memory cell may be connected to the word line WL to which the ferroelectric memory cell is connected as the control terminal of the ferroelectric memory cell, the first terminal of the switching transistor may be connected to the bit line BL to which the ferroelectric memory cell is connected as the first terminal of the ferroelectric memory cell, the second terminal of the switching transistor may be connected to the first plate of the capacitor of the ferroelectric memory cell, and the second plate of the capacitor may be connected to the plate line PL to which the ferroelectric memory cell is connected as the second terminal of the ferroelectric memory cell. The controller is further operable to input a third write level to the bit line BL connected to the target ferroelectric memory cell in the target row and to input a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row when inputting the first write level to the bit line BL connected to the non-target ferroelectric memory cell in the target row, to reduce the voltage of the capacitance of each ferroelectric memory cell in the target row. Here, the fifth write level is greater than the third write level and less than or equal to the first write level.

It will be appreciated that when the controller inputs the fifth write level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which the target ferroelectric memory cell is connected is the third write level), the voltage across the capacitor in the target ferroelectric memory cell is reduced from the difference between the third write level and the fourth write level to the difference between the third write level and the fifth write level. When the controller inputs a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row (at this time, the transfer level of the bit line BL connected to the non-target ferroelectric memory cell is the first write level), the voltage across the capacitor in the target ferroelectric memory cell is reduced from the difference between the first write level and the fourth write level to the difference between the first write level and the fifth write level. It will further be appreciated that when the controller inputs a chip select on-state to the first word line WL to which each ferroelectric memory cell in the target row is connected, the non-target ferroelectric memory cell is turned off, at which time the level difference between the control terminal of the ferroelectric memory cell in the non-target ferroelectric memory cell (the level is the chip select on-level) and the second terminal of the ferroelectric memory cell (the level is the fourth write level) is mainly assumed by the control terminal of the switching transistor and the second terminal of the switching transistor, and the capacitance in the non-target ferroelectric memory cell only needs to assume the difference between the first write level and the fifth write level (for example, when the fifth write level is equal to the first write level, the voltage across the capacitance is 0V). By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

With reference to the first aspect or any one of the possible implementation manners of the first aspect, in a fourth possible implementation manner, the controller may further include a plurality of reading units. Here, a first terminal of a ferroelectric memory cell located in the same column among the plurality of ferroelectric memory cells is connected to a first terminal of one of the plurality of read cells through the same bit line BL, and a second terminal of each of the plurality of read cells is connected to a reference ground. The controller is also operable to input a first read level to the bit line BL connected to each ferroelectric memory cell in the target row, a full select on level to the first word line WL connected to each ferroelectric memory cell in the target row, and an off level to the second word line WL connected to each ferroelectric memory cell in the non-target row to turn on each ferroelectric memory cell in the target row. Here, the first read level is equal to the first write level. The controller is further configured to control the first ends of the read cells connected to the ferroelectric memory cells in the target row to float, and input a second read level to the plate line PL connected to the ferroelectric memory cells in the target row to read the data stored in the ferroelectric memory cells in the target row through the read cells connected to the ferroelectric memory cells in the target row. Here, the second read level is equal to the second write level.

It will be appreciated that when the controller inputs the all-selected conduction level to the first word line WL to which each ferroelectric memory cell in the target row is connected, and inputs the first read level to the bit line BL to which each ferroelectric memory cell in the target row is connected, each ferroelectric memory cell in the target row is turned on. When each ferroelectric memory cell in the target row is in an on state, the controller inputs a second read level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transmission level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first read level), the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row in which the first data is stored is not inverted, almost no electric charge is discharged, the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row in which the second data is stored is inverted, a large amount of electric charge is discharged to the read cell, and further, the data stored in each ferroelectric memory cell in the target row can be read through the read cell to which each ferroelectric memory cell in the target row is connected. By adopting the embodiment of the application, the data reading operation is simple, the convenience and applicability of data storage can be improved, the data storage and reading efficiency can be improved, and the data storage cost can be reduced.

With reference to the fourth possible implementation manner of the first aspect, in a fifth possible implementation manner, the controller may further include at least one comparison circuit, and the comparison circuit may be connected to the first end of the target reading unit. The comparison circuit may be configured to obtain a data read level of the first end of the target read unit, obtain the data stored in the ferroelectric memory cell connected to the target read unit as first data when the data read level is greater than or equal to a level threshold, and obtain the data stored in the ferroelectric memory cell connected to the target read unit as second data when the data read level is less than the level threshold.

It will be appreciated that when each ferroelectric memory cell in the target row is in the on state, the controller inputs the second read level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transmission level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first read level), the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row storing the first data is not inverted, and almost no charge is discharged (here, the data read level at the first end of the target read cell is approximately equal to the first read level, that is, greater than or equal to the level threshold), and the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row storing the second data is inverted, and a large amount of charge is released to the read cell (here, the data read level at the first end of the target read cell is far lower than the first read level, that is smaller than the level threshold), and further, the data stored in the ferroelectric memory cell connected to the target read cell can be determined by the magnitude relation of the data read level and the level threshold. By adopting the embodiment of the application, the data reading operation is simple, the convenience and applicability of data storage can be improved, the data storage and reading efficiency can be improved, and the data storage cost can be reduced.

With reference to the fourth possible implementation manner of the first aspect or the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner, when the ferroelectric memory cells include a switch tube and a capacitor, the controller is further configured to input the first read level to the plate line PL connected to each ferroelectric memory cell in the target row to precharge the capacitor of each ferroelectric memory cell in the target row when the first read level is input to the bit line BL connected to each ferroelectric memory cell in the target row.

That is, when the controller inputs the first read level to the bit line BL connected to each ferroelectric memory cell in the target row (i.e., before the controller inputs the full selection on level to the first word line WL connected to each ferroelectric memory cell in the target row), the first read level may be input to the plate line PL connected to each ferroelectric memory cell in the target row to precharge the capacitance of each ferroelectric memory cell in the target row (i.e., raise the level of the second plate of the capacitance of each ferroelectric memory cell in the target row to the first read level), preventing the data stored in the ferroelectric memory cell from being disturbed because the difference between the level of the second plate of the capacitance and the level of the first plate is greater than the read-write voltage when the controller inputs the full selection on level to the first word line WL connected to each ferroelectric memory cell in the target row. By adopting the implementation mode provided by the application, the capacitor in each ferroelectric memory cell in the target row can be precharged before data is read, so that the stability of data storage is improved, and the accuracy and the efficiency of data storage and reading are improved.

With reference to any one of the fourth possible implementation manner of the first aspect to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner, the controller may be further configured to input a first write level to a bit line BL connected to a ferroelectric memory cell storing first data in the target row, and input a third write level to a bit line BL connected to a ferroelectric memory cell storing second data in the target row, and input a chip select on level to a first word line WL connected to each ferroelectric memory cell in the target row, so as to turn on the ferroelectric memory cell storing second data in the target row, and turn off the ferroelectric memory cell storing the first data in the target row. The controller herein may be further operable to input a fourth write level to the plate line PL to which each ferroelectric memory cell in the target row is connected to restore the second data to the ferroelectric memory cell in the target row storing the second data.

It will be appreciated that after a data read is performed, the polarization direction of the ferroelectric memory cell storing the first data in the target row will not be flipped, while the polarization direction of the ferroelectric memory cell storing the second data will be flipped again to the pre-read state for long-term storage of the data in order to maintain data stability. That is, when the controller inputs the first write level to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row and inputs the chip select on level to the first word line WL connected to each of the ferroelectric memory cells in the target row, the ferroelectric memory cell storing the first data is turned off. When the controller inputs a third write level to the bit line BL connected to the ferroelectric memory cells storing the second data in the target row and inputs a chip select on level to the first word line WL connected to each of the ferroelectric memory cells in the target row, the ferroelectric memory cells storing the second data are turned on. Further, when the ferroelectric memory cell storing the second data in the target row is in the on state, the controller inputs the fourth write level to the plate line PL to which the ferroelectric memory cell storing the second data in the target row is connected (at this time, the transfer level of the bit line BL to which the ferroelectric memory cell storing the second data is connected is the third write level), and can rewrite the second data to the ferroelectric memory cell storing the second data in the target row. Meanwhile, the level of the bit line BL connected with the ferroelectric memory cell storing the first data in the target row is the first writing level, the ferroelectric memory cell storing the first data in the target row is in an off state, and the process of rewriting the second data into the ferroelectric memory cell storing the second data in the target row does not interfere with the first data stored in the ferroelectric memory cell storing the first data in the target row. By adopting the embodiment of the application, the data can be rewritten into the ferroelectric memory unit after the data is read, and the controller is prevented from interfering the first data stored in the ferroelectric memory unit for storing the first data when rewriting the second data into the ferroelectric memory unit for storing the second data, thereby improving the reliability and stability of data storage.

With reference to the seventh possible implementation manner of the first aspect, in an eighth possible implementation manner, when the ferroelectric memory cells include a switch tube and a capacitor, the controller is further configured to input a first write level to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row and input a third write level to the bit line BL connected to the ferroelectric memory cell storing the second data in the target row, and input a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row, so as to reduce the voltage of the capacitor of each ferroelectric memory cell in the target row. By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

In a second aspect, the present application provides a ferroelectric memory comprising a controller in the first aspect or any one of the possible implementations of the first aspect, and a ferroelectric memory array in the first aspect or any one of the possible implementations of the first aspect.

In a third aspect, the present application provides an apparatus comprising the ferroelectric memory of the second aspect and a circuit board, the ferroelectric memory and the circuit board being electrically connected.

In a fourth aspect, the present application provides a method of controlling a ferroelectric memory array, the method being applicable to a controller of a ferroelectric memory array including a plurality of ferroelectric memory cells arranged in an array, a plurality of word lines WL, a plurality of plate lines PL, and a plurality of bit lines BL. Here, the control terminals of the ferroelectric memory cells located in the same row among the plurality of ferroelectric memory cells are connected to the same word line WL among the plurality of word lines WL, the first terminals of the ferroelectric memory cells located in the same column among the plurality of ferroelectric memory cells are connected to the same bit line BL among the plurality of bit lines BL, and the second terminals of the ferroelectric memory cells located in the same row among the plurality of ferroelectric memory cells are connected to the same plate line PL among the plurality of plate lines PL. Here, the plurality of word lines WL includes a first word line WL. The method comprises the following steps: when the controller inputs the full selection on level to the first word line WL connected to each ferroelectric memory cell in the target row and the transfer level input to the plate line PL connected to each ferroelectric memory cell in the target row is less than 0, the controller inputs the transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data into each ferroelectric memory cell in the target row. When the controller inputs a chip select on level to a first word line WL connected to each ferroelectric memory cell in the target row, the controller inputs a transmission level to a bit line BL and a plate line PL connected to each ferroelectric memory cell in the target row to control the target ferroelectric memory cells in the target row to be on and control other non-target ferroelectric memory cells in the target row to be off, and second data is written into the target ferroelectric memory cells. Here, the chip select on level is smaller than the full select on level.

In the present application, the controller may input a transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data to each ferroelectric memory cell in the target row when the first word line WL connected to each ferroelectric memory cell in the target row is inputted with the full selection on level and the transfer level inputted to the plate line PLPL connected to each ferroelectric memory cell in the target row is less than 0. Here, the transmission level of the bit line BL to which each ferroelectric memory cell in the target row is connected is less than or equal to the all-selected on level minus the on voltage of the ferroelectric memory cell, and is greater than or equal to the transmission level of the plate line PL plus the read-write voltage of the ferroelectric memory cell. At this time, since the transfer level of the plate line PL is less than 0, the transfer level of the bit line BL can be not more than the maximum level that this ferroelectric memory cell can withstand minus the on-voltage of the ferroelectric memory cell while satisfying that the difference from the transfer level of the plate line PL is greater than or equal to the read-write voltage of the ferroelectric memory cell. Here, the controller may also input a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row when a chip select on level is input to the first word line WL connected to each ferroelectric memory cell in the target row to control the target ferroelectric memory cell in the target row to be turned on and control other non-target ferroelectric memory cells in the target row to be turned off, and write the second data into the target ferroelectric memory cell. Here, the transmission level of the bit line BL connected to the target ferroelectric memory cell is less than or equal to the chip select on level minus the on voltage of the ferroelectric memory cell, and the transmission level of the bit line BL connected to the non-target ferroelectric memory cell is greater than the chip select on level minus the on voltage of the ferroelectric memory cell. By adopting the embodiment of the application, when the transmission level (for example, the transmission level of the bit line BL or the transmission level of the plate line PL connected with each ferroelectric memory cell in the target row) is low, data (for example, first data) can be written into the ferroelectric memory cell, the target ferroelectric memory cell is conducted and the non-target ferroelectric memory cell is turned off through controlling the transmission level of the bit line BL connected with the ferroelectric memory cell, further data (for example, second data) is written into the target ferroelectric memory cell, and the controller is prevented from writing data (for example, second data) into the target ferroelectric memory cell to interfere the data stored by the non-target ferroelectric memory cell, so that the reliability, stability and storage density of data storage are improved.

With reference to the fourth aspect, in a first possible implementation manner, the plurality of word lines WL further includes a second word line WL in addition to the first word line WL. When the controller inputs the full selection on level to the first word line WL connected to each ferroelectric memory cell in the target row and the transfer level input to the plate line PL connected to each ferroelectric memory cell in the target row is less than 0, the controller inputs the transfer level to the bit line BL connected to each ferroelectric memory cell in the target row, comprising: the controller inputs a full selection on level to a first word line WL connected with each ferroelectric memory cell in the target row, inputs an off level to a second word line WL connected with each ferroelectric memory cell in the non-target row, and inputs a first write level to a bit line BL connected with each ferroelectric memory cell in the target row as a transmission level of the bit line BL so as to conduct each ferroelectric memory cell in the target row. Here, the off level is smaller than the chip select on level, and the first write level is greater than 0 and smaller than the full select on level. The controller inputs the second write level as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected. Here, the second write level is less than 0.

It will be appreciated that the off level herein is a level (e.g., 0V) that causes each ferroelectric memory cell in the non-target row to be turned off, the fully selected on level herein is a level that causes each ferroelectric memory cell in the target row to be turned on (where the fully selected on level is less than or equal to the maximum level that the control terminal of the ferroelectric memory cell can withstand), and the first write level herein is less than or equal to the fully selected on level minus the on voltage of the ferroelectric memory cell (where the on voltage may be the minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell when turned on). That is, when the controller inputs the all-selected on level to the first word line WL to which each ferroelectric memory cell in the target row is connected and inputs the first write level to the bit line BL, each ferroelectric memory cell in the target row is turned on. It is further understood that the first write level is greater than the second write level, and the difference between the first write level and the second write level is greater than or equal to the read-write voltage of the ferroelectric memory cell (here, the read-write voltage may be the minimum applied voltage that causes the ferroelectric memory cell to be polarized in the direction of the electric field of the applied voltage, and still maintain the polarization after the applied voltage is removed). That is, when each ferroelectric memory cell in the target row is in the on state, the controller inputs the second write level as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first write level), the first data can be written to each ferroelectric memory cell in the target row. By adopting the embodiment provided by the application, when the transmission level (for example, the first writing level or the second writing level) is lower, data (for example, the first data) can be written into the ferroelectric memory cells of the target row, so that the limitation of the size of the ferroelectric memory cells on the transmission level (for example, the smaller the size of the ferroelectric memory cells is, the smaller the maximum level which can be born by the control end or the first end of the ferroelectric memory cells is), and when the transmission level of the transmission lines connected with the ends of the ferroelectric memory cells is fixed, the size of the ferroelectric memory cells can be reduced, and the storage density of data storage is improved; when the size of the ferroelectric memory cell is fixed, the voltage between the transmission levels (for example, the voltage between the first write level and the second write level) of the transmission line to which each end of the ferroelectric memory cell is connected can be increased, and the sensitivity and stability of data storage can be improved.

With reference to the first possible implementation manner of the fourth aspect, in a second possible implementation manner, when the controller inputs a chip select on level to the first word line WL connected to each ferroelectric memory cell in the target row, the controller inputs a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row, including: the controller inputs a third write level as a transmission level of the bit line BL to the bit line BL connected to the target ferroelectric memory cell in the target row, inputs a first write level to the bit line BL connected to the non-target ferroelectric memory cell in the target row, and inputs a chip select on level to the first word line WL connected to each ferroelectric memory cell in the target row. Here, the third write level is less than the chip select on level and greater than or equal to the off level, the chip select on level being less than the first write level. The controller inputs the fourth write level as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected. Here, the fourth write level is greater than the first write level.

With reference to the fourth aspect, in a third possible implementation manner, the ferroelectric memory cell may include a switch tube and a capacitor. Here, the control terminal of the switching transistor of the ferroelectric memory cell may be connected to the word line WL to which the ferroelectric memory cell is connected as the control terminal of the ferroelectric memory cell, the first terminal of the switching transistor may be connected to the bit line BL to which the ferroelectric memory cell is connected as the first terminal of the ferroelectric memory cell, the second terminal of the switching transistor may be connected to the first plate of the capacitor of the ferroelectric memory cell, and the second plate of the capacitor may be connected to the plate line PL to which the ferroelectric memory cell is connected as the second terminal of the ferroelectric memory cell. Before inputting the chip select on level to the first word line WL connected to each ferroelectric memory cell in the target row, the method further includes: when the controller inputs the third write level to the bit line BL connected to the target ferroelectric memory cell in the target row and inputs the first write level to the bit line BL connected to the non-target ferroelectric memory cell in the target row, the controller inputs the fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row to reduce the voltage of the capacitance of each ferroelectric memory cell in the target row. Here, the fifth write level is greater than the third write level and less than or equal to the first write level.

With reference to the fourth aspect or any one of the possible embodiments of the fourth aspect, in a fourth possible embodiment, the controller may further include a plurality of reading units. Here, a first terminal of a ferroelectric memory cell located in the same column among the plurality of ferroelectric memory cells is connected to a first terminal of one of the plurality of read cells through the same bit line BL, and a second terminal of each of the plurality of read cells is connected to a reference ground. After writing the second data to the target ferroelectric memory cell, the method further comprises: the controller inputs a first read level to the bit line BL connected to each ferroelectric memory cell in the target row, a full selection on level to the first word line WL connected to each ferroelectric memory cell in the target row, and an off level to the second word line WL connected to each ferroelectric memory cell in the non-target row to turn on each ferroelectric memory cell in the target row. Here, the first read level is equal to the first write level. The controller controls the first ends of the read units connected to the ferroelectric memory cells in the target row to float, and inputs a second read level to the plate line PL connected to the ferroelectric memory cells in the target row to read the data stored in the ferroelectric memory cells in the target row through the read units connected to the ferroelectric memory cells in the target row. Here, the second read level is equal to the second write level.

With reference to the fourth possible implementation manner of the fourth aspect, in a fifth possible implementation manner, the controller may further include at least one comparison circuit, and the comparison circuit may be connected to the first end of the target reading unit. After inputting the second read level to the plate line PL to which each ferroelectric memory cell in the target row is connected, the method further comprises: the comparison circuit obtains a data read level of a first end of the target read unit. When the data read level is greater than or equal to the level threshold, determining the data stored in the ferroelectric memory cell connected to the target read cell as first data. And when the data reading level is smaller than the level threshold value, determining the data stored in the ferroelectric memory cell connected with the target reading cell as second data.

With reference to the fourth possible implementation manner of the fourth aspect or the fifth possible implementation manner of the fourth aspect, in a sixth possible implementation manner, when the ferroelectric memory cell includes a switch tube and a capacitor, before inputting the all-selected on level to the first word line WL connected to each ferroelectric memory cell in the target row, the method further includes: when the controller inputs the first read level to the bit line BL to which each ferroelectric memory cell in the target row is connected, the controller inputs the first read level to the plate line PL to which each ferroelectric memory cell in the target row is connected, to precharge the capacitance of each ferroelectric memory cell in the target row.

With reference to any one of the fourth possible implementation manner to the sixth possible implementation manner of the fourth aspect, in a seventh possible implementation manner, after inputting the second read level to the plate line PL connected to each ferroelectric memory cell in the target row, the method further includes: the controller inputs a first write level to the bit line BL connected to the ferroelectric memory cells storing the first data in the target row, inputs a third write level to the bit line BL connected to the ferroelectric memory cells storing the second data in the target row, and inputs a chip select on level to the first word line WL connected to each ferroelectric memory cell in the target row to turn on the ferroelectric memory cells storing the second data in the target row and turn off the ferroelectric memory cells storing the first data in the target row. The controller inputs a fourth write level to the plate line PL to which each ferroelectric memory cell in the target row is connected to restore the second data to the ferroelectric memory cell in the target row storing the second data.

With reference to the seventh possible implementation manner of the fourth aspect, in an eighth possible implementation manner, when the ferroelectric memory cells include a switch tube and a capacitor, before inputting the chip select on level to the first word line WL connected to each ferroelectric memory cell in the target row, the method further includes: when the controller inputs a first write level to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row and inputs a third write level to the bit line BL connected to the ferroelectric memory cell storing the second data in the target row, the controller inputs a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row to reduce the voltage of the capacitance of each ferroelectric memory cell in the target row. By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

Drawings

Fig. 1 is a schematic diagram of an application scenario of a controller according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a ferroelectric memory according to an embodiment of the present application;

fig. 3 is another schematic structural diagram of a ferroelectric memory according to an embodiment of the present application;

Fig. 4 is a schematic diagram of the working principle of a ferroelectric memory cell according to an embodiment of the present application;

FIG. 5 is a schematic diagram of control logic of a ferroelectric memory according to an embodiment of the present application;

fig. 6 is another schematic structural diagram of a ferroelectric memory according to an embodiment of the present application;

fig. 7 is another schematic structural diagram of a ferroelectric memory according to an embodiment of the present application;

FIG. 8 is a schematic diagram of the operation principle of a comparison circuit according to an embodiment of the present application;

FIG. 9 is a flow chart of a control method of a ferroelectric memory array according to an embodiment of the present application;

fig. 10 is another flow chart of a control method of the ferroelectric memory array according to the embodiment of the present application.

Detailed Description

The controller, the control method and the related equipment of the ferroelectric memory array can store data, can be suitable for data storage in the fields of new energy intelligent micro-grid, power transmission and distribution or new energy (such as photovoltaic grid-connected field or wind power grid-connected field), light-storage power generation field (such as supplying power to household equipment (such as a refrigerator and an air conditioner) or a power grid), or wind-storage power generation field or high-power converter field (such as converting direct current into high-power high-voltage alternating current) and other application fields, and can be specifically determined according to practical application scenes without limitation. The controller, the control method and the related equipment of the ferroelectric memory array can be suitable for different application scenes, such as an application scene for storing data in a light storage power supply environment, an application scene for storing data in a wind storage power supply environment, an application scene for storing data in a pure energy storage power supply environment or other application scenes, and the application scene for storing data in the pure energy storage power supply environment is taken as an example for description and will not be repeated. The ferroelectric memory array provided by the application is a memory array formed by ferroelectric materials, wherein the ferroelectric materials can generate polarization under the action of an external electric field, and can generate polarization in different directions according to different directions of the external electric field, and the polarization is not repeated.

Referring to fig. 1 together, fig. 1 is a schematic view of an application scenario of a controller according to an embodiment of the present application. In the scenario of pure energy storage powered applications, as shown in fig. 1, a ferroelectric memory 2 includes a controller and a ferroelectric memory array, where the ferroelectric memory array includes a plurality of ferroelectric memory cells disposed in a plurality of rows and columns. Wherein the controller may be connected to a power supply 1, a plurality of ferroelectric memory cells arranged in a plurality of rows and columns, and a load 3. In the process of transmitting data to the plurality of ferroelectric memory cells by the controller in the ferroelectric memory 2, the controller can control the on or off of each ferroelectric memory cell in the plurality of ferroelectric memory cells and control each ferroelectric memory cell in the plurality of ferroelectric memory cells to generate polarization with different directions so as to store the data into each ferroelectric memory cell. In some possible embodiments, the power supply 1 may supply power to the load 3 via a controller. The controller provided by the application is suitable for an application scene of the power supply 1 for supplying power to base station equipment in a remote area without commercial power or with poor commercial power, or supplying power to a storage battery, or supplying power to household equipment (such as a refrigerator, an air conditioner and the like) and other electric equipment of various types, and can be specifically determined according to the actual application scene without limitation. It is further understood that the load 3 in fig. 1 may be an electrical grid, a battery, an electrical consumer of a building, a lighting device of a bridge, or other electrical device. The power grid may include transmission lines, power transfer sites, storage batteries, communication stations, or consumer or power transmission devices such as household devices. In the application scenario shown in fig. 1, the ferroelectric memory cell may include a switch tube and a capacitor, where in the working process of the ferroelectric memory cell, in order to change the polarization direction of the capacitor, a larger read-write voltage needs to be applied to the ferroelectric memory cell (for example, the capacitor in the ferroelectric memory cell), and the read-write voltage of the ferroelectric memory cell is related to a transmission level that can be borne by the ferroelectric memory cell (for example, a switch tube control end, where the switch tube control end may be a gate electrode of the switch tube, and the first end and the second end of the switch tube may be a source electrode and a drain electrode of the switch tube or a drain electrode and a source electrode of the switch tube)), and the lower the transmission level that can be borne by the ferroelectric memory cell with a smaller size (or the switch tube in the ferroelectric memory cell) is, that is, the smaller the transmission level of the ferroelectric memory cell is unable to provide a sufficiently large read-write voltage. By adopting the implementation mode provided by the application, the data can be written into the ferroelectric memory unit when the transmission level is lower, the controller is prevented from interfering the data stored in the non-target ferroelectric memory unit when the data is written into the target ferroelectric memory unit, and the reliability, the stability and the storage density of the data storage are improved.

The controller, the ferroelectric memory and the operating principle thereof provided by the present application will be exemplified with reference to fig. 2 to 10.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a ferroelectric memory according to an embodiment of the application. As shown in fig. 2, the ferroelectric memory includes a controller and a ferroelectric memory array including a plurality of ferroelectric memory cells arranged in an array, a plurality of word lines WL, a plurality of plate lines PL, and a plurality of bit lines BL. Here, the control terminals of the ferroelectric memory cells located in the same row among the plurality of ferroelectric memory cells are connected to the same word line WL among the plurality of word lines WL, the first terminals of the ferroelectric memory cells located in the same column among the plurality of ferroelectric memory cells are connected to the same bit line BL among the plurality of bit lines BL, and the second terminals of the ferroelectric memory cells located in the same row among the plurality of ferroelectric memory cells are connected to the same plate line PL among the plurality of plate lines PL. Here, for convenience of description, the plurality of word lines WL are defined to include a first word line WL (word line WL to which each ferroelectric memory cell in the target row is connected) and a second word line WL (word line WL to which each ferroelectric memory cell in the non-target row is connected), and will not be described in detail. The controller may be configured to input a transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data to each ferroelectric memory cell in the target row when the first word line WL connected to each ferroelectric memory cell in the target row is inputted with the full selection on level and the transfer level inputted to the plate line PL connected to each ferroelectric memory cell in the target row is less than 0. The controller is further configured to input a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row when a chip select on level is input to the first word line WL connected to each ferroelectric memory cell in the target row, so as to control the target ferroelectric memory cell in the target row to be turned on and control other non-target ferroelectric memory cells in the target row to be turned off, and write the second data into the target ferroelectric memory cell. Here, the chip select on level is smaller than the full select on level.

In the embodiments provided herein, the ferroelectric memory cell may be a ferroelectric memory or other memory element made of other materials that can generate polarization according to the direction and magnitude of an applied electric field. Here, one ferroelectric memory cell may be turned on or off according to the transmission level of the word line WL and the bit line BL to which the one ferroelectric memory cell is connected. It will be appreciated that when the transmission level of the word line WL to which one ferroelectric memory cell is connected by the controller is greater than the transmission level of the bit line BL to which that ferroelectric memory cell is connected, and the difference between the transmission level of the word line WL and the transmission level of the bit line BL is greater than or equal to the turn-on voltage Vth of that ferroelectric memory cell (here, the turn-on voltage Vth may be the minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell when turned on), that ferroelectric memory cell will be in the turned-on state. It will also be appreciated that a conductive ferroelectric memory cell may be polarized according to the transmission levels of the bit line BL and the plate line PL to which the ferroelectric memory cell is connected, and store different data according to the polarization direction. For example, when the transmission level of the bit line BL input to one ferroelectric memory cell is greater than the transmission level of the plate line PL input to the one ferroelectric memory cell, and the difference between the transmission level of the bit line BL and the transmission level of the plate line PL is greater than or equal to the read-write voltage Vwr of the one ferroelectric memory cell (here, the read-write voltage Vwr may be a minimum applied voltage that causes the ferroelectric memory cell to be polarized in the electric field direction of the applied voltage, and still maintains the polarization after the applied voltage is removed), the controller may write the first data (for example, "1") to the one ferroelectric memory cell. For another example, when the transfer level of the bit line BL to which one ferroelectric memory cell is connected by the controller is smaller than the transfer level of the plate line PL to which the one ferroelectric memory cell is connected, and the difference between the transfer level of the plate line PL and the transfer level of the bit line BL is greater than or equal to the read/write voltage Vwr of the one ferroelectric memory cell, the controller may write second data (e.g., "0") to the one ferroelectric memory cell. Here, the transmission level of the word line WL to which one ferroelectric memory cell is connected is less than or equal to the maximum level that this ferroelectric memory cell can withstand, and the transmission level of the bit line BL to which one ferroelectric memory cell is connected is less than or equal to the maximum level that this ferroelectric memory cell can withstand minus the turn-on voltage Vth of the ferroelectric memory cell (here, the turn-on voltage Vth may be the minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell at the time of turn-on).

In the present application, the controller may input a transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data to each ferroelectric memory cell in the target row when the full selection on level is input to the first word line WL connected to each ferroelectric memory cell in the target row and the transfer level input to the plate line PL connected to each ferroelectric memory cell in the target row is less than 0. Here, the transfer level of the bit line BL to which each ferroelectric memory cell in the target row is connected is less than or equal to the all-selected on level minus the on voltage Vth of the ferroelectric memory cell, and is greater than or equal to the transfer level of the plate line PL plus the read-write voltage Vwr of the ferroelectric memory cell. At this time, since the transfer level of the plate line PL is less than 0, the transfer level of the bit line BL can be not more than the maximum level that this ferroelectric memory cell can withstand minus the on voltage Vth of the ferroelectric memory cell while satisfying that the difference from the transfer level of the plate line PL is greater than or equal to the read-write voltage Vwr of the ferroelectric memory cell. Here, the controller may also input a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row when a chip select on level is input to the first word line WL connected to each ferroelectric memory cell in the target row to control the target ferroelectric memory cell in the target row to be turned on and control other non-target ferroelectric memory cells in the target row to be turned off, and write the second data into the target ferroelectric memory cell. Here, the transmission level of the bit line BL connected to the target ferroelectric memory cell is less than or equal to the chip select on level minus the on voltage Vth of the ferroelectric memory cell, and the transmission level of the bit line BL connected to the non-target ferroelectric memory cell is greater than the chip select on level minus the on voltage Vth of the ferroelectric memory cell. By adopting the embodiment of the application, when the transmission level (for example, the transmission level of the bit line BL or the transmission level of the plate line PL connected with each ferroelectric memory cell in the target row) is low, data (for example, first data) can be written into the ferroelectric memory cell, the target ferroelectric memory cell is conducted and the non-target ferroelectric memory cell is turned off through controlling the transmission level of the bit line BL connected with the ferroelectric memory cell, further data (for example, second data) is written into the target ferroelectric memory cell, and the controller is prevented from writing data (for example, second data) into the target ferroelectric memory cell to interfere the data stored by the non-target ferroelectric memory cell, so that the reliability, stability and storage density of data storage are improved.

Referring to fig. 3, fig. 3 is another schematic structure of the ferroelectric memory according to the embodiment of the present application. In some possible implementations, the ferroelectric memory cell may include a switching tube and a capacitor. As shown in part (a) of fig. 3, a control terminal (e.g., a gate) of a switching transistor of a ferroelectric memory cell may be connected to a word line WL to which the ferroelectric memory cell is connected as a control terminal of the ferroelectric memory cell, a first terminal (e.g., a source or a drain) of the switching transistor may be connected to a bit line BL to which the ferroelectric memory cell is connected as a first terminal of the ferroelectric memory cell, a second terminal (e.g., a drain or a source) of the switching transistor may be connected to a first plate of a capacitor of the ferroelectric memory cell, and a second plate of the capacitor may be connected to a plate line PL to which the ferroelectric memory cell is connected as a second terminal of the ferroelectric memory cell. It will be appreciated that in the present application, a ferroelectric memory cell may include a switching tube and a capacitor, and a ferroelectric memory cell may also include a plurality of switching tubes or a plurality of capacitors. As shown in part (b) of fig. 3, control terminals (e.g., gates) of the switching transistor T and the switching transistor T 'of the ferroelectric memory cell may be connected to the word line WL to which the ferroelectric memory cell is connected, first terminals (e.g., source or drain) of the switching transistor T and the switching transistor T' may be connected to the bit line BL and the bit line BL 'to which the ferroelectric memory cell is connected, second terminals (e.g., drain or source) of the switching transistor T and the switching transistor T' may be connected to first plates of the capacitor C and the capacitor C 'of the ferroelectric memory cell, respectively, and second plates of the capacitor C and the capacitor C' may be connected to the plate line PL to which the ferroelectric memory cell is connected. For convenience of description, the ferroelectric memory cell including a switching tube and a capacitor is only described as an example in the present application, and will not be described in detail.

Referring to fig. 4 and fig. 5 together, fig. 4 is a schematic diagram illustrating a working principle of a ferroelectric memory cell according to an embodiment of the present application, and fig. 5 is a schematic diagram illustrating a control logic of a ferroelectric memory according to an embodiment of the present application. As shown in fig. 4 and 5, in some possible embodiments (e.g., at time t 1), the controller may be configured to input a fully selected on level Von (e.g., 2V) to a first word line WL connected to each ferroelectric memory cell (e.g., ferroelectric memory cell 1a and ferroelectric memory cell 1 b) in the target row, and to input an off level Voff (e.g., 0V) to a second word line WL connected to each ferroelectric memory cell (e.g., ferroelectric memory cell 2a and ferroelectric memory cell 2 b) in the non-target row, and to input a first write level Vb1 (e.g., 0.8V) as a transmission level of the bit line BL to each ferroelectric memory cell connected to each ferroelectric memory cell in the target row. Here, the off-level Voff is smaller than the chip select on-level Vsel (e.g., 0.5V), and the first write level Vb1 is greater than 0 and smaller than the full select on-level Von. The controller here may also input the second write level-Vp 1 to the plate line PL to which each ferroelectric memory cell in the target row is connected as a transfer level (e.g., -0.7V) of the plate line PL to store the first data (e.g., "1") to each ferroelectric memory cell in the target row (as shown in part (a) of fig. 4, at this time, the polarization direction of the capacitor in each ferroelectric memory cell in the target row is upward (the direction of the applied electric field is downward)). Here, the second write level-Vp 1 is smaller than 0.

It will be appreciated that the off level Voff herein is a level (e.g., 0V) that may cause each ferroelectric memory cell in the non-target row to be turned off, the all-selected on level Von herein is a level that may cause each ferroelectric memory cell in the target row to be turned on (where the all-selected on level Von is less than or equal to a maximum level that the control terminal of the ferroelectric memory cell can withstand), and the first write level Vb1 herein is less than or equal to the all-selected on level Von minus the on voltage Vth of the ferroelectric memory cell (where the on voltage Vth may be a minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell when turned on). That is, when the controller inputs the all-selected on level Von to the first word line WL to which each ferroelectric memory cell in the target row is connected and inputs the first write level Vb1 to the bit line BL, each ferroelectric memory cell in the target row is turned on. It is further understood that the first writing level Vb1 is greater than the second writing level-Vp 1, and the difference between the first writing level Vb1 and the second writing level-Vp 1 is greater than or equal to the read-write voltage Vwr of the ferroelectric memory cell (here, the read-write voltage Vwr may be a minimum applied voltage that causes the ferroelectric memory cell to be polarized in the electric field direction of the applied voltage, and still maintains the polarization after the applied voltage is removed). That is, when each ferroelectric memory cell in the target row is in the on state, the controller inputs the second write level-Vp 1 as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first write level Vb 1), the first data can be written to each ferroelectric memory cell in the target row.

By adopting the embodiment of the application, when the transmission level (for example, the first writing level Vb1 or the second writing level-Vp 1) is lower, data (for example, first data) can be written into the ferroelectric memory cells of the target row, the limitation of the size of the ferroelectric memory cells on the transmission level (for example, the smaller the size of the ferroelectric memory cells is, the smaller the maximum level which can be born by the control end or the first end of the ferroelectric memory cells is), and when the transmission level of the transmission line connected with each end of the ferroelectric memory cells is fixed, the size of the ferroelectric memory cells can be reduced, and the storage density of data storage is improved; when the size of the ferroelectric memory cell is fixed, the voltage between the transmission levels of the transmission lines to which the respective ends of the ferroelectric memory cell are connected (for example, the voltage between the first writing level Vb1 and the second writing level-Vp 1) can be increased, and the sensitivity and stability of data storage can be improved.

Referring again to fig. 5, in some possible embodiments (e.g., at time t 2), the controller may be further configured to input a third write level Vb0 as a transmission level (e.g., 0V) of the bit line BL to the bit line BL connected to the target ferroelectric memory cells (e.g., ferroelectric memory cell 1 b) in the target row, and to input the first write level Vb1 to the bit line BL connected to the non-target ferroelectric memory cells (e.g., ferroelectric memory cell 1 a) in the target row, and to input the chip select on level Vsel to the first word line WL connected to each of the ferroelectric memory cells (e.g., ferroelectric memory cell 1b and ferroelectric memory cell 1 b) in the target row to turn on the target ferroelectric memory cells in the target row and turn off the other non-target ferroelectric memory cells in the target row. Here, the third write level Vb0 is smaller than the chip select on level Vsel, which is smaller than the first write level Vb1, and is greater than or equal to the off level Voff. The controller herein may also input the fourth write level Vp0 as a transfer level (e.g., 1.5V) of the plate line PL to which each ferroelectric memory cell in the target row is connected, to store the second data (e.g., "0") to the target ferroelectric memory cell in the target row. Here, the fourth write level Vp0 is greater than the first write level Vb1.

It will be appreciated that the chip select on level Vsel herein is a level that may cause a portion of the ferroelectric memory cells (e.g., ferroelectric memory cell 1 b) in the target row to be turned on and a portion of the ferroelectric memory cells (e.g., ferroelectric memory cell 1 a) to be turned off, and that the third write level Vb0 herein is less than the chip select on level Vsel minus the on voltage Vth of the ferroelectric memory cells, and the first write level Vb1 herein is greater than the chip select on level Vsel minus the on voltage Vth of the ferroelectric memory cells. That is, when the controller inputs the chip select on level Vsel to the first word line WL connected to each ferroelectric memory cell in the target row and inputs the third write level Vb0 to the bit line BL connected to the target ferroelectric memory cell, the target ferroelectric memory cell is turned on. When the controller inputs the chip select on level Vsel to the first word line WL connected to each ferroelectric memory cell in the target row and inputs the first write level Vb1 to the bit line BL connected to the non-target ferroelectric memory cell, the non-target ferroelectric memory cell is turned off. It is further understood that the fourth writing level Vp0 is greater than the third writing level Vb0, and the difference between the fourth writing level Vp0 and the third writing level Vb0 is greater than or equal to the read-write voltage Vwr of the ferroelectric memory cell. That is, when the target ferroelectric memory cell is in the on state, the controller inputs the fourth write level Vp0 to the plate line PL to which the target ferroelectric memory cell is connected (at this time, the transfer level of the bit line BL to which the target ferroelectric memory cell is connected is the third write level Vb 0), and the second data can be written to the target ferroelectric memory cell (as shown in part (b) of fig. 4, at this time, the polarization direction of the capacitor in the target ferroelectric memory cell in the target row is downward (the direction of the applied electric field is upward), that is, the polarization direction of the capacitor in the target ferroelectric memory cell is inverted). Meanwhile, the level of the bit line BL connected to the non-target ferroelectric memory cell is the first write level Vb1, the non-target ferroelectric memory cell is in an off state, and the process of writing the second data into the target ferroelectric memory cell does not interfere with the first data already stored in the non-target ferroelectric memory cell (as shown in part (c) of fig. 4, at this time, the polarization direction of the capacitor in the non-target ferroelectric memory cell in the target row is upward (although the direction of the external electric field of the non-target ferroelectric memory cell is downward at this time, the voltage generated by the external electric field is borne by the switching tube in the non-target ferroelectric memory cell, and the polarization direction of the capacitor is not changed), that is, the polarization direction of the capacitor in the non-target ferroelectric memory cell is not inverted). By adopting the implementation mode provided by the application, the controller can be prevented from interfering the data stored in the non-target ferroelectric memory unit when writing the data into the target ferroelectric memory unit, and the reliability and stability of data storage are improved.

In some possible embodiments, the controller may be further configured to input the third write level Vb0 to the bit line BL connected to the target ferroelectric memory cell in the target row and to input the fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row when the first write level Vb1 is input to the bit line BL connected to the non-target ferroelectric memory cell in the target row (e.g., at time t2 in fig. 5) to reduce the voltage of the capacitor of each ferroelectric memory cell in the target row. Here, the fifth write level is greater than the third write level Vb0 and less than or equal to the first write level Vb1. For convenience of description, the fifth write level is equal to the first write level Vb1 (e.g., 0.8V) in the present application, but all the level values provided in the present application are not limited to the values listed in the embodiments, but may be other values that can implement the embodiments of the present application.

It will be appreciated that when the controller inputs a fifth write level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which the target ferroelectric memory cell is connected is the third write level Vb 0), the voltage across the capacitor in the target ferroelectric memory cell is reduced from the difference between the third write level Vb0 and the fourth write level Vp0 to the difference between the third write level Vb0 and the fifth write level (where the voltage borne by the capacitor is the absolute value of the level difference between the first plate and the second plate, for example, from 1.5V to 0.8V). When the controller inputs a fifth write level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which the non-target ferroelectric memory cell is connected is the first write level Vb 1), the voltage across the capacitor in the target ferroelectric memory cell is reduced from the difference between the first write level Vb1 and the fourth write level Vp0 to the difference between the first write level Vb1 and the fifth write level (where the voltage borne by the capacitor is the absolute value of the level difference between the first plate and the second plate, for example, from 0.7V to 0V). It will further be appreciated that when the controller inputs the chip select on level Vsel to the first word line WL to which each ferroelectric memory cell in the target row is connected, the non-target ferroelectric memory cell is turned off, and at this time, the level difference (e.g., 0.7V) between the control terminal (the chip select on level Vsel) of the ferroelectric memory cell in the non-target ferroelectric memory cell and the second terminal (the fourth write level Vp 0) of the ferroelectric memory cell is mainly assumed by the control terminal of the switching transistor and the second terminal of the switching transistor, and the capacitance in the non-target ferroelectric memory cell only needs to be assumed to be the difference (e.g., 0V) between the first write level Vb1 and the fifth write level. By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

In some possible embodiments, the controller may further comprise a plurality of reading units. Referring to fig. 6, fig. 6 is another schematic structural diagram of a ferroelectric memory according to an embodiment of the present application. As shown in fig. 6, here, a first terminal of a ferroelectric memory cell located in the same column among the plurality of ferroelectric memory cells is connected to a first terminal of one of the plurality of read cells through the same bit line BL, and a second terminal of each of the plurality of read cells is connected to a reference ground.

In some possible embodiments, the controller (e.g., at time t5 in fig. 5) may be further configured to input a first read level to the bit line BL connected to each ferroelectric memory cell in the target row, a fully selected on level Von to the first word line WL connected to each ferroelectric memory cell in the target row, and an off level Voff to the second word line WL connected to each ferroelectric memory cell in the non-target row to turn on each ferroelectric memory cell in the target row. Here, the first read level is equal to the first write level Vb1.

In some possible implementations, the read unit may be a capacitor. Fig. 7 is a schematic diagram of another structure of a ferroelectric memory according to an embodiment of the present application. As shown in fig. 7, in the reading unit, the first electrode plate of the capacitor may be used as the first end of the reading unit to be connected to the bit line connected to the reading unit, and the second electrode plate of the capacitor may be used as the second end of the reading unit to be connected to the reference ground. The controller may also be configured to control the first ends of the read units connected to the ferroelectric memory cells in the target row to float (e.g., the controller may control the switch Ta and the switch Tb to turn off or otherwise control the first ends of the read units a and b to float, i.e., control the first ends of the capacitors Ca and Cb to float), and input a second read level to the plate line PL connected to the ferroelectric memory cells in the target row to read the data stored in the ferroelectric memory cells in the target row by the read units connected to the ferroelectric memory cells in the target row. Here, the second read level is equal to the second write level-Vp 1.

It will be appreciated that as shown at times t5-t6 in fig. 5, when the controller inputs the all-selected on level Von to the first word line WL to which each ferroelectric memory cell in the target row is connected and inputs the first read level to the bit line BL to which each ferroelectric memory cell in the target row is connected, each ferroelectric memory cell in the target row is turned on. When each ferroelectric memory cell in the target row is in an on state, the controller inputs a second read level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transmission level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first read level), the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row in which the first data is stored is not inverted, almost no electric charge is discharged, the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row in which the second data is stored is inverted, a large amount of electric charge is discharged to the read cell, and further, the data stored in each ferroelectric memory cell in the target row can be read through the read cell to which each ferroelectric memory cell in the target row is connected. By adopting the embodiment of the application, the data reading operation is simple, the convenience and applicability of data storage can be improved, the data storage and reading efficiency can be improved, and the data storage cost can be reduced.

In some possible embodiments, the controller may further comprise at least one comparison circuit. Referring to fig. 8, fig. 8 is a schematic diagram illustrating the operation principle of the comparison circuit according to the embodiment of the application. As shown in fig. 8, the comparison circuit may be connected to the first terminal of the target reading unit. The comparison circuit may be configured to obtain a data read level of the first end of the target read unit, obtain the data stored in the ferroelectric memory cell connected to the target read unit as first data when the data read level is greater than or equal to a level threshold, and obtain the data stored in the ferroelectric memory cell connected to the target read unit as second data when the data read level is less than the level threshold.

In some possible embodiments, referring again to fig. 5, when the ferroelectric memory cells include a switch tube and a capacitor, as shown at time t4 in fig. 5, the controller may be further configured to input a first read level to the plate line PL connected to each ferroelectric memory cell in the target row to precharge the capacitor of each ferroelectric memory cell in the target row when the first read level is input to the bit line BL connected to each ferroelectric memory cell in the target row.

That is, when the controller inputs the first read level to the bit line BL connected to each ferroelectric memory cell in the target row (i.e., before the controller inputs the all-selected on level Von to the first word line WL connected to each ferroelectric memory cell in the target row), the first read level may be input to the plate line PL connected to each ferroelectric memory cell in the target row to precharge the capacitance of each ferroelectric memory cell in the target row (i.e., raise the level of the second plate of the capacitance of each ferroelectric memory cell in the target row to the first read level), preventing the polarization direction of the ferroelectric memory cell from being inverted to interfere with the data stored in the ferroelectric memory cell when the controller inputs the all-selected on level Von to the first word line WL connected to each ferroelectric memory cell in the target row. By adopting the implementation mode provided by the application, the capacitor in each ferroelectric memory cell in the target row can be precharged before data is read, so that the stability of data storage is improved, and the accuracy and the efficiency of data storage and reading are improved.

In some possible embodiments, as shown at time t6 in fig. 5, the controller may be further configured to input a first write level Vb1 to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row, and input a third write level Vb0 to the bit line BL connected to the ferroelectric memory cell storing the second data in the target row, and input a chip select on level Vsel to the first word line WL connected to each of the ferroelectric memory cells in the target row, to turn on the ferroelectric memory cell storing the second data in the target row, and turn off the ferroelectric memory cell storing the first data in the target row. The controller herein may also be used to input the fourth write level Vp0 to the plate line PL connected to each ferroelectric memory cell in the target row to restore the second data to the ferroelectric memory cell storing the second data in the target row.

It will be appreciated that after a data read is performed, the polarization direction of the ferroelectric memory cell storing the first data in the target row will not be flipped, while the polarization direction of the ferroelectric memory cell storing the second data will be flipped again to the pre-read state for long-term storage of the data in order to maintain data stability. That is, when the controller inputs the first write level Vb1 to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row and inputs the chip select on level Vsel to the first word line WL connected to each of the ferroelectric memory cells in the target row, the ferroelectric memory cell storing the first data is turned off. When the controller inputs the third write level Vb0 to the bit line BL connected to the ferroelectric memory cells storing the second data in the target row and inputs the chip select on level Vsel to the first word line WL connected to each of the ferroelectric memory cells in the target row, the ferroelectric memory cells storing the second data are turned on. Further, when the ferroelectric memory cell storing the second data in the target row is in the on state, the controller inputs the fourth write level Vp0 to the plate line PL to which the ferroelectric memory cell storing the second data in the target row is connected (at this time, the transfer level of the bit line BL to which the ferroelectric memory cell storing the second data is connected is the third write level Vb 0), and can rewrite the second data to the ferroelectric memory cell storing the second data in the target row. Meanwhile, the level of the bit line BL connected with the ferroelectric memory cell storing the first data in the target row is the first writing level Vb1, the ferroelectric memory cell storing the first data in the target row is in an off state, and the process of rewriting the second data into the ferroelectric memory cell storing the second data in the target row does not interfere with the first data stored in the ferroelectric memory cell storing the first data in the target row. By adopting the embodiment of the application, the data can be rewritten into the ferroelectric memory unit after the data is read, and the controller is prevented from interfering the first data stored in the ferroelectric memory unit for storing the first data when rewriting the second data into the ferroelectric memory unit for storing the second data, thereby improving the reliability and stability of data storage.

In some possible embodiments, referring again to time t6 in fig. 5, when the ferroelectric memory cells include a switching transistor and a capacitor, the controller may be further configured to input a first write level Vb1 to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row and to input a third write level Vb0 to the bit line BL connected to the ferroelectric memory cell storing the second data in the target row, and to input a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row, so as to reduce the voltage of the capacitor of each ferroelectric memory cell in the target row. By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

Referring to fig. 9, fig. 9 is a flow chart illustrating a control method of a ferroelectric memory array according to an embodiment of the application. As shown in fig. 9, the detection method is applicable to the controller shown in any one of fig. 1 to 8, and includes the following steps:

and S701, when the controller inputs the full selection conduction level to the word line connected with each ferroelectric memory cell in the target row and the transmission level input to the plate line connected with each ferroelectric memory cell in the target row is smaller than 0, the controller inputs the transmission level to the bit line connected with each ferroelectric memory cell in the target row so as to write the first data into each ferroelectric memory cell in the target row.

S702: when the controller inputs a chip select on level to the word line connected to each ferroelectric memory cell in the target row, the controller inputs a transfer level to the bit line and the plate line connected to each ferroelectric memory cell in the target row to write the second data into the target ferroelectric memory cell.

In the present application, the controller may input a transfer level to the bit line BL connected to each ferroelectric memory cell in the target row to write the first data to each ferroelectric memory cell in the target row when the full selection on level Von is input to the first word line WL connected to each ferroelectric memory cell in the target row and the transfer level input to the plate line PL connected to each ferroelectric memory cell in the target row is less than 0. Here, the transfer level of the bit line BL to which each ferroelectric memory cell in the target row is connected is less than or equal to the all-selected on level Von minus the on voltage Vth of the ferroelectric memory cell, and is greater than or equal to the transfer level of the plate line PL plus the read-write voltage Vwr of the ferroelectric memory cell. At this time, since the transfer level of the plate line PL is less than 0, the transfer level of the bit line BL can be not more than the maximum level that this ferroelectric memory cell can withstand minus the on voltage Vth of the ferroelectric memory cell while satisfying that the difference from the transfer level of the plate line PL is greater than or equal to the read-write voltage Vwr of the ferroelectric memory cell. Here, the controller may also input a transfer level to the bit line BL and the plate line PL connected to each ferroelectric memory cell in the target row to control the target ferroelectric memory cell in the target row to be turned on and control other non-target ferroelectric memory cells in the target row to be turned off when the chip select on level Vsel is input to the first word line WL connected to each ferroelectric memory cell in the target row, and write the second data into the target ferroelectric memory cell. Here, the transmission level of the bit line BL connected to the target ferroelectric memory cell is less than or equal to the chip select on level Vsel minus the on voltage Vth of the ferroelectric memory cell, and the transmission level of the bit line BL connected to the non-target ferroelectric memory cell is greater than the chip select on level Vsel minus the on voltage Vth of the ferroelectric memory cell. By adopting the embodiment of the application, when the transmission level (for example, the transmission level of the bit line BL or the transmission level of the plate line PL connected with each ferroelectric memory cell in the target row) is low, data (for example, first data) can be written into the ferroelectric memory cell, the target ferroelectric memory cell is conducted and the non-target ferroelectric memory cell is turned off through controlling the transmission level of the bit line BL connected with the ferroelectric memory cell, further data (for example, second data) is written into the target ferroelectric memory cell, and the controller is prevented from writing data (for example, second data) into the target ferroelectric memory cell to interfere the data stored by the non-target ferroelectric memory cell, so that the reliability, stability and storage density of data storage are improved.

In some possible embodiments, please refer to fig. 10, fig. 10 is another flow chart of a control method of the ferroelectric memory array according to an embodiment of the present application. As shown in fig. 10, the detection method includes the steps of:

s801: the controller inputs a full selection on level to the word line connected with each ferroelectric memory cell in the target row, inputs an off level to the second word line connected with each ferroelectric memory cell in the non-target row, and inputs a first writing level to the bit line connected with each ferroelectric memory cell in the target row as a transmission level of the bit line so as to conduct each ferroelectric memory cell in the target row.

In some possible embodiments, the controller may input the all-selected on level Von to the first word line WL connected to each ferroelectric memory cell in the target row, input the off level Voff to the second word line WL connected to each ferroelectric memory cell in the non-target row, and input the first write level Vb1 to the bit line BL connected to each ferroelectric memory cell in the target row as the transmission level of the bit line BL to turn on each ferroelectric memory cell in the target row. Here, the off-level Voff is smaller than the chip select on-level Vsel, and the first write level Vb1 is greater than 0 and smaller than the full select on-level Von. The controller inputs the second write level-Vp 1 as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected. Here, the second write level-Vp 1 is smaller than 0.

It will be appreciated that the off level Voff herein is a level (e.g., 0V) that may cause each ferroelectric memory cell in the non-target row to be turned off, the all-selected on level Von herein is a level that may cause each ferroelectric memory cell in the target row to be turned on (where the all-selected on level Von is less than or equal to a maximum level that the control terminal of the ferroelectric memory cell can withstand), and the first write level Vb1 herein is less than or equal to the all-selected on level Von minus the on voltage Vth of the ferroelectric memory cell (where the on voltage Vth may be a minimum voltage between the control terminal and the first terminal of the ferroelectric memory cell when turned on). That is, when the controller inputs the all-selected on level Von to the first word line WL to which each ferroelectric memory cell in the target row is connected and inputs the first write level Vb1 to the bit line BL, each ferroelectric memory cell in the target row is turned on. It is further understood that the first writing level Vb1 is greater than the second writing level-Vp 1, and the difference between the first writing level Vb1 and the second writing level-Vp 1 is greater than or equal to the read-write voltage Vwr of the ferroelectric memory cell (here, the read-write voltage Vwr may be a minimum applied voltage that causes the ferroelectric memory cell to be polarized in the electric field direction of the applied voltage, and still maintains the polarization after the applied voltage is removed). That is, when each ferroelectric memory cell in the target row is in the on state, the controller inputs the second write level-Vp 1 as the transfer level of the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first write level Vb 1), the first data can be written to each ferroelectric memory cell in the target row. By adopting the embodiment of the application, when the transmission level (for example, the first writing level Vb1 or the second writing level-Vp 1) is lower, data (for example, first data) can be written into the ferroelectric memory cells of the target row, the limitation of the size of the ferroelectric memory cells on the transmission level (for example, the smaller the size of the ferroelectric memory cells is, the smaller the maximum level which can be born by the control end or the first end of the ferroelectric memory cells is), and when the transmission level of the transmission line connected with each end of the ferroelectric memory cells is fixed, the size of the ferroelectric memory cells can be reduced, and the storage density of data storage is improved; when the size of the ferroelectric memory cell is fixed, the voltage between the transmission levels of the transmission lines to which the respective ends of the ferroelectric memory cell are connected (for example, the voltage between the first writing level Vb1 and the second writing level-Vp 1) can be increased, and the sensitivity and stability of data storage can be improved.

S802: the controller inputs a second write level as a transfer level of the plate line to which each ferroelectric memory cell in the target row is connected, to write the first data to each ferroelectric memory cell in the target row.

S803: the controller inputs a third write level to the bit line connected with the target ferroelectric memory cells in the target row as a transmission level of the bit line, inputs a first write level to the bit line connected with the non-target ferroelectric memory cells in the target row, and inputs a chip selection conduction level to the word line connected with each ferroelectric memory cell in the target row so as to conduct the target ferroelectric memory cells in the target row and turn off other non-target ferroelectric memory cells in the target row.

S804: the controller inputs a fourth write level as a transfer level of the plate line to which each ferroelectric memory cell in the target row is connected, to write the second data to the target ferroelectric memory cell.

In some possible embodiments, the controller may input the third write level Vb0 to the bit line BL connected to the target ferroelectric memory cell in the target row, and input the first write level Vb1 to the bit line BL connected to the non-target ferroelectric memory cell in the target row, and input the chip select on level Vsel to the first word line WL connected to each ferroelectric memory cell in the target row. Here, the third write level Vb0 is smaller than the chip select on level Vsel, which is smaller than the first write level Vb1, and is greater than or equal to the off level Voff. The controller inputs the fourth write level Vp0 to the plate line PL to which each ferroelectric memory cell in the target row is connected. Here, the fourth write level Vp0 is greater than the first write level Vb1.

It will be appreciated that the chip select on level Vsel herein is a level that may cause a portion of ferroelectric memory cells (e.g., target ferroelectric memory cells) in a target row to be turned on and a portion of ferroelectric memory cells (e.g., non-target ferroelectric memory cells) to be turned off, and that the third write level Vb0 herein is less than the chip select on level Vsel minus the on voltage Vth of the ferroelectric memory cells, and the first write level Vb1 herein is greater than the chip select on level Vsel minus the on voltage Vth of the ferroelectric memory cells. That is, when the controller inputs the chip select on level Vsel to the first word line WL connected to each ferroelectric memory cell in the target row and inputs the third write level Vb0 to the bit line BL connected to the target ferroelectric memory cell, the target ferroelectric memory cell is turned on. When the controller inputs the chip select on level Vsel to the first word line WL connected to each ferroelectric memory cell in the target row and inputs the first write level Vb1 to the bit line BL connected to the non-target ferroelectric memory cell, the non-target ferroelectric memory cell is turned off. It is further understood that the fourth writing level Vp0 is greater than the third writing level Vb0, and the difference between the fourth writing level Vp0 and the third writing level Vb0 is greater than or equal to the read-write voltage Vwr of the ferroelectric memory cell. That is, when the target ferroelectric memory cell is in the on state, the controller inputs the fourth write level Vp0 to the plate line PL to which the target ferroelectric memory cell is connected (at this time, the transfer level of the bit line BL to which the target ferroelectric memory cell is connected is the third write level Vb 0), and can write the second data into the target ferroelectric memory cell (that is, the polarization direction of the target ferroelectric memory cell is inverted). Meanwhile, the level of the bit line BL connected with the non-target ferroelectric memory cell is the first writing level Vb1, the non-target ferroelectric memory cell is in an off state, and the process of writing second data into the target ferroelectric memory cell does not interfere with the first data stored in the non-target ferroelectric memory cell. By adopting the implementation mode provided by the application, the controller can be prevented from interfering the data stored in the non-target ferroelectric memory unit when writing the data into the target ferroelectric memory unit, and the reliability and stability of data storage are improved.

In some possible embodiments, when the ferroelectric memory cells include a switching transistor and a capacitor, before performing the step S803 of inputting the chip select on level to the word line connected to each ferroelectric memory cell in the target row, the method further includes: when the controller inputs the third write level Vb0 to the bit line BL connected to the target ferroelectric memory cell in the target row and inputs the first write level Vb1 to the bit line BL connected to the non-target ferroelectric memory cell in the target row, the controller inputs the fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row to reduce the voltage of the capacitance of each ferroelectric memory cell in the target row. Here, the fifth write level is greater than the third write level Vb0 and less than or equal to the first write level Vb1.

It will be appreciated that when the controller inputs the fifth write level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transfer level of the bit line BL to which the target ferroelectric memory cell is connected is the third write level Vb 0), the voltage across the capacitor in the target ferroelectric memory cell is reduced from the difference between the third write level Vb0 and the fourth write level Vp0 to the difference between the third write level Vb0 and the fifth write level. When the controller inputs a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row (at this time, the transfer level of the bit line BL connected to the non-target ferroelectric memory cell is the first write level Vb 1), the voltage across the capacitor in the target ferroelectric memory cell is reduced from the difference between the first write level Vb1 and the fourth write level Vp0 to the difference between the first write level Vb1 and the fifth write level. It will be further appreciated that when the controller inputs the chip select on level Vsel to the first word line WL to which each ferroelectric memory cell in the target row is connected, the non-target ferroelectric memory cell is turned off, and at this time, the level difference between the control terminal (the chip select on level Vsel) of the ferroelectric memory cell in the non-target ferroelectric memory cell and the second terminal (the fourth write level Vp 0) of the ferroelectric memory cell is mainly assumed by the control terminal of the switching transistor and the second terminal of the switching transistor, and the capacitance in the non-target ferroelectric memory cell only needs to assume the difference between the first write level Vb1 and the fifth write level (for example, when the fifth write level is equal to the first write level Vb1, the voltage across the capacitance is 0V). By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

S805: the controller inputs a first read level to the bit line connected to each ferroelectric memory cell in the target row, inputs a full selection on level to the word line connected to each ferroelectric memory cell in the target row, and inputs an off level to the second word line connected to each ferroelectric memory cell in the non-target row to turn on each ferroelectric memory cell in the target row.

S806: the controller controls the first ends of the reading units connected with the ferroelectric memory units in the target row to float, and inputs a second reading level to the plate line connected with the ferroelectric memory units in the target row so as to read the data stored by the ferroelectric memory units in the target row through the reading units connected with the ferroelectric memory units in the target row.

In some possible embodiments, the controller may input a first read level to the bit line BL connected to each ferroelectric memory cell in the target row, a full select on level Von to the first word line WL connected to each ferroelectric memory cell in the target row, and an off level Voff to the second word line WL connected to each ferroelectric memory cell in the non-target row to turn on each ferroelectric memory cell in the target row. Here, the first read level is equal to the first write level Vb1. The controller controls the first ends of the read units connected to the ferroelectric memory cells in the target row to float, and inputs a second read level to the plate line PL connected to the ferroelectric memory cells in the target row to read the data stored in the ferroelectric memory cells in the target row through the read units connected to the ferroelectric memory cells in the target row. Here, the second read level is equal to the second write level-Vp 1.

It will be appreciated that when the controller inputs the all-selected on level Von to the first word line WL to which each ferroelectric memory cell in the target row is connected, and inputs the first read level to the bit line BL to which each ferroelectric memory cell in the target row is connected, each ferroelectric memory cell in the target row is turned on. When each ferroelectric memory cell in the target row is in an on state, the controller inputs a second read level to the plate line PL to which each ferroelectric memory cell in the target row is connected (at this time, the transmission level of the bit line BL to which each ferroelectric memory cell in the target row is connected is the first read level), the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row in which the first data is stored is not inverted, almost no electric charge is discharged, the polarization direction of (the capacitor in) the ferroelectric memory cell in the target row in which the second data is stored is inverted, a large amount of electric charge is discharged to the read cell, and further, the data stored in each ferroelectric memory cell in the target row can be read through the read cell to which each ferroelectric memory cell in the target row is connected. By adopting the embodiment of the application, the data reading operation is simple, the convenience and applicability of data storage can be improved, the data storage and reading efficiency can be improved, and the data storage cost can be reduced.

In some possible embodiments, the controller may further include a comparison circuit that may obtain the data read level of the first end of the target read unit. When the data read level is greater than or equal to the level threshold, determining the data stored in the ferroelectric memory cell connected to the target read cell as first data. And when the data reading level is smaller than the level threshold value, determining the data stored in the ferroelectric memory cell connected with the target reading cell as second data.

In some possible embodiments, when the ferroelectric memory cells include a switching transistor and a capacitor, before the step S805 of inputting the all-selected on level Von to the first word line WL connected to each ferroelectric memory cell in the target row is performed, the method further includes: when the controller inputs the first read level to the bit line BL to which each ferroelectric memory cell in the target row is connected, the controller inputs the first read level to the plate line PL to which each ferroelectric memory cell in the target row is connected, to precharge the capacitance of each ferroelectric memory cell in the target row.

S807: the controller inputs a first write level to bit lines connected to ferroelectric memory cells in the target row that store the first data, inputs a third write level to bit lines connected to ferroelectric memory cells in the target row that store the second data, and inputs a chip select on level to word lines connected to each ferroelectric memory cell in the target row to turn on the ferroelectric memory cells in the target row that store the second data and turn off the ferroelectric memory cells in the target row that store the first data.

S808: the controller inputs a fourth write level to the plate line to which each ferroelectric memory cell in the target row is connected to restore the second data to the ferroelectric memory cells in the target row storing the second data.

In some possible embodiments, the controller may input the first write level Vb1 to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row, and input the third write level Vb0 to the bit line BL connected to the ferroelectric memory cell storing the second data in the target row, and input the chip select on level Vsel to the first word line WL connected to each of the ferroelectric memory cells in the target row to turn on the ferroelectric memory cell storing the second data in the target row and turn off the ferroelectric memory cell storing the first data in the target row. The controller inputs the fourth write level Vp0 to the plate line PL to which each ferroelectric memory cell in the target row is connected to restore the second data to the ferroelectric memory cell in the target row storing the second data.

In some possible embodiments, when the ferroelectric memory cells include a switching transistor and a capacitor, before the chip select on level Vsel is input to the first word line WL connected to each ferroelectric memory cell in the target row in step S807, the method further includes: when the controller inputs a first write level Vb1 to the bit line BL connected to the ferroelectric memory cell storing the first data in the target row and inputs a third write level Vb0 to the bit line BL connected to the ferroelectric memory cell storing the second data in the target row, the controller inputs a fifth write level to the plate line PL connected to each ferroelectric memory cell in the target row to reduce the voltage of the capacitance of each ferroelectric memory cell in the target row. By adopting the implementation mode provided by the application, when the ferroelectric memory unit is cut off, the voltage at two ends of the capacitor in the ferroelectric memory unit can be reduced, and the stability and the safety of data storage are improved.

In the application, when the transmission level (such as the transmission level of a bit line connected with each ferroelectric memory cell in a target row or the transmission level of a plate line) is low, data (such as first data) can be written into the ferroelectric memory cells, the target ferroelectric memory cells are conducted and non-target ferroelectric memory cells are turned off through controlling the transmission level of the bit line connected with the ferroelectric memory cells, and then data (such as second data) is written into the target ferroelectric memory cells, and the controller is prevented from writing data (such as second data) into the target ferroelectric memory cells to interfere the data stored in the non-target ferroelectric memory cells, so that the reliability, stability and storage density of data storage are improved.

It is to be understood that the various values of the levels recited in the present application are provided for convenience only in describing one embodiment, and that other values of the levels described herein are also within the scope of the present application.

The foregoing is merely illustrative embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about variations or substitutions within the technical scope of the present application, and the application should be covered. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims

1. A controller of a ferroelectric memory array, wherein the controller is configured to control the ferroelectric memory array, the ferroelectric memory array comprising a plurality of ferroelectric memory cells arranged in an array, a plurality of word lines WL, a plurality of plate lines PL, and a plurality of bit lines BL; memory cells in the same row of the plurality of ferroelectric memory cells are connected to the same one of the plurality of word lines WL and the same one of the plurality of plate lines PL, ferroelectric memory cells in the same column of the plurality of ferroelectric memory cells are connected to the same one of the plurality of bit lines BL, the plurality of WLs including a first WL;

The controller is configured to input a transfer level to the BL connected to each of the ferroelectric memory cells in a target row to write first data to each of the ferroelectric memory cells in the target row when the first WL connected to each of the ferroelectric memory cells in the target row is inputted with a full selection on level and a transfer level to the PL connected to each of the ferroelectric memory cells in the target row is less than 0;

the controller is further configured to input a transfer level to the BL and the PL connected to each of the ferroelectric memory cells in the target row to write second data to the target ferroelectric memory cell when the WL connected to each of the ferroelectric memory cells in the target row is on, wherein the on-chip level is less than the on-chip level.

2. The controller of claim 1, wherein the plurality of WLs further comprises a second WL in addition to the first WL;

the controller is configured to input the full selection on level to the first WL connected to each ferroelectric memory cell in the target row, input the off level to the second WL connected to each ferroelectric memory cell in a non-target row, and input the first write level to the BL connected to each ferroelectric memory cell in the target row as a transmission level of the BL to turn on each ferroelectric memory cell in the target row, where the off level is less than the chip selection on level, and the first write level is greater than 0 and less than the full selection on level;

The controller is further configured to input a second write level to the PL connected to each of the ferroelectric memory cells in the target row as a transmission level of the PL to store the first data to each of the ferroelectric memory cells in the target row, wherein the second write level is less than 0.

3. The controller of claim 2, further configured to input a third write level as a transmission level of the BL to the BL connected to a target ferroelectric memory cell in the target row, and to input the first write level to the BL connected to a non-target ferroelectric memory cell in the target row, and to input the chip select on level to the first WL connected to each of the ferroelectric memory cells in the target row to turn on a target ferroelectric memory cell in the target row and to turn off other non-target ferroelectric memory cells in the target row, wherein the third write level is less than the chip select on level and greater than or equal to the off level, the chip select on level being less than the first write level;

the controller is further configured to input a fourth write level to the PL connected to each of the ferroelectric memory cells in the target row as a transfer level of the PL to store the second data to the target ferroelectric memory cells in the target row, wherein the fourth write level is greater than the first write level.

4. A controller according to claim 3, wherein the ferroelectric memory cell comprises a switching tube and a capacitor, the control terminal of the switching tube of the ferroelectric memory cell being connected as the control terminal of the ferroelectric memory cell to the first WL to which the ferroelectric memory cell is connected, the first terminal of the switching tube being connected as the first terminal of the ferroelectric memory cell to the BL to which the ferroelectric memory cell is connected, the second terminal of the switching tube being connected to the first plate of the capacitor of the ferroelectric memory cell, the second plate of the capacitor being connected as the second terminal of the ferroelectric memory cell to the PL to which the ferroelectric memory cell is connected;

the controller is further configured to input the third write level to the BL connected to a target ferroelectric memory cell in the target row and input the fifth write level to the PL connected to each of the ferroelectric memory cells in the target row when the first write level is input to the BL connected to a non-target ferroelectric memory cell in the target row, so as to reduce a voltage of a capacitance of each of the ferroelectric memory cells in the target row, wherein the fifth write level is greater than the third write level and less than or equal to the first write level.

5. The controller according to any one of claims 1 to 4, further comprising a plurality of reading units;

the first ends of the ferroelectric memory cells in the same column in the plurality of ferroelectric memory cells are connected to the first end of one of the plurality of reading cells through the same BL, and the second end of each of the plurality of reading cells is connected to a reference ground;

the controller is further configured to input a first read level to the BL connected to each of the ferroelectric memory cells in the target row, input the all-selected on level to the first WL connected to each of the ferroelectric memory cells in the target row, and input the off level to the second WL connected to each of the ferroelectric memory cells in non-target rows to turn on each of the ferroelectric memory cells in the target row, wherein the first read level is equal to the first write level;

the controller is further configured to control a first end of a read unit connected to each of the ferroelectric memory cells in a target row to float, and input a second read level to the PL connected to each of the ferroelectric memory cells in the target row to read data stored by each of the ferroelectric memory cells in the target row through the read unit connected to each of the ferroelectric memory cells in the target row, wherein the second read level is equal to the second write level.

6. The controller of claim 5, further comprising at least one comparison circuit coupled to the first end of the target read unit;

the comparison circuit is used for acquiring a data reading level of a first end of the target reading unit, acquiring data stored in a ferroelectric storage unit connected with the target reading unit as the first data when the data reading level is greater than or equal to a level threshold value, and acquiring data stored in the ferroelectric storage unit connected with the target reading unit as the second data when the data reading level is less than the level threshold value.

7. The controller of claim 5 or 6, wherein when the ferroelectric memory cells include a switching transistor and a capacitor, the controller is further configured to input the first read level to the PL connected to each of the ferroelectric memory cells in the target row to precharge the capacitor of each of the ferroelectric memory cells in the target row when the first read level is input to the BL connected to each of the ferroelectric memory cells in the target row.

8. The controller according to any one of claims 5 to 7, wherein the controller is further configured to input the first write level to the BL connected to the ferroelectric memory cell storing the first data in the target row and to input the third write level to the BL connected to the ferroelectric memory cell storing the second data in the target row and to input the chip select on level to the first WL connected to each of the ferroelectric memory cells in the target row to turn on the ferroelectric memory cell storing the second data in the target row and to turn off the ferroelectric memory cell storing the first data in the target row;

The controller is further configured to input the fourth write level to the PL connected to each of the ferroelectric memory cells in the target row to restore the second data to the ferroelectric memory cells in the target row that store the second data.

9. The controller of claim 8, wherein when the ferroelectric memory cells include a switching transistor and a capacitor, the controller is further configured to input the fifth write level to the PL connected to each of the ferroelectric memory cells in the target row to reduce a voltage of a capacitor of each of the ferroelectric memory cells in the target row when the first write level is input to the BL connected to the ferroelectric memory cell storing the first data in the target row and the third write level is input to the BL connected to the ferroelectric memory cell storing the second data in the target row.

10. A ferroelectric memory comprising a controller according to any one of claims 1-9 and a ferroelectric memory array according to any one of claims 1-9.

11. An apparatus comprising the ferroelectric memory of claim 10 and a circuit board, the ferroelectric memory and the circuit board being electrically connected.

12. A control method of a ferroelectric memory array, wherein the method is applied to a controller of the ferroelectric memory array, and the ferroelectric memory array comprises a plurality of ferroelectric memory cells, a plurality of word lines WL, a plurality of strip lines PL and a plurality of bit lines BL which are arranged in an array; memory cells in the same row of the plurality of ferroelectric memory cells are connected to the same one of the word lines WL and the same one of the plate lines PL of the plurality of word lines WL, ferroelectric memory cells in the same column of the plurality of ferroelectric memory cells are connected to the same one of the bit lines BL, the plurality of WLs including a first WL, the method comprising:

when the controller inputs a full-select on level to the first WL connected to each of the ferroelectric memory cells in a target row and a transfer level of the PL connected to each of the ferroelectric memory cells in the target row is less than 0, the controller inputs a transfer level to the BL connected to each of the ferroelectric memory cells in the target row to write first data into each of the ferroelectric memory cells in the target row;

when the controller inputs a chip select on level to the first WL connected to each of the ferroelectric memory cells in the target row, the controller inputs a transfer level to the BL and PL connected to each of the ferroelectric memory cells in the target row to write second data into the target ferroelectric memory cell, wherein the chip select on level is smaller than the full select on level.

13. The method of claim 12, wherein the plurality of WLs further comprises a second WL in addition to the first WL, the controller inputting a transfer level to the BL connected to each of the ferroelectric memory cells in a target row when the controller inputs a full select on level to the first WL connected to each of the ferroelectric memory cells in the target row and a transfer level of the PL connected to each of the ferroelectric memory cells in the target row is less than 0, comprising:

the controller inputs the full selection on level to the first WL connected to each of the ferroelectric memory cells in the target row, inputs the off level to the second WL connected to each of the ferroelectric memory cells in non-target rows, and inputs a first write level as a transmission level of the BL to the BL connected to each of the ferroelectric memory cells in the target row to turn on each of the ferroelectric memory cells in the target row, wherein the off level is smaller than the chip selection on level, and the first write level is greater than 0 and smaller than the full selection on level;

the controller inputs a second write level as a transmission level of the PL to which each of the ferroelectric memory cells in the target row is connected, wherein the second write level is less than 0.

14. The method of claim 13, wherein the inputting, by the controller, a transfer level to the BL and PL connected to each of the ferroelectric memory cells in the target row when the controller inputs a chip select power on level to the first WL connected to each of the ferroelectric memory cells in the target row, comprises:

the controller inputs a third write level to the BL connected with the target ferroelectric memory cells in the target row as a transmission level of the BL, inputs the first write level to the BL connected with the non-target ferroelectric memory cells in the target row, and inputs the chip selection on level to the first WL connected with each ferroelectric memory cell in the target row, wherein the third write level is smaller than the chip selection on level and larger than or equal to the off level, and the chip selection on level is smaller than the first write level;

the controller inputs a fourth write level to the PL connected to each of the ferroelectric memory cells in the target row as a transfer level of the PL, wherein the fourth write level is greater than the first write level.

15. The method of claim 14, wherein the ferroelectric memory cell comprises a switch tube and a capacitor, a control terminal of the switch tube of the ferroelectric memory cell being connected as a control terminal of the ferroelectric memory cell to the first WL to which the ferroelectric memory cell is connected, a first terminal of the switch tube being connected as a first terminal of the ferroelectric memory cell to the BL to which the ferroelectric memory cell is connected, a second terminal of the switch tube being connected as a second terminal of the ferroelectric memory cell to a first plate of a capacitor of the ferroelectric memory cell, the second plate of the capacitor being connected as a second terminal of the ferroelectric memory cell to the PL to which the ferroelectric memory cell is connected, the method further comprising, prior to the inputting the chip select on level to the first WL to which each of the ferroelectric memory cells in the target row is connected:

When the controller inputs the third write level to the BL connected to the target ferroelectric memory cells in the target row and inputs the first write level to the BL connected to the non-target ferroelectric memory cells in the target row, the controller inputs a fifth write level to the PL connected to each of the ferroelectric memory cells in the target row to reduce a voltage of a capacitance of each of the ferroelectric memory cells in the target row, wherein the fifth write level is greater than the third write level and less than or equal to the first write level.

16. The method of any of claims 12-15, wherein the controller further comprises a plurality of read cells, a first terminal of a ferroelectric memory cell of the plurality of ferroelectric memory cells in a same column being connected to a first terminal of one of the plurality of read cells through a same BL, a second terminal of each of the plurality of read cells being connected to a ground reference, the method further comprising, after the writing of the second data to the target ferroelectric memory cell:

the controller inputs a first read level to the BL connected to each of the ferroelectric memory cells in the target row, inputs the full-selected on level to the first WL connected to each of the ferroelectric memory cells in the target row, and inputs the off level to the second WL connected to each of the ferroelectric memory cells in non-target rows to turn on each of the ferroelectric memory cells in the target row, wherein the first read level is equal to the first write level;

The controller controls a first end of a read unit connected to each of the ferroelectric memory cells in a target row to float and inputs a second read level to the PL connected to each of the ferroelectric memory cells in the target row to read data stored by each of the ferroelectric memory cells in the target row through the read unit connected to each of the ferroelectric memory cells in the target row, wherein the second read level is equal to the second write level.

17. The method of claim 16, wherein the controller further comprises at least one compare circuit connected to a first terminal of a target read cell, the method further comprising, after the PL input second read level to each of the ferroelectric memory cells in the target row:

the comparison circuit obtains a data reading level of a first end of the target reading unit;

when the data reading level is greater than or equal to a level threshold, determining that the data stored in the ferroelectric memory cell connected to the target reading cell is the first data;

and when the data reading level is smaller than the level threshold value, determining the data stored in the ferroelectric memory cell connected with the target reading cell as the second data.

18. The method of claim 16 or 17, wherein when the ferroelectric memory cells include a switching tube and a capacitor, before the inputting of the all-selected turn-on level to the first WL connected to each of the ferroelectric memory cells in the target row, the method further comprises:

when the controller inputs the first read level to the BL connected to each of the ferroelectric memory cells in the target row, the controller inputs the first read level to the PL connected to each of the ferroelectric memory cells in the target row to precharge the capacitance of each of the ferroelectric memory cells in the target row.

19. The method of any of claims 16-18, wherein after said inputting a second read level to the PL connected to each of the ferroelectric memory cells in the target row, the method further comprises:

the controller inputs the first write level to the BL connected to the ferroelectric memory cells storing the first data in the target row, inputs the third write level to the BL connected to the ferroelectric memory cells storing the second data in the target row, and inputs the chip select on level to the first WL connected to each of the ferroelectric memory cells in the target row to turn on the ferroelectric memory cells storing the second data in the target row and turn off the ferroelectric memory cells storing the first data in the target row;

The controller inputs the fourth write level to the PL connected to each of the ferroelectric memory cells in the target row to restore the second data to the ferroelectric memory cells storing the second data in the target row.

20. The method of claim 19, wherein when the ferroelectric memory cells include a switching transistor and a capacitor, the method further comprises, prior to the inputting the chip select on level to the first WL connected to each of the ferroelectric memory cells in the target row:

when the controller inputs the first write level to the BL connected to the ferroelectric memory cells storing the first data in the target row and inputs the third write level to the BL connected to the ferroelectric memory cells storing the second data in the target row, the controller inputs the fifth write level to the PL connected to each of the ferroelectric memory cells in the target row to reduce a voltage of a capacitance of each of the ferroelectric memory cells in the target row.