CN116860498A

CN116860498A - Watchdog dormancy and timing awakening method and integrated circuit

Info

Publication number: CN116860498A
Application number: CN202310772293.4A
Authority: CN
Inventors: 陈昀; 陈宇轩
Original assignee: Individual
Current assignee: Individual
Priority date: 2023-06-15
Filing date: 2023-06-27
Publication date: 2023-10-10

Abstract

A watchdog dormancy and timing wake-up method and integrated circuit belong to the integrated circuit field, it mainly comprises: the watchdog logic circuit unit 1, the overlength timer circuit unit 2, the logic and control circuit unit 3 and the power supply circuit unit 4. The circuit mainly used for using the program processor can be used without using the processor. The main function of the invention is to ensure the reliable timed awakening during the dormancy period of the program processor or the equipment controlled by the invention by outputting the awakening pulse, the awakening detection function and the reset function besides the timing function; the secondary function is to ensure reliable and safe operation during operation of the program processor or device controlled by the present invention by means of the watchdog logic circuit unit 1 and the logic and control circuit unit 3. The watchdog function and the timer function can be closed or dormant, and the watch dog function and the timer function are particularly suitable for battery-powered Internet of things equipment, space aviation aircrafts, military equipment with a silence function and the like, and ensure safe and reliable operation of the equipment and the military equipment.

Description

Watchdog dormancy and timing awakening method and integrated circuit

Technical Field

The invention belongs to the field of integrated circuits, in particular to a watchdog integrated circuit or a timer integrated circuit.

Background

In the current background art, watchdog circuits are widely used, and although the integrated circuits are not as complex as large-scale program processors, most of the integrated circuits are controlled by foreign countries such as the European America, and our countries have no or very few completely independent intellectual property rights, and the more common watchdog integrated circuits are as follows: MAX708, MAX809, TPS3828-33DBVR, NCP308, CAT823, etc. are basically governed by foreign countries. Moreover, such watchdog does not have sleep or shut down functionality, and a reset action may be triggered during program processor sleep.

In the current background, the timer circuit has: NE555, HEF4541, ICM7556, PCF8563, etc., most of which were originally intellectual property in foreign countries.

The prior watchdog technology and timer technology have the main problems that when a controlled program processor or equipment sleeps, the watchdog outputs a reset signal, so that the watchdog cannot sleep; when the controlled program processor or device is dormant, even if a timer generates a wake-up signal at regular time, the controlled program processor or device cannot be detected whether the controlled program processor or device is awakened; if not awakened, the user cannot awaken again; the reset action cannot be generated under the condition of wake-up failure; the use of both a watchdog and a timer also creates a power consumption problem. In addition, in the current background technology, no integrated circuit can simultaneously meet the requirements of reliably waking up after long-time dormancy, ensuring reliable operation after waking up and ensuring enough low power consumption for some devices with long dormancy requirements such as internet of things monitoring equipment for one report a day, outer space aviation aircrafts, military equipment with a silencing function and the like.

The invention aims to solve some defects of a program processor, a watchdog and a timer, and particularly aims to solve the problems that the program processor is possibly halted accidentally, cannot be reliably awakened after dormancy, is reset and restarted once entering dormancy due to the action of an external watchdog, and is periodically awakened at regular time and sporadically awakened and fails, and the like, and utilizes the existing digital logic technology, such as a gate trigger circuit and the like, to effectively fuse the watchdog circuit, the timer circuit and a digital logic control circuit together so as to realize the safe and reliable purpose of guaranteeing the program operation of the program processor. The system is particularly suitable for battery-powered Internet of things equipment, outer space aviation aircrafts, military equipment with a silencing function and the like, and ensures safe and reliable operation of the equipment and the military equipment.

Disclosure of Invention

The watchdog dormancy and timing wake-up method and integrated circuit mainly comprises a watchdog logic circuit unit 1, an ultra-long timer circuit unit 2, a logic and control circuit unit 3 and a power supply circuit unit 4, wherein the watchdog logic circuit unit 1 and the ultra-long timer circuit unit 2 both control the logic and control circuit unit 3 and are also controlled by the logic and control circuit unit 3, and the power supply circuit unit 4 supplies power for the normal work of all the partial circuits. See figure one.

Under the combined action of the circuit units, the invention has the functions of watchdog, timer, start/time reset and time setting, especially wake-up function, wake-up detection function and wake-up failure reset, and can ensure the safe, accurate and reliable operation of the program processor or equipment with sleep state controlled by the invention.

The advantages are that: 1, it is more intelligent and intelligent than the conventional watchdog integrated circuit, because it is not only the watchdog and the timer, but also understands the sleep control, can ensure the reliable operation of the program processor; 2, its watchdog function may sleep or shut down; 3, which is longer than the conventional timer integrated circuit timing time, can exceed 24 hours; and 4, the device is provided with a higher-level logic control circuit, and can effectively ensure the safe and reliable operation and dormancy of the controlled program processor. 5, the application is wide: the circuit can be applied to various circuits, not only can be used for circuits using a program processor, but also can be used for simple circuits without using the processor, and the circuit can be widely applied to civil, industrial, automobile, steamship, aerospace, weapon, national defense, toys and the like.

The invention has the following function PINs PIN: see figure two

1, power supply positive VDD Power supply positive

2, negative VSS power supply

3 reset input MR reset pulse input

4, outputting RESET pulse in abnormal condition of RESET output

5 wake-up output WKUP_OUT wake-up pulse output

6, wake-up detection success_in detection

7, watchdog pulse input WDI watchdog feeding pulse input

8, setting TSET0/DATA master timing set/IO mode or I2C mode

9, setting TSET1/CLK main timing setting/IO mode or I2C mode

10, set TSET2/MODE Master timing setup/MODE selection

11, multifunctional MF multifunctional settings

12, start run/timing reset

The main scope of the function pins according to the connection relation is divided as follows: the "power supply positive VDD" pin and the "power supply negative VSS" pin are assigned to the power supply circuit unit 4; the 'watchdog pulse input WDI' pin is attributed to the watchdog logic circuit unit 1; the remaining pins are assigned to the logic and control circuit unit 3. The "wake-up detect_in" pin controls only the overlength timer circuit unit 2; the START pin simultaneously controls the watchdog logic circuit unit 1 and the overlength timer circuit unit 2; the three pins of TSET0/DATA, TSET1/CLK and TSET2/MODE only control the ultra-long timer circuit unit 2; the 'wake-up output WKUP_OUT' pin only outputs a control signal by the overlength timer circuit unit 2; the RESET pin is controlled by the RESET input MR pin, the watchdog logic circuit unit 1 and the overlength timer circuit unit 2 to output a RESET signal.

The watchdog logic circuit is controlled by the START pin of the invention, so that the timer unit and the watchdog unit work in a time-sharing way, and the logic and control circuit unit 3 is connected with a trigger, so that the watchdog logic does not trigger a reset action when the program processor is dormant. The time-sharing working principle is as follows: the "START" pin, or "START run/time reset" pin, is typically low and when it receives a logic high pulse from either the inside or outside of the integrated circuit, the rising edge of the trigger triggers a generating action which causes the watchdog logic portion of the integrated circuit of the present invention to cease operation while the timer portion STARTs timing. The pause of the watchdog logic portion is equivalent to the dormancy of the watchdog circuit, so that the program processor is not reset and restarted by a reset signal output by the watchdog because the watchdog is not fed due to the dormancy. When the program is in a non-dormant running state, the watchdog circuit can still normally receive a watchdog feeding signal from a program processor or equipment from a watchdog pulse input WDI pin, and once the program is abnormal, the watchdog unit can still output a RESET signal through a RESET output RESET pin to RESET the program processor. If the program processor needs to sleep, the watchdog must be turned off, and only an adapted logic pulse level needs to be given to this pin. The pulse level can promote the watchdog to be closed, thereby achieving the purposes of preventing misoperation and reducing power consumption. It gates whether the watchdog circuit is running or the timer circuit is running. Since a timer is required to generate a timed wake-up output during sleep, the programmed processor is controlled to wake-up at a timed time. Therefore, this function is significant for the accurate action of the post-sleep timed wake-up function and the accurate operation of the watchdog during program processor operation. And the power consumption of the integrated circuit can be conveniently controlled.

The "wake-up output WKUP_OUT" pin and the "wake-up detect SUCCESS_IN" pin of the present invention are the most important control logic of the present invention. When the timing period of the ultra-long timer circuit unit 2 is finished, a timing wake-up pulse is required to be output to control the program processor to resume operation, and the control pulse outputs the wake-up pulse from the ultra-long timer circuit unit 2 through a 'wake-up output WKUP_OUT' pin of the logic and control circuit unit 3 to wake up the program processor or equipment in a dormant state, which is controlled by the invention. Then, the voltage change of the 'wake-up detection SUCCESS_IN' pin is used for judging whether the program processor or the equipment controlled by the invention is woken up or not, and the pin is connected to the output port of the woken-up processor or the equipment.

Its 3-cycle principle: as described above, if the detection result is successful, the "wake-up output WKUP_OUT" pin does not output the control pulse any more, and if the detection result is failed, the "wake-up output WKUP_OUT" pin outputs the control pulse again or continues to output the control pulse, and the cycle is 3-5 times. If the end of the cycle still does not detect that the program processor is awakened, the internal part of the integrated circuit of the invention starts a RESET action, and a RESET pulse is output from a RESET output RESET pin to control the RESET of the program processor.

And (3) time delay interaction: as described above, after the program processor is successfully awakened, the integrated circuit internal logic and control circuit unit 3 sends a control voltage signal to the "START" pin to control the internal circuit thereof to generate voltage change, so as to control the watchdog logic circuit unit 1 to START running and the ultra-long timer circuit unit 2 to be turned off, and after waiting for 20ms, the "START" pin is handed over to the program processor or the device for taking over. The brief logic flow is shown in the third figure.

The invention not only can wake up the controlled program processor or equipment at regular time, but also can detect and judge whether the controlled program processor or equipment is successfully woken up, and has the function of forcibly resetting and restarting the controlled program processor after a plurality of attempts still fail under the condition of wake-up failure, thereby ensuring safe and reliable wake-up operation of the controlled program processor in a dormant state.

The timer of the present invention has a longer time than conventional timers, which may be longer than 24 hours, typically 24 hours +10 minutes or 25 hours, and may be rated for special treatment not hours but days. Moreover, the timing time is controlled by the input logic levels of three IO ports of TSET0, TSET1 and TSET2 or the I2C digital signals of two IO ports of TSET0 and TSET1, when the 'set TSET 2/MODE' pin is set to be in a common IO MODE, 4 fixed timing time periods exist, and when the 'set TSET 2/MODE' pin is set to be in an I2C MODE, the timing time period can be set arbitrarily.

The combination is as follows:

note that: the pins TSET0/DATA are abbreviated as TSET0, TSET1/CLK are abbreviated as TSET1, and TSET2/MODE are abbreviated as TSET2

Other description of the invention:

a RESET circuit is output when the controlled program processor and the circuit thereof have abnormal conditions, the RESET pulse is output, the input of the RESET pulse is output from three sources of logical OR, firstly, the RESET pulse is output from a watchdog circuit, when the program of the program processor is in an operation state and fails and cannot be fed, the watchdog circuit is fed with the pulse required by the maintenance state of the watchdog circuit, the pulse is input by a 'watchdog pulse input WDI' pin, and the watchdog circuit outputs the RESET pulse to the program processor through the 'RESET output RESET' pin; secondly, from the timer circuit, when the program of the program processor is in a dormant state and the timing period of the timer arrives, if the integrated circuit of the invention sends a wake-up pulse to the wake-up output WKUP_OUT pin for 3-5 times and still cannot wake the program processor to enter a working state, the timer related circuit outputs a RESET pulse to the RESET output RESET pin; and thirdly, from a RESET input MR pin, when the pin receives a RESET signal, the related circuit part of the logic control circuit outputs a RESET pulse to a RESET output RESET pin. The three input sources are in logical OR relationship with each other, but the reset signal from the "reset in MR" pin can also control the timer timing cycle reset to zero.

2, judging whether the program processor is awakened from a dormant state or not through the signal level change received by the 'detect success_in' pin, if so, starting the operation of a watchdog part of the integrated circuit, ensuring the normal operation of the program processor, and closing a timer circuit; if not successfully awakened, the logic control circuit starts 3-5 times of awakening actions, and if still fails, a RESET pulse is output through a RESET output pin.

And 3, waking up the pulse output circuit. When the clock period of the timer arrives, the timer sends a wake-up notice to the logic control circuit, and the logic control circuit sends a wake-up pulse to the program processor through a wake-up output WKUP_OUT pin.

And 4, a RESET pulse input circuit inputs a RESET pulse to a RESET input MR pin, and the integrated circuit outputs the RESET pulse through a RESET output RESET pin by utilizing a digital logic circuit in the integrated circuit.

And 5, the watchdog feeding pulse input circuit inputs continuous pulses with pulse intervals not larger than a specified value to a 'watchdog pulse input WDI' pin, and when the 'START' pin is in watchdog operation logic, the watchdog circuit is ensured not to output reset pulses.

And 6, a multifunctional setting circuit, namely a multifunctional MF pin, can be externally connected with an RC circuit or other circuits, and provides an extended function for the integrated circuit or realizes ultra-long timing exceeding the self timing time of the integrated circuit through a logic and control circuit unit 3. The special function of the integrated circuit can be set through the 'multifunctional MF' pin, or other functions of the integrated circuit can be expanded, and the functions are set according to specific requirements, so that the whole integrated circuit can be further diversified and serialized to meet more application scenes.

Drawings

Fig. 1 is a block diagram of main components of the present invention:

fig. 2 is a schematic diagram of an integrated circuit pin composition according to the present invention:

fig. 3 is a schematic diagram of a partial flow:

fig. 4 is a timing diagram of the present invention:

FIG. 5 is a logic diagram of an integrated circuit control program processor of the present invention from run-sleep-run-cycle reciprocation:

Detailed Description

According to the prior digital logic gate technology, the watchdog circuit and the timer circuit are operated in a time-sharing mode according to the basic principle of the invention, which is beneficial to reducing the operation power consumption of the whole integrated circuit to a low enough level; the sleep type watchdog is controlled by the voltage change of the START pin, the watchdog can be easily closed to prevent the watchdog from illegally outputting a reset signal, the timer does not work during the working period of the watchdog, and the watchdog does not work during the working period of the timer.

For example, after the integrated circuit of the present invention is powered up, the default state of the "START" pin is low, the watchdog is turned off and the timer is running. The timing duration of the timer depends on the level states of three pins, namely a 'set TSET 2/MODE' pin, a 'set TSET 0/DATA' pin and a 'set TSET 1/CLK' pin, such as: the "set TSET2/MODE" pin level value is 0, the "set TSET0/DATA" pin, the "set TSET1/CLK" pin level value is also 0, i.e., the timing time is set to 4 hours, then 4 hours have elapsed since power-up, the integrated circuit will wake up the controlled program processor or device by outputting a wake-up pulse on the "wake-up output WKUP_OUT" pin. If the invention is applied to families, you can start the household equipment to get off duty and directly enjoy life when going out to work in the morning.

After the wake-up is successful, the logic and control circuit unit 3 in the integrated circuit outputs a changed voltage to the START-up START pin, the watchdog is restarted at the moment, and after the program processor or the equipment is started for about 20ms, the control right of the START-up START pin is not controlled by the logic and control circuit unit 3 any more and is controlled by the program processor or the equipment controlled by the invention.

When the processor or device wakes up, it begins to take over the "START" pin; meanwhile, the processor or the equipment after being awakened can continuously output a watchdog pulse to a 'watchdog pulse input WDI' pin, so that the watchdog logic circuit unit 1 starts to operate normally. If the invention is applied to the well lid monitor of the Internet of things, the well lid monitor can report the well lid state at regular time every day.

After the wake-up pulse of the "wake-up_out" pin is output, the "wake-up detection success_in" pin starts to detect whether the program processor or the device is woken up, and the default high level is not woken up, and the low level is woken up; if the multi-wake-up is unsuccessful, the logic and control circuit unit 3 outputs a RESET signal pulse on a RESET output RESET pin, so that the program processor or the equipment is restarted, and the normal operation of the program processor or the equipment is ensured not to be blocked.

And after the program processor is started, the normal operation of the program processor can be ensured by means of the watchdog, wherein the watchdog is the prior art until the program processor goes to sleep. When the program processor goes to sleep, a sleep signal is output to the START pin, so that the watchdog is closed and the timer is started for timing. The timer timing duration is further subject to three pins: TSET0/DATA is abbreviated as TSET0, TSET1/CLK is abbreviated as TSET1, control of TSET 2/MODE. The power supply circuit unit 4 limits the power consumption of the entire integrated circuit by turning on or off the power supply in addition to supplying power to the respective functional circuits.

The invention effectively solves the reset problem caused by the inability of the program processor to feed dogs in the sleep mode, and ensures that the integrated circuit has low enough power consumption, thereby meeting the power consumption requirements of the Internet of things equipment, space vehicles and military equipment with silent functions.

Claims

1. A watchdog dormancy and timing wake-up method and integrated circuit, its important characteristic lies in: the circuit mainly comprises a watchdog logic circuit unit 1, an ultra-long timer circuit unit 2, a logic and control circuit unit 3 and a power supply circuit unit 4, wherein the watchdog logic circuit unit 1 and the ultra-long timer circuit unit 2 both control the logic and control circuit unit 3 and are also controlled by the logic and control circuit unit 3, and the power supply circuit unit 4 supplies power for the normal work of each part of circuits.

2. The watchdog dormancy and timed wake-up method and the integrated circuit according to claim 1, wherein the important characteristics are that: it has the following functional PINs PIN:

3. a watchdog dormancy and timed wake-up method and integrated circuit according to claim 2, wherein the important features are: the functional pin connections are divided into the following main scope: the power supply positive VDD pin and the power supply negative VSS pin of the power supply circuit unit 4 are respectively assigned to the power supply circuit unit;

the 'watchdog pulse input WDI' pin is attributed to the watchdog logic circuit unit 1; the remaining pins are assigned to the logic and control circuit unit 3.

The 'wake-up detection success_in' pin is connected with a controlled processor or equipment, and only controls the ultra-long timer circuit unit 2; the 'START' pin is connected with a controlled processor or device and simultaneously controls the watchdog logic circuit unit 1 and the ultra-long timer circuit unit 2; the three pins of TSET0/DATA, TSET1/CLK and TSET2/MODE only control the ultra-long timer circuit unit 2; the 'wake-up output WKUP_OUT' pin only outputs a control signal by the overlength timer circuit unit 2; the RESET pin is controlled by the RESET input MR pin, the watchdog logic circuit unit 1 and the overlength timer circuit unit 2 to output a RESET signal.

4. A watchdog sleep and timed wake-up method and integrated circuit according to claims 1 and 2, characterized in that: the time-sharing working principle is that the watchdog logic circuit unit 1 and the ultra-long timer circuit unit 2 are in time-sharing working under the control of the voltage change of the START pin. When the program processor or the equipment with the dormant state controlled by the invention is dormant, the START pin receives a pulse signal sent by the program processor or the equipment, the voltage of the pulse signal is changed, the watchdog logic circuit unit 1 is closed, and the ultra-long timer circuit unit 2 STARTs to run; conversely, when the program processor or the device having the sleep state controlled by the present invention is operated, the watchdog logic circuit unit 1 starts to operate, and the overlength timer circuit unit 2 is turned off. The rising edge trigger is used in the START pin, the trigger result changes the voltage output by the trigger, and the watchdog logic circuit unit 1 and the ultra-long timer circuit unit 2 are determined to be turned off and turned on.

5. A watchdog sleep and timed wake-up method and integrated circuit according to claims 1 and 2, characterized in that: the wake-up and detection principle is that when the timing time of the ultra-long timer circuit unit 2 arrives, the ultra-long timer circuit unit 2 outputs a wake-up pulse through a 'wake-up output WKUP_OUT' pin of the logic and control circuit unit 3 to wake up the program processor or the equipment in a sleep state, which is controlled by the present invention. And determines whether the program processor or device controlled by the present invention is awakened via the "wakeup detect success_in" pin.

6. The watchdog dormancy and timed wake-up method and the integrated circuit according to claim 5, wherein the important characteristics are that: the 3-time circulation principle is that after the 'wake-up_out' pin outputs a wake-up pulse, if the 'wake-up_in_detected' pin does not detect that the program processor or the device controlled by the present invention is woken up, the 'wake-up_out' pin outputs a wake-up pulse again, then the 'wake-up_in_detected' pin detects whether the program processor or the device controlled by the present invention is woken up again, if the program processor or the device is not woken up yet, the 'wake-up_out' pin outputs a wake-up pulse for the third time, and if the program processor or the device is not woken up yet, the logic and control circuit unit 3 outputs a RESET signal to the program processor or the device controlled by the present invention through the 'reset_reset' pin, so as to cause the program processor or the device to RESET and restart. The reliable awakening of the program processor or the equipment controlled by the invention is ensured.

7. The watchdog dormancy and timed wake-up method and the integrated circuit according to claim 6, wherein the important characteristics are that: based on the principle of time delay interaction, when the 'wake-up detection success_in' pin detects that the program processor or equipment controlled by the invention is awakened, the logic and control circuit unit 3 controls the over-length timer circuit unit 2 to be closed, and the watchdog logic circuit unit 1 starts to operate. After a delay of about 20ms the time required for the program processor or device to START, the control right of the "START" pin is no longer controlled by the logic and control circuit unit 3, but is instead controlled by the program processor or device controlled by the present invention.

8. A watchdog sleep and timed wake-up method and integrated circuit according to claims 1 and 2, characterized in that: the timing principle is that the timer has two timing MODEs of setting 4 fixed timing time periods and setting arbitrary timing time periods through a 'setting TSET 2/MODE' pin and a 'setting TSET 0/DATA' pin and a 'setting TSET 1/CLK' pin. When the 'set TSET 2/MODE' pin is set to 4 fixed timing duration MODEs, 4 fixed timing durations can be set; the timing duration may be arbitrarily set when the "set TSET2/MODE" pin is set to I2C MODE.

9. A watchdog sleep and timed wake-up method and integrated circuit according to claims 1 and 2, characterized in that: the ultra-long timing and function expansion principle of the multifunctional MF pin can be externally connected with an RC circuit or other circuits, and the logic and control circuit unit 3 provides an expansion function for the integrated circuit and realizes the ultra-long timing exceeding the self timing time of the integrated circuit.