CN212276398U - Watchdog circuit capable of automatically configuring timing period - Google Patents

Abstract

The utility model discloses a watchdog circuit capable of automatically configuring timing period, which comprises a processor, wherein the processor is connected with a synchronous output timer signal, a timer overflow signal output end of the synchronous output timer is connected with an external reset module signal for resetting the synchronous output timer, and the synchronous output timer is also connected with a timer period configuration module signal for controlling the processor detection timing period, thereby forming the watchdog circuit; the processor is in signal connection with the timer period configuration module through the trigger module, so that a watchdog timer period time automatic selection circuit is formed. Through the utility model discloses can effectively strengthen the stability of system's circuit, improve the intellectuality of control, satisfy the use needs.

Description

Watchdog circuit capable of automatically configuring timing period

Technical Field

The utility model belongs to embedded electronic communication field especially relates to an automatic configuration timing cycle's watchdog circuit.

Background

In the embedded field, the stability of the processor usually requires the monitoring of the peripheral circuit, and most of the methods are to add a watchdog circuit in the peripheral circuit of the processor in the circuit. Therefore, the watchdog timer is a peripheral device which is often used for detecting whether the microprocessor is abnormal or not, the set watchdog timer is used for giving a signal given by periodically monitoring the microprocessor, if the watchdog cannot receive a trigger signal given by the processor, the working software or hardware of the microprocessor is considered to be abnormal, and the microprocessor circuit is forcibly reset after the timing time is exceeded.

At present, a watchdog is internally provided with a watchdog and an external circuit hardware watchdog, and most circuits adopt external hardware watchdog circuits. The external hardware watchdog needs to periodically feed the watchdog and needs to be controlled by software in time. The timing period of the existing watchdog circuit is fixed, generally ranges from hundreds of milliseconds to several seconds, software needs short intervals and needs to timely respond to dog feeding in an embedded system and a multitask system with strict requirements on the real-time performance of user application tasks, and the difficulty is high; some complex programs also require the flexibility to handle watchdog timer periods. In the prior art, an additional GPIO port is used to control a watchdog circuit having an unlock code, and specifically, before a microprocessor runs other real-time programs or is powered on and started, the watchdog circuit is turned off or an output signal of the watchdog circuit is blocked. Therefore, the current control method of the watchdog circuit needs to be improved in design. The existing scheme adopts a method of enabling a tri-state gate by RC delay to delay a watchdog time circuit, the RC delay circuit is not suitable for the situation of resetting in a charged restarting mode, and if a charged chip program runs away and is reset, RC delay is invalid and is only suitable for being effective when being electrified for the first time. There is a significant imperfect design and new designs are urgently needed to meet the needs of use.

SUMMERY OF THE UTILITY MODEL

The utility model aims at providing an automatic configuration timing cycle's watchdog circuit can effectively strengthen the stability of system circuit, and the intellectuality of high control satisfies the operation needs.

In order to achieve the first purpose, the utility model provides a watchdog circuit capable of automatically configuring timing cycle, comprising a processor, wherein the processor is connected with a synchronous output timer signal for monitoring the operation of the processor, wherein, a dog feeding signal output end of the processor is connected with a clearing signal end of the synchronous output timer, a synchronous signal output end of the synchronous output timer is connected with one end of the processor, a timer overflow signal output end of the synchronous output timer is connected with a reset end of the processor, a timer overflow signal output end of the synchronous output timer is further connected with an external reset module signal for resetting the synchronous output timer, an output end of the external reset module is connected with a reset end of the synchronous output timer, the synchronous output timer is further connected with a timer cycle configuration module signal for controlling the processor to detect the size of the timing cycle, thereby forming a watchdog circuit; the processor is in signal connection with the timer period configuration module through the trigger module, so that a watchdog timer period time automatic selection circuit is formed.

Preferably, the timer period configuration module is a resistor or a capacitor or a register.

Preferably, the trigger module sets at least one trigger.

Compared with the prior art, the utility model, its beneficial effect lies in:

the utility model discloses in through a synchronous output timer and timer period configuration module and trigger module, realize the watchdog work and can carry out automatic configuration timing period as required, can effectively strengthen the stability of system circuit, improve the intellectuality of control, satisfy the operation needs. The utility model discloses a send synchronizing signal to the treater for the timing cycle that the treater can obtain the configuration in real time can change in real time according to dormancy or low-power consumption mode use needs, improves the intellectuality, satisfies the use needs. The utility model discloses well treater can independently select the watchdog timer period of dormancy work, is fit for upgrading behind the procedure watchdog timer period and needs adjust in order to adapt to multiple circumstances such as new procedure system requirement. The utility model discloses can reliably monitor processor's operating condition, adopt synchronizing signal to replace RC or GPIO control to close the measure of watchdog, prevented that abnormal program from going down or running away, closed the hidden danger that the watchdog can not automatic recovery.

Drawings

FIG. 1 is a block diagram of the present invention;

fig. 2 is a control flow chart of the present invention.

Detailed Description

The technical solution of the present invention is described in further detail below with reference to the accompanying drawings, but the scope of the present invention is not limited to the following.

As shown in fig. 1, the utility model provides a watchdog circuit capable of automatically configuring timing cycle, comprising a processor 105, wherein the processor 105 is connected with a synchronous output timer 103 for monitoring the operation of the processor 105, a dog feeding signal output terminal of the processor 105 is connected with a clearing signal terminal of the synchronous output timer 103, a synchronous signal output terminal of the synchronous output timer 103 is connected with one terminal of the processor 105, a timer overflow signal output terminal of the synchronous output timer 103 is connected with a reset terminal of the processor 105, a timer overflow signal output terminal of the synchronous output timer 103 is further connected with an external reset module 101 for resetting the synchronous output timer 103, an output terminal of the external reset module 101 is connected with a reset terminal of the synchronous output timer 103, the synchronous output timer 103 is further connected with a timer cycle configuration module 102 for detecting the control of timing cycle size by the processor 105, thereby forming a watchdog circuit; the processor 105 is in signal connection with the timer period configuration module 102 through the trigger module 104, thereby forming a watchdog timer period time auto-selection circuit.

The timer period configuration module 102 is a resistor or capacitor or register. The trigger module 104 sets at least one trigger. In this embodiment, the clock signals for the flip-flops in the flip-flop module 104 are provided by the processor. The timer period configuration module 102 is a resistor and forms a combination corresponding to different period durations through different resistance values for use selection. Several flip-flops are provided in the flip-flop module 104 for different combinations of resistance values. After receiving the overflow signal of the synchronous output timer 103, the external reset module 101 sends a reset signal to control the synchronous output timer 103 to reset.

Referring to fig. 2, the present invention further provides a watchdog circuit control method for automatically configuring a timing cycle, comprising the following processing steps,

step 1: the system is powered on, the processor 105 is loaded and started, the synchronous output timer 103 obtains an initialization period through the timer period configuration module 102, the watchdog is started to work, if the processor 105 normally loads a program in the initialization period and sends a dog feeding signal to the synchronous output timer 103, the watchdog normally works, otherwise, the synchronous output timer 103 outputs a reset signal to the processor 105 and the external reset module 101, so that the synchronous output timer 103 and the processor 105 are reset and restarted;

step 2: after the processor 105 starts working normally, it receives the synchronous signal which is sent by the synchronous output timer 103 and takes the initialization period as the period, thus determining the initialization period;

and step 3: when the initialization period needs to be changed, the processor 105 sends a control signal to the trigger module 104 according to the duration of the required period, so that the configuration combination in the timer period configuration module 102 is selected by the trigger module 104 to obtain a new detection timing period and is locked by the trigger module 104;

and 4, step 4: the processor 105 controls to stop sending the dog feeding signal to the synchronous output timer 103, so that the synchronous output timer 103 outputs a reset signal to the processor 105 and the external reset module 101, so that the synchronous output timer 103 and the processor 105 are reset to restart, and when restarting, the trigger module 104 is used to enable the synchronous output timer 103 to obtain a new detection timing period through the timer period configuration module 102.

The timer period configuration module 102 sets a plurality of groups of combination selections corresponding to different period durations, and the trigger module 104 sets a plurality of triggers corresponding to the groups. The timer period configuration module 102 presets an initialization period greater than the time required for normal system startup. The system is electrified in step 1 and is the utility model discloses the system is the electric work of going up for the first time. In step 4, the processor 105 stops feeding the watchdog through software operation, and the trigger module 104 locks the configuration combination selection in the timer period configuration module 102, so that the requirement of changing the timing period of the watchdog timer in the sleep or low power consumption mode can be met, and meanwhile, the adoption of the synchronization signal can replace the measure of closing the watchdog under the control of the RC or GPIO in the prior art, thereby preventing abnormal programs from running or flying away, and closing the hidden danger that the watchdog cannot be automatically recovered, thereby effectively improving the reliability and meeting the use requirement.

In this embodiment, the timer period configuration module 102 uses the pre-reserved initialization period long enough to meet the time required for system startup. The synchronous signal output by the synchronous output timer 103 is periodically output a square wave pulse signal after being powered on and has a period consistent with that configured on the timer period configuration module 102.

The foregoing is merely a preferred embodiment of the invention, it is to be understood that the invention is not limited to the forms disclosed herein, but is not intended to be exhaustive of other embodiments, and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the invention as expressed in the above teachings or as known to the person skilled in the relevant art. But that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention, which is to be limited only by the claims appended hereto.

Claims (3)

1. A watchdog circuit capable of automatically configuring a timing cycle, comprising a processor (105), wherein the processor (105) is in signal connection with a synchronous output timer (103) for monitoring the operation of the processor (105), wherein a dog feeding signal output terminal of the processor (105) is connected with a clearing signal terminal of the synchronous output timer (103), a synchronous signal output terminal of the synchronous output timer (103) is connected with one end of the processor (105), a timer overflow signal output terminal of the synchronous output timer (103) is connected with a reset terminal of the processor (105), a timer overflow signal output terminal of the synchronous output timer (103) is further in signal connection with an external reset module (101) for performing reset control on the synchronous output timer (103), an output terminal of the external reset module (101) is connected with the reset terminal of the synchronous output timer (103), the synchronous output timer (103) is also in signal connection with a timer period configuration module (102) for controlling the size of the detection timing period of the processor (105), thereby forming a watchdog circuit; the processor (105) is in signal connection with the timer period configuration module (102) through the trigger module (104), so that a watchdog timer period time automatic selection circuit is formed.

2. The watchdog circuit of claim 1, wherein the timer period configuration module (102) is a resistor, a capacitor, or a register.

3. A watchdog circuit for automatically configuring timing periods according to claim 1, wherein the trigger module (104) sets at least one trigger.

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