CN116860051A - Switched capacitor circuit with comparator as core and current source thereof - Google Patents

Abstract

The disclosure provides a switched capacitor circuit with a comparator as a core and a current source thereof. The switched capacitor circuit with the comparator as a core is provided with a first output end and a second output end and comprises a switched capacitor network, a first current source and a second current source. The first current source and the second current source each include: the circuit comprises a first transistor, a second transistor, a capacitor and a buffer circuit. The first transistor has a first source, a first drain and a first gate, the first drain is coupled to the first output terminal, the first source is coupled to the reference voltage, and the first gate is coupled to the switched capacitor network. The second transistor has a second source, a second drain and a second gate, and the second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit is coupled between the second source and the second drain.

Description

Switched capacitor circuit with comparator as core and current source thereof

Technical Field

The present disclosure relates to a switched capacitor circuit, and more particularly, to a switched capacitor circuit with a comparator as a core and a current source thereof.

Background

Fig. 1 shows a conventional comparator-based switched capacitor circuit (SC circuit) (also referred to as zero-cross-based circuit (zbc)). The switched capacitor circuit 100 includes a comparator 110, a current source 120, a capacitor C1, a capacitor C2, a load capacitor CL and a switch SW. The switched capacitor circuit 100 may be derived from a variety of circuits, such as a pipelined ADC (also referred to as a multiplying DAC).

The comparator 110 compares the voltage Vx at the positive input terminal with the reference voltage Vcm at the negative input terminal to generate a control signal Dc0, and the control signal Dc0 controls the output current of the current source 120, thereby controlling the magnitude of the output voltage Vo (i.e., the terminal voltage of the load capacitor CL). When the switch SW is turned on, the output voltage Vo is reset to the power voltage VDD.

The current source 120 is typically implemented by a Metal-Oxide-semiconductor field effect transistor (MOSFET), and the output voltage Vo is the drain (drain) voltage of the transistor. However, since the drain-source (Ids), i.e., the output current of the current source 120, of the current source 120 is dependent on the drain-source voltage (Vds), the output current of the current source 120 is affected by the output voltage Vo, resulting in reduced linearity of the switched-capacitor circuit 100.

Disclosure of Invention

In view of the shortcomings of the prior art, an objective of the present disclosure is to provide a comparator-based switched capacitor circuit and a current source thereof, which are capable of improving the shortcomings of the prior art.

An embodiment of the disclosure provides a switched capacitor circuit with a comparator as a core, which has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The switched capacitor circuit with the comparator as a core comprises: a comparator, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a first transistor, a second transistor, a fifth capacitor, a first buffer circuit, a third transistor, a fourth transistor, a sixth capacitor and a second buffer circuit. The first capacitor has a first end coupled to the first input end through the first switch and the first output end through the fourth switch, and a second end coupled to the comparator and a first reference voltage through the third switch. The second capacitor has a third end and a fourth end, the third end is coupled to the first input end through the second switch and coupled to the first reference voltage through the fifth switch, and the fourth end is coupled to the comparator and coupled to the first reference voltage through the third switch. The third capacitor has a fifth end and a sixth end, wherein the fifth end is coupled to the second input end through the sixth switch and the second output end through the ninth switch, and the sixth end is coupled to the comparator and the first reference voltage through the eighth switch. The fourth capacitor has a seventh end coupled to the second input end through the seventh switch and coupled to the first reference voltage through the tenth switch, and an eighth end coupled to the comparator and coupled to the first reference voltage through the eighth switch. The first transistor has a first source, a first drain and a first gate, the first drain is coupled to the first output terminal, the first source is coupled to a second reference voltage, and the first gate is coupled to the comparator. The second transistor has a second source, a second drain and a second gate, and the second source is coupled to the first output terminal. The fifth capacitor is coupled between the second gate and the second source. The first buffer circuit is coupled between the first output terminal and the second drain. The third transistor has a third source, a third drain and a third gate, wherein the third drain is coupled to the second output terminal, the third source is coupled to a third reference voltage, and the third gate is coupled to the comparator. The fourth transistor has a fourth source, a fourth drain and a fourth gate, and the fourth source is coupled to the second output terminal. The sixth capacitor is coupled between the fourth gate and the fourth source. The second buffer circuit is coupled between the second output terminal and the fourth drain.

Another embodiment of the present disclosure provides a current source having a first input terminal and a first output terminal. The current source includes: a first transistor, a second transistor, a capacitor and a buffer circuit. The first transistor has a first gate, a first source and a first drain, the first gate is coupled to the first input terminal, the first source is coupled to a reference voltage, and the first drain is coupled to the first output terminal. The second transistor has a second gate, a second source and a second drain, and the second source is coupled to the first output terminal. The capacitor is coupled between the second gate and the second source. The buffer circuit has a second input end and a second output end, wherein the second input end is coupled with the second source electrode, and the second output end is coupled with the second drain electrode.

Another embodiment of the present disclosure provides a switched capacitor circuit with a comparator as a core, having a first input terminal, a second input terminal, a first output terminal and a second output terminal. The switched capacitor circuit with the comparator as a core comprises: a comparator, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a ninth switch, a tenth switch, a first current source, a second current source, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first current source is coupled to the comparator and the first output terminal. The second current source is coupled to the comparator and the second output terminal. The first capacitor has a first end coupled to the first input end through the first switch and the first output end through the fourth switch, and a second end coupled to the comparator and a first reference voltage through the third switch. The second capacitor has a third end and a fourth end, the third end is coupled to the first input end through the second switch and coupled to the first reference voltage through the fifth switch, and the fourth end is coupled to the comparator and coupled to the first reference voltage through the third switch. The third capacitor has a fifth end and a sixth end, wherein the fifth end is coupled to the second input end through the sixth switch and the second output end through the ninth switch, and the sixth end is coupled to the comparator and the first reference voltage through the eighth switch. The fourth capacitor has a seventh end coupled to the second input end through the seventh switch and coupled to the first reference voltage through the tenth switch, and an eighth end coupled to the comparator and coupled to the first reference voltage through the eighth switch. The first current source includes: a first transistor, a second transistor, a fifth capacitor and a buffer circuit. The first transistor has a first source, a first drain and a first gate, the first drain is coupled to the first output terminal, the first source is coupled to a second reference voltage, and the first gate is coupled to the comparator. The second transistor has a second source, a second drain and a second gate, and the second source is coupled to the first output terminal. The fifth capacitor is coupled between the second gate and the second source. The buffer circuit has a third input end and a third output end, wherein the third input end is coupled with the second source electrode, and the third output end is coupled with the second drain electrode.

The technical means embodied in the embodiments of the present disclosure may improve at least one of the disadvantages of the prior art, and thus the present disclosure has better linearity compared to the prior art.

The features, implementations and effects of the present disclosure will be described in detail below with reference to examples of embodiments shown in the accompanying drawings.

Drawings

FIG. 1 shows a conventional comparator-based switched capacitor circuit;

FIG. 2 is a circuit diagram of one embodiment of a comparator-centric switched capacitor circuit of the present disclosure; and

fig. 3 is a timing diagram according to an embodiment of the present disclosure.

Detailed Description

Technical terms used in the following description refer to terms commonly used in the art, and if a part of the terms are described or defined in the specification, the explanation of the part of the terms is to be interpreted as being in accordance with the description or definition of the specification.

The disclosure includes a comparator-centric switched capacitor circuit and its current source. Since the comparator-centric switched capacitor circuit of the present disclosure and the current source thereof may include some known components alone, the details of the known components will be omitted without affecting the full disclosure and the operability of the device invention.

Fig. 2 is a circuit diagram of an embodiment of a comparator-centric switched capacitor circuit of the present disclosure. The switched capacitor circuit 200 includes a switched capacitor network 210, a current source 220, and a current source 230. The switched-capacitor circuit 200 has a first input terminal (i.e., receives an input signalIs connected to the first input terminal (i.e. receives the input signal +.>Is connected to the first output terminal (i.e. outputs an output signal +>And a second output terminal (i.e. output signal +)>One end of (c) a). The current source 220 is coupled between the first output terminal and the ground voltage GND; the current source 230 is coupled between the power voltage VDD and the second output terminal. The load capacitor CL1 is coupled between the first output terminal and the ground voltage GND; the load capacitor CL2 is coupled between the second output terminal and the ground voltage GND. The switched capacitor circuit 200 is used for sampling the differential input signal V _in (comprising input Signal->A kind of electronic device with high-pressure air-conditioning system) Sampling is performed and a differential output signal V is output in a hold phase _out (including the output Signal->Is->)。

Switched capacitor network 210 includes a comparisonThe capacitor 212, the capacitor C0a, the capacitor C1a, the capacitor C0b, the capacitor C1b, the switches S0 a-S5 a and the switches S0 b-S5 b. The reference voltage Vcm is the input signalIs->Is a common mode voltage of (c). In some embodiments, the capacitance values of the capacitances C0a, C1a, C0b, C1b are substantially the same.

One end of the capacitor C0a is coupled to the first input terminal through the switch S0a and the first output terminal through the switch S3a, and the other end of the capacitor C0a is coupled to the comparator 212 and the reference voltage Vcm through the switch S2 a. One end of the capacitor C1a is coupled to the first input terminal through the switch S1a and the reference voltage Vcm through the switch S4a, and the other end of the capacitor C1a is coupled to the comparator 212 and the reference voltage Vcm through the switch S2 a. One end of the capacitor C0b is coupled to the second input terminal through the switch S0b and the second output terminal through the switch S3b, and the other end of the capacitor C0b is coupled to the comparator 212 and the reference voltage Vcm through the switch S2 b. One end of the capacitor C1b is coupled to the second input terminal through the switch S1b and the reference voltage Vcm through the switch S4b, and the other end of the capacitor C1b is coupled to the comparator 212 and the reference voltage Vcm through the switch S2 b.

The switched capacitor circuit 200 alternately operates in a sampling phase and a holding phase. In the sampling phase, the switches S0a, S1a, S2a, S0b, S1b and S2b are conductive, and the switches S3a, S4a, S3b and S4b are non-conductive; in the hold phase, the switches S3a, S4a, S3b, and S4b are on, and the switches S0a, S1a, S2a, S0b, S1b, and S2b are off.

Fig. 3 is a timing diagram according to an embodiment of the present disclosure. The sampling phase corresponds to the frequency Φ1 being at a first level (e.g., high level), and the holding phase corresponds to the frequency Φ2 being at a first level (e.g., between time T1 and time T4). The hold phase includes two sub-phases: stage P and stage E. Referring to fig. 2 together, the switches S5a and S5b are turned on for a predetermined time (T2-T1) in the phase P to reset the first output terminal and the second output terminal (the switches S5a and S5b are turned off at other times), and then the current sources 220 and 230 are turned on (i.e. provide current) in the phase E (between the time point T2 and the time point T3) to discharge the load capacitor CL1 and charge the load capacitor CL 2. The voltage V+ and the voltage V-are input voltages of the comparator 212. The comparator 212 compares the voltage v+ and the voltage V-and outputs a control signal Dc1 and a control signal Dc2. When V +.gtoreq.V-, the control signal Dc1 is at a first level (e.g., high level or logic 1) and the control signal Dc2 is at a second level (e.g., low level or logic 0); when V+ < V-, the control signal Dc1 is at the second level and the control signal Dc2 is at the first level.

Voltage v+ with output signalVarying, voltage V-with the output signal +.>And (3) a change. Time T3 corresponds to the voltage reversal at the input of comparator 212 (i.e., from V +.gtv-to V +<V-, or vice versa); that is, the current sources 220 and 230 are turned off (stop supplying current) at the time point T3.

The input terminal of the current source 220 (i.e., the gate of an N-channel Metal-Oxide-Semiconductor Field-Effect Transistor (NMOS transistor)) is coupled or electrically connected to the comparator 212, and the output terminal of the current source 220 (i.e., the drain of the NMOS transistor 222 and the source of a P-channel Metal-Oxide-Semiconductor Field-Effect Transistor (PMOS transistor)) 226 is coupled or electrically connected to the first output terminal. An input of the current source 230 (i.e., a gate of the PMOS transistor 232) is coupled or electrically connected to the comparator 212, and an output of the current source 230 (i.e., a drain of the PMOS transistor 232 and a source of the NMOS transistor 236) is coupled or electrically connected to the second output.

The current source 220 includes an NMOS transistor 222, a buffer circuit 224, a PMOS transistor 226, and a capacitor C2a. The gate of the NMOS transistor 222 is coupled to or electrically connected to the comparator 212, the source of the NMOS transistor 222 is coupled to or electrically connected to the ground voltage GND, and the drain of the NMOS transistor 222 is coupled to or electrically connected to the first output terminal. The gate of the PMOS transistor 226 is coupled or electrically connected to one end of the capacitor C2a, and the source of the PMOS transistor 226 is coupled or electrically connected to the other end of the capacitor C2a. The capacitor C2a is used to bias the PMOS transistor 226. The input terminal of the buffer circuit 224 is coupled to or electrically connected with the first output terminal, and the output terminal of the buffer circuit 224 is coupled to or electrically connected with the drain of the PMOS transistor 226. Buffer circuit 224 is a circuit capable of 1:1 gain conversion or 1:N gain conversion of an input to an output. The buffer circuit 224 is well known to those skilled in the art, and will not be described again.

Because the buffer circuit 224 is connected between the source and the drain of the PMOS transistor 226, the signal is outputIs amplified and reflected on the source-drain voltage (Vsd) of PMOS transistor 226, resulting in an increase in current Ia2 flowing through PMOS transistor 226. Thus, although the current Ia1 flowing through the NMOS transistor 222 is due to the output signal +.>The drop becomes smaller (because the drain-source voltage (Vds) of NMOS transistor 222 becomes smaller), but the larger current Ia2 can compensate for the drop of (offset) current Ia1 such that the total current (ia1+ia2) of current source 220 approaches a constant value (i.e., is less subject to the output signal)>Influence, in other words, linearity is higher). The gain N of the buffer circuit 224 may be designed according to characteristics (e.g., aspect ratio and/or bias conditions) of the NMOS transistor 222 and the PMOS transistor 226, so that the total current (Ia 1+ Ia 2) of the current source 220 approaches a constant value. In some embodiments, the gain N may be substantially equal to 2.

The current source 230 includes a PMOS transistor 232, a buffer circuit 234, an NMOS transistor 236, and a capacitor C2b. The operation principle of the current source 230 can be known by those skilled in the art from the above discussion, and thus will not be described in detail.

Because the output current of current source 220 (or current source 230) is not subject to the output signal(or output Signal->) The current sources 220 and 230 may also be referred to as constant output current sources.

In some embodiments, the switched capacitor circuit 200 only needs to include one constant output current source (i.e., the switched capacitor circuit 200 includes only one of the current source 220 and the current source 230, and the other of the current source 220 and the current source 230 is implemented by a conventional current source) to achieve the effect of improving linearity.

It should be noted that the shapes, sizes and proportions of the components in the foregoing drawings are merely illustrative, and are used by those skilled in the art to understand the present disclosure, and are not intended to limit the present disclosure.

Although the embodiments of the present disclosure have been described above, these embodiments are not intended to limit the present disclosure, and a person having ordinary skill in the art may apply variations to the technical features of the present disclosure according to the explicit or implicit disclosure of the present disclosure, where such variations may fall within the scope of patent protection sought herein, in other words, the scope of patent protection of the present disclosure shall be subject to the limitations set forth in the claims of the present specification.

[ symbolic description ]

100. 200: switched capacitor circuit

110. 212: comparator with a comparator circuit

120. 220, 230: current source

C1, C2, C0a, C1a, C0b, C1b, C2a, C2b: capacitance device

CL, CL1, CL2: load capacitor

SW, S0a, S1a, S2a, S3a, S4a, S5a, S0b, S1b, S2b, S3b, S4b, S5b: switch

Vx, v+, V-: voltage (V)

Vcm: reference voltage

Dc0, dc1, dc2: control signal

Vo: output voltage

VDD: supply voltage

Input signal (first input terminal)

Input signal (second input terminal)

Output signal (first output end)

Output signal (second output terminal)

210: switched capacitor network

GND: ground voltage

Φ1, Φ2: frequency of

P, E: stage(s)

T1, T2, T3, T4: time point

232. 226: PMOS transistor

236. 222: NMOS transistor

224. 234: buffer circuit

Ia1, ia2, ib1, ib2: electric current

Claims (10)

1. The utility model provides a take switching capacitance formula circuit of comparator as core, has first input, second input, first output and second output, this switching capacitance formula circuit of using comparator as core includes:

a comparator;

a first switch;

a second switch;

a third switch;

a fourth switch;

a fifth switch;

a sixth switch;

a seventh switch;

an eighth switch;

a ninth switch;

a tenth switch;

a first capacitor having a first end coupled to the first input end through the first switch and the first output end through the fourth switch, and a second end coupled to the comparator and the first reference voltage through the third switch;

a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first input end through the second switch and the first reference voltage through the fifth switch, and the fourth end is coupled to the comparator and the first reference voltage through the third switch;

a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the second input end through the sixth switch and the second output end through the ninth switch, and the sixth end is coupled to the comparator and the first reference voltage through the eighth switch;

a fourth capacitor having a seventh end coupled to the second input end through the seventh switch and the first reference voltage through the tenth switch, and an eighth end coupled to the comparator and the first reference voltage through the eighth switch;

a first transistor having a first source, a first drain and a first gate, the first drain being coupled to the first output terminal, the first source being coupled to a second reference voltage, the first gate being coupled to the comparator;

a second transistor having a second source, a second drain and a second gate, the second source being coupled to the first output terminal;

a fifth capacitor coupled between the second gate and the second source;

the first buffer circuit is coupled between the first output end and the second drain electrode;

a third transistor having a third source, a third drain and a third gate, the third drain being coupled to the second output terminal, the third source being coupled to a third reference voltage, the third gate being coupled to the comparator;

a fourth transistor having a fourth source, a fourth drain and a fourth gate, the fourth source being coupled to the second output terminal;

a sixth capacitor coupled between the fourth gate and the fourth source; and

the second buffer circuit is coupled between the second output terminal and the fourth drain.

2. The comparator-centric switched capacitor circuit of claim 1 wherein the first buffer circuit is configured to amplify the signal at the first output by a factor of N and the second buffer circuit is configured to amplify the signal at the second output by a factor of N, N being greater than 1.

3. The comparator-centric switched-capacitor circuit as claimed in claim 2, wherein N is substantially equal to 2.

4. A current source having a first input terminal and a first output terminal, the current source comprising:

the first transistor is provided with a first grid electrode, a first source electrode and a first drain electrode, wherein the first grid electrode is coupled with the first input end, the first source electrode is coupled with a reference voltage, and the first drain electrode is coupled with the first output end;

a second transistor having a second gate, a second source and a second drain, wherein the second source is coupled to the first output terminal;

a capacitor coupled between the second gate and the second source; and

the buffer circuit has a second input end and a second output end, wherein the second input end is coupled to the second source electrode, and the second output end is coupled to the second drain electrode.

5. The current source of claim 4, wherein the second input is further coupled to the first output, and the buffer circuit is configured to amplify the signal at the first output by N times, N being greater than 1.

6. The current source of claim 5, wherein N is substantially equal to 2.

7. The utility model provides a take switching capacitance formula circuit of comparator as core, has first input, second input, first output and second output, this switching capacitance formula circuit of using comparator as core includes:

a comparator;

a first switch;

a second switch;

a third switch;

a fourth switch;

a fifth switch;

a sixth switch;

a seventh switch;

an eighth switch;

a ninth switch;

a tenth switch;

the first current source is coupled with the comparator and the first output end;

the second current source is coupled with the comparator and the second output end;

a first capacitor having a first end coupled to the first input end through the first switch and the first output end through the fourth switch, and a second end coupled to the comparator and the first reference voltage through the third switch;

a second capacitor having a third end and a fourth end, wherein the third end is coupled to the first input end through the second switch and the first reference voltage through the fifth switch, and the fourth end is coupled to the comparator and the first reference voltage through the third switch;

a third capacitor having a fifth end and a sixth end, wherein the fifth end is coupled to the second input end through the sixth switch and the second output end through the ninth switch, and the sixth end is coupled to the comparator and the first reference voltage through the eighth switch; and

a fourth capacitor having a seventh end coupled to the second input end through the seventh switch and the first reference voltage through the tenth switch, and an eighth end coupled to the comparator and the first reference voltage through the eighth switch;

wherein the first current source comprises:

a first transistor having a first source, a first drain and a first gate, the first drain being coupled to the first output terminal, the first source being coupled to a second reference voltage, the first gate being coupled to the comparator;

a second transistor having a second source, a second drain and a second gate, the second source being coupled to the first output terminal;

a fifth capacitor coupled between the second gate and the second source; and

the buffer circuit has a third input end and a third output end, wherein the third input end is coupled with the second source electrode, and the third output end is coupled with the second drain electrode.

8. The comparator-centric switched-capacitor circuit as claimed in claim 7, wherein the third input terminal is further coupled to the first output terminal, and the buffer circuit is configured to amplify the signal of the first output terminal by N times, N being greater than 1.

9. The comparator-centric switched-capacitor circuit as claimed in claim 8, wherein N is substantially equal to 2.

10. The comparator-centric switched-capacitor circuit of claim 8, wherein the buffer circuit is a first buffer circuit, the second current source comprising:

a third transistor having a third source, a third drain and a third gate, the third drain being coupled to the second output terminal, the third source being coupled to a third reference voltage, the third gate being coupled to the comparator;

a fourth transistor having a fourth source, a fourth drain and a fourth gate, the fourth source being coupled to the second output terminal;

a sixth capacitor coupled between the fourth gate and the fourth source; and

the second buffer circuit has a fourth input end and a fourth output end, wherein the fourth input end is coupled with the fourth source electrode, and the fourth output end is coupled with the fourth drain electrode.