CN116841921A

CN116841921A - Data reading and writing method and device, electronic equipment and storage medium

Info

Publication number: CN116841921A
Application number: CN202210296688.7A
Authority: CN
Inventors: 宫一夫
Original assignee: Longxin Zhongke Hefei Technology Co ltd
Current assignee: Longxin Zhongke Hefei Technology Co ltd
Priority date: 2022-03-24
Filing date: 2022-03-24
Publication date: 2023-10-03

Abstract

The embodiment of the invention provides a data reading and writing method, a data reading and writing device, electronic equipment and a storage medium, and relates to the technical field of display. Wherein the method comprises the following steps: determining the next write pointer address according to the current write pointer address, the current write pointer spacing and the RAM depth of the dual-port RAM, and writing new display cache data when a spare storage address exists in the RAM; and determining the next read pointer address according to the current read pointer address of the RAM, the current read pointer distance and the RAM depth, and reading new display cache data from the RAM. The write pointer address of the nth write data can be the same as the read pointer address of the (N-D) th read data, D is the RAM depth, that is, one data is read from one address of the RAM, and one new data can be written at the address immediately, so that the utilization rate of the display buffer is improved, the display continuity is ensured, and the capacity of the display buffer is not required to be enlarged.

Description

Data reading and writing method and device, electronic equipment and storage medium

Technical Field

The present invention relates to the field of display technologies, and in particular, to a data reading and writing method, a data reading and writing device, an electronic device, and a storage medium.

Background

Computer display systems are an important component of many computer systems, such as computers, cell phones, wearable devices, and the like. At the present time of higher and higher refresh rates of the display, the memory access operation generated by the display controller (Display Controller) by scanning the frame buffer to read the pixel data occupies a large amount of bus bandwidth, and is also an important component of the power consumption of the computer, so that image compression has become an important method for reducing the overhead.

The image compression mode is to perform compression processing by regarding a block of 16 (4×4) pixels as one unit, and then to transmit the block in the block mode. Unlike linear transmission, the pixel arrangement order of the tile transmission mode is no longer scanned one by one in units of lines, but is transmitted in a certain order of pixels within a tile in units of tiles. Since the pixel data provided to the display device by the display controller is transferred one by one in a linear mode, it is necessary to optimize the display buffer inside the display controller so that it can convert the tile mode pixel data sequence into a linear mode pixel data sequence.

In general, the size of the display buffer only needs to ensure that the contradiction between read-write operation and the time continuity of display data update do not occur, however, in the block mode, since the display data acquired from the previous module by the display buffer is in the block mode pixel data sequence, but the display buffer data output by the display buffer needs to be in the linear mode pixel data sequence, the sequence of the read-write operation of the display buffer is different, and the sizes of the read-write logic and the display buffer need to be specially designed.

In one approach, to ensure that read and write operations do not conflict, the display buffer size needs to be increased to achieve that the read and write operations are directed to different tile rows (i.e., 4 rows of pixels) respectively. Because the pixel data output to the display device is scanned according to the rows, the capacity of the display buffer at least needs to ensure the pixel data storage of 4 rows of pixels, however, the method at least needs to increase the capacity of the display buffer to be twice the minimum capacity because the read-write operation is respectively aimed at different image block rows, namely at least needs to ensure the pixel data storage of 8 rows of pixels, but in this way, the area cost of the display buffer is increased.

In another way, to keep the capacity of the display buffer unchanged, it is necessary to wait for the display buffer data in the display buffer to be read to the last line of the tile, and then start to request the data writing of the next tile, which reduces the utilization rate of the display buffer. In addition, in this method, if a network delay is encountered when the data writing of the next tile line is requested, no new display buffer data is available in the display buffer, so that the continuity of display is adversely affected, and thus, the method further enlarges the possible adverse effect of the network delay on the display system.

Disclosure of Invention

In view of the above problems, embodiments of the present invention are provided to provide a data read/write method for overcoming the above problems or at least partially solving the above problems, so as to solve the problem that the existing manner of data read/write of the display buffer cannot be compatible with the capacity of the display buffer, the utilization rate of the display buffer, and the display continuity.

Correspondingly, the embodiment of the invention also provides a data read-write device, electronic equipment and a storage medium, which are used for ensuring the realization and application of the method.

In order to solve the above problems, an embodiment of the present invention discloses a data read-write method, which is applied to a display controller, wherein the display controller includes a display buffer, the display buffer includes a dual-port random access memory RAM, and the method includes:

determining the next write pointer address to be written into display cache data according to the current write pointer address of the dual-port RAM, the current write pointer interval and the depth of the dual-port RAM;

when the storage address of the display cache data which is read exists in the dual-port RAM, writing the display cache data into the dual-port RAM according to a write pointer address of the display cache data which is required to be written next;

Determining a next read pointer address required to read the display cache data according to the current read pointer address of the dual-port RAM, the current read pointer interval and the depth of the dual-port RAM;

reading the display cache data from the dual-port RAM according to the read pointer address of the display cache data to be read next;

the N-th write pointer address corresponding to the display cache data when being written into the dual-port RAM is the same as the (N-D) -th read pointer address corresponding to the display cache data when being read from the dual-port RAM; and D is the depth of the dual-port RAM.

Optionally, the determining the address of the next write pointer to be written into the display cache data according to the current address of the write pointer of the dual-port RAM, the current distance between the write pointers, and the depth of the dual-port RAM includes:

when the current write pointer address is not the last bit storage address of the dual-port RAM, determining the sum of quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer interval by the depth of the dual-port RAM as the next write pointer address needing to be written into the display cache data;

And when the current write pointer address is the last bit storage address of the dual-port RAM, determining the initial bit storage address of the dual-port RAM as the next write pointer address which needs to be written into the display cache data.

Optionally, the determining, according to the current read pointer address of the dual-port RAM, the current read pointer distance, and the depth of the dual-port RAM, the next read pointer address to be read from the display cache data includes:

when the current read pointer address is not the last bit storage address of the dual-port RAM, determining the sum of quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer interval by the depth of the dual-port RAM as the next read pointer address needing to read the display cache data;

and when the current read pointer address is the last bit storage address of the dual-port RAM, determining the initial bit storage address of the dual-port RAM as the next read pointer address which needs to read the display cache data.

Optionally, the method further comprises:

when the current write pointer address is the last bit storage address of the dual-port RAM, determining the write pointer interval corresponding to M times of writing the display cache data into the dual-port RAM according to the current write pointer interval, a first constant and the depth of the dual-port RAM;

Wherein, M equals the depth of the dual port RAM.

Optionally, when the current write pointer address is the last bit storage address of the dual-port RAM, determining, according to the current write pointer interval, the first constant, and the depth of the dual-port RAM, a write pointer interval corresponding to M times of writing the display cache data into the dual-port RAM, includes:

taking a first preset value as an initial value of the write pointer interval, and determining the first product as the write pointer interval corresponding to the process of writing the display cache data into the dual-port RAM for M times after determining the first product of the current write pointer interval and the first constant is smaller than the depth of the dual-port RAM;

and when the first product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM, determining that the sum of quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM is the corresponding write pointer spacing when the display cache data is written into the dual-port RAM for M times.

Optionally, the first constant is 4, and the first preset value is 1.

Optionally, the method further comprises:

When the current read pointer address is the last storage address of the dual-port RAM, determining the corresponding read pointer interval when the display cache data is read from the dual-port RAM for M times according to the current read pointer interval, a second constant and the depth of the dual-port RAM;

wherein, M equals the depth of the dual port RAM.

Optionally, when the current read pointer address is the last bit storage address of the dual-port RAM, determining, according to the current read pointer interval, the second constant, and the depth of the dual-port RAM, a read pointer interval corresponding to M times of reading the display cache data from the dual-port RAM, includes:

taking a second preset value as an initial value of the read pointer interval, and determining the second product of the current read pointer interval and the second constant as the read pointer interval corresponding to the process of reading the display cache data from the dual-port RAM M times later when the second product is smaller than the depth of the dual-port RAM;

and when the second product of the current read pointer interval and the second constant is greater than or equal to the depth of the dual-port RAM, determining the sum of quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM as the corresponding read pointer interval when the display cache data is read from the dual-port RAM for M times.

Optionally, the second constant is 4, and the second preset value is 4.

The embodiment of the invention also discloses a data read-write device, which is applied to a display controller, wherein the display controller comprises a display buffer, the display buffer comprises a dual-port random access memory RAM, and the device comprises:

the write pointer determining module is used for determining the next write pointer address to be written into the display cache data according to the current write pointer address of the dual-port RAM, the current write pointer interval and the depth of the dual-port RAM;

the data writing module is used for writing the display cache data into the dual-port RAM according to a write pointer address required to be written into the display cache data next when a storage address which is read out of the display cache data exists in the dual-port RAM;

the read pointer determining module is used for determining the next read pointer address required to read the display cache data according to the current read pointer address of the dual-port RAM, the current read pointer interval and the depth of the dual-port RAM;

the data reading module is used for reading the display cache data from the dual-port RAM according to the next read pointer address required to read the display cache data;

Optionally, the write pointer determination module includes:

a first write pointer determining sub-module, configured to determine, when the current write pointer address is not the last bit storage address of the dual-port RAM, a sum of quotient and remainder obtained by dividing a sum of the current write pointer address and the current write pointer interval by a depth of the dual-port RAM, as a write pointer address to be written into the display cache data next;

and the second write pointer determining submodule is used for determining the initial bit storage address of the dual-port RAM as the next write pointer address needing to be written into the display cache data when the current write pointer address is the last bit storage address of the dual-port RAM.

Optionally, the read pointer determination module includes:

a first read pointer determining sub-module, configured to determine, when the current read pointer address is not the last bit storage address of the dual-port RAM, a sum of quotient and remainder obtained by dividing a sum of the current read pointer address and the current read pointer interval by a depth of the dual-port RAM, as a next read pointer address where the display cache data needs to be read;

And the second read pointer determining submodule is used for determining the initial bit storage address of the dual-port RAM as the next read pointer address needing to read the display cache data when the current read pointer address is the last bit storage address of the dual-port RAM.

Optionally, the apparatus further comprises:

the write pointer interval determining module is used for determining the write pointer interval corresponding to the process of writing the display cache data into the dual-port RAM for M times according to the current write pointer interval, a first constant and the depth of the dual-port RAM when the current write pointer address is the last bit storage address of the dual-port RAM;

wherein, M equals the depth of the dual port RAM.

Optionally, the write pointer spacing determining module includes:

a first write pointer interval determining sub-module, configured to use a first preset value as an initial value of the write pointer interval, and determine, when a first product of the current write pointer interval and the first constant is smaller than a depth of the dual-port RAM, the first product as a write pointer interval corresponding to when the display cache data is written into the dual-port RAM M times later;

And the second write pointer interval determining submodule is used for determining the sum of quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM when the first product of the current write pointer interval and the first constant is larger than or equal to the depth of the dual-port RAM, and determining the sum as the write pointer interval corresponding to the process of writing the display cache data into the dual-port RAM for M times.

Optionally, the first constant is 4, and the first preset value is 1.

Optionally, the apparatus further comprises:

the read pointer interval determining module is used for determining the corresponding read pointer interval when the display cache data is read from the dual-port RAM for M times according to the current read pointer interval, a second constant and the depth of the dual-port RAM when the current read pointer address is the last storage address of the dual-port RAM;

wherein, M equals the depth of the dual port RAM.

Optionally, the read pointer spacing determining module includes:

a first read pointer interval determining sub-module, configured to use a second preset value as an initial value of the read pointer interval, and determine a second product of the current read pointer interval and the second constant as a read pointer interval corresponding to M times of reading the display cache data from the dual-port RAM after the second product is determined when the second product is smaller than the depth of the dual-port RAM;

And the second read pointer interval determining submodule is used for determining the sum of quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM as the read pointer interval corresponding to the process of reading the display cache data from the dual-port RAM for M times after when the second product of the current read pointer interval and the second constant is larger than or equal to the depth of the dual-port RAM.

Optionally, the second constant is 4, and the second preset value is 4.

The embodiment of the invention also discloses an electronic device which comprises a memory and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by one or more display buffers, and the one or more programs comprise instructions for:

The embodiment of the invention also discloses a readable storage medium, when the instructions in the storage medium are executed by the display buffer of the electronic equipment, the electronic equipment can execute one or more data read-write methods in the embodiment of the invention.

The embodiment of the invention has the following advantages:

in the embodiment of the invention, the display buffer can determine the next write pointer address needing to be written into the display buffer data according to the current write pointer address of the dual-port RAM, the current write pointer interval and the depth of the dual-port RAM, and write new display buffer data when the spare storage address exists in the dual-port RAM. In addition, the display buffer can determine the next read pointer address required to read the display buffer data according to the current read pointer address of the dual-port RAM, the current read pointer interval and the depth of the dual-port RAM, and read the new display buffer data from the dual-port RAM. The address of the write pointer of the display buffer data written in the nth time can be the same as the address of the read pointer of the (N-D) th time for reading the display buffer data, D is the depth of the dual-port RAM, namely, one data is read from one address of the dual-port RAM, and one new data can be written in the address immediately, so that the utilization rate of the display buffer can be improved, the display continuity is ensured, and the capacity of the display buffer is not required to be enlarged.

Drawings

FIG. 1 is a block diagram of a display architecture of the present invention;

FIG. 2 is a schematic diagram of a request read pointer moving in a FIFO queue in accordance with the present invention;

FIG. 3 is a schematic diagram of the movement of a decompressed read pointer in a FIFO queue in accordance with the present invention;

FIG. 4 is a schematic diagram of a pixel arrangement sequence in a tile transmission mode according to the present invention;

FIG. 5 is a schematic diagram of a transmission sequence within a decompressed block according to the present invention;

FIG. 6 is a schematic illustration of a transmission sequence within rearranged tiles according to the present invention;

FIG. 7 is a schematic diagram of a data writing sequence of a dual port RAM of the present invention;

FIG. 8 is a flow chart of steps of an embodiment of a data read/write method of the present invention;

FIG. 9 is a schematic diagram of the data arrangement of a dual port RAM of the present invention from first to third full write cycles;

FIG. 10 is a block diagram of an embodiment of a data read/write device of the present invention;

fig. 11 is a block diagram showing a structure of an electronic device for reading and writing display data according to an exemplary embodiment.

Detailed Description

In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.

Before describing the embodiments of the present invention in detail, a description is first given of a display architecture and a display manner to which the present invention is applied.

Fig. 1 shows a block diagram of a display architecture of the present invention, and referring to fig. 1, the display architecture includes a display driving apparatus 10 and a display apparatus 20, the display driving apparatus 10 includes a frame buffer 111 and a display controller 112, and the display controller 112 may be configured with a graphic card chip 11. The frame buffer 111, also called a video memory, may be used to store the rendering data processed or to be extracted by the graphics card chip 11, and the display controller 112 may be used to obtain the frame buffer data from the frame buffer 111, and output the frame buffer data to the display device 20 for display after a series of processing. In practical applications, the display controller 112 is not necessarily configured with the graphics card chip 11.

In practical applications, the display driving apparatus 10 and the display apparatus 20 may be two separate devices, such as a host and a display, and of course, may be an integrated device, such as a host-display integrated machine, which is not limited in particular by the embodiment of the present invention. In practical applications, the graphics card Chip 11 may be a system on Chip (SoC).

Referring to fig. 1, the display controller 112 may include a Meta (Pixel compression information) DMA (direct memory access) module, a Pixel DMA module, a Pixel Dec module, a tile sort module, and a display buffer optimized for using a tile transfer mode at decompression. The Meta DMA module is configured to obtain compression information (hereinafter referred to as Meta information) required for decompressing Pixel data from the Meta frame buffer in the frame buffer 111, the Pixel DMA module is configured to obtain compressed Pixel data from the Pixel frame buffer in the frame buffer 111, and the Pixel Dec module is configured to decompress the compressed Pixel data using the Meta information and provide the decompressed Pixel data to the display buffer.

The display buffer may specifically include: write data port, read data port, write pointer module, read pointer module, dual port RAM (RandomAccess Memory ).

The write pointer module is used for guiding the write data port to write the output of the block ordering module to a specific position of the dual-port RAM. And the read pointer module is used for guiding the read data port to read data from a specific position of the dual-port RAM.

After one data in the dual-port RAM is read, the storage space corresponding to the data can be used for writing new data, which can be understood as the free storage space corresponding to the data, and the new data can directly cover the original data in the storage space when being written. When there is free memory space in the dual port RAM, the display buffer may send a read request to the Pixel DMA module, which sends a read request to the Pixel frame buffer in combination with Meta information previously obtained from the Meta DMA module. The Meta information obtained by the Meta DMA module may be obtained from the Meta frame buffer in advance. After the Pixel DMA module obtains the compressed Pixel data from the Pixel frame buffer, the compressed Pixel data may be sent to the Pixel Dec module. In addition, after the Meta DMA module obtains the Meta information, the Meta information may also be sent to the Pixel Dec module. The Pixel Dec module may decompress the compressed Pixel data according to the Meta information and then send the decompressed Pixel data to the tile ordering module, where the decompressed Pixel data is in the form of tiles. The tile sort module rearranges the tile Pixel data received from the Pixel Dec module and sends the rearranged tile Pixel data to the display buffer.

The display controller uses image compression technology, and can compress a block formed by 16 (4×4) pixels in an ARGB8888 or RGBA8888 color format (each pixel occupies 4 bytes, which respectively represent 4 channels, each channel has 8 bits, and 16 pixels totally have 512 bits) to 0 bits, 256 bits or 512 bits by a specific compression algorithm. Wherein 0 bits indicate that the compressed tile is black or white; 256 bits indicate that the compressed tile is solid or no more than 6 colors within the tile; 512 bits indicate that the compressed tile is the original pixel data, uncompressed. The Meta information may indicate a compression manner of the tiles, that is, compressing the tiles into 0 bits, 256 bits, or 512 bits, and the Meta information corresponding to each tile has a size of 4 bits. The Meta information generated during compression is used in the subsequent decompression process, and the decompressed pixel data is stored in a display buffer and then output to a display device.

The display controller reduces the number of memory access operations of the display controller by compressing the image data, thereby reducing the bus load.

For bandwidth saving purposes, meta information is used to change the length of Pixel data read by the Pixel DMA module from the Pixel frame buffer, and Meta information can also be used in the decompression process of the Pixel Dec module. The Meta DMA module is responsible for retrieving Meta information from the Meta frame buffer and providing it to the Pixel DMA module and the Pixel Dec module, respectively, to coordinate the above operations.

Specifically, the basic operating principle of the Meta DMA module is similar to that of a FIFO (First InputFirst Output, first-in-first-out) queue, except that the Meta DMA module has two read pointers. The request read pointer (ReqPtr) is responsible for providing Meta information to the Pixel DMA module to determine the requested data length, and the Meta DMA module may send Meta information indicated by the request read pointer (ReqPtr) to the Pixel DMA module. The decompression read pointer (DecPtr) is responsible for sending Meta information to the Pixel Dec module to complete decompression after the Pixel DMA module obtains the compressed Pixel data, and the Meta DMA module may send Meta information indicated by the decompression read pointer (DecPtr) to the Pixel DMA module.

In the invention, the FIFO queue is divided into two parts for ping-pong operation, and temporary transfer of Meta information is carried out through a register.

As shown in FIG. 2, when the request read pointer (ReqPtr) moves to another region of the FIFO queue, the Meta DMA module will request the Meta information (Meta 2 in FIG. 2) currently indicated by the read pointer (ReqPtr) ¹ ) And sending a read request to the Pixel DMA module, wherein the requested data length is 128 bits (namely 32 pieces of Meta information), and then storing the 32 pieces of Meta information returned by the Meta frame buffer into a register to wait for later writing into the FIFO queue. Since the Meta DMA module can request 32 Meta information at a time, one area of the FIFO queue can include the storage space required for 32 Meta information, referring to fig. 2, meta 1 ¹ -Meta 1 ³² Occupy a region, meta 2 ¹ -Meta2 ³² Occupying another area.

As shown in FIG. 3, when the decompressed read pointer (DecPtr) moves to another area of the FIFO queue, the Meta DMA module will decompress the Meta information (Meta 2 in FIG. 3) currently indicated by the read pointer (DecPtr) ¹ ) Send to the Pixel Dec module and write the 32 Meta information in the register to the FIFO queue.

It should be noted that each time the read pointer (ReqPtr) is requested to move, the currently indicated Meta information needs to be sent to the Pixel DMA module, but only when the area is cross, the Meta information is sent to the Pixel DMA module, and at the same time, the read request is sent to the Meta frame buffer. Similarly, each time the decompression read pointer (DecPtr) moves, it is necessary to send the currently indicated Meta information to the Pixel Dec module, but only when the pointer is cross-regional, the Meta information is sent to the Pixel Dec module, and at the same time, the Meta information temporarily stored in the register is written into the FIFO queue.

The design can lead the Pixel DMA module to acquire the compressed Pixel data and synchronously carry out the operation of decompressing the compressed Pixel data by the Pixel Dec module without waiting for Meta information for decompression to be sent and after decompression is realized, the next read request is sent to the Meta frame buffer memory.

After obtaining the Meta information, the Pixel DMA module sends a read request to the Pixel frame buffer, where the requested data length may be selected from 0 bits, 256 bits, or 512 bits according to the Meta information. In practical application, the read request is transmitted from the Pixel DMA module bottom layer to the Pixel DMA module upper layer, specifically, when the requested data length is 0 bit, the Pixel DMA module upper layer intercepts the request when receiving the read request, and returns a virtual handshake signal to the Pixel DMA module bottom layer, so that the Pixel DMA module bottom layer considers that the requested data is successfully cached to the Pixel frame, and does not cache the actual requested data to the Pixel frame, thereby completing a virtual receiving flow. Therefore, the consistency of the request and receiving flow of the Pixel DMA module can be ensured on the premise of not occupying the bus bandwidth.

The Pixel Dec module may decompress compressed Pixel data obtained from the Pixel DMA module according to the Meta information and send the decompressed data to the tile ordering module. Wherein the decompression algorithm corresponds to the compression algorithm.

In the process of transmitting the Pixel data from the Pixel frame buffer to the tile sorting module, the Pixel data is transmitted through a tile mode, and the arrangement sequence of the pixels in the tile transmission mode is shown in fig. 4. The width of the dual port RAM used in the display buffer may be designed to be 128 bits (4 pixels), and accordingly, the decompressed tiles may be divided into 4 sub-tiles as shown in fig. 5 in the transmission order. During the transmission prior to the tile ordering module, the pixel Data is transmitted in the order of tile 1-tile n, where each tile is transmitted in the order of sub-tiles data_dec1-data_dec4 shown in FIG. 5. Wherein data_dec1 in fig. 5 comprises pixels 1,2,3 and 4 in fig. 4, data_dec2 comprises pixels 5,6,7 and 8 in fig. 4, data_dec3 comprises pixels 9, 10, 11 and 12 in fig. 4, and data_dec4 comprises pixels 13, 14, 15 and 16 in fig. 4.

The tile sort module may rearrange the pixels within a tile by rows into 4 sub-tile Data as shown in FIG. 6, and send the sub-tiles data_rod 1-data_rod4 within a tile in the order of tile 1-tile n to the display buffer for further processing. Wherein data_rod1 in fig. 6 includes pixels 1,2,5 and 6 in fig. 4, data_rod2 includes pixels 3,4,7 and 8 in fig. 4, data_rod3 includes pixels 9, 10, 13 and 14 in fig. 4, and data_rod4 includes pixels 11, 12, 15 and 16 in fig. 4.

The display buffer is used for storing the reordered pixel data and providing the pixel data to the display device. Since the pixel data output to the display device is scanned by rows, the capacity of the dual-port RAM in the display buffer should be at least 128×4096 (4 rows×4096 pixels, 1024 tiles in total) bits to support the 4K resolution, and accordingly, the depth of the dual-port RAM should be at least 4096. 1024 tiles are stored in the dual port RAM in the write order of tile 1-tile 1024, with the write order within the tiles being sub-tiles data_rod1-data_rod4. In the reading operation of the pixel data, the pixel data with the same sub-image block ordinal number in the block is preferentially read. Taking the write sequence shown in FIG. 7 as an example, the write sequence is 1 ¹ ，2 ¹ ，3 ¹ ，4 ¹ ，1 ² ，2 ² ，3 ² ，4 ² ，…，1 ¹⁰²⁴ ，2 ¹⁰²⁴ ，3 ¹⁰²⁴ ，4 ¹⁰²⁴ Correspondingly, the readout order is 1 ¹ ，1 ² ，…，1 ¹⁰²⁴ ，2 ¹ ，2 ² ，…，2 ¹⁰²⁴ ，3 ¹ ，3 ² ，…，3 ¹⁰²⁴ ，4 ¹ ，4 ² …，4 ¹⁰²⁴ Wherein, the upper corner is marked as a block number.

Based on the read-write mode of the dual-port RAM in the display buffer, the data read-write method, the device, the electronic equipment and the storage medium of the embodiment of the invention are provided. One of the core ideas of the embodiment of the invention is that by increasing the changing factor of the write pointer interval when the write pointer address of the dual-port RAM is calculated and increasing the changing factor of the read pointer interval when the read pointer address of the dual-port RAM is calculated, the write pointer address corresponding to the nth time of writing the display cache data into the dual-port RAM is the same as the read pointer address corresponding to the (N-D) time of reading the display cache data from the dual-port RAM, wherein D is the depth of the dual-port RAM, so that after each data is read from the dual-port RAM, new data can be written into the address corresponding to the data, namely, the display cache can be written into the next data immediately when the dual-port RAM has a spare position, thereby improving the utilization rate of the display cache, ensuring the display continuity and without expanding the capacity of the display cache.

Referring to fig. 8, a flowchart illustrating steps of an embodiment of a data read/write method of the present invention is shown, where the method may be applied to a display controller, where the display controller includes a display buffer, and the display buffer includes a dual port RAM, and the method may specifically include the steps of:

Step 801: and determining the next write pointer address to be written into the display cache data according to the current write pointer address of the dual-port RAM, the current write pointer interval and the depth of the dual-port RAM.

In the embodiment of the invention, a write pointer pitch (WrPtrGap) register can be added, when the next write pointer address (NxtWrPtr) needing to be written into display cache data needs to be determined, the current write pointer pitch can be read from the write pointer pitch (WrPtrGap) register, and the write pointer address (WrPtr) can be increased according to the corresponding write pointer pitch (WrPtrGap) when being updated.

When the write pointer address needs to be updated, the display buffer may determine the next write pointer address (NxtWrPtr) to be written into the display buffer data according to the current write pointer address (WrPtr) of the dual port RAM, the current write pointer pitch (WrPtrGap), and the Depth (Depth) of the dual port RAM.

Optionally, step 801 may be specifically implemented by the following manner, including:

when the current write pointer address is not the last bit storage address of the dual-port RAM, determining the sum of quotient and remainder obtained by dividing the sum of the current write pointer address and the current write pointer distance by the depth of the dual-port RAM as the next write pointer address needing to be written with display cache data;

When the current write pointer address is the last bit storage address of the dual-port RAM, the initial bit storage address of the dual-port RAM is determined as the next write pointer address which needs to be written with display cache data.

Wherein the above steps can be represented by the following formula (1):

in the above formula (1), rem represents a remainder symbol, and in practical application, since each parameter in the formula (1) is a non-negative number, the rem symbol in the formula (1) may be replaced by a mod (modulo) symbol.

In a specific application, since the address of the dual port RAM starts from 0, the last bit address of the dual port RAM is (Depth-1). When the current write pointer address (WrPtr) is not located at the last bit of the dual-port RAM, the next write pointer address (nxtswrptr) is the sum of quotient and remainder obtained by dividing the sum of the current write pointer address (WrPtr) and the current write pointer pitch (WrPtrGap) by the Depth (Depth) of the dual-port RAM; when the current write pointer address (WrPtr) is at the last bit of the dual port RAM, then the next write pointer address (NxtWrPtr) is the first bit of the dual port RAM.

The formula (1) can construct a writing rule for displaying the cache data, so that the address of the writing pointer can be increased according to the current interval of the writing pointer when the address of the writing pointer is updated.

Optionally, the method further comprises the steps of:

when the current write pointer address is the last bit storage address of the dual-port RAM, determining the corresponding write pointer interval when the display cache data is written into the dual-port RAM for M times according to the current write pointer interval, the first constant and the depth of the dual-port RAM;

where M is equal to the depth of the dual port RAM.

In the embodiment of the invention, when currentWhen the write pointer address (WrPtr) is at the last bit of the dual port RAM, the write pointer address (WrPtr) can be determined according to the current write pointer pitch (WrPtr), the first constant (k ₁ ) And the Depth (Depth) of the dual port RAM, the current write pointer pitch (WrPtrGap) is updated to get a new write pointer pitch (nxtwrtptrgap) that will be used for the subsequent M execution of step 801.

The writing time of the data is required by writing the data once in the display buffer, so that the writing pointer interval is required to be updated every time after the data is written once in the display buffer, and the aim of matching the rule of the writing data of the round with the reading data of the previous round can be achieved by updating the writing pointer interval of each round.

Optionally, when the current write pointer address is the last bit storage address of the dual-port RAM, determining, according to the current write pointer interval, the first constant, and the depth of the dual-port RAM, the corresponding write pointer interval when writing the display cache data into the dual-port RAM M times later may further specifically include:

taking a first preset value as an initial value of the write pointer interval, and determining the first product as the write pointer interval corresponding to M times of writing the display cache data into the dual-port RAM after the first product of the current write pointer interval and the first constant is smaller than the depth of the dual-port RAM;

when the first product of the current write pointer spacing and the first constant is greater than or equal to the depth of the dual-port RAM, determining that the sum of quotient and remainder obtained by dividing the first product by the depth of the dual-port RAM is the corresponding write pointer spacing when the display cache data is written into the dual-port RAM for M times later.

Wherein the above steps can be represented by the following formula (2):

in practical applications, since each parameter in the formula (2) is a non-negative number, the rem symbol in the formula (2) may be replaced by a mod symbol.

Therefore, through the formula (2), the distance between the writing pointers can be changed according to a certain rule, and the writing pointers return to the initial value, so that the data writing rule forms a cycle and is staggered with the data reading rule which also forms the cycle by one step, and the aim of writing new data at the corresponding position immediately after reading one data is realized.

Optionally, a first constant (k ₁ ) May be 4 and the first preset value may be 1.

In practice, the initial value of the write pointer pitch (WrPtrGap) may be 1, when the write pointer address (WrPtr) is at the last bit of the dual port RAM, if the write pointer pitch (WrPtrGap) is k ₁ The Depth (Depth) of the dual-port RAM is smaller than that of the dual-port RAM, the write pointer spacing (WrPtrGap) can be enlarged to the original k ₁ Doubling; if k is the write pointer spacing (WrPtrgap) ₁ The next write pointer pitch (NxtWrPtrGap) is k ₁ The sum of the quotient and remainder of the write pointer spacing (WrPtrGap) divided by the Depth (Depth) of the dual port RAM.

Step 802: when the storage address of the display cache data which is read exists in the dual-port RAM, the display cache data is written into the dual-port RAM according to the next write pointer address which needs to be written into the display cache data.

In this step, when a storage address of the display cache data that has been read exists in the dual-port RAM, it indicates that the display cache data corresponding to the storage address is used, the display cache data corresponding to the storage address may be overwritten by new data, and the storage address may be regarded as a spare location. The display buffer may write the next display buffer data at the storage address of the display buffer data that has been read, that is, the original display buffer data of the storage address is overwritten by the new display buffer data. In the embodiment of the present invention, the next write pointer address (NxtWrPtr) to be written into the display cache data is the latest storage address that has been read out of the display cache data.

Step 803: and determining the next read pointer address required to read the display cache data according to the current read pointer address of the dual-port RAM, the current read pointer interval and the depth of the dual-port RAM.

In the embodiment of the present invention, a read pointer pitch (RdPtrGap) register may be added, when a next read pointer address (nxttrdptr) to be read of the display cache data needs to be determined, a current read pointer pitch may be read from the read pointer pitch (RdPtrGap) register, and the read pointer address (RdPtr) may be incremented according to the corresponding read pointer pitch (RdPtrGap) when being updated.

When the read pointer address needs to be updated, the display buffer can determine the next read pointer address (nxtrddtr) needed to read the display buffer data according to the current read pointer address (RdPtr) of the dual-port RAM, the current read pointer distance (RdPtrGap), and the Depth (Depth) of the dual-port RAM.

Alternatively, step 803 may be specifically implemented in the following manner, including:

when the current read pointer address is not the last bit storage address of the dual-port RAM, determining the sum of quotient and remainder obtained by dividing the sum of the current read pointer address and the current read pointer interval by the depth of the dual-port RAM as the read pointer address of the next display cache data to be read;

When the current read pointer address is the last bit storage address of the dual-port RAM, the initial bit storage address of the dual-port RAM is determined as the next read pointer address which needs to read the display cache data.

Wherein the above step can be represented by the following formula (3):

in practical applications, since each parameter in the formula (3) is a non-negative number, the rem symbol in the formula (3) may be replaced by a mod symbol.

When the current read pointer address (RdPtr) is not located at the last bit of the dual-port RAM, the next read pointer address (NxtRdPtr) is the sum of quotient and remainder obtained by dividing the sum of the current read pointer address (RdPtr) and the current read pointer distance (RdPtrgap) by the Depth (Depth) of the dual-port RAM; when the current read pointer address (RdPtr) is at the last bit of the dual port RAM, then the next read pointer address (NxtRdPtr) is the first bit of the dual port RAM.

In this way, the above formula (3) can construct a reading rule for displaying the cache data, so that the read pointer address can be increased according to the current read pointer interval when updating. Therefore, the aim that the data written in the round is the same as the data read in the previous round can be achieved by adjusting the numerical values of the write pointer interval and the degree pointer interval, and therefore after each display cache data is read, a new display cache data can be written in the corresponding position of the display cache data.

Step 804: and reading the display cache data from the dual-port RAM according to the next read pointer address needing to read the display cache data.

The address of the write pointer corresponding to the nth time of writing the display cache data into the dual-port RAM is the same as the address of the read pointer corresponding to the (N-D) th time of reading the display cache data from the dual-port RAM; d is the depth of the dual port RAM.

In the embodiment of the invention, the write pointer address corresponding to the Nth data writing operation is the same as the read pointer address corresponding to the (N-D) th data writing operation, namely, after the dual-port RAM is fully written with data for the first time, one data is read from the dual-port RAM every time in the follow-up process, so that a spare position is generated, and new data can be written in the spare position, thereby improving the utilization rate of the display buffer, ensuring the display continuity and not expanding the capacity of the display buffer.

Optionally, the method further comprises the steps of:

when the current read pointer address is the last bit storage address of the dual-port RAM, determining the corresponding read pointer interval when the cache data is read from the dual-port RAM for M times according to the current read pointer interval, the second constant and the depth of the dual-port RAM;

Where M is equal to the depth of the dual port RAM.

In an embodiment of the present invention, when the current read pointer address (RdPtr) is located at the last bit of the dual port RAM, the second constant (k) may be determined according to the current read pointer distance (RdPtr) ₂ ) And the Depth (Depth) of the dual port RAM, the current read pointer pitch (RdPtrGap) is updated to obtain a new read pointer pitch (nxtrddptrgap) that will be used for the subsequent M execution of step 803.

The M is the number of times of reading required by reading the data once in the display buffer, so that the read pointer interval needs to be updated every time the data is read once in the display buffer, and the purpose of matching the rule of the read data of the round with the written data of the next round can be achieved by updating the read pointer interval of each round.

Optionally, when the current read pointer address is the last bit storage address of the dual-port RAM, determining, according to the current read pointer interval, the second constant, and the depth of the dual-port RAM, the read pointer interval corresponding to M times of reading display cache data from the dual-port RAM, includes:

Taking a second preset value as an initial value of the read pointer interval, and determining the second product as the read pointer interval corresponding to M times of reading display cache data from the dual-port RAM after the second product of the current read pointer interval and the second constant is smaller than the depth of the dual-port RAM;

when the second product of the current read pointer spacing and the second constant is greater than or equal to the depth of the dual-port RAM, determining the sum of quotient and remainder obtained by dividing the second product by the depth of the dual-port RAM as the corresponding read pointer spacing when the display cache data is read from the dual-port RAM for M times.

Wherein the above step can be represented by the following formula (4):

in practical applications, since each parameter in equation (4) is a non-negative number, the rem symbol in equation (4) may be replaced by a mod symbol.

Therefore, through the formula (4), the distance between the read pointers can be changed according to a certain rule, and the distance is returned to the initial value, so that the data reading rule forms a cycle and is staggered with the data writing rule which also forms the cycle by one step, and the aim of writing new data at the corresponding position immediately after reading one data is realized.

Optionally, a second constant (k ₂ ) May be 4 and the second preset value may be 4.

In practice, the initial value of the read pointer spacing (RdPtrGap) may be 4, when the read pointer address (RdPtr) is at the last bit of the dual port RAM, if k of the read pointer spacing (RdPtrGap) ₂ The Depth (Depth) of the dual-port RAM is smaller than that of the dual-port RAM, so that the read pointer spacing (RdPtrGap) can be enlarged to be k ₂ Doubling; if k is the read pointer spacing (RdPtrgap) ₂ The next read pointer pitch (NxtRdPtrGap) is k ₂ The sum of the quotient and remainder of the read pointer spacing (RdPtrGap) divided by the Depth (Depth) of the dual port RAM.

Specifically, the depth of the dual port RAM is 8, a first constant (k ₁ ) Is 4, and a second constant (k ₂ ) For example 4, a dual port RAM of depth 8 may hold two tiles of data. Referring to fig. 9 (a), 9 (b) and 9 (c), the arrangement of the cache data is shown when the dual port RAM is full from left to right in the first to third rounds, respectively. The number on the left side of the display cache data represents the ith written display cache data in the round, and the number on the right side of the display cache data represents the ith read display cache data in the round.

The first round of full writing process:

referring to fig. 9 (a), the write pointer pitch is an initial value of 1 at the 1 st to 8 th times of writing data. According to the formula (1), the addresses of the write pointers which are required to be written into the display cache data for 1 st to 8 th times are determined to be 0, 1, 2, 3, 4, 5, 6 and 7 respectively. After the first round of writing full data, the write pointer spacing may be updated from an initial value of 1 to 4 according to equation (2) above.

Referring to fig. 9 (a), the read pointer pitch is an initial value of 4 at the 1 st to 8 th times of data reading. According to the above formula (3), it may be determined that the addresses of the read pointers for reading the display cache data for the 1 st to 8 th times are respectively 0, 4, 1, 5, 2, 6, 3, and 7. After the data written in the first round is read, the read pointer interval may be updated from the initial value 4 to 2 according to the above formula (4).

The second round of full writing process:

referring to fig. 9 (b), the write pointer pitch is 4 at the 9 th to 16 th times of writing data. According to the formula (1), the addresses of the write pointers which are required to be written into the display cache data for the 9 th to 16 th times are determined to be 0, 4, 1, 5, 2, 6, 3 and 7 respectively. It can be seen that the addresses of 8 times of writing data of the second round are equal to the addresses of 8 times of reading data of the full data written by the first round in one-to-one correspondence, namely the addresses of 9 th to 16 th writing data and 1 st to 8 th reading data are equal in one-to-one correspondence. After the second round is full of data, the write pointer spacing can be updated from 4 to 2 according to equation (2) above.

Referring to fig. 9 (b), the read pointer pitch is 2 at the 9 th to 16 th times of reading data. According to the above formula (3), it may be determined that the addresses of the read pointers for reading the display cache data for the 9 th to 16 th times are respectively 0, 2, 4, 6, 1, 3, 5, and 7. After the data written in the second round is read, the read pointer interval can be updated from 2 to 1 according to the above formula (4).

And (3) a third full-write process:

referring to fig. 9 (c), the write pointer pitch is 2 at the 17 th to 24 th times of writing data. According to the formula (1), the addresses of the write pointers which are required to be written into the display cache data for 17 th to 24 th times are determined to be 0, 2, 4, 6, 1, 3, 5 and 7 respectively. It can be seen that the addresses of the 8 times of data writing of the third round are equal to the addresses of the 8 times of data reading of the full data written by the second round in one-to-one correspondence, namely the addresses of the 17 th to 24 th times of data writing and the 9 th to 16 th times of data reading are equal in one-to-one correspondence. After the third round of full data, the write pointer spacing may be updated from 2 to 1 according to equation (2) above.

Referring to fig. 9 (c), the read pointer pitch is 1 at 17-24 times of reading data. According to the above formula (3), it may be sequentially determined that the addresses of the read pointers for reading the display cache data for 17 th to 24 th times are 0, 1, 2, 3, 4, 5, 6, and 7, respectively. After the data written on the third round is read, the read pointer interval may be updated from 1 to 4 according to the above formula (4).

The writing pointer interval is returned to 1, the reading pointer interval is returned to 4, so that the data reading and writing sequence of the fourth round, the fifth round and the sixth round is consistent with the data reading and writing sequence of the first round, the second round and the third round, the data reading and writing sequence of the seventh round, the eighth round and the ninth round is consistent with the data reading and writing sequence of the first round, the second round and the third round, and the like, namely, the reading and writing display buffer data takes three rounds as a period.

As can be seen from the above example, the address of the 1 st read data in the first round is 0, and the 9 th write data in the second round is also 0, that is, one data is read from the address 0, and one data can be written at the address 0 immediately. Similarly, the address of the 2 nd read data in the first round is 4, and the 10 th write data in the second round is also 4, that is, one data is read from the address 4, and one data can be written at the address 4 immediately. By analogy, according to the data read-write method provided by the embodiment of the invention, the display buffer can immediately write the next data when the dual-port RAM has a spare position, and compared with the existing first data read-write mode, the size of the RAM can be saved by 50%, the capacity of the RAM is not required to be enlarged, the utilization rate of the display buffer is improved, and the area cost of the display buffer is reduced. In addition, in the existing second data reading and writing method, at least 4 sub-blocks (i.e. 1 block) of display cache data need to be read, and then new 4 sub-blocks of display cache data can be rewritten, but in the data reading and writing method provided by the embodiment of the invention, new sub-block data can be written in the read position after the display cache data of the same amount is read, so that even if network delay is encountered when the data of the next block is requested to be written, 3 sub-block data of the same amount can be used in the display cache, and therefore, compared with the existing second data reading and writing method, the network delay containing capacity can be improved by 3 times, and the display continuity is ensured.

In summary, compared with the design scheme with the same performance, the display buffer provided by the invention saves 50% of RAM size, and can improve the capacity of three times of network delay.

Finally, it should be noted that the present invention is not limited to the (4×4) pixel tile transmission mode, and the specific values of the first constant, the first preset value, the second constant, the second preset value, etc. may be changed correspondingly.

It should be noted that, for simplicity of description, the method embodiments are shown as a series of acts, but it should be understood by those skilled in the art that the embodiments are not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the embodiments. Further, those skilled in the art will appreciate that the embodiments described in the specification are presently preferred embodiments, and that the acts are not necessarily required by the embodiments of the invention.

Referring to fig. 10, there is shown a block diagram of an embodiment of a data read/write device of the present invention, where the device 1000 is applied to a display controller, and the display controller includes a display buffer, and the display buffer includes a dual-port random access memory RAM, and the device 1000 may specifically include the following modules:

the write pointer determining module 1001 is configured to determine, according to the current write pointer address of the dual-port RAM, the current write pointer interval, and the depth of the dual-port RAM, a write pointer address to which display cache data needs to be written next;

a data writing module 1002, configured to, when a storage address of the display cache data that has been read exists in the dual-port RAM, write the display cache data into the dual-port RAM according to a write pointer address of the display cache data that needs to be written next;

The read pointer determining module 1003 is configured to determine, according to the current read pointer address of the dual-port RAM, the current read pointer interval, and the depth of the dual-port RAM, a next read pointer address that needs to read the display cache data;

a data reading module 1004, configured to read the display cache data from the dual-port RAM according to a read pointer address of the display cache data to be read next;

Optionally, the write pointer determination module includes:

Optionally, the read pointer determination module includes:

Optionally, the apparatus further comprises:

wherein, M equals the depth of the dual port RAM.

Optionally, the write pointer spacing determining module includes:

Optionally, the first constant is 4, and the first preset value is 1.

Optionally, the apparatus further comprises:

Wherein, M equals the depth of the dual port RAM.

Optionally, the read pointer spacing determining module includes:

Optionally, the second constant is 4, and the second preset value is 4.

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments for relevant points.

Fig. 11 is a block diagram illustrating a configuration of an electronic device 1100 for image filtering, according to an example embodiment. For example, the electronic device 1100 may be a computer, a server, or the like.

Referring to fig. 11, an electronic device 1100 may include one or more of the following components: a processing component 1102, a memory 1104, a power component 1106, a multimedia component 1108, an audio component 1110, an input/output (I/O) interface 1112, a sensor component 1114, and a communication component 1116.

The processing component 1102 generally controls overall operation of the electronic device 1100, such as operations associated with display, telephone calls, data communications, camera operations, and recording operations. The processing component 1102 may include one or more processors 1120 to execute instructions to perform all or part of the steps of the methods described above. Further, the processing component 1102 can include one or more modules that facilitate interactions between the processing component 1102 and other components. For example, the processing component 1102 may include a multimedia module to facilitate interaction between the multimedia component 1108 and the processing component 1102.

Memory 1104 is configured to store various types of data to support operations at device 1100. Examples of such data include instructions for any application or method operating on the electronic device 1100, contact data, phonebook data, messages, pictures, videos, and so forth. The memory 1104 may be implemented by any type or combination of volatile or nonvolatile memory devices such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk.

The power supply component 1106 provides power to the various components of the electronic device 1100. The power supply component 1106 can include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power for the electronic device 1100.

The multimedia component 1108 includes a screen between the electronic device 1100 and the user that provides an output interface. In some embodiments, the screen may include a Liquid Crystal Display (LCD) and a Touch Panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensor may sense not only the boundary of a touch or slide action, but also the duration and pressure associated with the touch or slide operation. In some embodiments, multimedia component 1108 includes a front camera and/or a rear camera. When the electronic device 1100 is in an operational mode, such as a shooting mode or a video mode, the front-facing camera and/or the rear-facing camera may receive external multimedia data. Each front camera and rear camera may be a fixed optical lens system or have focal length and optical zoom capabilities. The screen may be correspondingly configured with a display controller including a display buffer for outputting display buffer data to the screen, the display buffer may store the display buffer data through a dual port Random Access Memory (RAM).

The audio component 1110 is configured to output and/or input an audio signal. For example, the audio component 1110 includes a Microphone (MIC) configured to receive external audio signals when the electronic device 1100 is in an operational mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signals may be further stored in the memory 1104 or transmitted via the communication component 1116. In some embodiments, the audio component 1110 further comprises a speaker for outputting audio signals.

The I/O interface 1112 provides an interface between the processing component 1102 and peripheral interface modules, which may be keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to: homepage button, volume button, start button, and lock button.

The sensor assembly 1114 includes one or more sensors for providing status assessment of various aspects of the electronic device 1100. For example, the sensor assembly 1114 may detect an on/off state of the device 1100, a relative positioning of components such as a display and keypad of the electronic device 1100, a change in position of the electronic device 1100 or a component of the electronic device 1100, the presence or absence of a user's contact with the electronic device 1100, an orientation or acceleration/deceleration of the electronic device 1100, and a change in temperature of the electronic device 1100. The sensor assembly 1114 may include a proximity sensor configured to detect the presence of nearby objects in the absence of any physical contact. The sensor assembly 1114 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, the sensor assembly 1114 may also include an acceleration sensor, a gyroscopic sensor, a magnetic sensor, a pressure sensor, or a temperature sensor.

The communication component 1116 is configured to facilitate communication between the electronic device 1100 and other devices, either wired or wireless. The electronic device 1100 may access a wireless network based on a communication standard, such as WiFi,2G, or 3G, or a combination thereof. In one exemplary embodiment, the communication component 1116 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component 1116 further includes a Near Field Communication (NFC) module to facilitate short range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, infrared data association (IrDA) technology, ultra Wideband (UWB) technology, bluetooth (BT) technology, and other technologies.

In an exemplary embodiment, the electronic device 1100 may be implemented by one or more Application Specific Integrated Circuits (ASICs), digital Signal Processors (DSPs), digital Signal Processing Devices (DSPDs), programmable Logic Devices (PLDs), field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic elements for executing the methods described above.

In an exemplary embodiment, a non-transitory computer-readable storage medium is also provided, such as a memory 1104 including instructions executable by the processor 1120 of the electronic device 1100 to perform the above-described method. For example, the non-transitory computer readable storage medium may be ROM, random Access Memory (RAM), CD-ROM, magnetic tape, floppy disk, optical data storage device, etc.

A non-transitory computer readable storage medium that, when executed by a display buffer of an electronic device, enables the electronic device to perform a data read-write method, the method comprising:

Optionally, the method further comprises:

wherein, M equals the depth of the dual port RAM.

Optionally, the first constant is 4, and the first preset value is 1.

Optionally, the method further comprises:

wherein, M equals the depth of the dual port RAM.

Optionally, the second constant is 4, and the second preset value is 4.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

It will be apparent to those skilled in the art that embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the invention may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The foregoing has described in detail a data read-write method and apparatus, an electronic device and a storage medium, and specific examples have been applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims

1. A method for reading and writing data, the method being applied to a display controller, the display controller comprising a display buffer, the display buffer comprising a dual port random access memory RAM, the method comprising:

2. The method of claim 1, wherein determining the next write pointer address to be written to display cache data based on the current write pointer address of the dual port RAM, the current write pointer spacing, and the depth of the dual port RAM comprises:

3. The method of claim 1, wherein determining the next read pointer address to read the display cache data based on the current read pointer address of the dual port RAM, the current read pointer spacing, and the depth of the dual port RAM comprises:

4. The method according to claim 1, wherein the method further comprises:

wherein, M equals the depth of the dual port RAM.

5. The method of claim 4, wherein determining, when the current write pointer address is a last bit memory address of the dual port RAM, a write pointer pitch corresponding to M subsequent writing of the display cache data to the dual port RAM according to the current write pointer pitch, a first constant, and a depth of the dual port RAM, comprises:

6. The method of claim 5, wherein the first constant is 4 and the first preset value is 1.

7. The method according to claim 1, wherein the method further comprises:

wherein, M equals the depth of the dual port RAM.

8. The method of claim 7, wherein determining, when the current read pointer address is a last bit memory address of the dual port RAM, a read pointer distance corresponding to M subsequent reads of the display cache data from the dual port RAM according to the current read pointer distance, a second constant, and a depth of the dual port RAM, comprises:

9. The method of claim 8, wherein the second constant is 4 and the second preset value is 4.

10. A data read-write device, the device being applied to a display controller, the display controller comprising a display buffer, the display buffer comprising a dual port random access memory RAM, the device comprising:

11. The apparatus of claim 10, wherein the write pointer determination module comprises:

12. The apparatus of claim 10, wherein the read pointer determination module comprises:

13. The apparatus of claim 10, wherein the apparatus further comprises:

Wherein, M equals the depth of the dual port RAM.

14. The apparatus of claim 13, wherein the write pointer spacing determination module comprises:

15. The apparatus of claim 14, wherein the first constant is 4 and the first preset value is 1.

16. The apparatus of claim 10, wherein the apparatus further comprises:

wherein, M equals the depth of the dual port RAM.

17. The apparatus of claim 16, wherein the read pointer spacing determination module comprises:

18. The apparatus of claim 17, wherein the second constant is 4 and the second preset value is 4.

19. An electronic device comprising a memory, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by one or more display buffers, the one or more programs comprising instructions for:

20. A readable storage medium, characterized in that instructions in the storage medium, when executed by a display buffer of an electronic device, enable the electronic device to perform a data read-write method according to one or more of the method claims 1-9.