CN116841811A - Chip register test method and device, electronic equipment and storage medium - Google Patents
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Abstract
The application provides a method and a device for testing a chip register, electronic equipment and a storage medium, wherein the method comprises the following steps: acquiring the bit number and the initial address of a register to be tested and the value to be tested; calculating the number of the registers to be tested according to the number of the registers to be tested and the number of the values to be tested; according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, performing zero padding operation on the value to be tested to obtain an initial value to be tested; splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested; and testing the registers to be tested, which are the same as the number of the tests, from the starting address by the target value to be tested. The method can test a plurality of chip registers at the same time so as to improve the test efficiency of the chip registers.
Description
Technical Field
The present application relates to the field of chip testing technologies, and in particular, to a method and apparatus for testing a chip register, an electronic device, and a storage medium.
Background
With the rapid development of the semiconductor chip industry, the duration of semiconductor test work downstream of the semiconductor chip industry chain has extracted higher demands. In the conventional semiconductor test process, one of the important test links is to test a chip register, and a general test method is to write a binary number input by a user and having the same number of bits as the register into a register designated by the user and then read the binary number to complete the test of the register.
However, when the registers are tested by the test method, a user can only test one register at a time, and the test efficiency is low.
Disclosure of Invention
Accordingly, an object of the present application is to provide a method, apparatus, electronic device and storage medium for testing chip registers, which can test a plurality of chip registers at the same time to improve the testing efficiency of the chip registers.
In a first aspect, an embodiment of the present application provides a method for testing a chip register, where the method for testing a chip register includes:
acquiring the bit number and the initial address of a register to be tested and the value to be tested;
calculating the number of the registers to be tested according to the number of the registers to be tested and the number of the values to be tested;
according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, performing zero padding operation on the value to be tested to obtain an initial value to be tested;
splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested;
and testing the registers to be tested, which are the same as the number of the tests, from the starting address by the target value to be tested.
In one possible implementation manner, calculating the number of tests of the register to be tested according to the number of bits of the register to be tested and the number of bits of the value to be tested includes:
determining the ratio of the number of bits of the numerical value to be tested to the number of bits of the register to be tested as an initial test number;
if the initial test number is an integer, determining the initial test number as a target test number;
if the initial test quantity is a non-integer, performing an operation on the initial test quantity to obtain a target test quantity.
In one possible implementation manner, according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of tests of the register to be tested, performing zero padding operation on the value to be tested to obtain an initial value to be tested, including:
calculating the quantity to be supplemented according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested and the number of the registers to be tested;
and supplementing zeros with the same quantity as the quantity to be supplemented at the front edge of the value to be tested, so as to obtain the initial value to be tested.
In one possible implementation, calculating the number to be complemented according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested and the number of tests of the register to be tested includes:
the amount to be replenished is calculated by the following formula:
zeroNum＝n*dataWidth-binartValue.length；
wherein zeroNum is the number to be supplemented, n is the number of the registers to be tested, dataWidth is the number of bits of the registers to be tested, and binaryvalue.
In one possible implementation, splitting the initial value to be tested into at least one target value to be tested that is the same as the number of bits of the register to be tested includes:
according to the sequence from left to right, the initial values to be tested are sequentially split into target values to be tested, wherein the target values are the same as the digits of the registers to be tested.
In a second aspect, an embodiment of the present application further provides a device for testing a chip register, where the device for testing a chip register includes:
the acquisition module is used for acquiring the number of bits and the initial address of the register to be tested and the value to be tested;
the calculation module is used for calculating the test quantity of the register to be tested according to the number of bits of the register to be tested and the number of bits of the numerical value to be tested;
the zero-filling module is used for performing zero-filling operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, so as to obtain an initial value to be tested;
the splitting module is used for splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested;
and the test module is used for testing the registers to be tested, which are the same as the test number, from the initial address by the target value to be tested.
In one possible implementation manner, the calculating module is specifically configured to determine, as the initial test number, a ratio of a number of bits of the value to be tested to a number of bits of the register to be tested; if the initial test number is an integer, determining the initial test number as a target test number; if the initial test quantity is a non-integer, performing an operation on the initial test quantity to obtain a target test quantity.
In one possible implementation manner, the zero padding module is specifically configured to calculate the number to be padded according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested, and the number of tests of the register to be tested; and supplementing zeros with the same quantity as the quantity to be supplemented at the front edge of the value to be tested, so as to obtain the initial value to be tested.
In one possible implementation, the zero padding module is further configured to calculate the number to be padded by the following formula:
zeroNum＝n*dataWidth-binaryValue.length；
wherein zeroNum is the number to be supplemented, n is the number of the registers to be tested, dataWidth is the number of bits of the registers to be tested, and binaryvalue.
In one possible implementation, the splitting module is specifically configured to split the initial values to be tested into target values to be tested, which have the same number of bits as the registers to be tested, sequentially in a left-to-right order.
In a third aspect, an embodiment of the present application further provides an electronic device, including: a processor, a storage medium, and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium in communication over the bus when the electronic device is operating, the processor executing the machine-readable instructions to perform the steps of the method of testing a chip register as in any of the first aspects.
In a fourth aspect, embodiments of the present application also provide a computer readable storage medium having a computer program stored thereon, which when executed by a processor performs the steps of the method for testing a chip register according to any of the first aspects.
The embodiment of the application provides a method and a device for testing a chip register, electronic equipment and a storage medium, wherein the method for testing the chip register comprises the following steps: acquiring the bit number and the initial address of a register to be tested and the value to be tested; calculating the number of the registers to be tested according to the number of the registers to be tested and the number of the values to be tested; according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, performing zero padding operation on the value to be tested to obtain an initial value to be tested; splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested; and testing the registers to be tested, which are the same as the number of the tests, from the starting address by the target value to be tested. According to the application, the number of the registers to be tested, which are the same as the number of the test, from the initial address is tested by splitting the zero-filled value to be tested into at least one target value to be tested, which is the same as the number of the registers to be tested, so that a plurality of chip registers can be tested at the same time, and the test efficiency of the chip registers is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 shows a flowchart of a method for testing a chip register according to an embodiment of the present application;
FIG. 2 is a flowchart illustrating another method for testing a chip register according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a device for testing a chip register according to an embodiment of the present application;
fig. 4 shows a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described with reference to the accompanying drawings in the embodiments of the present application, and it should be understood that the drawings in the present application are for the purpose of illustration and description only and are not intended to limit the scope of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. A flowchart, as used in this disclosure, illustrates operations implemented according to some embodiments of the present application. It should be understood that the operations of the flow diagrams may be implemented out of order and that steps without logical context may be performed in reverse order or concurrently. Moreover, one skilled in the art may add one or more other operations to the flowchart and may remove one or more operations from the flowchart under the direction of this disclosure.
In addition, the described embodiments are only some, but not all, embodiments of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
In order to enable one skilled in the art to use the present disclosure, the following embodiments are presented in connection with a specific application scenario "chip test technical field". It will be apparent to those having ordinary skill in the art that the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the application. Although the application is described primarily around the "chip test technology field", it should be understood that this is only one exemplary embodiment.
It should be noted that the term "comprising" will be used in embodiments of the application to indicate the presence of the features stated hereafter, but not to exclude the addition of other features.
The following describes a test method of a chip register provided in the embodiment of the present application in detail.
Referring to fig. 1, a flow chart of a method for testing a chip register according to an embodiment of the present application is shown, where a specific implementation process of the method for testing a chip register includes:
s101, acquiring the bit number and the initial address of a register to be tested and the value to be tested.
S102, calculating the test quantity of the register to be tested according to the number of bits of the register to be tested and the number of bits of the numerical value to be tested.
S103, performing zero padding operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, and obtaining an initial value to be tested.
S104, splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested.
S105, testing the registers to be tested, which are the same as the number of the tested registers, from the initial address through the target value to be tested.
The embodiment of the application provides a test method of a chip register, which comprises the following steps: acquiring the bit number and the initial address of a register to be tested and the value to be tested; calculating the number of the registers to be tested according to the number of the registers to be tested and the number of the values to be tested; according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, performing zero padding operation on the value to be tested to obtain an initial value to be tested; splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested; and testing the registers to be tested, which are the same as the number of the tests, from the starting address by the target value to be tested. According to the application, the number of the registers to be tested, which are the same as the number of the test, from the initial address is tested by splitting the zero-filled value to be tested into at least one target value to be tested, which is the same as the number of the registers to be tested, so that a plurality of chip registers can be tested at the same time, and the test efficiency of the chip registers is improved.
Exemplary steps of embodiments of the present application are described below:
s101, acquiring the bit number and the initial address of a register to be tested and the value to be tested.
In the embodiment of the application, the initial address of the register to be tested, the value to be tested and the corresponding binary type of the value to be tested, which are sent by a user, are obtained; acquiring the bit number corresponding to the register to be tested in a register bit number storage table; the register bit number storage table stores registers to be tested and corresponding bits; if the binary type is binary type, taking the value to be tested as the final value to be tested; if the binary type is a non-binary type, converting the value to be tested into a binary type value to obtain a final value to be tested.
The register to be tested refers to a register of a semiconductor chip to be tested. The number of bits of the register to be tested may be 8 bits, 16 bits, 32 bits, etc. The initial address of the register to be tested refers to the address of the register to be tested at the forefront among all the registers to be tested, and the value to be tested refers to the value used for testing the register to be tested. The type of the value to be tested may be 2, 10, 16, etc.
S102, calculating the test quantity of the register to be tested according to the number of bits of the register to be tested and the number of bits of the numerical value to be tested.
In the embodiment of the application, the number of the registers to be tested refers to the number of the registers to be tested determined according to the number of digits of the values to be tested input by a user, and the number is also used for representing the number of the target values to be tested obtained after the values to be tested are split. The number of bits of the value to be tested is the length of the value to be tested.
If the value to be tested is 1111, the number of bits of the value to be tested is 4.
Specifically, determining the ratio of the number of bits of the value to be tested to the number of bits of the register to be tested as an initial test number; if the initial test number is an integer, determining the initial test number as a target test number; if the initial test quantity is a non-integer, performing an operation on the initial test quantity to obtain a target test quantity.
S103, performing zero padding operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, and obtaining an initial value to be tested.
In the embodiment of the application, zero padding is carried out on the value to be tested, and the number of bits of the initial value to be tested after zero padding is a multiple of the number of bits of the register to be tested; the multiple is an integer; the purpose of this is to facilitate subsequent splitting.
Specifically, the number to be supplemented is calculated according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested and the number of tests of the register to be tested.
In the embodiment of the application, the number to be supplemented refers to the number of zeros which need to be supplemented to the value to be tested.
Here, the amount to be replenished is calculated by the following formula:
zeroNum＝n*dataWidth-binaryValue.length；
wherein zeroNum is the number to be supplemented, n is the number of the registers to be tested, dataWidth is the number of bits of the registers to be tested, and binaryvalue.
For example, if the number of bits of the register to be tested is 16, the number of tests of the register to be tested is 2, the number of bits of the numerical value to be tested is 30, and the number to be supplemented is 12×16-30=2.
Specifically, the same number of zeros as the number to be replenished is replenished in front of the value to be tested, so as to obtain the initial value to be tested.
For example, if the value to be tested is 101101110011011001001100111010 and the number to be supplemented is 2, the initial value to be tested after supplementation is 00101101110011011001001100111010.
S104, splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested.
In the embodiment of the application, the number of the target to-be-tested values obtained through splitting is the same as the number of the to-be-tested registers.
Specifically, according to the sequence from left to right, the initial value to be tested is sequentially split into target values to be tested, which have the same number of bits as the register to be tested.
For example, the initial value to be tested is 00101101110011011001001100111010 and the number of bits of the register to be tested is 16, then the target values to be tested include 0010110111001101 and 1001001100111010.
S105, testing the registers to be tested, which are the same as the number of the tested registers, from the initial address through the target value to be tested.
In the embodiment of the application, each target value to be tested is sequentially stored in each register to be tested, so as to obtain the storage content of each register to be tested; reading the content of each register to be tested after the storage is completed, and obtaining the read content of each register to be tested; if the storage content and the reading content of the register to be tested are the same, the test result is qualified; if the storage content of the register to be tested is the same as the reading content, the test result is unqualified.
For example, the target to-be-tested values include 0010110111001101 and 1001001100111010, if the starting address is n and the number of tests is 2, the to-be-tested registers include a to-be-tested register with an address of n and a to-be-tested register with an address of n+1, 0010110111001101 is stored in the to-be-tested register with an address of n, and 1001001100111010 is stored in the to-be-tested register with an address of n+1; after the storage is completed, reading the contents in the register to be tested, including the register to be tested with the address of n and the register to be tested with the address of n+1; if the storage content and the reading content of the register to be tested are the same, the test result is qualified; if the storage content of the register to be tested is the same as the reading content, the test result is unqualified.
Referring to fig. 2, a flow chart of a method for testing a chip register according to an embodiment of the present application is shown, and the method is used for calculating the number of tests of the register to be tested according to the number of bits of the register to be tested and the number of bits of the numerical value to be tested, and the following description is given of exemplary steps of the embodiment of the present application:
s201, determining the ratio of the number of bits of the value to be tested to the number of bits of the register to be tested as the initial test number.
In the embodiment of the application, the initial test quantity is used for representing the split quantity which can be obtained by splitting the value to be tested and is the same as the number of bits of the register to be tested. The number of splits obtained here may be an integer or a non-integer.
In example 1, the number of bits of the value to be tested is 30, the number of bits of the register to be tested is 16, and the initial test number is 30/16=1.875.
In example 2, the number of bits of the value to be tested is 32, the number of bits of the register to be tested is 16, and the initial test number is 32/16=2.
S202, if the initial test number is an integer, determining the initial test number as a target test number.
In the embodiment of the present application, if the initial test number is an integer, it indicates that the value to be tested can be completely split into at least one value identical to the number of bits of the register to be tested. For example, if the initial test number is 2, the target test number is 2.
S203, if the initial test number is a non-integer, performing an operation on the initial test number to obtain a target test number.
In the embodiment of the application, if the initial test number is an integer, it is indicated that the value to be tested cannot be completely split into at least one value identical to the number of bits of the register to be tested. For example, if the initial test number is 1.875, then after proceeding to the initial test number, the target test number is 2; if the initial test number is 3.22, the target test number is 4 after the initial test number is further.
The embodiment of the application provides another method for testing chip registers, which comprises the steps of determining the ratio of the number of bits of a numerical value to be tested to the number of bits of a register to be tested as initial test quantity; if the initial test number is an integer, determining the initial test number as a target test number; if the initial test quantity is a non-integer, performing an operation on the initial test quantity to obtain a target test quantity. By the method, the target test quantity can be determined.
Based on the same inventive concept, the embodiment of the application also provides a device for testing a chip register, which corresponds to the method for testing a chip register.
Referring to fig. 3, a schematic diagram of a testing apparatus for a chip register according to an embodiment of the present application is shown, where the testing apparatus for a chip register includes:
the obtaining module 301 is configured to obtain a number of bits and a start address of a register to be tested, and a value to be tested;
the calculating module 302 is configured to calculate a test number of the register to be tested according to a number of bits of the register to be tested and a number of bits of the value to be tested;
the zero-filling module 303 performs zero-filling operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, so as to obtain an initial value to be tested;
the splitting module 304 is configured to split the initial value to be tested into at least one target value to be tested, where the target value to be tested has the same number of bits as the register to be tested;
the test module 305 is configured to test the same number of registers to be tested as the number of tests, starting from the start address, by targeting the value to be tested.
In one possible implementation, the calculating module 302 is specifically configured to determine, as the initial test number, a ratio of a number of bits of the value to be tested to a number of bits of the register to be tested; if the initial test number is an integer, determining the initial test number as a target test number; if the initial test quantity is a non-integer, performing an operation on the initial test quantity to obtain a target test quantity.
In one possible implementation manner, the zero padding module 303 is specifically configured to calculate the number to be padded according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested, and the number of tests of the register to be tested; and supplementing zeros with the same quantity as the quantity to be supplemented at the front edge of the value to be tested, so as to obtain the initial value to be tested.
In one possible implementation, the zero padding module 303 is further configured to calculate the amount to be padded by the following formula:
zeroNum＝n*dataWidth-binaryValue.length；
wherein zeroNum is the number to be supplemented, n is the number of the registers to be tested, dataWidth is the number of bits of the registers to be tested, and binaryvalue.
In one possible implementation, the splitting module 304 is specifically configured to split the initial values to be tested into target values to be tested, which have the same number of bits as the registers to be tested, sequentially in a left-to-right order.
The embodiment of the application provides a testing device of a chip register, which comprises: the obtaining module 301 is configured to obtain a number of bits and a start address of a register to be tested, and a value to be tested; the calculating module 302 is configured to calculate a test number of the register to be tested according to a number of bits of the register to be tested and a number of bits of the value to be tested; the zero-filling module 303 performs zero-filling operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, so as to obtain an initial value to be tested; the splitting module 304 is configured to split the initial value to be tested into at least one target value to be tested, where the target value to be tested has the same number of bits as the register to be tested; the test module 305 is configured to test the same number of registers to be tested as the number of tests, starting from the start address, by targeting the value to be tested. According to the application, the number of the registers to be tested, which are the same as the number of the test, from the initial address is tested by splitting the zero-filled value to be tested into at least one target value to be tested, which is the same as the number of the registers to be tested, so that a plurality of chip registers can be tested at the same time, and the test efficiency of the chip registers is improved.
As shown in fig. 4, an electronic device 400 provided in an embodiment of the present application includes: the device comprises a processor 401, a memory 402 and a bus, the memory 402 storing machine-readable instructions executable by the processor 401, the processor 401 executing the machine-readable instructions to perform steps of a method for testing a chip register as described above when the electronic device is running, the processor 401 communicating with the memory 402 via the bus.
Specifically, the memory 402 and the processor 401 can be general-purpose memories and processors, and are not particularly limited herein, and the method for testing the chip registers can be performed when the processor 401 runs a computer program stored in the memory 402.
Corresponding to the above method for testing the chip register, the embodiment of the application also provides a computer readable storage medium, on which a computer program is stored, which executes the steps of the above method for testing the chip register when being executed by a processor.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described system and apparatus may refer to corresponding procedures in the method embodiments, and are not repeated in the present disclosure. In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, and the division of the modules is merely a logical function division, and there may be additional divisions when actually implemented, and for example, multiple modules or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, indirect coupling or communication connection of devices or modules, electrical, mechanical, or other form.
The modules described as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the information processing method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily appreciate variations or alternatives within the scope of the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.
Claims (10)
1. The test method of the chip register is characterized by comprising the following steps of:
acquiring the bit number and the initial address of a register to be tested and the value to be tested;
calculating the number of the registers to be tested according to the number of the registers to be tested and the number of the numerical values to be tested;
performing zero padding operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of the registers to be tested, so as to obtain an initial value to be tested;
splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested has the same number of bits as the register to be tested;
and testing the registers to be tested, which are started from the starting address and have the same number as the test number, by the target value to be tested.
2. The method for testing a chip register according to claim 1, wherein calculating the number of tests of the register to be tested according to the number of bits of the register to be tested and the number of bits of the value to be tested comprises:
determining the ratio of the number of bits of the numerical value to be tested to the number of bits of the register to be tested as an initial test number;
if the initial test number is an integer, determining the initial test number as a target test number;
and if the initial test quantity is a non-integer, carrying out an operation on the initial test quantity to obtain a target test quantity.
3. The method for testing a chip register according to claim 1 or 2, wherein performing zero padding operation on the value to be tested according to the number of bits of the register to be tested, the number of bits of the value to be tested and the number of tests of the register to be tested to obtain an initial value to be tested, comprises:
calculating the quantity to be supplemented according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested and the number of the registers to be tested;
and supplementing zeros with the same quantity as the quantity to be supplemented at the front edge of the value to be tested, so as to obtain an initial value to be tested.
4. A method for testing a chip register according to claim 3, wherein said calculating the number to be complemented based on the number of bits of the register to be tested, the number of bits of the numerical value to be tested, and the number of tests of the register to be tested comprises:
the amount to be replenished is calculated by the following formula:
zeroNum＝n*dataWidth-binartValue.length；
wherein zeroNum is the number to be supplemented, n is the number of the registers to be tested, dataWidth is the number of bits of the registers to be tested, and binaryvalue.
5. The method for testing a chip register according to claim 1, wherein splitting the initial value to be tested into at least one target value to be tested having the same number of bits as the register to be tested comprises:
and sequentially splitting the initial value to be tested into target value to be tested, which is the same as the number of bits of the register to be tested, according to the sequence from left to right.
6. A device for testing a chip register, the device comprising:
the acquisition module is used for acquiring the number of bits and the initial address of the register to be tested and the value to be tested;
the calculation module is used for calculating the test quantity of the register to be tested according to the bit number of the register to be tested and the bit number of the numerical value to be tested;
the zero-filling module is used for performing zero-filling operation on the to-be-tested numerical value according to the number of bits of the to-be-tested register, the number of bits of the to-be-tested numerical value and the test number of the to-be-tested register to obtain an initial to-be-tested numerical value;
the splitting module is used for splitting the initial value to be tested into at least one target value to be tested, wherein the target value to be tested is the same as the number of bits of the register to be tested;
and the test module is used for testing the registers to be tested, which are started from the starting address and have the same number as the test number, through the target value to be tested.
7. The device for testing a chip register according to claim 6, wherein the computing module is specifically configured to:
determining the ratio of the number of bits of the numerical value to be tested to the number of bits of the register to be tested as an initial test number;
if the initial test number is an integer, determining the initial test number as a target test number;
and if the initial test quantity is a non-integer, carrying out an operation on the initial test quantity to obtain a target test quantity.
8. The device for testing a chip register according to claim 6 or 7, wherein the zero padding module is specifically configured to:
calculating the quantity to be supplemented according to the number of bits of the register to be tested, the number of bits of the numerical value to be tested and the number of the registers to be tested;
and supplementing zeros with the same quantity as the quantity to be supplemented at the front edge of the value to be tested, so as to obtain an initial value to be tested.
9. An electronic device, comprising: a processor, a storage medium and a bus, the storage medium storing machine-readable instructions executable by the processor, the processor and the storage medium communicating over the bus when the electronic device is running, the processor executing the machine-readable instructions to perform the steps of the method of testing a chip register as claimed in any one of claims 1 to 5.
10. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, performs the steps of the method for testing a chip register according to any one of claims 1 to 5.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117215857A (en) * | 2023-10-31 | 2023-12-12 | 紫光同芯微电子有限公司 | Method for verifying eligibility of chip register, chip and electronic equipment |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117215857A (en) * | 2023-10-31 | 2023-12-12 | 紫光同芯微电子有限公司 | Method for verifying eligibility of chip register, chip and electronic equipment |
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