CN116841617A - Multi-priority hardware timer in real-time field - Google Patents
Multi-priority hardware timer in real-time field Download PDFInfo
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- CN116841617A CN116841617A CN202310798367.1A CN202310798367A CN116841617A CN 116841617 A CN116841617 A CN 116841617A CN 202310798367 A CN202310798367 A CN 202310798367A CN 116841617 A CN116841617 A CN 116841617A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
Abstract
The invention relates to a multi-priority hardware timer in the real-time field, which comprises a timer unit and a priority control unit; the timer unit includes: a timing module and a plurality of comparison registers; the timing module and each comparison register form a hardware timer, and when the value in the timing module is greater than or equal to the value of the comparison register, an interrupt signal is generated; the priority control unit includes: an interrupt arbitration module, a low priority mask register, a timing enable register, a timer ID register, and a priority configuration register; the timer enabling register enables the timing module; the priority configuration register is used for configuring the priority of the comparison register; the low-priority shielding register is used for shielding the interrupt signals with low priority; the interrupt arbitration module is used for arbitrating the interrupt signal of the hardware timer, updating the content of the timer ID register into the ID number of the hardware timer with the highest priority after interrupt arbitration, and forwarding the interrupt signal to the processor.
Description
Technical Field
The invention belongs to the technical field of instantaneity, and relates to a multi-priority hardware timer in the field of instantaneity.
Background
There are typically multiple tasks in real-time systems with different priorities and execution periods. Strict task scheduling and control is necessary to ensure the real-time and reliability of the system. In this case, the timer is a very important tool, which can trigger some actions at regular time, such as periodic tasks and delay waiting. Conventional timers are largely divided into software timers and hardware timers.
Conventional software timers are typically implemented on a software basis, typically in the following manner: a global variable timer_counter is defined, which represents a timer counter for recording the time elapsed since the system was started, and has an initial value of 0. A timer handling function timer _ isr is defined for handling timer interrupts. The function will trigger an interrupt when the timer reaches the set time, depending on the setting of the timer. A timer initialization function timer init is defined for initializing timer related parameters. This function requires setting parameters such as the counting mode, counting rate, timing time of the timer, etc., and an associated timer handling function timer _ isr. And when the system is initialized, a timer initialization function timer_init is called for initialization. The timer counter will be continuously incremented while the system is running. When the timer counter reaches the set timing time, a timer interrupt is triggered, and a timer processing function timer_isr is executed. In the timer processing function timer_isr, relevant processing is performed according to specific requirements. For example, a timer interrupt may be considered an event that notifies the relevant task to process.
The conventional software timer has the following problems: the precision of the traditional timer is influenced by factors such as the precision of a system clock, the scheduling delay of an operating system and the like, and the requirement of a real-time system on high-precision timing cannot be met. The timers are typically managed using linked lists and arrays of data structures, which require traversing all timers to find and process, which is inefficient. Typically user-oriented, if the timer handling function is problematic, it may cause a system crash or security breach. Only fixed trigger modes and timing modes are usually supported, and flexible expansion and customization are not possible. Usually only a single priority can be supported, and the timers of different tasks cannot be prioritized, which causes the following problems: timer interrupts for low priority tasks can interfere with the execution of high priority tasks, affecting the response time of high priority tasks. The priority is reversed, the low priority is higher than the high priority response, and the low priority task is equivalent to the high priority task when seen from the scheduling layer, so that the scheduling performance and the real-time performance are affected.
Conventional hardware timers are typically composed of one or more counters, one or more comparators, and one or more interrupt controllers, implemented as follows: one or more counter registers are defined for counting. The counter is typically a binary counter of fixed length, which will generate an interrupt when overflowed. One or more comparator registers are defined for setting the trigger time of the timer. An interrupt will be generated when the value of the counter is equal to the value of the comparator. An interrupt controller is defined for controlling the triggering and handling of timer interrupts. The interrupt controller may receive the interrupt signal from the counter and the comparator and forward the interrupt signal to the processor. When the system is initialized, parameters such as a counting mode, a counting rate, a set value of a comparator and the like of the timer are configured. The timer will be incremented continuously while the system is running and a timer interrupt will be triggered when the value of the counter is equal to the set value of the comparator. In the timer interrupt processing function, relevant processing is performed according to specific requirements. For example, a timer interrupt may be considered an event that notifies the relevant task to process.
The conventional hardware timer has the following problems: conventional hardware timers typically only support a single priority, cannot perform multi-priority scheduling and management, and cannot distinguish timers for different tasks. This makes it difficult to use in complex multitasking systems. Conventional hardware timers typically require setting the trigger time of the timer at initialization and once set cannot be dynamically adjusted at run-time. This makes it difficult to cope with dynamic system demands.
Disclosure of Invention
In order to solve the technical problems, the invention aims to provide a multi-priority hardware timer in the real-time field, which can support multiple tasks and multiple priorities, can distinguish different tasks, supports multiple timing modes and triggering modes and can meet the requirements of different real-time tasks.
The invention provides a multi-priority hardware timer in the real-time field, which comprises a timer unit and a priority control unit which are connected with each other;
the timer unit includes: the timing module and the plurality of comparison registers are connected with the timing module; the timing module and each comparison register form a hardware timer, the timing module counts at a specific frequency after being enabled by the priority control unit, and when the value in the timing module is greater than or equal to the value of the comparison register, the corresponding comparison register can generate a timing interrupt signal;
the priority control unit includes: an interrupt arbitration module, a low priority mask register, a timing enable register, a timer ID register, and a plurality of priority configuration registers; the low-priority shielding register is respectively connected with the plurality of comparison registers, the plurality of priority configuration registers and the interrupt arbitration module;
the timer enabling register is used for enabling the timing module; the priority configuration register is used for configuring the priority of the corresponding comparison register according to the instruction of the processor; the low-priority shielding register is used for shielding the interrupt signal of the low-priority hardware timer; the interrupt arbitration module is used for arbitrating the interrupt signal of the hardware timer, updating the content of the timer ID register into the ID number of the hardware timer with the highest priority after interrupt arbitration, and forwarding the interrupt signal of the hardware timer to the processor.
Further, when executing a high priority task, the processor updates the low priority mask register to the priority of the high priority task, and all timed interrupt signals below the priority will be masked.
Further, the processor allocates corresponding access addresses for the low priority mask register, the timing enable register, the timer ID register, the priority configuration register, and the comparison register; the priority configuration register and the comparison register are addressed in sequence, and the ID number of the hardware timer is distributed from 0;
and the processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address in a memory mapping input/output mode.
Further, the processor configures the hardware timer to different priorities by writing a priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer at run-time; the highest bit of the priority configuration register is used for recording whether the corresponding hardware timer is idle currently, and the rest bits are used for recording the priority of the corresponding hardware timer; if the hardware timer is idle, then the interrupt signal generated by the hardware timer is also masked by the low priority mask register.
Further, the ID number of the hardware timer stored in the timer ID register is read by the processor to determine which task the timer interrupt of the hardware timer belongs to.
Further, when a task needs to apply for a hardware timer, firstly, reading the value of a priority configuration register corresponding to the first hardware timer according to the sequence of the ID numbers, and judging whether the corresponding hardware timer is idle according to whether the highest bit of the value of the priority configuration register is 0; if the hardware timer is idle, the allocation is successful, the highest bit of the priority configuration register is modified to be 1, and the priority of the hardware timer is written into the priority configuration register together; if not, accessing the priority configuration register corresponding to the next hardware timer to judge again.
Furthermore, the timing module and each comparison register perform reading and writing in a memory mapping input/output mode.
The invention relates to a multi-priority hardware timer in the real-time field, which at least comprises the following steps
The beneficial effects are that:
1. compared with a software timer, the multi-priority hardware timer has the characteristic of high precision, the timing precision of the timer can be configured according to the requirement, and the upper limit is limited only by the time sequence of a processor and the highest frequency of a hardware crystal oscillator.
2. No look-up and processing of the timer is required. The timer is directly managed by hardware, so that the processing efficiency of the timer is greatly improved.
3. The hardware timers of different tasks in the timer unit can be distinguished, and the priority can be configured according to different demands of the tasks, so that the requirements of various tasks can be met more flexibly. Meanwhile, the hardware timers are classified and managed according to the priorities, the hardware timers with different priorities can be independently triggered, and the interrupt arbitration module can determine whether to respond to the interrupt of the corresponding hardware timer by judging the priorities, so as to determine whether to execute a scheduling algorithm for scheduling and processing. The interference of low-priority tasks to high-priority tasks is avoided, the problems that the system response is slow and even deadlock occurs possibly are avoided, and the real-time performance and the reliability of the system are greatly improved.
4. The processing function of the software layer is realized on the kernel of the operating system, so that the processing efficiency of the timer is improved, and the safety of the system is ensured.
5. The system has flexible configuration and expansion modes, the hardware aspect has flexible and expandable characteristics through an implementation mode similar to an accelerator, and a user can perform customized configuration and adjustment according to own requirements and even add new functions; the software aspect is more flexible, and a user can directly use the timer or package the timer based on the timer, design a new timer library and fully play the characteristics of the timer.
6. The time and priority of the timer can be dynamically adjusted, avoiding the problems of the traditional hardware timer in this aspect.
7. The design of the timing enabling register enables the actual multitasking configuration and execution to be more in accordance with the assumption conditions in theoretical research, namely, from the time axis, the simultaneous release and execution of a plurality of tasks is truly realized.
8. The software timer needs to occupy CPU resources to perform timing operation, and the multi-priority hardware timer is controlled by hardware, does not need to occupy CPU resources, and can make the CPU concentrate on the execution of other tasks.
9. The multi-priority hardware timer is controlled by hardware, is not influenced by software, can realize higher real-time performance, and can execute timing tasks more accurately.
10. The multi-priority hardware timer can better utilize system resources, effectively distinguish high-priority tasks from low-priority tasks, reduce the interference of the low-priority tasks on the high-priority tasks, and improve the response speed of the high-priority tasks.
Drawings
FIG. 1 is a block diagram of a multi-priority hardware timer in the field of real-time performance of the present invention;
fig. 2 is a block diagram of the structure of the priority control unit of the present invention.
Detailed Description
As shown in fig. 1 and 2, a multi-priority hardware timer in the real-time domain of the present invention includes a timer unit and a priority control unit connected to each other. The timer unit includes: the timing module and the plurality of comparison registers are connected with the timing module; the timing module and each comparison register form a hardware timer, the timing module counts at a specific frequency after being enabled by the priority control unit, and when the value in the timing module is greater than or equal to the value of the comparison register, the corresponding comparison register generates a timing interrupt signal.
The priority control unit includes: an interrupt arbitration module, a low priority mask register, a timing enable register, a timer ID register, and a plurality of priority configuration registers; the low-priority mask register is respectively connected with the plurality of comparison registers, the plurality of priority configuration registers and the interrupt arbitration module. The timer enabling register is used for enabling the timing module; the priority configuration register is used for configuring the priority of the corresponding comparison register according to the instruction of the processor; the low-priority shielding register is used for shielding the interrupt signal of the low-priority hardware timer; the interrupt arbitration module is used for arbitrating the interrupt signal of the hardware timer, updating the content of the timer ID register into the ID number of the hardware timer with the highest priority after interrupt arbitration, and forwarding the interrupt signal of the hardware timer to the processor.
In specific implementation, the timing module and each comparison register perform reading and writing in a memory mapping input/output mode.
In particular, when executing a high priority task, the processor updates the low priority mask register to the priority of the high priority task, and all timed interrupt signals below that priority will be masked.
In specific implementation, the processor allocates corresponding access addresses for a low-priority mask register, a timing enable register, a timer ID register, a priority configuration register and a comparison register; the priority configuration register and the comparison register are addressed in sequence, and the ID number of the hardware timer is distributed from 0; and the processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address in a memory mapping input/output mode.
In particular, the processor configures the hardware timer to different priorities by writing a priority configuration register corresponding to the hardware timer, and dynamically adjusts the priority of the hardware timer at run-time; the highest bit of the priority configuration register is used for recording whether the corresponding hardware timer is idle currently, and the rest bits are used for recording the priority of the corresponding hardware timer; if the hardware timer is idle, then the interrupt signal generated by the hardware timer is also masked by the low priority mask register.
In practice, the ID number of the hardware timer stored in the timer ID register will be read by the processor to determine which task the timer interrupt of the hardware timer belongs to.
Examples
When a task needs to apply for a hardware timer, firstly reading the value of a priority configuration register corresponding to the first hardware timer according to the sequence of ID numbers, and judging whether the corresponding hardware timer is idle according to whether the highest bit of the value of the priority configuration register is 0; if the hardware timer is idle, the allocation is successful, the highest bit of the priority configuration register is modified to be 1, and the priority of the hardware timer is written into the priority configuration register together; if not, accessing the priority configuration register corresponding to the next hardware timer to judge again.
After the task applies to a timer, a corresponding comparison register can be calculated and configured according to the timing requirement by reading the count value in the current timing module. For example: the counting frequency of the timing module is a (Hz), the counting value of the current timer module is x, and the task needs to count b(s), and then the value of x+a×b is written into a corresponding comparison register.
When the timer unit generates a plurality of interrupt signals in the same time period, the low-priority shielding register firstly shields the interrupt signals sent by the hardware timers with priority lower than that of the low-priority shielding register, the rest interrupt signals enter the priority control unit to be arbitrated, the interrupt signal with the highest priority is selected and sent to the processor, and the content of the timer ID register is updated to the ID number of the hardware timer with the highest priority. The processor reads the ID number stored in the timer ID register, determines which task the timer interrupt of the hardware timer belongs to, and executes the task.
In practice, if a task is to log off a timer, it is only necessary to configure the highest bit of the corresponding priority configuration register to 0.
In specific implementation, when the task execution starts, the low-priority shielding register can be configured as the priority of the task to shield all low-priority timer interrupts, so that the interference of the low-priority timer interrupts to the current task is avoided, and the situation of priority inversion is also avoided.
In particular, if the priority of the task needs to be adjusted in the running process, the priority configuration register of the allocated hardware timer can be modified.
In particular, if the timer time needs to be adjusted in the running process, the comparison register of the allocated hardware timer can be modified.
In specific implementation, some theoretical research works have the requirement of releasing and executing a plurality of periodic tasks at the same time, but the actual hardware timer is always timing, which leads to that the releasing and executing time of each task is not the same, but the timing can be started after all tasks are established and completed through the timing enabling register, so that the requirement of releasing and executing a plurality of tasks at the same time can be met, and errors existing in releasing and executing a plurality of tasks at the same time are eliminated for related theoretical research. And the design of the timing enabling register enables the user to use the timer more flexibly.
The multi-priority hardware timer in the real-time field mainly comprises a timer unit and a priority control unit, wherein the timer unit is used for timing, and the priority control unit is used for realizing the functions of enabling a timing module in the timer unit, configuring priority, distributing a hardware timer, shielding interrupt signals of the low-priority hardware timer and the like.
The register in the multi-priority hardware timer in the real-time field can be read and written in a Memory-mapped I/O (MMIO) mode, and can also be controlled in a custom instruction mode.
The design of the timing enabling register can enable the application of a user to the timer to be more flexible, and can meet the requirements of some research works.
The design of the low-priority shielding register can realize shielding of the interrupt signal of the low-priority hardware timer, so that the interference of the interrupt signal of the low-priority hardware timer to the current task is avoided, and the condition of priority inversion is also avoided.
The design of the priority configuration register can be used for configuring the priority of the hardware timer, and meanwhile, the highest bit of the priority configuration register is used as the idle flag bit of the hardware timer, so that the idle flag modifying operation and the priority distributing operation can be combined into one operation to be executed.
The design of the timer ID register realizes the distinction of the interrupts of different hardware timers, and an interrupt processing program can know which task the interrupts of the hardware timers belong to by reading the register. The design reduces the complexity of the hardware interface and ensures that the whole interrupt processing flow is simpler and more visual.
Each time the multi-priority hardware timer of the present invention is generated, it will operate based on the current configuration of each register. Thanks to this implementation logic, the priority and time of the timer can be dynamically adjusted at run-time.
The foregoing description of the preferred embodiments of the invention is not intended to limit the scope of the invention, but rather to enable any modification, equivalent replacement, improvement or the like to be made without departing from the spirit and principles of the invention.
Claims (7)
1. The multi-priority hardware timer in the real-time field is characterized by comprising a timer unit and a priority control unit which are connected with each other;
the timer unit includes: the timing module and the plurality of comparison registers are connected with the timing module; the timing module and each comparison register form a hardware timer, the timing module counts at a specific frequency after being enabled by the priority control unit, and when the value in the timing module is greater than or equal to the value of the comparison register, the corresponding comparison register can generate a timing interrupt signal;
the priority control unit includes: an interrupt arbitration module, a low priority mask register, a timing enable register, a timer ID register, and a plurality of priority configuration registers; the low-priority shielding register is respectively connected with the plurality of comparison registers, the plurality of priority configuration registers and the interrupt arbitration module;
the timer enabling register is used for enabling the timing module; the priority configuration register is used for configuring the priority of the corresponding comparison register according to the instruction of the processor; the low-priority shielding register is used for shielding the interrupt signal of the low-priority hardware timer; the interrupt arbitration module is used for arbitrating the interrupt signal of the hardware timer, updating the content of the timer ID register into the ID number of the hardware timer with the highest priority after interrupt arbitration, and forwarding the interrupt signal of the hardware timer to the processor.
2. The multi-priority hardware timer for the real-time domain of claim 1 wherein when a high priority task is executing, the processor updates the low priority mask register to the priority of the high priority task, all timed interrupt signals below the priority being masked.
3. The multi-priority hardware timer of claim 1 wherein the processor assigns corresponding access addresses to the low priority mask register, the timing enable register, the timer ID register, the priority configuration register, and the compare register; the priority configuration register and the comparison register are addressed in sequence, and the ID number of the hardware timer is distributed from 0;
and the processor reads and writes all registers of the multi-priority hardware timer according to the allocated access address in a memory mapping input/output mode.
4. A multi-priority hardware timer in the real-time domain as claimed in claim 3 wherein the processor configures the hardware timer to different priorities by writing a priority configuration register corresponding to the hardware timer and dynamically adjusts the priority of the hardware timer at run-time; the highest bit of the priority configuration register is used for recording whether the corresponding hardware timer is idle currently, and the rest bits are used for recording the priority of the corresponding hardware timer; if the hardware timer is idle, then the interrupt signal generated by the hardware timer is also masked by the low priority mask register.
5. The multi-priority hardware timer in the real-time domain of claim 1 wherein the ID number of the hardware timer stored in the timer ID register is read by the processor for determining which task the timer interrupt of the hardware timer belongs to.
6. The multi-priority hardware timer in real-time domain according to claim 3, wherein when a task needs to apply for a hardware timer, firstly reading the value of the priority configuration register corresponding to the first hardware timer according to the sequence of the ID number, and judging whether the corresponding hardware timer is idle according to whether the highest bit of the value of the priority configuration register is 0; if the hardware timer is idle, the allocation is successful, the highest bit of the priority configuration register is modified to be 1, and the priority of the hardware timer is written into the priority configuration register together; if not, accessing the priority configuration register corresponding to the next hardware timer to judge again.
7. The multi-priority hardware timer in the real-time domain according to claim 1, wherein the timing module and each comparison register are read and written by means of memory mapping input and output.
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| CN202310798367.1A CN116841617A (en) | 2023-07-03 | 2023-07-03 | Multi-priority hardware timer in real-time field |
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| CN202310798367.1A CN116841617A (en) | 2023-07-03 | 2023-07-03 | Multi-priority hardware timer in real-time field |
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