CN116828967A - Manufacturing method of memory structure, memory structure and memory - Google Patents

Manufacturing method of memory structure, memory structure and memory Download PDF

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Publication number
CN116828967A
CN116828967A CN202310768708.0A CN202310768708A CN116828967A CN 116828967 A CN116828967 A CN 116828967A CN 202310768708 A CN202310768708 A CN 202310768708A CN 116828967 A CN116828967 A CN 116828967A
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CN
China
Prior art keywords
layer
conductive metal
insulating layer
metal
memory
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CN202310768708.0A
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Chinese (zh)
Inventor
贾萌恩
郭秋生
张继伟
丁甲
胡林辉
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GTA Semiconductor Co Ltd
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GTA Semiconductor Co Ltd
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Priority to CN202310768708.0A priority Critical patent/CN116828967A/en
Publication of CN116828967A publication Critical patent/CN116828967A/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

The application discloses a manufacturing method of a memory structure, the memory structure and the memory, wherein the manufacturing method of the memory structure comprises the steps of carrying out patterning treatment on a first metal layer, and forming a first insulating layer on the first metal layer; etching a first through hole communicated with the first metal layer on the first insulating layer; depositing a memory cell within the first insulating layer and the first via, and depositing a first conductive metal over the memory cell; developing the memory cell on the first conductive metal, and respectively etching the first conductive metal and the memory cell to obtain a memory cell pattern; a stop layer is deposited over the first insulating layer and the first conductive metal. According to the application, the memory unit can be arranged in the VIA hole of the semiconductor, so that the area of the memory is increased, the problem that the effective area of the memory is difficult to increase on the basis of the prior art in the prior art is solved, and the device performance of the memory is improved.

Description

Manufacturing method of memory structure, memory structure and memory
Technical Field
The present application relates to the field of semiconductor manufacturing devices, and in particular, to a method for manufacturing a memory structure, and a memory.
Background
The phase change or ferroelectric memory is a device with a memory cell integrated with a back-end circuit layer, and the device performance of the memory is proportional to the effective areas of the memory layer material and the electrode layer material.
The memory unit of the existing memory is a planar material structure composed of upper and lower electrodes and intermediate phase change materials, ferroelectric materials or magnetoresistive materials, and the effective area of the memory obtained based on the mode is difficult to increase on the basis of the prior art, so that the device performance of the memory is difficult to improve.
Based on this, a new solution is needed.
Disclosure of Invention
In view of the above, embodiments of the present application provide a method for manufacturing a memory structure, a memory structure and a memory.
The embodiment of the application provides the following technical scheme:
the manufacturing method of the memory structure provided by the embodiment of the application comprises the following steps:
patterning the first metal layer, and forming a first insulating layer on the first metal layer;
etching a first through hole communicated with the first metal layer on the first insulating layer;
depositing a memory cell within the first insulating layer and the first via, and depositing a first conductive metal on the memory cell;
developing the memory cell on the first conductive metal, and respectively etching the first conductive metal and the memory cell to obtain a memory cell pattern;
a stop layer is deposited over the first insulating layer and the first conductive metal.
Further, after depositing a stop layer on the first insulating layer and the first conductive metal, further comprising:
depositing a second insulating layer on the stop layer, and forming a second through hole penetrating through the second insulating layer and the stop layer;
depositing a second conductive metal in the second through hole so as to connect the second conductive metal with the first conductive metal;
and a second metal layer is arranged on the second insulating layer.
Further, the etching the first conductive metal and the memory cell, respectively, to obtain a memory cell pattern includes:
applying an anti-reflective coating over the first conductive metal to protect the memory cell;
etching the area of the first conductive metal corresponding to the non-memory cell;
and etching the non-storage area of the storage unit based on the etched first conductive metal to obtain a storage unit pattern.
Further, etching the non-storage area of the storage unit based on a metal etching process to obtain a storage unit pattern.
Further, depositing a memory cell on the first insulating layer and the sidewall of the first via includes:
and sequentially depositing a lower electrode, a functional layer and an upper electrode in the first insulating layer and the first through hole.
Further, the lower electrode, the functional layer and the upper electrode are sequentially deposited in the first insulating layer and the first via hole based on an atomic layer deposition method.
The memory structure provided by the embodiment of the application comprises:
a first metal layer;
the first insulating layer is arranged on the first metal layer, and a first through hole communicated with the first metal layer is formed in the first insulating layer;
the storage unit is arranged on the first through hole and the first insulating layer;
a first conductive metal disposed on the memory cell;
and the stop layer is arranged on the first insulating layer and the first conductive metal.
Further, the memory structure further includes:
a second insulating layer disposed on the stop layer;
a second via hole penetrating through the second insulating layer and the stop layer and extending to the first conductive metal;
the second conductive metal is arranged in the second through hole and is connected with the first conductive metal;
and the second metal layer is arranged on the second insulating layer and is connected with the second conductive metal.
Further, the lower electrode of the memory cell is in contact connection with the first metal layer, and the upper electrode of the memory cell is in contact connection with the second metal layer through the first conductive metal and the second conductive metal.
Further, the first conductive metal and the second conductive metal are tungsten or copper.
The memory provided by the embodiment of the application is characterized by comprising the memory structure.
Compared with the prior art, the beneficial effects achieved by the at least one technical scheme adopted by the embodiment of the application at least comprise:
the application relates to a manufacturing method of a memory structure, which comprises the steps of carrying out patterning treatment on a first metal layer, and forming a first insulating layer on the first metal layer; etching a first through hole communicated with the first metal layer on the first insulating layer; depositing a memory cell within the first insulating layer and the first via, and depositing a first conductive metal over the memory cell; developing the memory cell on the first conductive metal, and respectively etching the first conductive metal and the memory cell to obtain a memory cell pattern; a stop layer is deposited on the first insulating layer and the first conductive metal, so that a memory unit can be arranged in a VIA hole of the semiconductor, the area of the memory is definitely increased, the problem that the effective area of the memory is difficult to increase on the basis of the prior art in the prior art is solved, and the device performance of the memory is improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a side cross-sectional view of a first metal layer and a first insulating layer according to an embodiment of the present application;
FIG. 2 is a side cross-sectional view of a first metal layer and a first insulating layer connected by a connection hole according to an embodiment of the present application;
FIG. 3 is a side cross-sectional view of a first insulating layer with a first via opening according to an embodiment of the present application;
FIG. 4 is a side cross-sectional view of a first insulating layer and a first via with a memory cell thereon according to an embodiment of the present application;
FIG. 5 is a side cross-sectional view of a memory cell having a first conductive metal thereon according to an embodiment of the present application;
FIG. 6 is a side cross-sectional view of an embodiment of the present application after the first conductive metal and memory cell have been etched;
FIG. 7 is a side cross-sectional view of a first conductive metal and a first insulating layer with a stop layer disposed thereon according to an embodiment of the present application;
FIG. 8 is a side cross-sectional view of a stop layer with a second insulating layer disposed thereon according to an embodiment of the present application;
FIG. 9 is a side cross-sectional view of a stop layer with a second conductive metal deposited thereon in accordance with an embodiment of the present application;
FIG. 10 is a side cross-sectional view of a second insulating layer with a second metal layer disposed thereon according to an embodiment of the present application;
the reference numerals of the present application are as follows:
10. a first metal layer;
20. a first insulating layer; 21. a first through hole;
30. a storage unit;
40. a first conductive metal;
50. a stop layer;
60. a second insulating layer;
70. a second through hole;
80. a second conductive metal;
90. a second metal layer.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, apparatus may be implemented and/or methods practiced using any number and aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present application by way of illustration, and only the components related to the present application are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the present application may be practiced without these specific details.
The memory with a planar structure is composed of upper and lower electrodes and a phase change material, ferroelectric material or magneto-resistive material in between, but the effective area of the memory with the planar structure is difficult to increase, so that the device performance of the memory is difficult to improve.
Based on the above, the application provides a technical scheme that: according to the application, the memory unit is deposited in the through hole of the first metal layer, so that the effective area is increased on the basis of the original memory structure, and the device performance of the memory is improved.
The following describes the technical scheme provided by each embodiment of the present application with reference to the accompanying drawings.
As shown in fig. 1 to 7, a method for manufacturing a memory structure according to an embodiment of the present application includes:
step S102, patterning the first metal layer, and forming a first insulating layer on the first metal layer;
step S104, etching a first through hole communicated with the first metal layer on the first insulating layer;
step S106, depositing a storage unit in the first insulating layer and the first through hole, and depositing a first conductive metal on the storage unit;
step S108, developing the memory cells on the first conductive metal, and respectively etching the first conductive metal and the memory cells to obtain memory cell patterns;
step S110, depositing a stop layer on the first insulating layer and the first conductive metal.
In step S102, the first metal layer is patterned, which is required to be achieved through a deposition process and a photolithography technique.
After the first metal layer is processed by a deposition process and a photolithography technique, unprotected areas of the first metal layer are removed by an etching process to form a first insulating layer.
In step S104, after the first insulating layer is formed, a first via hole is etched in the first insulating layer based on an etching process, and the first via hole is connected to the first metal layer, so that the memory cell is connected to the first metal layer after the memory cell is formed in the first via hole.
The first through hole can be formed by processing the first insulating layer through dry etching, or can be formed by processing the first insulating layer through wet etching.
In some of these embodiments, before etching the first via hole, a connection via hole may also be etched, the connection via hole being connected to the first metal layer, and a connection metal being provided in the connection via hole.
Wherein, the connection metal can be tungsten metal.
In step S106, the memory cell is deposited in the first via hole, which increases the usage area of the memory area, improves the device performance, and solves the problem that the area of the effective area is difficult to increase due to the planar structure of the memory in the prior art.
Specifically, depositing the memory cell on the first insulating layer and the sidewall of the first via includes sequentially depositing a lower electrode, a functional layer, and an upper electrode within the first insulating layer and the first via.
More specifically, a lower electrode, a functional layer, and an upper electrode may be sequentially deposited on the first insulating layer and the first via hole based on an atomic layer deposition method.
Wherein the lower electrode, the functional layer and the upper electrode together form a memory cell.
Wherein the first conductive metal comprises tungsten or copper.
Wherein in case the cross section of the memory cell is deposited as an inverted Ω structure, the hollow structure of the memory cell may be filled with the first conductive metal.
In step S108, developing the memory cell on the first conductive metal includes depositing an anti-reflective coating and a photoresist on the first conductive metal and then developing the memory cell.
Etching the first conductive metal and the memory cell to obtain a memory cell pattern, respectively, includes:
step S108a, an anti-reflection coating is laid on the first conductive metal to protect the memory unit;
step S108b, etching the area corresponding to the first conductive metal and the non-memory cell;
step S108c, etching the non-storage area of the storage unit based on the etched first conductive metal to obtain a storage unit pattern.
In step S108a and step S108b, the anti-reflective coating is used to protect the memory cells from etching away the memory cell areas.
And under the condition of etching the first conductive metal, etching the first conductive metal by adopting an etching back process, wherein the first conductive metal of the non-memory cell area is etched away as the memory cell area is protected by the anti-reflection coating.
Specifically, in the case of etching the first conductive metal using an etch-back process, the anti-reflection coating layer and the first conductive metal are consumed at the same time, the first conductive metal without the anti-reflection coating layer is finally etched away, and the first conductive metal remains on the memory cell region after the first conductive metal is etched back.
The first conductive metal is reserved on the memory cell to protect the memory cell from being damaged during etching.
In step S108c, after etching away the first conductive metal of the non-memory region, the first conductive metal on the memory region can act as a protection to protect the memory cell region from being etched away, thereby forming a memory cell pattern.
The etching of the memory cell can be performed in a metal etching mode, at this time, the first conductive metal can be used as a protective layer, and finally the memory cell area is completely reserved under the protection of the first conductive metal, and the non-memory cell area is etched.
In step S110, after the memory cell pattern is acquired, a stop layer is deposited on the first insulating layer and the first conductive metal to take the stop layer as a base layer of a subsequent metal layer.
The memory cells are arranged in the through holes on the first insulating layer through the steps S102 to S110, so that the area of the effective area of the memory is increased, and the performance of the memory is improved.
The application improves the effective working area of the device through the VIA structure (vertical interconnection hole), and gradually deposits to form the lower electrode, the functional layer and the upper electrode of the memory, thereby completing the main structure of the memory structure.
As shown in fig. 8 to 10, after depositing the stop layer on the first insulating layer and the first conductive metal, further includes:
step S202, depositing a second insulating layer on the stop layer, and forming a second through hole penetrating through the second insulating layer and the stop layer;
step S204, depositing a second conductive metal in the second through hole so as to connect the second conductive metal with the first conductive metal;
step S206, disposing a second metal layer on the second insulating layer.
In step S202, a second via is used to deposit a second conductive metal, and the second via penetrates through the second insulating layer and the stop layer to connect with the first conductive metal.
In step S204, a second conductive metal is deposited within the second via based on the deposition process.
The second conductive metal may be tungsten or copper.
In step S206, a second metal layer is disposed on the second insulating layer, so as to form a three-dimensional structure in cooperation with the first metal layer.
After the second metal layer is deposited, the third layer, the fourth layer, and the like of the metal line can be formed continuously.
The following is a specific implementation of the embodiment of the present application:
patterning the M1 metal layer through a deposition process and a photoetching technology, and removing unprotected areas in the M1 metal layer to form a first insulating layer;
processing the first insulating layer by using an etching process to form a required hole structure, and filling the hole structure with metal tungsten;
etching the first insulating layer in the memory cell region to form a first via hole, and connecting the first via hole to the M1 metal layer;
depositing memory cells (lower electrode, functional layer, and upper electrode) on the first via based on ALD (atomic layer deposition);
filling tungsten metal in the storage unit;
developing a memory unit pattern based on PHOTO, and etching the area corresponding to the metal tungsten and the memory unit in two steps;
depositing a stop layer over the tungsten metal and the first insulating layer;
depositing a second insulating layer on the stop layer;
a hole structure is formed in the second insulating layer, and tungsten metal is filled in the hole structure;
a second metal layer is disposed on the second insulating layer.
The application achieves the purpose of increasing the polarization area by reducing the size of the critical hole of the filling storage unit or improving the lamination precision of the through hole and the storage unit, and finally achieves the purpose of further improving the functionality of the storage.
Example 2
As shown in fig. 1 to 10, a memory structure according to an embodiment of the present application includes a first metal layer 10, a first insulating layer 20, a memory cell 30, a first conductive metal 40, and a stop layer 50. The first insulating layer 20 is disposed on the first metal layer 10, and a first through hole 21 communicating with the first metal layer 10 is formed on the first insulating layer 20; the memory cell 30 is disposed on the first via 21 and the first insulating layer 20; the first conductive metal 40 is disposed on the memory cell 30; the stop layer 50 is disposed on the first insulating layer 20 and the first conductive metal 40.
The first metal layer 10 is any layer of a metal line, and may be formed by a deposition process.
Wherein the first insulating layer 20 is an insulating layer deposited over the first metal layer 10.
The memory cell 30 includes an upper electrode, a lower electrode, and a functional layer.
The memory cell 30 may sequentially deposit a lower motor, a functional layer, and an upper electrode in the first insulating layer 20 and the first via hole 21 by an atomic layer deposition method.
Wherein the first conductive metal 40 may be tungsten or copper.
Preferably, the first conductive metal 40 is tungsten metal.
The stop layer 50 is an initial layer of a layer structure under the metal line.
Further, the memory structure further includes a second insulating layer 60, a second via 70, a second conductive metal 80, and a second metal layer 90. Wherein the second insulating layer 60 is disposed on the stop layer 50; the second via hole 70 is disposed through the second insulating layer 60 and the stop layer 50, and extends to the first conductive metal 40; the second conductive metal 80 is disposed in the second through hole 70 and connected to the first conductive metal 40; the second metal layer 90 is disposed on the second insulating layer 60 and connected to the second conductive metal 80.
Wherein the second insulating layer 60 is an insulating layer obtained based on a deposition process.
Wherein the second via hole 70 may be formed by dry etching or wet etching.
Wherein the second conductive metal 80 is a metal formed based on a deposition process.
The first metal layer 10 of the present application is not specifically a first layer of a metal line in a semiconductor, the first metal layer 10 may be any layer of the metal line, and the second metal layer 90 is a next layer structure of the first metal layer 10.
Further, the lower electrode of the memory cell 30 is in contact with the first metal layer 10, and the upper electrode of the memory cell 30 is in contact with the second metal layer 90 through the first conductive metal 40 and the second conductive metal 80.
Example 3
The embodiment of the application provides a memory, which is characterized by comprising the memory structure as described in the embodiment 2.
In this specification, identical and similar parts of the embodiments are referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the description is relatively simple, and reference is made to the description of parts of the system embodiments.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the application is subject to the protection scope of the claims.

Claims (10)

1. A method of manufacturing a memory structure, comprising:
patterning the first metal layer, and forming a first insulating layer on the first metal layer;
etching a first through hole communicated with the first metal layer on the first insulating layer;
depositing a memory cell within the first insulating layer and the first via, and depositing a first conductive metal on the memory cell;
developing the memory cell on the first conductive metal, and respectively etching the first conductive metal and the memory cell to obtain a memory cell pattern;
a stop layer is deposited over the first insulating layer and the first conductive metal.
2. The method of manufacturing of claim 1, further comprising, after depositing a stop layer on the first insulating layer and the first conductive metal:
depositing a second insulating layer on the stop layer, and forming a second through hole penetrating through the second insulating layer and the stop layer;
depositing a second conductive metal in the second through hole so as to connect the second conductive metal with the first conductive metal;
and a second metal layer is arranged on the second insulating layer.
3. The method of manufacturing of claim 1, wherein the etching the first conductive metal and the memory cell, respectively, to obtain a memory cell pattern comprises:
applying an anti-reflective coating over the first conductive metal to protect the memory cell;
etching the area of the first conductive metal corresponding to the non-memory cell;
and etching the non-storage area of the storage unit based on the etched first conductive metal to obtain a storage unit pattern.
4. The method of manufacturing of claim 3, wherein the non-storage area of the memory cell is etched based on a metal etching process to obtain a memory cell pattern.
5. The method of manufacturing of claim 1, wherein depositing memory cells on sidewalls of the first insulating layer and the first via comprises:
and sequentially depositing a lower electrode, a functional layer and an upper electrode in the first insulating layer and the first through hole.
6. A memory structure, comprising:
a first metal layer;
the first insulating layer is arranged on the first metal layer, and a first through hole communicated with the first metal layer is formed in the first insulating layer;
the storage unit is arranged on the first through hole and the first insulating layer;
a first conductive metal disposed on the memory cell;
and the stop layer is arranged on the first insulating layer and the first conductive metal.
7. The memory structure of claim 6, further comprising:
a second insulating layer disposed on the stop layer;
a second via hole penetrating through the second insulating layer and the stop layer and extending to the first conductive metal;
the second conductive metal is arranged in the second through hole and is connected with the first conductive metal;
and the second metal layer is arranged on the second insulating layer and is connected with the second conductive metal.
8. The memory structure of claim 7, wherein a lower electrode of the memory cell is in contact with the first metal layer and an upper electrode of the memory cell is in contact with the second metal layer through a first conductive metal and the second conductive metal.
9. The memory structure of any of claims 7-8, wherein the first conductive metal and the second conductive metal are tungsten or copper.
10. A memory comprising a memory structure as claimed in any one of claims 6 to 9.
CN202310768708.0A 2023-06-27 2023-06-27 Manufacturing method of memory structure, memory structure and memory Pending CN116828967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310768708.0A CN116828967A (en) 2023-06-27 2023-06-27 Manufacturing method of memory structure, memory structure and memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310768708.0A CN116828967A (en) 2023-06-27 2023-06-27 Manufacturing method of memory structure, memory structure and memory

Publications (1)

Publication Number Publication Date
CN116828967A true CN116828967A (en) 2023-09-29

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310768708.0A Pending CN116828967A (en) 2023-06-27 2023-06-27 Manufacturing method of memory structure, memory structure and memory

Country Status (1)

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