CN116828897A

CN116828897A - Display device and method of manufacturing the same

Info

Publication number: CN116828897A
Application number: CN202111538571.7A
Authority: CN
Inventors: 魏丽真; 柳宜政
Original assignee: Taizhou Guanyu Technology Co ltd
Current assignee: Taizhou Guanyu Technology Co ltd
Priority date: 2021-09-09
Filing date: 2021-12-15
Publication date: 2023-09-29
Also published as: CN218388532U; CN218451114U; CN116828893A; CN116828924A; CN116828890A

Abstract

The present disclosure provides a display device and a method of manufacturing the same. The display device includes a substrate, a first light emitting unit, a second light emitting unit, a pixel defining layer, and a reflective layer. The first light-emitting unit is arranged on the substrate. The second light-emitting unit is arranged on the substrate. The pixel definition layer is arranged between the first light-emitting unit and the second light-emitting unit. The reflective layer is located in the pixel defining layer.

Description

Display device and method of manufacturing the same

Technical Field

The present disclosure relates to a display device, and more particularly, to a display device including a reflective layer.

Background

Display devices including an optical component layer have been widely used in most electronic apparatuses, and there has been a demand for larger display devices in recent years. However, in the method of manufacturing the display device, there is a step in which the light extraction efficiency is not good. In fact, one of the challenges recognized in the art is to increase the light extraction efficiency of the display device. Accordingly, the display device industry is seeking ways to address the issues described above.

Disclosure of Invention

A display device includes a substrate, a first light emitting unit, a second light emitting unit, a pixel defining layer, and a reflective layer. The first light-emitting unit is arranged on the substrate. The second light-emitting unit is arranged on the substrate. The pixel definition layer is arranged between the first light-emitting unit and the second light-emitting unit. The reflective layer is located in the pixel defining layer.

In some embodiments, the pixel defining layer includes a plurality of scattering particles.

In certain embodiments, each scattering particle has a particle size between about 0.1nm and about 1000nm.

In certain embodiments, the scattering particles comprise a metal oxide.

In some embodiments, the first light emitting unit includes a carrier injection layer, a first carrier transport layer, and a light emitting layer, and the thickness of the reflective layer is less than the sum of the thicknesses of the carrier injection layer, the first carrier transport layer, and the light emitting layer.

In some embodiments, the first light emitting unit includes a carrier injection layer, a first carrier transport layer, a light emitting layer, and a second carrier transport layer, and the thickness of the pixel defining layer is greater than or equal to the sum of the thicknesses of the carrier injection layer, the first carrier transport layer, the light emitting layer, and the second carrier transport layer.

In some embodiments, the display device further includes an insulating layer between the reflective layer and the substrate.

A method of manufacturing a display device comprising: providing a substrate; forming a first electrode and a second electrode on a substrate; forming a reflecting layer between the first electrode and the second electrode; and forming a pixel definition layer to cover the reflective layer.

In certain embodiments, the method further comprises: a dielectric layer is formed to cover the substrate, the first electrode and the second electrode.

In certain embodiments, the method further comprises: forming a support on the dielectric layer, wherein the reflective layer covers the support.

Drawings

Fig. 1 is a cross-sectional view of a display device according to some embodiments.

Fig. 2 is a partial enlarged view of the display device shown in fig. 1.

Fig. 3A-3J are schematic diagrams illustrating display devices at various stages of manufacture according to methods of certain embodiments of the present disclosure.

Fig. 4 is a cross-sectional view of a display device, according to some embodiments.

Description of the drawings

100a display device

100b display device

110. Substrate board

120a light emitting unit

120b light emitting unit

120c light emitting unit

121. Electrode

122. Carrier injection layer

123. Carrier transport layer

124. Light-emitting layer

125. Carrier transport layer

126. Electrode

130. Pixel definition layer

130' pixel definition layer

131. Insulating layer

132. Scattering particles

140. Reflection structure

141. Support body

141s1 upper surface

142. Reflective layer

142s1 upper surface

150. Flat layer

152. Filling layer

160a optical component layer

160b optical component layer

160c optical component layer

170a filter layer

170b filter layer

170c filter layer

180. Light shielding layer

190. Cover plate

T1 thickness

T2 thickness

T3 thickness

T4 thickness

P1 Top end

P2 Top end

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the application. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the application from that described above. For example, the following description of forming a first feature over or on a second feature may include embodiments in which first and second features are formed in direct contact, and may also include embodiments in which other features are formed between the first and second features, such that the first and second features are not in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or architectures discussed.

Furthermore, the present application may be described using the shorthand notation of spatially corresponding terms such as "lower," "higher," "upper," and the like, to describe a relationship of one element or feature to another element or feature in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be positioned (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

Notwithstanding that the numerical ranges and parameters setting forth the broad scope of the disclosure are approximations, the numerical values set forth in the specific examples are reported as precisely as possible. Any numerical value, however, inherently contains certain errors necessarily resulting from the standard deviation found in their respective testing measurements. Further, as used herein, "about" generally refers to within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the term "about" refers to within an acceptable standard error of average value considered by one of ordinary skill in the art. Except in the operating/working examples, or where otherwise indicated, all numerical ranges, amounts, values, and ratios of materials, time periods, temperatures, operating conditions, amounts, and the like disclosed herein are to be understood as modified in all instances by the term "about. Accordingly, unless indicated to the contrary, the numerical parameters set forth in the present disclosure and claims are approximations that may vary as desired. Each numerical parameter should at least be construed in light of the number of reported significant digits and by applying ordinary rounding techniques. Ranges can be expressed herein as from one end point to another, or between two end points. Unless specifically stated otherwise, all ranges disclosed herein are inclusive of the endpoints.

Fig. 1 is a cross-sectional view of a display device 100a, according to some embodiments.

In some embodiments, the display apparatus 100a includes a substrate 110, light emitting units 120a, 120b, 120c, a pixel defining layer 130, a reflective structure 140, a planarization layer 150, a filling layer 152, optical component layers 160a, 160b, 160c, filter layers 170a, 170b, 170c, a light shielding layer 180, and a cover plate 190.

In some embodiments, the substrate 110 includes a substrate (not shown), a dielectric layer (not shown), and one or more circuits (not shown) disposed on or within the substrate. In some embodiments, the substrate is a transparent substrate, or at least a portion is transparent. In some embodiments, the substrate is a non-flexible substrate, and the material of the substrate may include glass, quartz, low temperature polysilicon (low temperature poly-silicon, LTPS), or other suitable materials. In some embodiments, the substrate is a flexible substrate, and the material of the substrate may include transparent epoxy, polyimide, polyvinyl chloride, methyl methacrylate, or other suitable materials. The dielectric layer may be optionally disposed on the substrate. In some embodiments, the dielectric layer may comprise silicon oxide, silicon nitride, silicon oxynitride, or other suitable material.

In some embodiments, the circuit may comprise a Complementary Metal Oxide Semiconductor (CMOS) circuit, or may comprise a plurality of transistors and a plurality of capacitors adjacent to the transistors, wherein the transistors and the capacitors are formed on a dielectric layer. In some embodiments, the transistor is a thin-film transistor (TFT). Each transistor includes a source/drain region (including at least a source region and a drain region), a channel (channel) region between the source/drain regions, a gate electrode disposed over the channel region, and a gate insulator between the channel region and the gate electrode. The channel region of the transistor may be made of a semiconductor material, such as silicon or other elements selected from group IV or group III and group V.

The gate electrode may be made of a conductive material such as a metal, silicide, or metal alloy. In some embodiments, the gate electrode may be a composite structure comprising several different layers, and the different layers may be distinguished from each other by applying an etchant and observing under a microscope. In some embodiments, the substrate 110 includes an interlayer dielectric structure, a first metal layer, and the like. The interlayer dielectric structure is arranged on the circuit or the transistor. The first metal layer and other circuit layers may be used to electrically connect to the light emitting units 120a, 120b and/or 120c.

The light emitting units 120a, 120b, and 120c are disposed on the substrate 110. In some embodiments, the light emitting units 120a, 120b, or 120c may be organic light emitting diodes (organic light-emitting diode), micro light emitting diodes (micro LEDs or mini LEDs), quantum dot LEDs (QLEDs), or other suitable light emitting units, respectively. In some embodiments, the light emitting units 120a, 120b, and 120c are organic light emitting diodes.

In some embodiments, the light emitting units 120a, 120b, and 120c may include an electrode 121, a carrier injection layer 122, a carrier transport layer 123, a light emitting layer 124, a carrier transport layer 125, and an electrode 126, respectively.

The electrode 121 is disposed on the surface of the substrate 110. Each electrode 121 is configured to: one side is connected to circuitry embedded or electrically connected in the substrate 110 and the other side contacts the carrier injection layer 122. The electrode 121 includes a metal material, such as Ag, mg, or the like. In some embodiments, the electrode 121 includes Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or other suitable materials.

The carrier injection layer 122 is disposed on the electrode 121. In some embodiments, the carrier implant layer 122 is used for hole implantation. In some embodiments, the carrier injection layer 122 is used for electron injection. In some embodiments, the carrier implant layer 122 is in contact with the pixel definition layer 130. In some embodiments, the carrier injection layer 122 comprises an organic compound. In some embodiments, the carrier injection layer 122 is a composite structure.

The carrier transport layer 123 is disposed on the carrier injection layer 122. In some embodiments, the carrier transport layer 123 is a hole transport layer (hole transportation layer, HTL). In some embodiments, the carrier transport layer 123 is an electron transport layer (electron transportation layer, ETL). In some embodiments, the carrier transport layer 123 is in contact with the pixel definition layer 130. In some embodiments, the carrier transport layer 123 comprises an organic compound. In some embodiments, the carrier transport layer 123 has the property of unidirectionally transporting electrons or holes (e.g., from the electrode 121 toward the electrode 126). In some embodiments, the carrier transport layer 123 is a composite structure.

An emission layer (EML) 124 is disposed on the carrier transport layer 123. The light emitting layer 124 may entirely cover the carrier transport layer 123. In some embodiments, the light emitting layers 124 of the light emitting units 120a, 120b, 120c comprise different materials to emit wavelengths of light in different wavelength bands. For example, the light emitting layer 124 of light emitting unit 120a is configured to emit a first color, the light emitting layer 124 of light emitting unit 120b is configured to emit a second color, and the light emitting layer 124 of light emitting unit 120c is configured to emit a third color. In some embodiments, the first color comprises red light (e.g., light having a wavelength between 620nm and 780 nm), the second color comprises green light (e.g., light having a wavelength between 500nm and 580 nm), and the third color comprises blue light (e.g., light having a wavelength between 400nm and 500 nm).

The carrier transport layer 125 is disposed on the light emitting layer 124. In some embodiments, the carrier transport layer 125 is an electron transport layer. In some embodiments, the carrier transport layer 125 is a hole transport layer. In some embodiments, carrier transport layer 125 and carrier transport layer 123 are configured in opposite valence states. In some embodiments, the carrier transport layer 125 is a composite structure.

The electrode 126 is disposed on the carrier transport layer 125. The electrode 126 comprises a metallic material, such as Ag, mg, or the like. In some embodiments, the electrode 126 comprises Indium Tin Oxide (ITO), indium Zinc Oxide (IZO), or other suitable materials.

The pixel defining layer 130 is disposed between two light emitting units (e.g., the light emitting units 120a, 120b, or 120 c). The pixel defining layer 130 may be used to define the light emitting area of the light emitting unit. In some embodiments, the pixel defining layer 130 includes a light absorbing material that may have an absorbance greater than 85%, such as 85%, 88%, 90%, 93%, 95%, 97%, 98%, or 99%. In some embodiments, the pixel defining layer 130 includes a light transmissive material that may have a light transmittance of greater than 85%, such as 85%, 88%, 90%, 93%, 95%, 97%, 98%, or 99%.

In some embodiments, the display device 100a further includes an insulating layer 131. The insulating layer 131 is provided to prevent the reflective structure 140 from contacting the electrode 121. In some embodiments, the insulating layer 131 is disposed on the substrate 110. In some embodiments, the insulating layer 131 covers a portion of the light emitting cells 120a, 120b, or 120c. In some embodiments, the insulating layer 131 covers the upper surface of the electrode 121 of a portion of the light emitting unit 120a, 120b, or 120c. The insulating layer 131 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other suitable material. In some embodiments, the thickness of the insulating layer 131 is in the range of about 50nm-200nm, such as 50nm, 100nm, 150nm, or 200nm.

In some embodiments, the reflective structure 140 is disposed on the insulating layer 131. In some embodiments, the reflective structure 140 is disposed within the pixel definition layer 130. In some embodiments, the reflective structure 140 includes a support 141 and a reflective layer 142 disposed on the support 141. The supporting body 141 is provided to adjust the profile and the horizontal height of the reflective layer 142. In some embodiments, the support 141 may have a convex upper surface 141s1. In some embodiments, the thickness and/or profile of the support 141 may be determined by determining the respective thicknesses or thicknesses and thereafter of the carrier injection layer 122, the carrier transport layer 123, and the light emitting layer 124. In some embodiments, the support 141 comprises a light sensitive material, such as a photoresist or other suitable material. In some embodiments, the support 141 comprises a dielectric material, such as silicon oxide, silicon nitride, or other suitable material.

The reflective layer 142 covers the support 141 and is conformally provided on the support 141. In some embodiments, the reflective layer 142 may have a convex upper surface 142s1. In some embodiments, the upper surface 142s1 of the reflective layer 142 includes a semi-circular profile, a semi-elliptical profile, or other suitable profile. In some embodiments, the reflective layer 142 is disposed within the pixel defining layer 130. In some embodiments, the reflective layer 142 is spaced from the electrode 121 via an insulating layer 131. In some embodiments, the reflective layer 142 is separated from the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, the carrier transport layer 125, and the electrode 126 by the pixel definition layer 130.

The reflective layer 142 is configured to reflect the lateral light emitted from the light emitting unit 120a, 120b or 120c, and reflect the lateral light as light toward the optical component layer 160a, 160b or 160c, thereby improving the light emitting efficiency (out-coupling efficiency) of the display apparatus 100a. When the upper surface 142s1 of the reflective layer 142 is in a convex shape or has a semicircular or semi-elliptical profile, the reflection angle of the lateral light can be adjusted. In some embodiments, the reflective layer 142 comprises Al, mg, ag, au, yb, a mixture of the above materials, an alloy, or other suitable reflective material. In some embodiments, the reflective layer 142 comprises a composite layer. For example, the reflective layer 142 further comprises a metal nitride, metal oxide or other material coating the metal or alloy layer. In some embodiments, the metal nitride or metal oxide comprises TiN, tiO ₂ Or other suitable material. In some embodiments, the reflective layer 142 is structured as a metal nitride-metal nitride, such as TiN-Al-TiN.

As shown in fig. 1, the reflective layer 142 has a thickness T1, and the sum of the thicknesses of the carrier injection layer 122, the carrier transport layer 123, and the light emitting layer 124 is T2. In some embodiments, thickness T1 is less than or equal to thickness sum T2. In some embodiments, the top end P1 of the reflective layer 142 has a level substantially the same as the level of the upper surface of the light emitting layer 124. In some embodiments, the top P1 of the reflective layer 142 has a level between the upper surface of the light emitting layer 124 and the lower surface of the carrier transport layer 123. In some embodiments, the top P1 of the reflective layer 142 has a level between the upper surface of the light emitting layer 124 and the lower surface of the light emitting layer 124. When the thickness T1 is smaller than the thickness T2 or the horizontal height of the top end P1 of the reflective layer 142 is between the upper surface of the light emitting layer 124 and the lower surface of the light emitting layer 124, the reflective layer 142 can sufficiently reflect the lateral light emitted from the light emitting units 120a, 120b and 120c, and reflect the lateral light back to the light emitting region or into the forward light to be directed to the optical component layer 160a, 160b or 160c, so as to improve the light emitting efficiency of the display device 100a. In some embodiments, the thickness T1 is in the range of about 100nm-500nm, such as 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, or 500nm.

In a comparison, the thickness T1 is greater than the thickness sum T2, in which case the lateral light reflected by the reflective layer 142 back to the light emitting layer 124 will interfere with the forward light perpendicular to the lateral light, reducing the light extraction efficiency. In a comparative example, P1 is higher than the upper surface of the light emitting layer 124, in which case the lateral light reflected by the reflective layer 142 back to the light emitting layer 124 will interfere with the forward light perpendicular to the lateral light, reducing the light extraction efficiency. In a comparative example, P1 is lower than the lower surface of the carrier transport layer 123, in which case lateral light reflected by the reflective layer 142 back to the light emitting layer 124 is difficult to enter the optical component layer 160a, 160b, or 160c.

In some embodiments, the thicknesses of the support 141 and the reflective layer 142 may be determined after determining the respective thicknesses or thicknesses and (e.g., T2) of the carrier injection layer 122, the carrier transport layer 123, and the light emitting layer 124. In some embodiments, the thickness of the reflective layer 142 may be determined after the thickness of the support 141 is determined. In some embodiments, the profile of the upper surfaces (e.g., upper surface 141s1 and upper surface 142s 1) of the support 141 and the reflective layer 142 may be determined after determining the respective thicknesses or thicknesses and (e.g., T2) of the carrier injection layer 122, the carrier transport layer 123, and the light emitting layer 124.

As shown in fig. 1, the pixel defining layer 130 has a thickness T3, and the sum of the thicknesses of the carrier injecting layer 122, the carrier transporting layer 123, the light emitting layer 124 and the carrier transporting layer 125 is T4. In some embodiments, thickness T3 is greater than or equal to thickness sum T4. When the thickness T3 is greater than or equal to the thickness sum T4, electrons and/or holes transported by the layers of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125 are converted by the light emitting unit, so that the light emitting efficiency of the display device 100a can be improved. In some embodiments, the top P2 of the pixel defining layer 130 is higher than the top surface of the carrier transporting layer 125. When the top P2 of the pixel defining layer 130 is higher than the top surface of the carrier transporting layer 125, electrons and/or holes transported by the carrier injecting layer 122, the carrier transporting layer 123, the light emitting layer 124 and the carrier transporting layer 125 can be converted by the light emitting unit, so as to improve the light emitting efficiency of the display device 100a. In a comparison example, the thickness T3 is smaller than the thickness and T4, in which case, electrons and/or holes transferred from each of the carrier injection layer 122, the carrier transfer layer 123, the light emitting layer 124 and the carrier transfer layer 125 may be transferred to adjacent pixels or light emitting units, thereby reducing light extraction efficiency. In some embodiments, the thickness T3 of the pixel defining layer 130 may be determined after the thicknesses of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125 and T4 are determined. In some embodiments, the thickness T3 is in the range of about 500nm-1000nm, such as 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm. In some embodiments, the thickness and T4 are in the range of about 200nm-400nm, such as 200nm, 250nm, 300nm, 350nm, or 400nm. In some embodiments, the thicknesses and T4 of the respective carrier injection layer 122, carrier transport layer 123, light emitting layer 124, and carrier transport layer 125 of the light emitting units 120a, 120b, 120c may be different from each other. In some embodiments, the sum of the thicknesses of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125 of the light emitting unit 120a is greater than the sum of the thicknesses of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125 of the light emitting unit 120b. In some embodiments, the sum of the thicknesses of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125 of the light emitting unit 120b is greater than the sum of the thicknesses of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125 of the light emitting unit 120c.

The planarization layer 150 is disposed on the substrate 110. The planarization layer 150 covers the light emitting units 120a, 120b, 120c and the pixel defining layer 130 and provides a planarized upper surface. The planarization layer 150 may comprise an oxide, nitride, or other dielectric material.

The fill layer 152 is disposed on the planarization layer 150. The filler layer 152 comprises a substantially transparent material, such as a resin or other suitable material, and may comprise any filler. The light transmittance of the fill layer 152 may be greater than 85%, such as 85%, 88%, 90%, 93%, 95%, 97%, 98%, or 99%.

In some embodiments, optical component layers 160a, 160b, and 160c are disposed on filler layer 152. The optical assembly layer 160a is disposed on the light emitting unit 120a and aligns the light emitting unit 120a in the longitudinal direction. The optical assembly layer 160b is disposed on the light emitting unit 120b, and aligns the light emitting unit 120b in the longitudinal direction. The optical assembly layer 160c is disposed on the light emitting unit 120c, and aligns the light emitting unit 120c in the longitudinal direction. In some embodiments, the optical component layers 160a, 160b, and 160c are configured to change the light path (light path) of the light emitted by the light emitting unit. In some embodiments, optical component layers 160a, 160b, and 160c include lenses (lens) or other suitable components. In some embodiments, the optical component layers 160a, 160b, and 160c may have contours that protrude toward the substrate 110. In some embodiments, the upper surface of the filler layer 152 is substantially coplanar with the upper surfaces of the optical component layers 160a, 160b, and 160c.

As shown in fig. 1, the filter layer 170a is disposed on the optical component layer 160a, and is aligned with the optical component layer 160a in the longitudinal direction. The filter layer 170b is disposed on the optical component layer 160b and is aligned with the optical component layer 160b in the longitudinal direction. The filter layer 170c is disposed on the optical component layer 160c and is aligned with the optical component layer 160c in the longitudinal direction. The filter layers 170a, 170b and 170c can pass light of different wavelength bands, respectively. For example, filter 170a may pass red light (e.g., light having a wavelength between 620nm and 780 nm), filter 170b may pass green light (e.g., light having a wavelength between 500nm and 580 nm), and filter 170c may pass blue light (e.g., light having a wavelength between 400nm and 500 nm). In some embodiments, the filter layers 170a, 170b, and 170c may be removed.

The light blocking layer 180 may be selectively disposed between the two filter layers. The light shielding layer 180 may include black photoresist or other suitable materials, and is not limited thereto.

The cover plate 190 is disposed on the filter layers 170a, 170b, 170c and the light shielding layer 180. In some embodiments, the cover plate 190 includes a substantially transparent component, such as glass or other suitable component.

In this embodiment, the display device 100a includes the reflective layer 142, so as to improve the light-emitting efficiency of the display device 100a.

In this embodiment, the thickness (or sum of thicknesses) of the pixel defining layer 130, the reflective layer 142, the electrode 121, the carrier injecting layer 122, the carrier transporting layer 123, and the light emitting layer 124, or the relative horizontal height thereof is adjusted to achieve higher light extraction efficiency, so as to improve the performance of the display device 100a. In some embodiments, display device 100a may achieve a pixel density of 1500ppi or higher.

Fig. 2 is a partial enlarged view of the display device 100a shown in fig. 1.

In some embodiments, the pixel defining layer 130 may include a plurality of scattering particles 132. The scattering particles 132 may be located within the pixel defining layer 130. The scattering particles 132 can make the lateral light emitted from the light emitting units 120a, 120b and 120c more easily reflect or convert into longitudinal light, so as to improve the light emitting efficiency of the display device 100a. In some embodiments, the scattering particles 132 may comprise a metal oxide or other suitable material. In some embodiments, the scattering particles 132 comprise Al, ti, zr, W, fe, co, ni, cu, ag, zn, sn, pt or Au oxide. In some embodiments, the scattering particles 132 have a particle size of about 0.1nm to about 1000nm, such as 0.1nm, 1nm, 10nm, 100nm, or 1000nm. When the particle size of the scattering particles 132 is within the above range, the light-emitting efficiency of the display device 100a can be improved.

The schematic diagrams of fig. 3A-3J illustrate display device 100a at various stages of manufacture according to methods of certain embodiments of the present disclosure.

Referring to fig. 3A, a substrate 110 is provided.

Referring to fig. 3B, a plurality of electrodes 121 are formed on a substrate 110. The electrode 121 may be formed on the substrate 110 by vapor deposition, sputtering, atomic layer deposition (atomic layer deposition, ALD), thermal evaporation, coating, or sputtering, and patterned by photolithography and etching techniques.

Referring to fig. 3C, a plurality of insulating layers 131 are formed on the substrate 110. The insulating layer 131 may cover a portion of the electrode 121. The insulating layer 131 may be formed on the substrate 110 by vapor deposition, ALD, and patterning by photolithography and etching techniques.

Referring to fig. 3D, a plurality of supports 141 are formed on the insulating layer 131. In some embodiments, the support 141 comprises a light sensitive material, such as a photoresist or other suitable material. The support 141 may be formed on the insulating layer 131 by coating or other suitable means, and patterned by photolithography and etching techniques. In addition, the supporting body 141 may be hardened through a baking process or the like. In some embodiments, the thickness of the support 141 is determined after determining the respective thicknesses or thicknesses and sums of the predetermined formed carrier injection layer 122, carrier transport layer 123, light emitting layer 124. In some embodiments, the profile of the upper surface 141s1 of the support 141 may be determined after determining the respective thicknesses or thickness sums of the predetermined formed carrier injection layer 122, carrier transport layer 123, light emitting layer 124.

Referring to fig. 3E, a plurality of reflective layers 142 are formed to cover the corresponding supporting bodies 141, thereby forming the reflective structure 140. The reflective layer 142 may be formed on the substrate 110 by vapor deposition, sputtering, atomic layer deposition, thermal evaporation, coating, or sputtering, and patterned by photolithography and etching. In some embodiments, after determining the respective thicknesses or sums of thicknesses of the predetermined formed carrier injection layer 122, carrier transport layer 123, light emitting layer 124, the thickness T1 of the reflective layer 142 is determined. In some embodiments, after determining the thickness of the support 141, the thickness T1 of the reflective layer 142 is determined. In some embodiments, the profile of the upper surface 142s1 of the reflective layer 142 may be determined after determining the respective thicknesses or thicknesses and sums of the carrier injection layer 122, the carrier transport layer 123, and the light emitting layer 124.

Referring to fig. 3F, a plurality of pixel defining layers 130 are formed on the insulating layer 131 so as to cover the supporting body 141 and the reflective layer 142. In some embodiments, a photosensitive material may be filled in the gaps between adjacent electrodes 121. The photosensitive material is heated to a predetermined temperature and then exposed to a specified wavelength. After exposure, the photosensitive material is wetted in a solution for development and a portion of the photosensitive material is removed, leaving the photosensitive material between the electrodes 121 to form the pixel defining layer 130. In some embodiments, the thickness T3 of the pixel defining layer 130 may be determined after determining the sum of thicknesses of the predetermined carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, and the carrier transport layer 125.

Referring to fig. 3G, a carrier injection layer 122, a carrier transport layer 123, a light emitting layer 124, a carrier transport layer 125, and an electrode 126 are formed on the electrode 121 to form light emitting cells 120a, 120b, and 120c. The layers of carrier injection layer 122, carrier transport layer 123, light emitting layer 124, carrier transport layer 125, and electrode 126 may be formed and patterned by deposition, lithography, and etching.

Referring to fig. 3H, a planarization layer 150 is formed to cover the light emitting units 120a, 120b, 120c and the pixel defining layer 130.

Referring to fig. 3I, a cover plate 190 is provided, and a light shielding layer 180, filter layers 170a, 170b, 170c, optical element layers 160a, 160b, 160c, and the like are formed on the cover plate 190. In some embodiments, forming the optical element layers 160a, 160b, and 160c includes forming an optical element material (not shown) on the filter layers 170a, 170b, and 170c, patterning the optical element material, and performing a reflow (reflow) process to provide the optical element layers 160a, 160b, and 160c with curved profiles.

Referring to fig. 3J, an alignment operation is performed, a cover plate 190 and a structure of components formed thereon are bonded to a substrate 110, and a filling layer 152 is formed to form a display device 100a.

Fig. 4 is a cross-sectional view of a display device 100b, according to some embodiments. Display device 100b may be similar to display device 100a, except that the outline of pixel definition layer 130' of display device 100b is different from pixel definition layer 130. In some embodiments, the profile of the pixel defining layer 130' includes a cylinder. In this embodiment, each of the carrier injection layer 122, the carrier transport layer 123, the light emitting layer 124, the carrier transport layer 125, and the electrode 126 may cover the upper surface of the pixel defining layer 130'.

The present disclosure accordingly provides a display device. A display device includes a substrate, a first light emitting unit, a second light emitting unit, a pixel defining layer, and a reflective layer. The first light-emitting unit is arranged on the substrate. The second light-emitting unit is arranged on the substrate. The pixel definition layer is arranged between the first light-emitting unit and the second light-emitting unit. The reflective layer is located in the pixel defining layer.

In certain embodiments, the scattering particles comprise a metal oxide.

In some embodiments, the top of the reflective layer is level between the upper surface of the light emitting layer and the lower surface of the light emitting layer.

In some embodiments, the top of the pixel defining layer is higher than the top surface of the carrier transporting layer.

The present disclosure accordingly provides a method of manufacturing a display device. The method comprises the following steps: providing a substrate; forming a first electrode and a second electrode on a substrate; forming a reflecting layer between the first electrode and the second electrode; and forming a pixel definition layer to cover the reflective layer.

In certain embodiments, the method further comprises: forming a carrier injection layer, a carrier transmission layer, a light-emitting layer and a carrier transmission layer.

In certain embodiments, the method further comprises: the thicknesses of the carrier injection layer, the carrier transport layer, the light emitting layer and then the thickness of the reflective layer are determined.

In certain embodiments, the method further comprises: the thicknesses of the carrier injection layer, the carrier transport layer, the light emitting layer, and the carrier transport layer are determined and then the thickness of the pixel defining layer is determined.

The foregoing outlines features of some embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments of the present application. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Furthermore, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of skill in the art will appreciate from the disclosure of the present disclosure that a process, machine, manufacture, composition of matter, means, methods, or steps, presently existing or later to be developed that perform the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, such processes, machines, manufacture, compositions of matter, means, methods, or steps, are included in the claims.

Claims

1. A display device, comprising:

a substrate;

the first light-emitting unit is arranged on the substrate;

the second light-emitting unit is arranged on the substrate;

the pixel definition layer is arranged between the first light-emitting unit and the second light-emitting unit; and

and the reflecting layer is positioned in the pixel definition layer.

2. The display apparatus of claim 1, wherein the pixel definition layer comprises a plurality of scattering particles.

3. The display device of claim 2, wherein each of the plurality of scattering particles has a particle size between about 0.1nm and about 1000nm.

4. The display device of claim 2, wherein the plurality of scattering particles comprise a metal oxide.

5. The display apparatus of claim 1, wherein the first light emitting unit includes a carrier injection layer, a first carrier transport layer, and a light emitting layer, and a thickness of the reflective layer is less than a sum of thicknesses of the carrier injection layer, the first carrier transport layer, and the light emitting layer.

6. The display apparatus of claim 1, wherein the first light emitting unit includes a carrier injection layer, a first carrier transport layer, a light emitting layer, and a second carrier transport layer, and a thickness of the pixel definition layer is greater than or equal to a sum of thicknesses of the carrier injection layer, the first carrier transport layer, the light emitting layer, and the second carrier transport layer.

7. The display device of claim 1, further comprising:

and the insulating layer is positioned between the reflecting layer and the substrate.

8. A method of manufacturing a display device, further comprising:

providing a substrate;

forming a first electrode and a second electrode on the substrate;

forming a reflective layer between the first electrode and the second electrode; and

a pixel defining layer is formed to cover the reflective layer.

9. The method of claim 8, further comprising, prior to forming the pixel definition layer:

a dielectric layer is formed to cover the substrate, the first electrode and the second electrode.

10. The method of claim 9, further comprising:

forming a support on the dielectric layer,

wherein the reflective layer covers the support.