CN116828846A - Semiconductor structure and preparation method thereof - Google Patents

Abstract

The present disclosure provides a semiconductor structure and a preparation method thereof, which relate to the technical field of semiconductors and are used for solving the technical problem of poor alignment precision of a contact plug; forming a first interconnection layer in the peripheral circuit region, the first interconnection layer having a plurality of first conductive bumps and second conductive bumps; forming a second interconnection layer above the first interconnection layer, wherein the second interconnection layer is at least provided with a first conductive structure, a second conductive structure and a third conductive block, the third conductive block is connected with the first conductive block through the first conductive structure, the second conductive structure is positioned on the second conductive block and is in contact connection with the second conductive block, and the top of the second conductive structure is level with the top of the third conductive block; contact plugs are formed on the third conductive block and the second conductive structure, respectively, and are in contact connection therewith. The method and the device can improve the alignment precision of the contact plug, reduce the contact resistance and improve the performance of the semiconductor device.

Description

Semiconductor structure and preparation method thereof

Technical Field

The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.

Background

In the process of manufacturing a semiconductor structure, an interconnection structure is an indispensable structure in the semiconductor structure, for example, a dynamic random access memory ((Dynamic Random Access Memory, abbreviated as DRAM)) and the formed dynamic random access memory generally includes an array region and a peripheral circuit region adjacent to the array region, wherein the array region is used for providing a plurality of memory cells for storing data information, and the peripheral circuit region is generally provided with an interconnection layer for electrically connecting with the memory cells so that the memory cells complete the storage or reading of the data information.

Along with the development of the semiconductor structure toward miniaturization and integration, the wiring density of the interconnection layer is continuously increased, which can bring about the problems of short circuit among devices and the like.

However, due to the different aspect ratios of the contact plugs connecting the two different interconnection layers, the alignment accuracy of the contact plugs is poor in the preparation process, and the preparation process is complex.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can improve alignment accuracy of a contact plug, reduce contact resistance, and thereby improve performance of a semiconductor device.

In order to achieve the above object, the embodiments of the present disclosure provide the following technical solutions:

a first aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

providing a substrate, wherein the substrate comprises an array region and a peripheral circuit region adjacent to the array region;

forming a first interconnection layer in the peripheral circuit region, wherein the first interconnection layer is provided with a plurality of first conductive blocks and second conductive blocks which are arranged at intervals;

forming a second interconnection layer above the first interconnection layer, wherein the second interconnection layer is provided with at least a first conductive structure, a second conductive structure and a third conductive block, the third conductive block is at least positioned on the first conductive structure and is in contact connection with the first conductive structure, the first conductive structure is positioned on the first conductive block and is in contact connection with the first conductive block, the second conductive structure is positioned on the second conductive structure and is in contact connection with the second conductive block, and the top of the second conductive structure is flush with the top of the third conductive block;

And forming contact plugs which are in contact connection with the third conductive block and the second conductive structure respectively.

In some alternative embodiments, the step of forming a second interconnect layer over the first interconnect layer includes:

forming a first dielectric layer on the first interconnection layer;

forming a first contact groove and a second contact groove in the first dielectric layer, wherein the first contact groove comprises a first groove and a second groove which are exposed at least partially of the first conductive block, the second groove is positioned above the first groove and is communicated with the first groove, the projection area of the second groove on the substrate is larger than the projection area of the first groove on the substrate, and at least partially of the second groove is exposed;

depositing a conductive material in the first contact trench and the second contact trench, respectively, wherein the conductive material deposited in the first trench is formed as the first conductive structure, the conductive material deposited in the second trench is formed as the third conductive bump, the conductive material deposited in the second contact trench is formed as the second conductive structure, and the first conductive structure, the third conductive bump, and the second conductive structure are collectively formed as the second interconnect layer;

The tops of the third conductive block and the second conductive structure are respectively flush with the top of the first dielectric layer.

In some alternative embodiments, the step of forming the first contact trench and the second contact trench in the first dielectric layer includes:

forming a first groove and a second contact groove in the first dielectric layer synchronously;

forming a sacrificial material layer in the first trench and the second contact trench;

forming a patterned first mask layer on the first dielectric layer and the sacrificial material layer, wherein the patterned first mask layer covers part of the first dielectric layer and the sacrificial material layer in the second contact groove and at least exposes the sacrificial material layer in the first groove and the first dielectric layer at the opening edge of the first groove;

and removing the exposed part of the first dielectric layer and the sacrificial material layer by taking the patterned first mask layer as a mask, so as to form at least a second groove communicated with the second groove, wherein the first groove and the second groove are formed into the first contact groove together.

In some alternative embodiments, the step of forming the first trench and the second contact trench in the first dielectric layer simultaneously includes:

Forming a patterned second mask layer on the first dielectric layer;

and removing part of the first dielectric layer by taking the patterned second mask layer as a mask, so as to respectively form a first groove exposing at least part of the first conductive block and a second contact groove exposing at least part of the second conductive block.

In some alternative embodiments, the step of forming the first contact trench and the second contact trench in the first dielectric layer includes:

forming an initial second groove in the first dielectric layer, wherein the projection of the initial second groove on the substrate at least partially coincides with the projection of the first conductive block on the substrate;

forming a patterned third mask layer on the first dielectric layer, wherein the patterned third mask layer exposes part of the initial second groove and the first dielectric layer corresponding to the second conductive block;

removing the exposed first dielectric layer by taking the patterned third mask layer as a mask so as to form an initial first groove and an initial second contact groove respectively;

and after the third mask layer is removed, etching along the initial second groove until a second groove is formed, etching along the initial first groove until a first groove exposing at least part of the first conductive block is formed, and etching along the initial second contact groove until a second contact groove exposing at least part of the second conductive block is formed, wherein the groove is communicated with the second groove, and the first groove and the second groove are jointly formed into the first contact groove.

In some alternative embodiments, after depositing the conductive material in the first contact trench and the second contact trench, respectively, further comprising:

and taking the first dielectric layer as a stop layer, and flattening the conductive material through a chemical mechanical polishing process so that the tops of the formed third conductive block and the formed second conductive structure are respectively level with the top of the first dielectric layer.

In some alternative embodiments, the step of forming contact plugs on the third conductive block and the second conductive structure, respectively, includes:

forming a second dielectric layer over the second interconnect layer;

forming at least two contact holes which are arranged at intervals on the second dielectric layer, wherein the at least two contact holes are respectively arranged in one-to-one correspondence with the third conductive blocks and the second conductive structures, at least part of the third conductive blocks are exposed by the contact holes corresponding to the third conductive blocks, and at least part of the second conductive structures are exposed by the contact holes corresponding to the second conductive structures;

forming a barrier layer on the side wall of the contact hole;

and forming a contact plug in each contact hole.

In some alternative embodiments, further comprising:

forming a capacitor contact pad in the array region while forming a first interconnect layer in the peripheral circuit region;

forming a first dielectric layer on the first interconnection layer, and forming a third dielectric layer in the array region, wherein the third dielectric layer covers the top of the capacitor contact pad;

removing a part of the third dielectric layer of the array region after forming the second interconnection layer above the first interconnection layer to expose the capacitance contact pad;

and forming a capacitor electrically connected with the capacitor contact pad in the array region.

The second aspect of the disclosed embodiments also provides a semiconductor structure, comprising:

a substrate including an array region and a peripheral circuit region adjacent to the array region;

the first interconnection layer is arranged in the peripheral circuit area and is provided with a plurality of first conductive blocks and second conductive blocks which are arranged at intervals;

a second interconnect layer disposed over the first interconnect layer, the second interconnect layer including a first conductive structure, a second conductive structure, and a third conductive block, the third conductive block being located at least on and in contact with the first conductive structure, the first conductive structure being located on and in contact with the first conductive block, the second conductive structure being located on and in contact with the second conductive block, and a top of the second conductive structure being flush with a top of the third conductive block;

At least two contact plugs are arranged at intervals, at least two contact plugs are respectively arranged in one-to-one correspondence with the third conductive blocks and the second conductive structures, one third conductive block corresponds to one contact plug and is in contact connection with the contact plug, and one second conductive structure corresponds to one contact plug and is in contact connection with the contact plug.

In some alternative embodiments, the semiconductor structure further includes a first dielectric layer, the second interconnect layer is disposed in the first dielectric layer, and tops of the third conductive block and the second conductive structure are respectively level with a top of the first dielectric layer.

According to the semiconductor structure and the preparation method thereof, the independent second conductive structure is arranged in the second interconnection layer, so that the contact plug corresponding to the second conductive structure can be connected to the second conductive block through the second conductive structure, the contact plug corresponding to the third conductive block can be connected to the first conductive block through the third conductive block and the first conductive structure in sequence, and the top of the second conductive structure is flush with the top of the third conductive block, namely the top of the second conductive structure is in the same plane with the top of the third conductive block, so that the problem of poor alignment precision of the contact plug caused by different depths of the contact plugs respectively used for connecting the third conductive block and the second conductive block can be solved, the alignment precision of the contact plug can be improved, the health degree of the contact plug is guaranteed, the contact resistance of the contact plug is reduced, and the performance of a semiconductor device is further improved.

In addition to the technical problems, technical features constituting the technical solutions, and beneficial effects caused by the technical features of the technical solutions described above, the semiconductor structure and the method for manufacturing the semiconductor structure provided in the embodiments of the present disclosure solve other technical problems, other technical features included in the technical solutions, and beneficial effects caused by the technical features, which are described in detail above, will be described in detail in the detailed description.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief description will be given below of the drawings required for the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 2 is a schematic cross-sectional view of a substrate in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 3 is a schematic cross-sectional view of a first conductive block and a second conductive block formed on a substrate in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

Fig. 4 is a schematic cross-sectional view illustrating a first dielectric layer formed in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

fig. 5 is a schematic cross-sectional view of forming a first trench and a first contact trench in the first dielectric layer based on fig. 4;

FIG. 6 is a schematic cross-sectional view of the sacrificial material layer formed in the first trench and the first contact trench on the basis of FIG. 5;

FIG. 7 is a schematic cross-sectional view of a second trench formed over the first trench based on FIG. 6;

FIG. 8 is a schematic cross-sectional view of forming an initial second trench in the first dielectric layer based on FIG. 3;

fig. 9 is a schematic cross-sectional view illustrating filling of conductive materials in a first contact trench and a second contact trench in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 10 is a schematic cross-sectional view illustrating a surface of a planarized first dielectric layer in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;

fig. 11 is a schematic cross-sectional view of a contact hole formed in a second dielectric layer in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 12 is a schematic cross-sectional view of a contact plug formed in a contact hole in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure;

fig. 13 is a schematic cross-sectional view of forming a first dielectric layer in a peripheral circuit region and forming a third dielectric layer in an array region in a method for manufacturing a semiconductor structure according to an embodiment of the disclosure;

FIG. 14 is a schematic cross-sectional view of the array region of FIG. 13 with portions of the third dielectric layer removed to expose the capacitive contact pads;

fig. 15 is a schematic cross-sectional view of a capacitor formed on the capacitor contact pad of the array region based on fig. 14.

Reference numerals:

a 100-semiconductor structure; 110-a substrate; a 111-insulating layer; 120-a first interconnect layer;

121-a first conductive block; 122-a second conductive block; 130-a second interconnect layer;

131-a first conductive structure; 132-a second conductive structure; 133-a third conductive block;

140-a first dielectric layer; 150-a first contact trench; 151-a first trench;

152-a second trench; 152 a-an initial second trench;

160-a second contact trench; 170-a layer of sacrificial material; 180-a first mask layer;

190-a second dielectric layer; 191-contact holes; 192-contact plugs;

200-a third dielectric layer; 210-capacitive contact pads; 220-capacitor.

Detailed Description

In order to solve the problem of high wiring density, the inventor of the present disclosure has found that, in an actual working process, as a semiconductor structure is developed toward miniaturization and integration, the wiring density of an interconnection layer is continuously increased, and in a related art, the interconnection layer includes at least a first interconnection layer and a second interconnection layer stacked in a vertical direction, so as to reduce the wiring density of the interconnection layer in the same layer, and the first interconnection layer and the second interconnection layer are electrically connected with a memory unit through contact plugs respectively, so as to implement storage or reading of data information. However, because the aspect ratios of the contact holes corresponding to the contact plugs respectively connecting the first interconnection layer and the second interconnection layer are different, for example, the contact hole corresponding to the first interconnection layer is represented by the first contact hole, the contact hole corresponding to the second interconnection layer is represented by the second contact hole, and the aspect ratio of the first contact hole is larger than that of the second contact hole, in the preparation process, the problem that the first contact hole is not etched in place and the second contact hole is over-etched exists, and the connection part of the contact plug and the first interconnection layer and the second interconnection layer is easy to be broken or open, therefore, the technical problems of poor alignment accuracy of the contact plug and complex preparation process exist.

In order to solve the above-mentioned problems, the embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, by providing an independent second conductive structure in a second interconnection layer, so that a contact plug corresponding to the second conductive structure may be connected to a second conductive block through the second conductive structure, and a contact plug corresponding to a third conductive block may sequentially pass through the third conductive block and the first conductive structure and be connected to a first conductive block.

In order to make the above objects, features and advantages of the embodiments of the present disclosure more comprehensible, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present disclosure. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of the present disclosure.

Referring to fig. 1 to 12, an embodiment of the disclosure provides a method for manufacturing a semiconductor structure, for example, a Dynamic Random Access Memory (DRAM), although the semiconductor structure in the embodiment of the disclosure may be other structures; the following description will take a semiconductor structure as an example of a Dynamic Random Access Memory (DRAM).

Referring to fig. 1, the method for preparing the semiconductor structure includes:

step S101: a substrate is provided that includes an array region and a peripheral circuit region adjacent to the array region.

In some embodiments, the material comprising substrate 110 may include any one or more of silicon, germanium, silicon carbide, silicon-on-insulator, and germanium-on-insulator; alternatively, the material constituting the substrate 110 may be other materials known to those skilled in the art. In the disclosed embodiment, at least a portion of the substrate 110 is a silicon substrate 110, and the silicon material may be monocrystalline silicon. Illustratively, the substrate 110 may be formed by chemical vapor deposition (Chemical Vapor Deposition, simply CVD) preparation.

Wherein the substrate 110 serves as a support member for the semiconductor structure 100 for supporting other components disposed thereon.

In some embodiments, the substrate 110 may be provided with a plurality of active areas arranged in an array, where the plurality of active areas are arranged in an array, the area where the plurality of active areas are arranged forms an array area, and the area where the active areas are not arranged on the periphery of the array area forms a peripheral circuit area, where the peripheral circuit area and the array area may be adjacent and arranged side by side or arranged side by side, or the peripheral circuit area may surround the periphery of the array area, which may be specifically designed adaptively according to practical requirements, and is not limited herein.

For example, please refer to fig. 2, in which the array area is denoted by a, the peripheral circuit area is denoted by B, and the array area and the peripheral circuit area are disposed adjacently.

In the subsequent process, the array region may be formed with capacitors arranged in an array, and the peripheral circuit region may be formed with a first interconnect layer 120 and a second interconnect layer 130 stacked in a vertical direction and electrically connected to each other, for example, the second interconnect layer 130 is located above the first interconnect layer 120, and the first interconnect layer 120 and the second interconnect layer 130 are respectively electrically connected to the capacitors and/or the peripheral transistors, so as to implement storage or reading of data information by the dynamic random access memory.

Step S102: a first interconnect layer is formed in the peripheral circuit region, the first interconnect layer having a plurality of first conductive bumps and second conductive bumps disposed at intervals.

Referring to fig. 3, in some embodiments, in the step of forming the first interconnect layer 120 in the peripheral circuit region, the first interconnect layer 120 has a plurality of first conductive blocks 121 and second conductive blocks 122 disposed at intervals, the method specifically includes:

forming an insulating layer 111 on the substrate 110 of the peripheral circuit region, the insulating layer 111 being, for example, a silicon oxide layer; after the insulating layer 111 is formed on the substrate 110, a first conductive layer may be formed on the insulating layer 111 by a process such as physical vapor deposition (Physical Vapor Deposition, abbreviated as PVD), chemical vapor deposition (Chemical Vapor Deposition, abbreviated as CVD), or atomic layer deposition (Atomic Layer Deposition, abbreviated as ALD), wherein a material of the first conductive layer is a metal conductive material such as aluminum (Al), tungsten (W), and tin (Sn); after forming the first conductive layer, forming a patterned mask on the first conductive layer, using the patterned mask as a mask, and removing a part of the first conductive layer through a dry etching or wet etching process, wherein the remaining first conductive layer is formed into a first conductive block 121 and a second conductive block 122, respectively, as shown in fig. 3, wherein the first conductive block 121 may be one or more, and the second conductive block 122 may be one or more.

After forming the first conductive bump 121 and the second conductive bump 122 that are disposed at intervals, further comprising forming an isolation layer on the surfaces of the first conductive bump 121 and the second conductive bump 122, as shown in fig. 4, the isolation layer being made of an insulating material such as silicon oxide, the isolation layer being used to electrically isolate the first conductive bump 121 and the second conductive bump 122 from devices thereof, the first conductive bump 121 and the second conductive bump 122 being formed as the first interconnect layer 120, and an arrangement pattern of the first conductive bump 121 and the second conductive bump 122 in a horizontal plane being formed as a wiring pattern of the first interconnect layer 120.

Step S103: and forming a second interconnection layer above the first interconnection layer, wherein the second interconnection layer is at least provided with a first conductive structure, a second conductive structure and a third conductive block, the third conductive block is at least positioned on the first conductive structure and is in contact connection with the first conductive structure, the first conductive structure is positioned on the first conductive block and is in contact connection with the first conductive block, the second conductive structure is positioned on the second conductive block and is in contact connection with the second conductive block, and the top of the second conductive structure is flush with the top of the third conductive block.

It will be appreciated that, as shown in fig. 12, the second interconnect layer 130 is electrically connected to the first conductive block 121 in the first interconnect layer 120 through the third conductive block 133 and the first conductive structure 131, so that the electrical connection between the first interconnect layer 120 and the second interconnect layer 130 can be achieved, so as to avoid the problem that the arrangement space is insufficient due to too high density when the first conductive block 121, the second conductive block 122 and the third conductive block 133 are located in the same layer, while in the embodiment of the present disclosure, the second interconnect layer 130 is provided with the independent second conductive structure 132, so that the top of the second conductive structure 132 is electrically connected to the second conductive block 122 in the first interconnect layer 120 and the top of the third conductive block 133, that is, the connection surface of the second conductive block 122 and the contact plug 192 is moved to the plane where the top of the third conductive block 133 is located, so that the connection points of the contacts 192 respectively connected to the second conductive block 122 and the third conductive block 133 are located in the same plane in the subsequent process, so that the problem that the contact plug 192 is not aligned to have the same depth and the same precision of the contact plug 192 can be avoided.

As shown in conjunction with fig. 3 and 4, in some embodiments, the step of forming the second interconnect layer 130 over the first interconnect layer 120 includes:

a first dielectric layer 140 is formed on the first interconnect layer 120, the first dielectric layer 140 covering a surface of the first interconnect layer 120, as shown in fig. 4, wherein a material of the first dielectric layer 140 may be, for example, silicon oxide, wherein the first dielectric layer 140 fills a gap between the first conductive block 121 and the second conductive block 122 in the first interconnect layer 120 and covers a surface of the first interconnect layer 120 to protect and support sidewalls of the first conductive block 121 and the second conductive block 122 through the first dielectric layer 140, and in addition, the first dielectric layer 140 may electrically isolate between the first conductive block 121 and the second conductive block 122.

After forming the first dielectric layer 140 on the first interconnection layer 120, a first contact trench 150 and a second contact trench 160 are formed in the first dielectric layer 140, respectively, the first contact trench 150 includes a first trench 151 and a second trench 152 exposing at least a portion of the first conductive bump 121, the second trench 152 is located above the first trench 151 and communicates with the first trench 151, and a projected area of the second trench 152 on the substrate 110 is larger than a projected area of the first trench 151 on the substrate 110, and the second contact trench 160 exposes at least a portion of the second conductive bump 122, as shown in fig. 7, a process of forming the first contact trench 150 and the second contact trench 160 will be described in detail below with reference to the drawings.

In some embodiments, as shown in fig. 5 to 7, the step of forming the first contact trench 150 and the second contact trench 160 in the first dielectric layer 140 includes:

first, the first trench 151 and the second contact trench 160 are simultaneously formed in the first dielectric layer 140, as shown in fig. 5, specifically, a patterned second mask layer (not shown in the figure) is formed on the first dielectric layer 140; with the patterned second mask layer as a mask, a portion of the first dielectric layer 140 is removed by a dry etching or wet etching process to form a first trench 151 exposing at least a portion of the first conductive block 121 and a second contact trench 160 exposing at least a portion of the second conductive block 122, respectively.

Thereafter, a sacrificial material layer 170 is formed in the first trench 151 and the second contact trench 160, as shown in fig. 6; specifically, a sacrificial material is deposited in the first and second contact trenches 151 and 160 to form a sacrificial material layer 170 in the first and second contact trenches 151 and 160.

And forming a patterned first mask layer 180 on the first dielectric layer 140 and the sacrificial material layer 170, as shown in fig. 6, the patterned first mask layer 180 covering portions of the sacrificial material layer 170 in the first dielectric layer 140 and the second contact trench 160 and exposing at least the sacrificial material layer 170 in the first trench 151 and the first dielectric layer 140 at the opening edge of the first trench 151, and then removing the exposed portions of the first dielectric layer 140 and the sacrificial material layer 170 with the patterned first mask layer 180 as a mask to form at least a second trench 152 in communication with the first trench 151, the first trench 151 and the second trench 152 collectively forming a first contact trench 150, as shown in fig. 7, exemplary first trench 151 and second trench 152 may have, for example, a circular shape, a rectangular shape, etc. in a cross section in a direction perpendicular to the depth direction of the first trench 151, and central axes of the first trench 151 and the second trench 152 coincide;

The projected area of the second trench 152 on the substrate 110 is larger than the projected area of the first trench 151 on the substrate 110, so as to increase the area of the third conductive block 133 formed in the second trench 152 in the subsequent process, thereby increasing the contact area of the third conductive block 133 and the corresponding contact plug 192 and reducing the contact resistance.

In other embodiments, as shown in fig. 4 and 8, the step of forming the first contact trench 150 and the second contact trench 160 in the first dielectric layer 140 includes:

after forming the first dielectric layer 140 on the first interconnect layer 120, an initial second trench 152a is first formed within the first dielectric layer 140, as shown in fig. 8, with the projection of the initial second trench 152a onto the substrate 110 at least partially coinciding with the projection of the first conductive bump 121 onto the substrate 110.

Specifically, a patterned third mask layer (not shown) is formed on the first dielectric layer 140, where a portion of the patterned third mask layer exposes the initial second trench 152a and the first dielectric layer 140 corresponding to the second conductive block 122; the exposed first dielectric layer 140 is removed using the patterned third mask layer as a mask to form an initial first trench 151 and an initial second contact trench 160, respectively.

After forming the initial first trench 151 and the initial second contact trench 160, the third mask layer is removed, etching is performed along the initial second trench 152a until the second trench 152 is formed, etching is performed along the initial first trench 151 until the first trench 151 exposing at least a portion of the first conductive block 121 is formed, etching is performed along the initial second contact trench 160 until the second contact trench 160 exposing at least a portion of the second conductive block 122 is formed, wherein the first trench 151 communicates with the second trench 152, the first trench 151 and the second trench 152 are collectively formed as the first contact trench 150, and finally the structure as shown in fig. 7 is formed.

In some embodiments, as shown in connection with fig. 9, after forming the first contact trench 150 and the second contact trench 160 in the first dielectric layer 140, a conductive material, such as tungsten, aluminum, titanium nitride, titanium, etc., is deposited in the first contact trench 150 and the second contact trench 160, respectively.

Wherein the conductive material deposited in the first trench 151 is formed as the first conductive structure 131 and the conductive material deposited in the second trench 152 is formed as the third conductive block 133, such that the first conductive block 121 and the third conductive block 133 are connected through the first conductive structure 131, thereby achieving electrical connection between the first interconnect layer 120 and the second interconnect layer 130; and the conductive material deposited in the second contact trench 160 is formed as the second conductive structure 132, i.e., the second conductive structure 132 is electrically connected to the second conductive bump 122.

In some embodiments, after depositing the conductive material in the first contact trench 150 and the second contact trench 160, respectively, further comprises:

referring to fig. 10, the first dielectric layer 140 is used as a stop layer, and the conductive material is planarized by a chemical mechanical polishing process, so that the top of the third conductive bump 133 and the top of the second conductive structure 132 are respectively level with the top of the first dielectric layer 140.

According to the above scheme, the top of the third conductive block 133 and the top of the second conductive structure 132 are flush with the top of the first dielectric layer 140, so that the first dielectric layer 140 can protect and support the side wall of the third conductive block 133 and the side wall of the second conductive structure 132, and a protective layer is not required to be formed on the side wall of the third conductive block 133 and the side wall of the second conductive structure 132, thereby simplifying the preparation process and reducing the preparation cost.

Step S104: contact plugs are formed on the third conductive block and the second conductive structure, respectively, and are in contact connection therewith.

In some embodiments, the step of forming the contact plugs 192 in contact with the third conductive bumps 133 and the second conductive structures 132, respectively, includes:

referring to fig. 11, a second dielectric layer 190 is formed over the second interconnect layer 130, where the material of the second dielectric layer 190 is, for example, silicon oxide or the like; thereafter, a patterned fourth mask layer (not shown) is formed on the second dielectric layer 190, the patterned fourth mask layer exposes a portion of the second dielectric layer 190 corresponding to the third conductive bump 133 and the second conductive structure 132, the patterned fourth mask layer is used as a mask, and a portion of the second dielectric layer 190 is removed to form contact holes 191 in the second dielectric layer 190 exposing the third conductive bump 133 and the second conductive structure 132, respectively, i.e., the contact holes 191 corresponding to the third conductive bump 133 expose at least a portion of the third conductive bump 133, and the contact holes 191 corresponding to the second conductive structure 132 expose at least a portion of the second conductive structure 132.

In some embodiments, after forming the contact holes 191 in the second dielectric layer 190, a barrier layer (not shown) is deposited on the sidewalls of each contact hole 191, wherein the material of the barrier layer is, for example, titanium nitride (TiN) or the like, and then a conductive material, for example, metallic tungsten or the like, is deposited in each contact hole 191 to form a contact plug 192, as shown in fig. 12.

It is understood that the barrier layer serves to prevent diffusion of ions of the contact plug 192 by forming the barrier layer between the sidewall of the contact hole 191 and the contact plug 192.

In the above-mentioned scheme, since the top of the third conductive block 133 and the top of the second conductive structure 132 are located on the same plane, the depths of the contact holes 191 corresponding to the third conductive block 133 and the second conductive structure 132 respectively are formed in the second dielectric layer 190, so that each contact hole 191 can be formed synchronously by the same etching process, the problem of asynchronous etching of each contact hole 191 in the preparation process is avoided, and thus the alignment accuracy of the contact holes 191 in the preparation process can be improved, and the conductivity of the contact plugs 192 formed in the contact holes 191 subsequently can be improved.

It can be seen that, in the embodiment of the disclosure, by providing the independent second conductive structure 132 in the second interconnection layer 130, and the second conductive structure 132 is in contact connection with the second conductive block 122, so that the contact plug 192 corresponding to the second conductive structure 132 can be connected to the second conductive block 122 through the second conductive structure 132, and the contact plug 192 corresponding to the third conductive block 133 can be connected to the first conductive block 121 through the third conductive block 133 and the first conductive structure 131 in sequence, since the top of the second conductive structure 132 and the top of the third conductive block 133 are respectively level with the top of the first dielectric layer 140, that is, the third conductive block 133 and the second conductive structure 132 are embedded in the first dielectric layer 140, on one hand, the dielectric layer can protect the sidewalls of the third conductive block 133 and the second conductive structure 132, without forming a protective layer on the sidewalls of the third conductive block 133 and the second conductive structure 132, thereby simplifying the manufacturing process and reducing the manufacturing cost; on the other hand, the top of the second conductive structure 132 and the top of the third conductive block 133 are on the same plane, so that the alignment accuracy of the contact plug 192 electrically connected with the second conductive structure 132 and the third conductive structure respectively can be improved, the preparation difficulty of the contact plug 192 is reduced, the health of the contact plug 192 is improved, and the contact resistance is reduced, thereby improving the performance of the semiconductor device.

In some embodiments, as shown in fig. 13 to 15, the capacitor contact pad 210 may be formed in the array region simultaneously with the formation of the first interconnect layer 120 in the peripheral circuit region; thereafter, while forming the first dielectric layer 140 on the first interconnection layer 120, simultaneously forming a third dielectric layer 200 in the array region, the third dielectric layer 200 covering the top of the capacitance contact pad 210, as shown in fig. 13; after forming the second interconnect layer 130 over the first interconnect layer 120, removing a portion of the third dielectric layer 200 of the array region to expose the capacitive contact pad 210, as shown in fig. 14; then, a capacitor 220 electrically connected to the capacitor contact pad 210 is formed in the array region, and the other end of the contact plug 192 of the peripheral circuit region is electrically connected to the capacitor 220, as shown in fig. 15, so that the first interconnect layer 120 and the second interconnect layer 130 are respectively connected to the capacitor 220 through the corresponding contact plug 192 thereof, thereby realizing storage or reading of data information.

It can be appreciated that when the first interconnect layer 120 and the second interconnect layer 130 are formed in the peripheral circuit region, the capacitor contact pad 210 and the third dielectric layer 200 are formed in the array region simultaneously, which can simplify the manufacturing process and shorten the manufacturing time, thereby improving the manufacturing efficiency.

With continued reference to fig. 12, an embodiment of the present disclosure further provides a semiconductor structure 100, including a substrate 110, a first interconnect layer 120, a second interconnect layer 130, and at least two contact plugs 192 disposed at intervals; wherein the substrate 110 includes an array region and a peripheral circuit region adjacent to the array region; the first interconnection layer 120 is disposed in the peripheral circuit region, and the first interconnection layer 120 has a plurality of first conductive blocks 121 and second conductive blocks 122 disposed at intervals; the second interconnection layer 130 is disposed above the first interconnection layer 120, the second interconnection layer 130 includes a first conductive structure 131, a second conductive structure 132, and a third conductive block 133, the third conductive block 133 is at least on the first conductive structure 131 and is in contact with the first conductive structure 131, the first conductive structure 131 is on the first conductive block 121 and is in contact with the first conductive block 121, the second conductive structure 132 is on the second conductive block 122 and is in contact with the second conductive block 122, and the top of the second conductive structure 132 is flush with the top of the third conductive block 133; at least two contact plugs 192 are respectively in one-to-one correspondence with the third conductive blocks 133 and the second conductive structures 132, i.e. one third conductive block 133 corresponds to one contact plug 192 and the second conductive structure 132 corresponds to one contact plug 192.

The first interconnect layer 120 and the second interconnect layer 130 are disposed in the peripheral circuit area, the array area is provided with capacitors 220 arranged in an array, the substrate 110 may provide a supporting base for devices such as the first interconnect layer 120 and the second interconnect layer 130 in the peripheral circuit area, and meanwhile, the substrate 110 may also provide a supporting base for devices such as the capacitors 220 in the array area, for example, the substrate 110 may be a silicon substrate 110 or the like.

In the above-mentioned scheme, the contact plugs 192 corresponding to the second conductive structures 132 are connected to the second conductive blocks 122 through the second conductive structures 132, and the contact plugs 192 corresponding to the third conductive blocks 133 are connected to the first conductive blocks 121 through the third conductive blocks 133 and the first conductive structures 131 in turn, so as to achieve the purpose that the first interconnection layer 120 and the second interconnection layer 130 are connected to the capacitors 220 of the array region, so as to realize the storage or reading of data information; in addition, by making the top of the second conductive structure 132 and the top of the third conductive block 133 flush, the contact plugs 192 corresponding to the second conductive structure 132 and the third conductive block 133 can be formed simultaneously, so that the problem of high difficulty in the preparation process due to different heights of the contact plugs 192 is avoided, the alignment accuracy of the contact plugs 192 in the preparation process is improved, the health of the contact plugs 192 is improved, and the contact resistance is reduced.

In some embodiments, the semiconductor structure 100 further includes a first dielectric layer 140, the second interconnect layer 130 is disposed in the first dielectric layer 140, and tops of the third conductive block 133 and the second conductive structure 132 are respectively level with a top of the first dielectric layer 140.

The first dielectric layer 140 may be, for example, a silicon oxide layer, and the first dielectric layer 140 may be used to realize electrical isolation between adjacent first conductive structures 131 and second conductive structures 132, and in addition, tops of the third conductive blocks 133 and the second conductive structures 132 are flush with tops of the first dielectric, that is, the first dielectric layer 140 wraps up a side wall of the third conductive blocks 133 and a side wall of the second conductive structures 132, so that the first dielectric layer 140 may protect and support the side walls of the third conductive blocks 133 and the second conductive structures 132 respectively, without additionally providing protective layers on the side walls of the third conductive blocks 133 and the second conductive structures 132, thereby improving working reliability of the third conductive blocks 133 and the second conductive structures 132, simplifying a preparation process, and reducing preparation cost.

In some embodiments, a second dielectric layer 190 is further disposed above the first dielectric layer 140, and each contact plug 192 is disposed on the second dielectric layer 190 to support the contact plug 192 and electrically isolate adjacent contact plugs 192 through the second dielectric layer 190, where a material of the second dielectric layer 190 is made of an insulating material such as silicon oxide.

It can be understood that the first conductive block 121 sequentially passes through the first conductive structure 131 and the third conductive block 133 and is connected to the capacitor 220 or the peripheral circuit device through the contact plug 192 corresponding thereto, and the second conductive block 122 passes through the second conductive structure 132 and is connected to the capacitor 220 or the peripheral circuit device through the contact plug 192 corresponding thereto, so as to implement the storage or the reading of data information by the dynamic random access memory.

According to the semiconductor structure and the preparation method thereof, the independent second conductive structure is arranged in the second interconnection layer, and the second conductive structure is in contact connection with the second conductive block, so that the contact plug corresponding to the second conductive structure can be connected to the second conductive block through the second conductive structure, and the contact plug corresponding to the third conductive block can be connected to the first conductive block through the third conductive block and the first conductive structure in sequence; on the other hand, the top of the second conductive structure and the top of the third conductive block are on the same plane, so that the alignment precision of the contact plugs electrically connected with the second conductive structure and the third conductive structure respectively can be improved, the preparation difficulty of the contact plugs is reduced, the health of the contact plugs is improved, the contact resistance is reduced, and the performance of the semiconductor device is improved.

In this specification, each embodiment or implementation is described in a progressive manner, and each embodiment focuses on a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.

In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present disclosure. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present disclosure.

Claims (10)

1. A method of fabricating a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises an array region and a peripheral circuit region adjacent to the array region;

forming a first interconnection layer in the peripheral circuit region, wherein the first interconnection layer is provided with a plurality of first conductive blocks and second conductive blocks which are arranged at intervals;

forming a second interconnection layer above the first interconnection layer, wherein the second interconnection layer is provided with at least a first conductive structure, a second conductive structure and a third conductive block, the third conductive block is at least positioned on the first conductive structure and is in contact connection with the first conductive structure, the first conductive structure is positioned on the first conductive block and is in contact connection with the first conductive block, the second conductive structure is positioned on the second conductive block and is in contact connection with the second conductive block, and the top of the second conductive structure is flush with the top of the third conductive block;

and forming contact plugs which are in contact connection with the third conductive block and the second conductive structure respectively.

2. The method of manufacturing a semiconductor structure according to claim 1, wherein in the step of forming a second interconnect layer over the first interconnect layer, comprising:

Forming a first dielectric layer on the first interconnection layer;

forming a first contact groove and a second contact groove in the first dielectric layer, wherein the first contact groove comprises a first groove and a second groove which are exposed at least partially of the first conductive block, the second groove is positioned above the first groove and is communicated with the first groove, the projection area of the second groove on the substrate is larger than the projection area of the first groove on the substrate, and the second contact groove is exposed at least partially of the second conductive block;

depositing a conductive material in the first contact trench and the second contact trench, respectively, wherein the conductive material deposited in the first trench is formed as the first conductive structure, the conductive material deposited in the second trench is formed as the third conductive block, the conductive material deposited in the second contact trench is formed as the second conductive structure, and the first conductive structure, the third conductive block and the second conductive structure are formed together as the second interconnect layer;

the tops of the third conductive block and the second conductive structure are respectively flush with the top of the first dielectric layer.

3. The method of manufacturing a semiconductor structure according to claim 2, wherein the step of forming the first contact trench and the second contact trench in the first dielectric layer respectively includes:

forming a first groove and a second contact groove in the first dielectric layer synchronously;

forming a sacrificial material layer in the first trench and the second contact trench;

forming a patterned first mask layer on the first dielectric layer and the sacrificial material layer, wherein the patterned first mask layer covers part of the first dielectric layer and the sacrificial material layer in the second contact groove and at least exposes the sacrificial material layer in the first groove and the first dielectric layer at the opening edge of the first groove;

and removing the exposed part of the first dielectric layer and the sacrificial material layer by taking the patterned first mask layer as a mask, so as to form at least a second groove communicated with the first groove, wherein the first groove and the second groove are formed into the first contact groove together.

4. The method of manufacturing a semiconductor structure according to claim 3, wherein the step of forming the first trench and the second contact trench in the first dielectric layer simultaneously comprises:

Forming a patterned second mask layer on the first dielectric layer;

and removing part of the first dielectric layer by taking the patterned second mask layer as a mask, so as to respectively form a first groove exposing at least part of the first conductive block and a second contact groove exposing at least part of the second conductive block.

5. The method of manufacturing a semiconductor structure according to claim 2, wherein the step of forming the first contact trench and the second contact trench in the first dielectric layer respectively includes:

forming an initial second groove in the first dielectric layer, wherein the projection of the initial second groove on the substrate at least partially coincides with the projection of the first conductive block on the substrate;

forming a patterned third mask layer on the first dielectric layer, wherein the patterned third mask layer exposes part of the initial second groove and the first dielectric layer corresponding to the second conductive block;

removing the exposed first dielectric layer by taking the patterned third mask layer as a mask so as to form an initial first groove and an initial second contact groove respectively;

and after the third mask layer is removed, etching along the initial second groove until a second groove is formed, etching along the initial first groove until a first groove exposing at least part of the first conductive block is formed, and etching along the initial second contact groove until a second contact groove exposing at least part of the second conductive block is formed, wherein the first groove is communicated with the second groove, and the first groove and the second groove are formed together to form the first contact groove.

6. The method of any of claims 2-5, further comprising, after depositing conductive material in the first contact trench and the second contact trench, respectively:

and taking the first dielectric layer as a stop layer, and flattening the conductive material through a chemical mechanical polishing process so that the tops of the formed third conductive block and the formed second conductive structure are respectively level with the top of the first dielectric layer.

7. The method of manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein the step of forming contact plugs on the third conductive block and the second conductive structure, respectively, to be in contact therewith, comprises:

forming a second dielectric layer over the second interconnect layer;

forming at least two contact holes which are arranged at intervals on the second dielectric layer, wherein the at least two contact holes are respectively arranged in one-to-one correspondence with the third conductive blocks and the second conductive structures, at least part of the third conductive blocks are exposed by the contact holes corresponding to the third conductive blocks, and at least part of the second conductive structures are exposed by the contact holes corresponding to the second conductive structures;

Forming a barrier layer on the side wall of the contact hole;

and forming corresponding contact plugs in the contact holes respectively.

8. The method of manufacturing a semiconductor structure according to any one of claims 2 to 5, further comprising:

forming a capacitor contact pad in the array region while forming a first interconnect layer in the peripheral circuit region;

forming a first dielectric layer on the first interconnection layer, and forming a third dielectric layer in the array region, wherein the third dielectric layer covers the top of the capacitor contact pad;

removing a part of the third dielectric layer of the array region after forming the second interconnection layer above the first interconnection layer to expose the capacitance contact pad;

and forming a capacitor electrically connected with the capacitor contact pad in the array region.

9. A semiconductor structure, comprising:

a substrate including an array region and a peripheral circuit region adjacent to the array region;

the first interconnection layer is arranged in the peripheral circuit area and is provided with a plurality of first conductive blocks and second conductive blocks which are arranged at intervals;

a second interconnect layer disposed over the first interconnect layer, the second interconnect layer including a first conductive structure, a second conductive structure, and a third conductive block, the third conductive block being located at least on and in contact with the first conductive structure, the first conductive structure being located on and in contact with the first conductive block, the second conductive structure being located on and in contact with the second conductive block, and a top of the second conductive structure being flush with a top of the third conductive block;

At least two contact plugs are arranged at intervals, at least two contact plugs are respectively arranged in one-to-one correspondence with the third conductive blocks and the second conductive structures, one third conductive block corresponds to one contact plug and is in contact connection with the contact plug, and one second conductive structure corresponds to one contact plug and is in contact connection with the contact plug.

10. The semiconductor structure of claim 9, further comprising a first dielectric layer, wherein the second interconnect layer is disposed in the first dielectric layer, and wherein tops of the third conductive block and the second conductive structure are respectively level with a top of the first dielectric layer.