CN116827492A - Error code analysis method, error code analysis architecture and error code analyzer based on sampling - Google Patents
Error code analysis method, error code analysis architecture and error code analyzer based on sampling Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
- H04L1/203—Details of error rate determination, e.g. BER, FER or WER
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0823—Errors, e.g. transmission errors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/08—Monitoring or testing based on specific metrics, e.g. QoS, energy consumption or environmental parameters
- H04L43/0852—Delays
- H04L43/087—Jitter
Abstract
The invention provides a sampling-based error code analysis method, an error code analysis architecture and an error code analyzer, wherein the method comprises the following steps: acquiring a transmission rate of transmission data; selecting a corresponding working mode according to the obtained transmission rate to sample the transmission data to obtain sampling data; the faster the transmission rate is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1; the obtained sampled data can also restore the transmission data according to the samplings of the discrete sequence so as to realize error code of the transmission data with low analysis rate and high transmission rateAnd (5) analyzing.
Description
Technical Field
The present invention relates to the field of data transmission, and in particular, to a sampling-based error code analysis method, an error code analysis architecture, and an error code analyzer.
Background
In binary communication systems, an error refers to a wrong 0-1 inversion. False detection is a common measure of the ability of a communication system to properly transmit bit data. The false alarm detection process is roughly as follows: the Bit Error Rate (BER) of the device to be tested in the process of transmitting data can be obtained by sending a known bit sequence to the device to be tested (DUT), acquiring the transmitted data at the output end, analyzing and counting the number of bits with errors in the data, and dividing the number of bits by the total number of transmitted bits. Wherein, the lower the bit error rate of a system, the higher the transmission reliability.
In the prior art, the device used to analyze the bit error rate of the device under test is called a bit error analyzer (BER Tester, BERT). When the transmission rate of the output data of the device to be tested is higher than the analysis rate upper limit of the error code analyzer, the output data of the device to be tested is demultiplexed to adapt to the analysis rate of the error code analyzer. For example, the transmission rate of the output data is 80Gbps, the upper limit of the analysis rate of the error code analyzer is 20Gbps, and the output data needs to be first 1:4 demultiplexed to use the error code analyzer of 20 Gbps. Demultiplexing the output data requires expensive high-speed demultiplexers and may introduce additional jitter.
There is a need for a low cost error code analysis method and corresponding error code analyzer that can accommodate high data transmission rates at low analysis rates.
Disclosure of Invention
The invention provides a sampling-based error code analysis method, an error code analysis architecture and an error code analyzer, which are used for realizing error code analysis of transmission data with low analysis rate and high transmission rate.
According to a first aspect of the present invention, there is provided a sample-based error analysis method for detecting a bit error rate of transmission data; wherein the transmission data is a binary digital signal, the method comprising:
acquiring a transmission rate of transmission data;
selecting corresponding operation mode pairs according to the obtained transmission rateSampling the transmission data to obtain sampling data; the faster the transmission rate is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1;
and carrying out error code analysis on the obtained sampling data.
Optionally, selecting a corresponding working mode to sample the transmission data specifically includes:
generating a first signal and a phase discrimination signal according to the selected working mode;
sampling the transmission data according to the first signal and the phase discrimination signal; wherein the phase-discrimination signal is used for discriminating jitter of the transmission data; jitter of the transmitted data is used to characterize rising or falling edges of the transmitted data as leading or lagging relative to a standard signal.
Optionally, performing error code analysis on the obtained sampling data specifically includes:
according to the first signal, carrying out sequence regeneration on the sampling data to obtain a first sequence;
performing first processing on the sampling data and the first sequence, and outputting a second sequence; wherein the sampled data, the first sequence, and the second sequence are all used to characterize a binary digital signal;
calculating the error rate of the sampled data according to the second sequence; the error rate of the sampled data is used for representing the error rate of the transmission data.
Optionally, the first processing is performed on the sampled data and the first sequence, specifically including: and performing exclusive nor on the sampling data and the first sequence.
Optionally, calculating the error rate of the sampled data according to the second sequence specifically includes:
dividing the low level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
Optionally, the first processing is performed on the sampled data and the first sequence, specifically including: exclusive or is performed on the sampled data and the first sequence.
Optionally, calculating the error rate of the sampled data according to the second sequence specifically includes:
dividing the high level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
According to a second aspect of the present invention, there is provided an error analysis architecture for the sample-based error analysis method according to the first aspect and the optional aspects of the present invention, the error analyzer includes:
the transmission rate acquisition module is used for acquiring the transmission rate of the transmission data;
the working mode selection module is used for selecting a corresponding working mode according to the obtained transmission rate; the higher the transmission rate of the transmission data is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1;
the sampling unit is used for sampling the transmission data according to the selected working mode to obtain sampling data;
and the error code analysis module is used for carrying out error code analysis on the transmission data according to the sampling data.
Optionally, the error code analysis module includes a signal generation module; the signal generation module is used for generating a first signal and a phase discrimination signal according to the selected working mode;
the sampling unit is used for sampling the transmission data according to the first signal and the phase discrimination signal to obtain sampling data; wherein the phase-discrimination signal is used for discriminating jitter of the transmission data; jitter of the transmitted data is used to characterize rising or falling edges of the transmitted data as leading or lagging relative to a standard signal.
Optionally, the error code analysis module further includes:
a sequence generation unit coupled to the signal generation unit and the sampling unit, respectively; the sequence generating unit is used for carrying out sequence regeneration on the sampling data according to the first signal and outputting a first sequence;
a first processing unit coupled to the sequence generation unit and the sampling unit, respectively; the first processing unit is used for performing first processing on the sampling data and the first sequence and outputting a second sequence; wherein the sampled data, the first sequence, and the second sequence are all used to characterize a binary digital signal;
the error signal counting unit is coupled to the first processing unit; the error counting unit is used for calculating the error rate of the sampling data according to the second sequence; the error rate of the sampled data is used for representing the error rate of the transmission data.
Optionally, the first processing unit is configured to perform a first process on the sampled data and the first sequence, specifically: the first processing unit is configured to nor the sample data and the first sequence.
Optionally, the error counting unit is configured to calculate, according to the second sequence, an error rate of the sampled data, specifically:
the error counting unit is used for dividing the high-level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
Optionally, the first processing unit is configured to perform a first process on the sampled data and the first sequence, specifically: the first processing unit is configured to exclusive-or the sampled data with the first sequence.
Optionally, the error counting unit is configured to calculate, according to the second sequence, an error rate of the sampled data, specifically:
the error counting unit is used for dividing the low-level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
According to a third aspect of the present invention, there is provided an error code analyzer, including the error code analyzing architecture according to the second aspect and the optional aspects of the present invention.
The invention provides a sampling-based error code analysis method, an error code analysis architecture and an error code analyzer. Acquiring the transmission rate of the transmission data, corresponding to different working modes according to different transmission rates, and carrying out error code analysis on the transmission data according to different working modes; the faster the transmission rate is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; by the technical scheme, error code analysis is carried out on the transmission data with high transmission rate by using low analysis rate.
Drawings
The invention will be described in further detail with reference to the drawings and the detailed description.
FIG. 1 is a flowchart illustrating a sample-based error analysis method according to an embodiment of the present invention;
FIG. 2 is a second flowchart of a sample-based error analysis method according to an embodiment of the present invention;
FIG. 3 is a block diagram illustrating an architecture for error analysis according to an embodiment of the present invention;
fig. 4 is a block diagram of a second embodiment of an error analysis architecture according to the present invention.
10-a transmission rate acquisition module;
20-an operation mode selection module;
30-sampling unit;
40-an error code analysis module;
41-a signal generation module;
42-a sequence generation unit;
43-a first processing unit;
44-an error counting unit.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
In a brief description of the design concept of the present invention, brief additions are made to the design background of the present invention:
bit error rate is defined as the proportion of the number of erroneously received symbols in the total number of transmitted symbols, i.e. the probability that a symbol is transmitted in the transmission system. The bit error rate, also called bit error rate, is defined as the proportion of the amount of information received in error in the total amount of transmitted information, i.e., the probability that the amount of information of a symbol is lost in the transmission system. And the information amount carried by each code element is expressed as follows:
i=log2m: wherein I is used to characterize the amount of information carried by each symbol, and M is used to characterize the system.
The bit error rate is thus equal to the bit error rate in binary communication systems, but will be greater in other binary communication systems.
In a binary communication system, the detection of the error rate is a common measure for measuring the ability of the communication system to correctly transmit bit data, and the method comprises the following steps: and sending a known bit sequence to the device to be tested, acquiring the transmitted data at the output end of the device to be tested, analyzing the number of erroneous bits in the transmitted data, and dividing the number of erroneous bits by the total number of bits in the data to obtain the error rate of the data transmitted by the device to be tested. The lower the error rate of a transmitting device, the higher the transmission reliability thereof. The bit sequences used for performing the error rate test, i.e., the transmission data mentioned below in the present invention, are all Pseudo random binary sequences (Pseudo-Random Binary Sequence, PRBS). The difference compared to a truly random binary sequence is that the pseudo-random binary sequence is periodically repeated, only in one period the sequence is random and the sequence of each period is fully repeated. Wherein the number of n-order pseudo random binary numbers in a period is 2 (n-1) to the power; for example, the sequence of 3 rd order pseudo random binary numbers in one period is 0100111. The generator of the n-order pseudo-random binary sequence comprises a cyclic shift register formed by n D flip-flops and an exclusive OR gate; for example, the 3-order pseudo-random binary number comprises 3D flip-flops and an exclusive OR gate, and the generation formula of the sequence is 1+X2+X3; wherein the meaning of the formula is: and performing exclusive OR on the binary number output by the second bit D trigger and the binary number output by the third bit D trigger, wherein the exclusive OR result is used as the input of the first bit D trigger.
Before explaining the embodiments of the present invention, a brief explanation of the design idea of the present invention is given:
the analysis rate of the error code analyzer is usually 20Gbps-25Gbps, but the current data transmission rate can generally reach 80Gbps or higher. In order to enable the error code analyzer to perform error code analysis on the transmission data with high transmission rate, the prior art adopts an expensive high-speed demultiplexer to demultiplex the transmission rate of the transmission data to below 25Gbps, but this increases the cost of error code analysis and may introduce additional data jitter. Here, the data jitter refers to the leading or trailing edge of the transmission data as compared to the standard signal. The basic idea of error code analysis for high transmission rate transmission data is to reduce the transmission rate of transmission data, but in order not to increase the analysis cost, the invention does not adjust the transmission rate of transmission data, but samples the transmission data, for example, the transmission rate of transmission data is 80Gbps, the upper limit of the analysis rate of error code analyzer is 25Gbps, and then samples the transmission data at intervals of 4 times of cycles are performed, so that the analysis rate of error code analyzer is improved to 100Gbps. Meanwhile, according to the samplings of the discrete sequence, as long as the sampling interval is the power of 2 of the initial period, the sampled data can be equal to the transmission data, and the technical scheme can be used for carrying out error code analysis on the transmission data with high transmission rate at low analysis rate.
Referring to fig. 1, an embodiment of the present invention provides a sampling-based error analysis method for detecting a bit error rate of transmission data; the method comprises the following steps:
s1: acquiring a transmission rate of transmission data;
s2: selecting a corresponding working mode according to the obtained transmission rate to sample the transmission data to obtain sampling data; the faster the transmission rate is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1;
s3: and carrying out error code analysis on the obtained sampling data.
According to the embodiment of the invention, through the technical scheme, the error code analysis of the transmission data with the low analysis rate and the high transmission rate is realized. The principle is as follows:
determining a corresponding working mode according to the transmission rate of the acquired transmission data, and sampling the transmission data according to the acquired transmission data to obtain sampling data; and the faster the transmission rate is,the sampling bit interval of the corresponding working mode is larger, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first working mode to the N-th working mode adjacent working mode i Multiple times, so that the high-speed transmission data can be replaced by 2-fold reduction i A sample rate of the multiple rate; meanwhile, according to the samplings of the discrete sequence, as long as the sampling interval is the power of 2 of the initial period, the sampled data can be equal to the transmission data so as to ensure the reliability of error code analysis.
As an alternative to the use of a single-piece carrier,
and S2, selecting a corresponding working mode according to the obtained transmission rate to sample the transmission data to obtain sampled data, wherein the method specifically comprises the following steps of: generating a first signal and a phase discrimination signal according to the selected working mode; sampling the transmission data according to the first signal and the phase discrimination signal; wherein the phase-discrimination signal is used for discriminating jitter of the transmission data; jitter of the transmitted data is used to characterize rising or falling edges of the transmitted data as leading or lagging relative to a standard signal. The first signal is used as a sampling signal for sampling the transmission data and is also used as a clock signal for carrying out error code analysis on the sampling data.
The faster the transmission rate in S2, the larger the sampling bit interval of the corresponding working mode, which specifically includes: setting the basic analysis rate as nGbps, and if the transmission rate of the transmission data is 3nGbps, selecting the sampling bit interval of the working module to be at least 4 times of the initial sampling bit interval; if the transmission rate of the transmission data is 5nGbps, the sampling bit interval of the selection work module is at least 8 times of the initial sampling bit interval.
In S2, the sampling bit interval of the transmission data is sequentially increased by 2 from the first working mode to the N working mode i The method specifically comprises the following steps: the sampling bit interval of the transmission data from the first working mode to the Nth working mode can be increased by 2 times in sequence or increased by 4 times in sequence; or the sampling bit interval from the first working mode to the second working mode is increased by 2 times, and the second working mode to the third working moduleThe sampling bit interval is increased by 4 times; therefore, the increase times of the sampling bit intervals of the transmission data from the first working module to the nth working mode can be adjusted according to actual requirements, and the method is not limited herein.
Referring to fig. 2, as a specific embodiment, S3 performs error analysis on the obtained sampled data, and specifically includes:
s31: and carrying out sequence regeneration on the sampling data according to the first signal so as to obtain a first sequence.
S32: and carrying out first processing on the sampling data and the first sequence, and outputting a second sequence.
S33: and calculating the error rate of the sampled data according to the second sequence.
As a specific embodiment, the step S31 of performing the sequence reproduction on the sampled data specifically includes: reproducing the sampled data; if the sampling data have no error code, the first sequence obtained by reproduction is consistent with the sampling data; if the sampling data has error codes, the data of the first sequence at the position of the error codes of the sampling data is opposite to the sampling data; for example: a string of the sample data should originally be 1011, but because the occurrence of an error code becomes 1010, the string of sample data becomes 1011 after reproduction.
As a specific embodiment, the step S32 of performing a first process on the sample data and the first sequence and the step S33 of calculating the error rate of the sample data according to the second sequence specifically includes: the sampling data and the first sequence are subjected to the same OR so as to obtain a second sequence; if the sampling data has error codes, the sampling data and the first sequence are different data with opposite levels at the position where the error codes occur, and the data at other positions are the same. Therefore, the second sequence obtained by combining the sample data with the first sequence is low at the position where the error code of the sample data occurs and high at other positions. Therefore, the error rate of the sampled data can be obtained by calculating the proportion of the low level bit number in the second sequence to the whole bit number of the second sequence. Also because of the samplings of the discrete sequences, the error rate of the sampled data may represent the error rate of the transmitted data to obtain the error rate of the transmitted data.
As a specific embodiment, the step S32 of performing a first process on the sample data and the first sequence and the step S33 of calculating the error rate of the sample data according to the second sequence specifically includes: exclusive-or the sampled data with the first sequence to obtain a second sequence; if the sampling data has error codes, the sampling data and the first sequence are different data with opposite levels at the position where the error codes occur, and the data at other positions are the same. Therefore, the second sequence obtained by exclusive-or of the sample data and the first sequence will be at a high level at the position where the error code of the sample data occurs and at a low level at other positions. Therefore, the error rate of the sampled data can be obtained by calculating the proportion of the high level bit number in the second sequence to the whole bit number of the second sequence. Also because of the samplings of the discrete sequences, the error rate of the sampled data may represent the error rate of the transmitted data to obtain the error rate of the transmitted data.
Referring to fig. 3, an embodiment of the present invention further provides an error code analysis structure for implementing the sample-based error code analysis method provided by the embodiment of the present invention, where the error code analyzer includes:
a transmission rate acquisition module 10 for acquiring a transmission rate of transmission data;
an operation mode selection module 20, configured to select a corresponding operation mode according to the obtained transmission rate; the higher the transmission rate of the transmission data is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1;
a sampling unit 30, configured to sample the transmission data according to the selected operation mode, so as to obtain sampled data;
and the error code analysis module 40 is configured to perform error code analysis on the transmission data according to the sampled data.
The transmission rate acquisition module 10 and the operation mode selection module 20 in the embodiment of the present invention are specifically described below:
as a specific embodiment, the transmission rate obtaining module 10 and the operation mode selecting module 20 may specifically include a computer, and may also be other digital processing chips; for example: MCU, etc., are not limited herein. The N working modes are all set in advance and stored in a register, the transmission rate of the transmission data is determined by frequency discrimination of the transmission data, and a proper working mode is selected according to the transmission rate; for example, the upper limit of the analysis rate of the error code analysis module 40 is 25Gbps; if the transmission rate of the transmission data is between 25Gbps and 50Gbps, the sampling bit interval of the selected working mode is at least 2 times of the initial sampling bit interval, and of course, the working mode that the sampling bit interval is 2 times greater than the initial sampling bit interval can be selected, which is not limited herein; if the transmission rate of the transmission data is between 50Gbps and 100Gbps, the sampling bit interval of the selected working mode is at least 4 times of the initial sampling bit interval, and of course, the working mode that the sampling bit interval is 4 times greater than the initial sampling bit interval can be selected, which is not limited herein.
The sampling unit 30 in the embodiment of the present invention is specifically described below:
in one embodiment, the sampling unit 30 is disposed between the input of the transmission data and the error analysis module 40. The sampling unit 30 is specifically a controlled single pole single throw switch, and the working principle thereof is as follows: corresponding on and off according to the selected operation mode, for example: the sampling bit interval of the selected mode of operation is 2 times the initial sampling bit interval, then the single pole single throw switch is turned on once every 2 times the initial sampling bit interval to sample the transmission data and turned off during the interval.
The error analysis module 40 in the embodiment of the present invention is specifically described below:
referring to fig. 4, as a specific embodiment, the error code analysis module 40 includes a signal generation module 41; the signal generating module 41 is configured to generate a first signal and a phase discrimination signal according to the selected operation mode;
the sampling unit 30 is configured to sample the transmission data according to the first signal and the phase-discriminating signal, so as to obtain sampled data; wherein the phase-discrimination signal is used for discriminating jitter of the transmission data; jitter of the transmitted data is used to characterize rising or falling edges of the transmitted data as leading or lagging relative to a standard signal. The signal generating module 41 is specifically a clock recovery module, also called CDR, and functions as: and extracting clock information embedded in the transmission data according to the selected working mode to generate the first signal. However, since the transmission data is random binary data, no spectral line containing the data rate exists, that is, no direct information required for clock extraction is needed, the CDR generally adopts an edge detection technique to extract the clock information of the transmission data; also, in order to determine the clock phase of the first signal, the CDR must also have a phase error detection circuit to discriminate jitter of the transmitted data. The specific structure and the corresponding working principle of the CDR are conventional technical means in the art, and are not described herein.
Referring to fig. 4, as an embodiment, the error analysis module 40 further includes:
a sequence generation unit 42 coupled to the signal generation unit and the sampling unit 30, respectively; the sequence generating unit 42 is configured to perform sequence regeneration on the sampled data according to the first signal, and output a first sequence; the sequence generating unit 42 is specifically a PRBS reproducing unit, and its specific structure corresponds to the generator of the transmission data, so as to reproduce the correct sample data. The principle of operation of the PRBS regeneration unit is common knowledge in the art and will not be described in detail here.
A first processing unit 43 coupled to the sequence generation unit 42 and the sampling unit 30, respectively; the first processing unit 43 is configured to perform a first process on the sample data and the first sequence, and output a second sequence; wherein the sampled data, the first sequence, and the second sequence are all used to characterize a binary digital signal; wherein, if the first process is an exclusive nor, the first processing unit 43 is an exclusive nor; if the first process is an exclusive OR, the first processing unit 43 is an exclusive OR gate
A false signal counting unit 44 coupled to the first processing unit 43; the error counting unit 44 is configured to calculate an error rate of the sampled data according to the second sequence; the error rate of the sampled data is used for representing the error rate of the transmission data. If the first processing unit 43 is an exclusive or gate, the error counting unit 44 is configured to divide the number of bits of the high level in the second sequence by the number of bits of the whole second sequence, so as to obtain the error rate of the sampled data. If the first processing unit 43 is an exclusive or gate, the error count unit 44 is configured to divide the number of low-level bits in the second sequence by the number of whole bits in the second sequence, so as to obtain the error rate of the sampled data.
The embodiment of the invention also provides an error code analyzer, which comprises the error code analysis framework provided by the embodiment of the invention.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.
Claims (15)
1. A bit error analysis method based on sampling is used for detecting the bit error rate of transmission data; wherein the transmission data is a binary digital signal, the method comprising:
acquiring a transmission rate of transmission data;
selecting a corresponding working mode according to the obtained transmission rate to sample the transmission data to obtain sampling data; the faster the transmission rate is, the larger the sampling bit interval of the corresponding working mode is; wherein the operation modes comprise N operation modes, and the sampling bit interval of the transmission data is sequentially increased by 2 from the first operation mode to the N operation mode i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1;
and carrying out error code analysis on the obtained sampling data.
2. The sample-based error analysis method of claim 1, wherein selecting a corresponding operating mode to sample the transmission data comprises:
generating a first signal and a phase discrimination signal according to the selected working mode;
sampling the transmission data according to the first signal and the phase discrimination signal; wherein the phase-discrimination signal is used for discriminating jitter of the transmission data; jitter of the transmitted data is used to characterize rising or falling edges of the transmitted data as leading or lagging relative to a standard signal.
3. The sample-based error analysis method of claim 2, wherein the error analysis is performed on the obtained sample data, and specifically comprises:
according to the first signal, carrying out sequence regeneration on the sampling data to obtain a first sequence;
performing first processing on the sampling data and the first sequence, and outputting a second sequence; wherein the sampled data, the first sequence, and the second sequence are all used to characterize a binary digital signal;
calculating the error rate of the sampled data according to the second sequence; the error rate of the sampled data is used for representing the error rate of the transmission data.
4. A sample-based bit error analysis method as claimed in claim 3, wherein the first processing of the sample data and the first sequence comprises: and performing exclusive nor on the sampling data and the first sequence.
5. The sample-based bit error analysis method of claim 4, wherein calculating the bit error rate of the sample data based on the second sequence comprises:
dividing the low level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
6. A sample-based bit error analysis method as claimed in claim 3, wherein the first processing of the sample data and the first sequence comprises: exclusive or is performed on the sampled data and the first sequence.
7. The sample-based bit error analysis method of claim 6, wherein calculating the bit error rate of the sample data based on the second sequence comprises:
dividing the high level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
8. An error analysis architecture for implementing the sample-based error analysis method of any one of claims 1 to 7, the error analyzer comprising:
the transmission rate acquisition module is used for acquiring the transmission rate of the transmission data;
the working mode selection module is used for selecting a corresponding working mode according to the obtained transmission rate; the higher the transmission rate of the transmission data is, the larger the sampling bit interval of the corresponding working mode is; wherein the working modes comprise N working modes, from a first working mode to a second working modeSequentially increasing the sampling bit interval of the transmission data by 2 in N working modes i Doubling; wherein N is a positive integer, and N is more than 1; i is a positive integer, and i is more than or equal to 1;
the sampling unit is used for sampling the transmission data according to the selected working mode to obtain sampling data;
and the error code analysis module is used for carrying out error code analysis on the transmission data according to the sampling data.
9. The architecture of claim 8, wherein the error analysis module comprises a signal generation module; the signal generation module is used for generating a first signal and a phase discrimination signal according to the selected working mode;
the sampling unit is used for sampling the transmission data according to the first signal and the phase discrimination signal to obtain sampling data; wherein the phase-discrimination signal is used for discriminating jitter of the transmission data; jitter of the transmitted data is used to characterize rising or falling edges of the transmitted data as leading or lagging relative to a standard signal.
10. The bit error analysis architecture of claim 9, wherein the bit error analysis module further comprises:
a sequence generation unit coupled to the signal generation unit and the sampling unit, respectively; the sequence generating unit is used for carrying out sequence regeneration on the sampling data according to the first signal and outputting a first sequence;
a first processing unit coupled to the sequence generation unit and the sampling unit, respectively; the first processing unit is used for performing first processing on the sampling data and the first sequence and outputting a second sequence; wherein the sampled data, the first sequence, and the second sequence are all used to characterize a binary digital signal;
the error signal counting unit is coupled to the first processing unit; the error counting unit is used for calculating the error rate of the sampling data according to the second sequence; the error rate of the sampled data is used for representing the error rate of the transmission data.
11. The architecture of claim 10, wherein the first processing unit is configured to perform a first process on the sampled data and the first sequence, specifically: the first processing unit is configured to nor the sample data and the first sequence.
12. The architecture of claim 11, wherein the error count unit is configured to calculate, according to the second sequence, an error rate of the sampled data, specifically:
the error counting unit is used for dividing the high-level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
13. The architecture of claim 10, wherein the first processing unit is configured to perform a first process on the sampled data and the first sequence, specifically: the first processing unit is configured to exclusive-or the sampled data with the first sequence.
14. The architecture of claim 13, wherein the error count unit is configured to calculate, according to the second sequence, an error rate of the sampled data, specifically:
the error counting unit is used for dividing the low-level bit number in the second sequence by the whole bit number of the second sequence to obtain the error rate of the sampled data.
15. An error code analyzer comprising the error code analysis architecture of any of claims 8-14.
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