CN116827313A - Digital circuit delay unit, delay circuit, chip and control method - Google Patents
Digital circuit delay unit, delay circuit, chip and control method Download PDFInfo
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- CN116827313A CN116827313A CN202310766447.9A CN202310766447A CN116827313A CN 116827313 A CN116827313 A CN 116827313A CN 202310766447 A CN202310766447 A CN 202310766447A CN 116827313 A CN116827313 A CN 116827313A
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Abstract
The application provides a digital circuit delay unit, which is externally provided with a first input interface, a second input interface, a first output interface, a second output interface and an enabling signal interface, wherein a buffer and a data selector are arranged in the delay unit; the first input interface is connected with the input end of the buffer in an inscription manner, and the output end of the buffer is respectively connected to the first input end of the data selector and the first output interface; the second input interface is connected with a second input end of the data selector in an inscription manner, and an output end of the data selector is connected to the second output interface; the enabling signal interface is connected with the enabling end of the data selector in an inscription mode. The application provides a novel delay unit structure, which can ensure the accurate control of delay and realize delay control by connecting any number of delay units in series without causing delay difference except the delay units.
Description
Technical Field
The present application relates to the field of digital circuits, and in particular, to a digital circuit delay unit, a delay circuit, a chip, and a control method.
Background
In some higher speed serial SPI, SDIO, etc. communication protocols, the slave uses the clock sent by the host as drive data to the host, which then samples the input data with an on-chip version of the drive clock. As shown in fig. 1, since the clock is output from the host register, passes through the buffer, then passes through the host package, the host output pin, the PCB trace, the slave input pin, passes through the slave buffer, and finally drives the slave register to output the return data, the return data passes through the buffer, the slave package, the slave output pin, the PCB trace, the host input pin, the host package, and the host buffer, and finally is sampled by the host register.
The sampling clock of the host register and the output clock of the host are one clock, but the path of the host output clock and the return data is long, so that the time is very long, and the delay of the host sampling clock in the host is relatively small, so that the sampling time is wrong. This requires the ability to adjust the position of the host sampling clock to ensure that the sampling is correct. As shown in fig. 2, the clock a is an internal clock of the host, the slave sees a delayed clock B after outputting data from the clock edge of the slave B, and the host sees data C. In this example, with DDR mode transmitting data, A samples the data at the down dashed arrow, but because the delay of C is greater than half a period of A, the sampled data is corrupted. The solid arrow down is the clock edge sampling delayed using a. Since C has returned and stabilized at this point, the sampling is correct.
Therefore, how to realize accurate delay control is a very critical part, and the delay mode is shown in fig. 3, and each buffer buf is set to be a manually exemplified device with the same size, so that the delay error is only dependent on process, voltage and temperature deviation when the layout and wiring are performed, but the delay of the data selector MUX has two significant disadvantages: (1) If there are many bufs to choose, the circuitry of the MUX is very large, resulting in a significant base delay time, which cannot be achieved if a value less than this is required. (2) If the MUX circuit structure and its layout are not carefully controlled, the delay differences from the MUX inputs to the outputs can be significant. For example, FIG. 4 is a 4-input MUX, X1 through Y pass through 3 MUXs, and X4 through Y only need to pass through one MUX, which causes a delay of 3 bufs more for X4, and the initial purpose of the delayed value of the circuit is controlled by only bufs, all of the input to output delays of the MUX circuit being the same. If not carefully controlled, this is not possible.
Disclosure of Invention
Aiming at the problems existing in the prior art, a digital circuit delay unit, a delay circuit, a chip and a control method are provided, and the step precision of delay can be remarkably improved by providing a novel delay unit structure and a control method.
The first aspect of the present application proposes a digital circuit delay unit, wherein a first input interface, a second input interface, a first output interface, a second output interface and an enabling signal interface are provided outside the delay unit, and a buffer and a data selector are provided inside the delay unit; the first input interface is connected with the input end of the buffer in an inscription manner, and the output end of the buffer is respectively connected to the first input end of the data selector and the first output interface; the second input interface is connected with a second input end of the data selector in an inscription manner, and an output end of the data selector is connected to the second output interface; the enabling signal interface is connected with the enabling end of the data selector in an inscription mode.
As a preferable scheme, the data selector selects data input by different input ends according to the enabling signal to output, and when the enabling signal is 0, the data of the first input end is output; when the enable signal is 1, data of the second input terminal is output.
As a preferred solution, the buffer and the data selector have a fixed delay, and the delay of each delay unit is the sum of the delays of the buffer and the data selector.
As a preferred solution, the delay unit can be made as a hard core, facilitating delay control.
The second aspect of the present application provides a delay circuit using the above digital circuit delay units, including N digital circuit delay units connected in series, wherein a first output terminal of each digital circuit delay unit is connected to a first input terminal of a next digital circuit delay unit, and a second input terminal of each digital circuit delay unit is connected to a second output terminal of the next digital circuit delay unit; the final digital circuit delay cell enables a signal input of 0.
As a preferable scheme, the delay circuit correspondingly controls each delay unit through a plurality of enabling signals so as to complete delay control of the whole delay unit.
The third aspect of the present application provides a chip based on the delay circuit, wherein the delay circuit formed by N series digital circuit delay units is packaged as a chip, and delay control is realized by control of an enable signal.
The fourth aspect of the present application provides a delay control method based on the above delay circuit, wherein the delay control of the delay circuit is completed by the effective value of the N-bit binary enable signal.
Compared with the prior art, the beneficial effects of adopting the technical scheme are as follows: the application provides a novel delay unit structure, which can ensure the accurate control of delay and realize delay control by connecting any number of delay units in series without causing delay difference except the delay units.
Drawings
Fig. 1 is a schematic diagram of data transmission in a master-slave communication protocol in the prior art.
Fig. 2 is a schematic diagram of data sampling in a master-slave communication protocol according to the prior art.
Fig. 3 is a schematic diagram of a delay structure in the prior art.
Fig. 4 is a schematic diagram of another delay structure in the prior art.
Fig. 5 is a schematic diagram of a delay unit of a digital circuit according to the present application.
FIG. 6 is a schematic diagram of a delay circuit in an embodiment of the application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar modules or modules having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application. On the contrary, the embodiments of the application include all alternatives, modifications and equivalents as may be included within the spirit and scope of the appended claims.
In order to realize accurate control of delay, the embodiment of the application provides a digital circuit delay unit, which can avoid larger basic delay and can control delay step length more accurately by selecting fixed devices and circuits without being influenced by a data selector. The specific scheme is as follows:
as shown in fig. 5, a digital circuit delay unit is provided with a first input interface, a second input interface, a first output interface, a second output interface and an enable signal interface, and a buffer and a data selector are arranged inside the delay unit; the first input interface is connected with the input end of the buffer in an inscription manner, and the output end of the buffer is respectively connected to the first input end of the data selector and the first output interface; the second input interface is connected with a second input end of the data selector in an inscription manner, and an output end of the data selector is connected to the second output interface; the enabling signal interface is connected with the enabling end of the data selector in an inscription mode.
In practical application, the data selector selects data input by different input ends according to the enabling signal to output, and when the enabling signal is 0, the data of the first input end is output; when the enable signal is 1, data of the second input terminal is output.
Taking the delay cell (DLC) shown in fig. 5 as an example, if the enable signal EN is 1, the path 1 is closed, the signal enters from the port SI, is output from the port si_o, delays by one buffer buf, is input from the port so_i again, and delays by one data selector mux again, the total delay is a fixed delay of one buffer buf and one data selector mux.
If the enable signal EN is 0, path 1 is on, the delay loops back at the delay cell DLC, the latter delay cell does not participate in the delay, the DLC increasing the delay to a fixed delay of one buffer buf and one data selector mux.
In this embodiment, the delay is fixed after the buffer and the data selector are selected.
Based on the delay unit, a plurality of delay units are connected in series, any required delay can be obtained, and the increase of the delay does not cause the change of a circuit structure and the change of a circuit load, so that the delay does not cause extra uncontrollable difference due to the change of a delay unit DLC.
The corresponding embodiment provides a delay circuit applying the digital circuit delay units, which comprises N digital circuit delay units connected in series, wherein a first output end of each digital circuit delay unit is connected to a first input end of a next data circuit delay unit, and a second input end of each digital circuit delay unit is connected to a second output end of the next data circuit delay unit; in general, the enable signal input to the final stage digital circuit delay cell is 0, and the first and second inputs of the final stage delay cell are floating.
The delay circuit correspondingly controls each delay unit through a plurality of enabling signals so as to complete delay control of the whole delay unit. In practical application, the effective value of the N-bit binary enable signal can be directly adopted to complete delay control of the delay circuit. The delay of the delay circuit is that N is the fixed delay of the corresponding number of delay units of the first 0 from right to left in the effective value of the binary enable signal.
In practical application, each delay unit can be made into a hard core, made into a hard IP, and has a fixed shape, and directly cascaded according to the number of stages required by the requirement.
The following describes a delay circuit control manner proposed by the present application with a specific delay circuit example:
referring to fig. 6, a delay circuit formed by serially connecting 4 delay cells DLC, in which if the effective value of the enable signal EN is 0111b, it means that three delay cells DLC0, DLC1 and DLC2 are serially connected to the delay cells before and after, and DLC3 is looped back at the selector, so that a total of 4 DLC are effective, and the delay value is 4 DLC. After the delay unit DLC is made into a hard core, the delay unit DLC is placed in sequence through careful layout and wiring, and delay control can be very accurate.
According to the delay unit, the delay can be accurately controlled, and delay control can be realized through serial connection of any number of delay units, so that delay difference except the delay units is avoided.
Example 1
The embodiment provides a digital circuit delay unit, wherein a first input interface, a second input interface, a first output interface, a second output interface and an enabling signal interface are arranged outside the delay unit, and a buffer and a data selector are arranged inside the delay unit; the first input interface is connected with the input end of the buffer in an inscription manner, and the output end of the buffer is respectively connected to the first input end of the data selector and the first output interface; the second input interface is connected with a second input end of the data selector in an inscription manner, and an output end of the data selector is connected to the second output interface; the enabling signal interface is connected with the enabling end of the data selector in an inscription mode.
Example 2
Based on embodiment 1, the data selector in this embodiment selects data input from different input ends according to the enable signal to output, and outputs data of the first input end when the enable signal is 0; when the enable signal is 1, data of the second input terminal is output.
Example 3
On the basis of embodiment 1, the buffer and the data selector have fixed delays in this embodiment, and the delay of each delay unit is the sum of the delays of the buffer and the data selector.
Example 4
On the basis of embodiment 1, the delay unit in this embodiment can be made as a hard core, which facilitates delay control.
Example 5
The present embodiment proposes a delay circuit applying the digital circuit delay unit of embodiment 1, including N serially connected digital circuit delay units, a first output terminal of each digital circuit delay unit being connected to a first input terminal of a next data circuit delay unit, a second input terminal of each digital circuit delay unit being connected to a second output terminal of the next data circuit delay unit; the final digital circuit delay cell enables a signal input of 0.
Example 6
On the basis of embodiment 5, the delay circuit in this embodiment controls each delay unit correspondingly by a plurality of enable signals, thereby completing delay control of the overall delay unit.
Example 7
The present embodiment proposes a chip based on the delay circuit described in embodiment 5, in which the delay circuits formed by N serial digital circuit delay units are packaged as a chip, and delay control is implemented by one enable signal control.
Example 8
The present embodiment proposes a delay control method based on the delay circuit described in embodiment 5, wherein delay control of the delay circuit is completed by the N-bit binary enable signal effective value.
The present application can be preferably realized by the above examples 1 to 8.
It should be noted that, in the description of the embodiments of the present application, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present application will be understood in detail by those skilled in the art; the accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
While embodiments of the present application have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the application, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the application.
Claims (8)
1. A digital circuit delay unit is characterized in that a first input interface, a second input interface, a first output interface, a second output interface and an enabling signal interface are arranged outside the delay unit, and a buffer and a data selector are arranged inside the delay unit; the first input interface is connected with the input end of the buffer in an inscription manner, and the output end of the buffer is respectively connected to the first input end of the data selector and the first output interface; the second input interface is connected with a second input end of the data selector in an inscription manner, and an output end of the data selector is connected to the second output interface; the enabling signal interface is connected with the enabling end of the data selector in an inscription mode.
2. The digital circuit delay unit of claim 1 wherein the data selector selects data input from different input terminals for output according to an enable signal, and outputs data from a first input terminal when the enable signal is 0; when the enable signal is 1, data of the second input terminal is output.
3. A digital circuit delay unit according to claim 1 or 2, wherein the buffer and the data selector have a fixed delay, the delay of each delay unit being the sum of the delays of the buffer and the data selector.
4. The digital circuit delay cell of claim 1 wherein the delay cell can be fabricated as a hard core.
5. A delay circuit employing the digital circuit delay unit of any one of claims 1-4, comprising N serially connected digital circuit delay units, a first output of each digital circuit delay unit being terminated to a first input of a next data circuit delay unit, a second input of each digital circuit delay unit being terminated to a second output of the next data circuit delay unit; the final digital circuit delay cell enables a signal input of 0.
6. The delay circuit of claim 5, wherein the delay circuit controls each delay cell by a plurality of enable signals to perform delay control of the overall delay cell.
7. A chip based on a delay circuit as claimed in any one of claims 5-6, characterized in that the delay circuit formed by N series digital circuit delay cells is packaged as a chip, the delay control being effected by one enable signal control.
8. A delay control method based on a delay circuit as claimed in any one of claims 5-6, characterized in that the delay control of the delay circuit is done by means of an N-bit binary enable signal valid value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310766447.9A CN116827313A (en) | 2023-06-27 | 2023-06-27 | Digital circuit delay unit, delay circuit, chip and control method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310766447.9A CN116827313A (en) | 2023-06-27 | 2023-06-27 | Digital circuit delay unit, delay circuit, chip and control method |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW548659B (en) * | 2000-09-05 | 2003-08-21 | Samsung Electronics Co Ltd | Delay locked loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably |
| CN1941623A (en) * | 2005-09-27 | 2007-04-04 | 三星电子株式会社 | Adjustable delay cells and delay lines including the same |
| JP2007336028A (en) * | 2006-06-13 | 2007-12-27 | Sharp Corp | Variable delay control apparatus |
| CN101325409A (en) * | 2007-06-15 | 2008-12-17 | 联发科技股份有限公司 | Delay circuit and related method for signal thereof |
| CN110224692A (en) * | 2019-07-24 | 2019-09-10 | 电子科技大学 | A kind of high linearity delay chain |
| CN116192102A (en) * | 2022-12-27 | 2023-05-30 | 灿芯半导体(上海)股份有限公司 | Small-area full-digital programmable delay circuit |
-
2023
- 2023-06-27 CN CN202310766447.9A patent/CN116827313A/en not_active Withdrawn
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW548659B (en) * | 2000-09-05 | 2003-08-21 | Samsung Electronics Co Ltd | Delay locked loop circuit for reducing load of variable delay unit at high-frequency operation and locking external clock signal stably |
| CN1941623A (en) * | 2005-09-27 | 2007-04-04 | 三星电子株式会社 | Adjustable delay cells and delay lines including the same |
| JP2007336028A (en) * | 2006-06-13 | 2007-12-27 | Sharp Corp | Variable delay control apparatus |
| CN101325409A (en) * | 2007-06-15 | 2008-12-17 | 联发科技股份有限公司 | Delay circuit and related method for signal thereof |
| CN110224692A (en) * | 2019-07-24 | 2019-09-10 | 电子科技大学 | A kind of high linearity delay chain |
| CN116192102A (en) * | 2022-12-27 | 2023-05-30 | 灿芯半导体(上海)股份有限公司 | Small-area full-digital programmable delay circuit |
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