CN116827308A - Resource optimization type FIR filter and implementation method thereof - Google Patents
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Abstract
The application discloses a source optimization type FIR filter, which comprises: a data delay unit; the data preprocessing unit is used for calculating a data tap mixing variable; a data tap mixture inner product calculation unit for base calculating a data tap mixture multiplication component; a data inner product calculation unit for calculating a data inner product amount; and the summation unit is used for calculating the tap inner integral quantity, calling the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity to sum, and obtaining a filtering result. The application has the beneficial effect of obviously reducing the number of multipliers used for the high-order filter. The implementation method of the FIR filter comprises the steps of performing delay calculation on input data; calculating a data tap mixing variable in real time; calculating the data tap mixed multiplication component in real time; calculating the inner integral quantity of the data in real time; the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity are summed to obtain a filtering result. Has the beneficial effect of obviously reducing the number of multipliers.
Description
Technical Field
The application relates to the technical field of communication technology and filter technology. More particularly, the present application relates to a resource-optimized FIR filter and a method for implementing the same.
Background
Finite length filter (Finite Impulse Response, FIR) is one of the most basic digital filters in digital signal processing systemsThe communication field has wide application, and can be mainly used in the fields of signal filtering, digital predistortion cancellation and the like. As communication bandwidth increases and signal quality requirements increase, the order of FIR filters is also increasing. The time domain expression of the FIR filter isWhere n is the number of samples, h (k) is the tap coefficient of the kth tap of the FIR filter, and y (n) is the nth output sample. The adders and multipliers included in the FIR filter are proportional to the number of taps included therein, and when a large number of taps are included in the FIR filter, the large number of multipliers and adders are included therein, so that the size of the FIR filter becomes large and the power consumption and cost are also high. In complex communication systems, multiple higher order FIR filters are required, which is costly to implement logically. The FIR filters have different concerns in terms of area, power consumption and speed in different scenarios. High performance scenarios require that the FIR can operate at very high operating rates, while hand-held terminal oriented scenarios require less area and power consumption. Logic implementation optimization for FIR filters in different scenarios is a challenging task. Therefore, for the scenario of using a higher order FIR filter for area and rate sensitive applications, such as a digital filter in a communication chip, a resource-optimized FIR filter is contemplated, reducing the number of multipliers used, and thus reducing the consumed logic resources.
Disclosure of Invention
It is an object of the present application to solve at least the above problems and to provide at least the advantages to be described later.
To achieve these objects and other advantages and in accordance with the purpose of the application, there is provided a resource-optimized FIR filter comprising:
a data delay unit for performing delay calculation on the input data to obtain real-time delay dataa 0 ~a M Andb 0 ~b 3 ；
a data preprocessing unit for delaying data based on real timea 0 ~a M And the filter tap coefficient is calculated in real time to obtain a data tap mixing variable;
a data tap mixture inner product calculation unit for calculating in real time based on the data tap mixture variable to obtain a data tap mixture multiplication component;
a data inner product calculation unit for delaying data based on real timeb 0 ~b 3 Calculating in real time to obtain the data inner integral quantity;
and the summing unit is used for calculating based on the tap coefficient of the filter to obtain the tap inner integral quantity, storing the tap inner integral quantity, calling the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity to sum, and performing bit width processing to obtain the output data of the FIR filter.
Preferably, the data is delayed in real timea 0 ~a M Andb 0 ~b 3 the generation rule of (2) is shown in formula 1:
equation 1
Wherein, x n() representation ofnInput data of time; when the filter orderNWhen the number is odd, thenM=N+1, and tap coefficienth M =0; when the filter orderNWhen the number is even, thenM=N。
Preferably, the calculation method of the data tap mixing variable is as shown in formula 2:
equation 2
Wherein, hrepresenting the tap coefficients of the filter.
Preferably, the calculation method of the data inner integral quantity, the data tap mixture multiplication component and the tap inner integral quantity is as shown in formula 3:
equation 3
Wherein, d xx representing the amount of data inner integration;d xh representing the data tap mix multiplied component;d hh representing the amount of intra-tap integration.
Preferably, when the data tap mixed inner product calculating unit and the data inner product calculating unit perform multiplication operation, the method further comprises a pre-coding sub-module, which is used for coding, calculating partial products and mapping each string of data by adopting a base 4 booth coding method, wherein the coding, calculating partial products and mapping methods are respectively shown in a formula 4 and a formula 5:
equation 4
Wherein, X i 、2X i 、Miall represent the result of the pre-coding, indexiIs determined by the bit width of the input data;
equation 5
Wherein, Y xi representing a single partial product;Y 2xi representing a double partial product;PPT i representing the partial product mapping result;e i representation ofPP i Is a symbol of (c).
Preferably, when the data tap mixed inner product calculating unit and the data inner product calculating unit perform multiplication operation, the data tap mixed inner product calculating unit further includes a compressing submodule, configured to compress and sum partial products output by the pre-coding submodule, as shown in formula 6:
equation 6
Wherein 4 data are input at a timeD 1 、D 2 、D 3 、D 4 Conversion to intermediate variablesTP 1 ~TP 7 。。
The implementation method of the resource optimization type FIR filter comprises the following steps:
step one, carrying out delay calculation on input data to obtain real-time delay dataa 0 ~a M Andb 0 ~b 3 ；
step two, based on real-time delay dataa 0 ~a M And the filter tap coefficient is calculated in real time to obtain a data tap mixing variable;
step three, calculating in real time based on the data tap mixing variable to obtain a data tap mixing multiplication component;
step four, based on real-time delay datab 0 ~b 3 Calculating in real time to obtain the data inner integral quantity;
and fifthly, calculating based on the tap coefficient of the filter to obtain a tap inner integral quantity, and summing based on the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity to obtain output data of the FIR filter.
There is provided an electronic device including: the system comprises at least one processor, and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor, the instructions being executable by the at least one processor to cause the at least one processor to perform the method of claim.
There is provided a storage medium having stored thereon a computer program which, when executed by a processor, implements the method of claim.
The application at least comprises the following beneficial effects:
first, the application reduces the number of multipliers required to be used by optimizing the FIR filter structure, specifically, modifies the original convolution summation into the data inner integral quantity, the data tap mixed multiplication component and the tap inner integral quantity by reconstructing the filter inner product. And taking the fact that the tap is fixed into consideration, storing the tap inner integral quantity in advance, and calculating the data inner integral quantity and the data tap mixed multiplication quantity in real time so as to calculate the filter output.
Secondly, aiming at the reconstructed FIR filter structure, the number of partial integral is reduced through partial integral pre-coding, and the logic delay of an addition array is reduced through compression coding, so that the operation efficiency of multiplication and addition logic is improved.
Additional advantages, objects, and features of the application will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the application.
Drawings
Fig. 1 is a schematic diagram of a connection structure of unit modules of a filter according to the present application;
FIG. 2 is a block diagram of an implementation in an embodiment of a data delay unit of the present application;
FIG. 3 is a diagram illustrating an implementation of a data preprocessing unit according to an embodiment of the present application;
FIG. 4 is a block diagram of an implementation in an embodiment of a data tap hybrid inner product calculation unit of the present application;
FIG. 5 is a block diagram of an implementation in an embodiment of the module 3-1 of the present application;
FIG. 6 is a block diagram of an implementation in an embodiment of the module 3-1-1 of the present application;
FIG. 7 is a block diagram of an implementation in an embodiment of the module 3-2 of the present application;
FIG. 8 is a block diagram of an implementation in an embodiment of the module 3-2-1 of the present application;
FIG. 9 is a block diagram of an implementation in an embodiment of the module 3-2-2 of the present application;
FIG. 10 is a diagram showing an implementation of the data inner product calculation unit according to the embodiment of the present application;
FIG. 11 is a block diagram of an implementation in an embodiment of the module 4-2 of the present application;
FIG. 12 is a block diagram of an implementation in an embodiment of the module 4-3 of the present application;
fig. 13 is a block diagram of an implementation in an embodiment of the summing unit of the application.
Detailed Description
The present application is described in further detail below with reference to the drawings to enable those skilled in the art to practice the application by referring to the description.
It should be noted that the experimental methods described in the following embodiments, unless otherwise specified, are all conventional methods, and the reagents and materials, unless otherwise specified, are all commercially available; in the description of the present application, the orientation or positional relationship indicated by the terms are based on the orientation or positional relationship shown in the drawings, are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
< example >
By filter orderNFor 19, 20, the input data and filter taps are each illustrated as 16-bit fixed-point complex numbers. As shown in fig. 1 to 13, a module 1 is a data delay unit; the module 2 is a data preprocessing unit; the module 3 is a data tap mixed inner product calculation unit; module 4 is a data inner product calculation unit; the module 5 is a sum unit.
As shown in fig. 1 to 13, the resource-optimized FIR filter of the present application includes:
the data delay unit receives the input data, delays the input data, outputs a first output result,a 0 、a 1 、…、a 18 、a 19 (total 20 data) and second output resultb 0 、b 1 、b 2 、b 3 (4 data in total), the data delay unit is shown in fig. 2, wherein,
equation 1
x n() Representation ofnInput data of time; when the filter order N is odd, letM=N+1, and tap coefficienth M =0; when the filter orderNWhen the number is even, thenM=N。
The data preprocessing unit receives the data delay unita 0 、a 1 、…、a 18 、a 19 And filter tap coefficientsh 0 、h 1 、…、h 18 、h 19 As input, outputc 0 、c 1 、…、c 18 、c 19 The data preprocessing unit structure is shown in fig. 3, the generation rule is shown in formula 2,
equation 2
The data tap mixed inner product calculation unit receives the data preprocessing unitc 0 、c 1 、…、c 18 、c 19 As input, 2×160 partial product generation is implemented by using 2×20 modules 3-1, and 160 partial product summation is implemented by 2 modules 3-2 respectively, so as to obtain a fourth output resultd xh ：
d xh Representing the data tap mix multiplied components.
If it isN=19, then direct commandh 19 And=0. The data tap mixture inner product calculation unit is shown in fig. 4.
In particular, the method comprises the steps of,
each module 3-1 converts the multiplication calculation (X Y) into 8 partial products using the booth coding of base 4PP 0 ~PP 7 ，PP 0 ~PP 7 The sum result of (a) is X Y, and the code mapping process is shown in fig. 5.
Wherein the Booth coding and selection of a single partial product is performed by module 3-1-1, specific coding rules and partial product generation are shown in FIG. 6, the index of FIG. 6i= 0,1,…,7。
The coding formula:
equation 4
Wherein, X i 、2X i 、Miall represent the encoding result of the pre-encoding;
single partial product intermediate variable mapping mode:
equation 5
Wherein, Y xi representing a single partial product;Y 2xi representing a double partial product;PPT i representing the partial product mapping result;e i representation ofPP i Is a symbol of (c).
Finally, makePPT i Representation part mapping intoPP i 。
As shown in fig. 7, the module 3-2 receives 160 partial products, compresses the partial products to 2 data by using the 7-stage module 3-2-1, and sums and truncates the data by using the module 3-2-2 to obtain the fourth output result.
As shown in fig. 8, each module 3-2-1 compresses 4 data to 2 data in the following manner:
equation 6
As shown in FIG. 9, module 3-2-2 first intercepts compressed 2 dataF-2 bits (hereF=15), then the data is divided into a high-order part and a low-order 2-order part, and the mapping relation of the low-order 2-order part is used for determiningadd 1 Andadd 2 finally, the high-order part of 2 input data,add 1 Andadd 2 *2, obtaining a fourth output result (data tap mixed multiplication component). Wherein, add 1 andadd 2 is two marks;add 1 =1, indicating that 1 needs to be added to the calculation result;add 1 =0, meaning that 1 need not be added to the calculation result;add 2 =1, indicating that 2 needs to be added to the calculation result;add 2 =0, meaning that 2 need not be added to the calculation result.
As shown in fig. 10, the data inner product calculation unit receives the second output result of the data delay unitb 0 、b 1 、b 2 、b 3 As input, 2×32 partial product generation is implemented by using the module 3-1, 32 partial product summation is implemented by the 2 modules 4-2, and the fifth output result is obtained by accumulating by the module 4-3:
d xx representing the amount of data inner integration.
In particular, the method comprises the steps of,
as shown in FIG. 11, module 4-2 accepts 32 partial products, compresses them to 2 data using 4-stage module 3-2-1, and sums the truncated bits through module 3-2-2.
As shown in fig. 12, the module 4-3 uses an accumulator with a delay of 2 to accumulate the output of the module 4-2 to obtain the fifth output resultd xx 。
As shown in fig. 13, the summing unit receives the fourth output resultd xh (data tap mix multiplication component), fifth output resultd xx (data inner integral quantity) and filter tap pre-operation resultd hh (tap inner integral quantity), summing and cutting saturation to obtain filtering result.
The filter tap pre-operation result is as follows:
when the filter orderNWhen=19, leth 19 =0。
The original order is made to be by the structural optimization of the filterNThe filter of (2) is required to useNThe current situation of the multipliers is changed into the situation that only the multipliers need to be usedceil(N2) +2) multipliers,ceilthe function representation is rounded towards positive infinity. Namely, for the order 19 and 20 filters of this embodiment, 19 and 20 multipliers are needed, and after the structure of the present application is optimized, only 12 multipliers are needed, and the higher the order is, the more obvious the gain is.
Although embodiments of the present application have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the application would be readily apparent to those skilled in the art, and accordingly, the application is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (9)
1. A resource-optimized FIR filter, characterized by comprising:
a data delay unit for performing delay calculation on the input data to obtain real-time delay dataa 0 ~a M Andb 0 ~b 3 ；
a data preprocessing unit for delaying data based on real timea 0 ~a M And the filter tap coefficient is calculated in real time to obtain a data tap mixing variable;
a data tap mixture inner product calculation unit for calculating in real time based on the data tap mixture variable to obtain a data tap mixture multiplication component;
a data inner product calculation unit for delaying data based on real timeb 0 ~b 3 Calculating in real time to obtain the data inner integral quantity;
and the summing unit is used for calculating based on the tap coefficient of the filter to obtain the tap inner integral quantity, storing the tap inner integral quantity, calling the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity to sum, and performing bit width processing to obtain the output data of the FIR filter.
2. The resource-optimized FIR filter according to claim 1, characterized by delaying data in real timea 0 ~a M Andb 0 ~b 3 the generation rule of (2) is shown in formula 1:
equation 1
Wherein, x n() representation ofnInput data of time; when the filter orderNWhen the number is odd, thenM=N+1, and tap coefficienth M =0; when the filter order N is even, letM=N。
3. The resource optimized FIR filter according to claim 2, wherein the method of calculating the data tap mixing variable is as shown in equation 2:
equation 2
Wherein, hrepresenting the tap coefficients of the filter.
4. The resource optimized FIR filter according to claim 3, wherein the data inner integral quantity, the data tap mix multiplication quantity and the tap inner integral quantity are calculated as shown in formula 3:
equation 3
Wherein, d xx representing the amount of data inner integration;d xh representing the data tap mix multiplied component;d hh representing the amount of intra-tap integration.
5. The resource-optimized FIR filter according to claim 4, further comprising a pre-coding sub-module for coding, partial product calculation and mapping each string of data using a base 4 booth coding method when the data tap hybrid inner product calculation unit and the data inner product calculation unit perform multiplication, wherein the coding, partial product calculation and mapping methods are shown in formula 4 and formula 5, respectively:
equation 4
Wherein, X i 、2X i 、Miall represent the result of the pre-coding, indexiIs determined by the bit width of the input data;
equation 5
Wherein, Y xi representing a single partial product;Y 2xi representing a double partial product;PPT i representing the partial product mapping result;e i representation ofPP i Is a symbol of (c).
6. The resource-optimized FIR filter according to claim 5, further comprising a compression sub-module for compressing and summing partial products outputted from the pre-coding sub-module when the data tap mixed inner product calculation unit and the data inner product calculation unit multiply, as shown in equation 6:
equation 6
Wherein 4 data are input at a timeD 1 、D 2 、D 3 、D 4 Conversion to intermediate variablesTP 1 ~TP 7 。
7. The method for implementing a resource-optimized FIR filter according to any one of claims 1 to 6, comprising the steps of:
step one, carrying out delay calculation on input data to obtain real-time delay dataa 0 ~a M Andb 0 ~b 3 ；
step two, based on real-time delay dataa 0 ~a M And the filter tap coefficient is calculated in real time to obtain a data tap mixing variable;
step three, calculating in real time based on the data tap mixing variable to obtain a data tap mixing multiplication component;
step four, based on real-time delay datab 0 ~b 3 Calculating in real time to obtain the data inner integral quantity;
and fifthly, calculating based on the tap coefficient of the filter to obtain a tap inner integral quantity, and summing based on the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity to obtain output data of the FIR filter.
8. An electronic device, comprising: at least one processor, and a memory communicatively coupled to the at least one processor, wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of claim 7.
9. A storage medium having stored thereon a computer program, which when executed by a processor, implements the implementation method of claim 7.
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