CN116827308A - Resource-optimized FIR filter and its implementation method - Google Patents

Abstract

The application discloses a source optimization type FIR filter, which comprises: a data delay unit; the data preprocessing unit is used for calculating a data tap mixing variable; a data tap mixture inner product calculation unit for base calculating a data tap mixture multiplication component; a data inner product calculation unit for calculating a data inner product amount; and the summation unit is used for calculating the tap inner integral quantity, calling the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity to sum, and obtaining a filtering result. The application has the beneficial effect of obviously reducing the number of multipliers used for the high-order filter. The implementation method of the FIR filter comprises the steps of performing delay calculation on input data; calculating a data tap mixing variable in real time; calculating the data tap mixed multiplication component in real time; calculating the inner integral quantity of the data in real time; the tap inner integral quantity, the data tap mixed multiplication component and the data inner integral quantity are summed to obtain a filtering result. Has the beneficial effect of obviously reducing the number of multipliers.

Description

Resource-optimized FIR filter and its implementation method

Technical field

The invention relates to the fields of communication technology and filter technology. More specifically, the present invention relates to a resource-optimized FIR filter and an implementation method thereof.

Background technique

Finite Impulse Response (FIR) is the most basic digital filter in digital signal processing systems. It is widely used in the field of communications and can be mainly used in signal filtering, digital predistortion cancellation and other fields. With the increase of communication bandwidth and the improvement of signal quality requirements, the order of FIR filter is also gradually increasing. The time domain expression of the FIR filter is , where n is the number of the sample point, h(k) is the tap coefficient of the k-th tap of the FIR filter, and y(n) is the n-th output sample point. The adders and multipliers included in the FIR filter are proportional to the number of taps it includes. When the FIR filter includes a large number of taps, it contains a large number of multipliers and adders, which makes the size of the FIR filter become larger. It is very large and has higher power consumption and cost. In complex communication systems, multiple high-order FIR filters are required, and the cost of logic implementation is high. Different scenarios have different concerns about area, power consumption, and speed of FIR filters. High-performance scenarios require FIR to operate at a very high operating rate, while scenarios for handheld terminals require smaller area and power consumption. Optimizing the logic implementation of FIR filters in different scenarios is a challenging task. Therefore, for scenarios where high-order FIR filters are used in area- and rate-sensitive applications, such as digital filters in communication chips, consider designing a resource-optimized FIR filter to reduce the number of multipliers used, thereby reducing the logic consumed. resource.

Contents of the invention

It is an object of the present invention to solve at least the above-mentioned problems and to provide at least the advantages to be explained later.

In order to achieve these objects and other advantages according to the present invention, a resource-optimized FIR filter is provided, including:

The data delay unit is used to perform delay calculation on the input data to obtain real-time delay data a ₀ ~ a _M and b ₀ ~ b ₃ ;

A data preprocessing unit, which is used for real-time calculation based on real-time delay data a ₀ ~ a _M and filter tap coefficients to obtain data tap mixing variables;

The data tap mixing inner product calculation unit is used for real-time calculation based on the data tap mixing variable to obtain the data tap mixing multiplication component;

The data inner product calculation unit is used for real-time calculation based on the real-time delay data b ₀ ~ b ₃ to obtain the data inner product amount;

The summation unit is used to calculate the tap coefficient based on the filter, obtain the integral amount within the tap, and store it, and to call the integral amount within the tap, the mixed multiplication component of the data tap and the summation of the integral amount within the data, and to perform the bit width After processing, the output data of the FIR filter is obtained.

Preferably, the generation rules of real-time delay data a ₀ ~ a _M and b ₀ ~ b ₃ are as shown in Formula 1:

Formula 1

Among them, x _{( n )} represents the input data at time n ; when the filter order N is an odd number, then let M = N +1, and the tap coefficient h _M =0; when the filter order N is an even number, then Let M = N .

Preferably, the data tap mixing variable is calculated as shown in Equation 2:

Formula 2

Among them, h represents the tap coefficient of the filter.

Preferably, the calculation method of the intra-data integral amount, the data tap mixing multiplication component and the intra-tap integral amount is as shown in Equation 3:

Formula 3

Among them, d _xx represents the integration amount within the data; d _xh represents the data tap mixing multiplication component; d _hh represents the integration amount within the tap.

Preferably, when the data tap mixed inner product calculation unit and the data inner product calculation unit perform multiplication operations, they also include a precoding submodule, which is used to use the radix 4 Booth encoding method to encode each string of data and perform partial products. Calculation and mapping, where the encoding, partial product calculation and mapping methods are shown in Equation 4 and Equation 5 respectively:

Formula 4

Among them, X _i , 2 X _i , and Mi all represent the coding results of precoding, and the index i is determined by the input data bit width;

Formula 5

Among them, Y _xi represents a single partial product; Y _2xi represents a double partial product; PPT _i represents the partial product mapping result; e _i represents the symbol of PP _i .

Preferably, when the data tap mixed inner product calculation unit and the data inner product calculation unit perform multiplication operations, they also include a compression submodule, which is used to compress and sum the partial products output by the precoding submodule, as shown in the formula As shown in 6:

Formula 6

Among them, four pieces of data D ₁ , D ₂ , D ₃ , and D ₄ are input each time and converted into intermediate variables TP ₁ ~ TP ₇ . .

An implementation method of the resource-optimized FIR filter is provided, including the following steps:

Step 1: Perform delay calculation on the input data to obtain real-time delay data a ₀ ~ a _M and b ₀ ~ b ₃ ;

Step 2: Based on the real-time delay data a ₀ ~ a _M and the filter tap coefficient, real-time calculation is performed to obtain the data tap mixing variable;

Step 3: Calculate the data tap mixing variable in real time to obtain the data tap mixing multiplication component;

Step 4: Calculate in real time based on the real-time delay data b ₀ ~ b ₃ to obtain the integration amount within the data;

Step 5: Based on the calculation of the filter tap coefficient, obtain the integral amount within the tap, and based on the summation of the integral amount within the tap, the mixed multiplication component of the data tap and the integral amount within the data, the output data of the FIR filter is obtained.

An electronic device is provided, including: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are The at least one processor executes, so that the at least one processor executes the method described in the claim.

A storage medium is provided, on which a computer program is stored. When the program is executed by a processor, the method described in the claims is implemented.

The present invention at least includes the following beneficial effects:

First, the present invention reduces the number of multipliers that need to be used by optimizing the FIR filter structure. Specifically, by reconstructing the filter inner product, the original convolution summation is modified into a data inner integral component and a data tap mixed multiplication component. and the integral amount within the tap. And considering that the taps are fixed, the integral amount within the tap is stored in advance, and the integral amount within the data and the mixed multiplication component of the data tap are calculated in real time to calculate the filter output.

Second, for the reconstructed FIR filter structure, partial product precoding is used to reduce the number of partial integrals, and compression coding is used to reduce the logic delay of the addition array and improve the operating efficiency of the multiply-accumulate logic.

Other advantages, objects, and features of the present invention will be apparent in part from the description below, and in part will be understood by those skilled in the art through study and practice of the present invention.

Description of the drawings

Figure 1 is a schematic diagram of the connection structure of each unit module of the filter of the present invention;

Figure 2 is an implementation structure diagram in an embodiment of the data delay unit of the present invention;

Figure 3 is an implementation structure diagram in an embodiment of the data preprocessing unit of the present invention;

Figure 4 is an implementation structure diagram of the data tap mixed inner product calculation unit in an embodiment of the present invention;

Figure 5 is an implementation structure diagram in the embodiment of module 3-1 of the present invention;

Figure 6 is an implementation structure diagram in the embodiment of module 3-1-1 of the present invention;

Figure 7 is an implementation structure diagram in the embodiment of module 3-2 of the present invention;

Figure 8 is an implementation structure diagram in the embodiment of module 3-2-1 of the present invention;

Figure 9 is an implementation structure diagram in the embodiment of module 3-2-2 of the present invention;

Figure 10 is an implementation structure diagram in an embodiment of the data inner product calculation unit of the present invention;

Figure 11 is an implementation structure diagram in the embodiment of module 4-2 of the present invention;

Figure 12 is an implementation structure diagram in the embodiment of module 4-3 of the present invention;

Figure 13 is an implementation structure diagram in an embodiment of the summation unit of the present invention.

Detailed ways

The present invention will be further described in detail below with reference to the accompanying drawings, so that those skilled in the art can implement it with reference to the text of the description.

It should be noted that the experimental methods described in the following embodiments, unless otherwise specified, are all conventional methods, and the reagents and materials, unless otherwise specified, can be obtained from commercial sources; in the description of the present invention, The orientation or positional relationship indicated by the terms is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description. It does not indicate or imply that the device or element referred to must have a specific orientation or in a specific manner. orientation construction and operation and therefore should not be construed as limitations of the invention.

<Example>

The explanation is based on the assumption that the filter order N is 19 and 20, and the input data and filter taps are both 16-bit specific point complex numbers. As shown in Figures 1 to 13, module 1 is the data delay unit; module 2 is the data preprocessing unit; module 3 is the data tap mixed inner product calculation unit; module 4 is the data inner product calculation unit; module 5 is the summation unit.

As shown in Figures 1 to 13, the resource-optimized FIR filter of the present invention includes:

The data delay unit accepts input data, delays the input data, and outputs the first output results, a ₀ , a ₁ , ..., a ₁₈ , a ₁₉ (a total of 20 data) and the second output results b ₀ , b ₁ , b ₂ , b ₃ (a total of 4 data), the data delay unit is shown in Figure 2, where,

Formula 1

x _{( n )} represents the input data at time n ; when the filter order N is an odd number, then let M = N +1, and the tap coefficient h _M =0; when the filter order N is an even number, then let M = N .

The data preprocessing unit accepts a ₀ , a ₁ ,..., a ₁₈ , a ₁₉ of the data delay unit and the filter tap coefficients h ₀ , h ₁ ,..., h ₁₈ , h ₁₉ as input, and outputs c ₀ , c ₁ , …, c ₁₈ , c ₁₉ , the structure of the data preprocessing unit is shown in Figure 3, and the generation rules are shown in Formula 2,

Formula 2

The data tap mixed inner product calculation unit accepts c ₀ , c ₁ ,..., c ₁₈ , c ₁₉ from the data preprocessing unit as input, and uses 2*20 modules 3-1 to achieve 2*160 partial product generation, 2 modules 3-2 implements the summation of 160 partial products respectively, and obtains the fourth output result d _xh :

d _xh represents the data tap mix multiplication component.

If N =19, just set h ₁₉ =0 directly. The data tap mixed inner product calculation unit is shown in Figure 4.

specific,

Each module 3-1 uses base 4 Booth coding to convert the multiplication calculation (X*Y) into 8 partial products PP ₀ ~ PP _7. The summation result of PP ₀ ~ PP ₇ is X*Y, The encoding mapping process is shown in Figure 5.

Among them, the Booth encoding and selection of a single partial product are completed by module 3-1-1. The specific encoding rules and partial product generation methods are shown in Figure 6. The index i = 0,1,...,7 in Figure 6.

Coding formula:

Formula 4

Among them, X _i , 2 X _i , and Mi all represent the coding results of precoding;

Single partial product intermediate variable mapping method:

Formula 5

Among them, Y _xi represents a single partial product; Y _2xi represents a double partial product; PPT _i represents the partial product mapping result; e _i represents the symbol of PP _i .

Finally, the PPT _i representation part is mapped to PP _i .

As shown in Figure 7, module 3-2 accepts 160 partial products, uses 7-level module 3-2-1 to compress it to 2 data, and then uses module 3-2-2 to sum and truncate to obtain the fourth output. result.

As shown in Figure 8, each module 3-2-1 compresses 4 data to 2 data. The compression method is as follows:

Formula 6

As shown in Figure 9, module 3-2-2 first intercepts F -2 bits (here F = 15) of the two compressed data, and then divides the data into the high-bit part and the low-order 2-bit part. The 2-bit mapping relationship determines add ₁ and add _2. Finally, the high-order parts of the two input data, add ₁ and add ₂ *2, are added to obtain the fourth output result (data tap mixed multiplication component) . Among them, add ₁ and add ₂ are two identifiers; add ₁ =1 means that 1 needs to be added to the calculation result; add ₁ =0 means that there is no need to add 1 to the calculation result; add ₂ =1 means that it needs to be added to the calculation result. Add 2 to the result; add ₂ =0 means there is no need to add 2 to the calculation result.

As shown in Figure 10, the data inner product calculation unit accepts the second output results b ₀ , b ₁ , b ₂ , b ₃ of the data delay unit as input, and uses module 3-1 to realize 2*32 partial product generation, 2 Module 4-2 implements the summation of 32 partial products respectively, and accumulates them through module 4-3 to obtain the fifth output result:

d _xx represents the amount of integration within the data.

specific,

As shown in Figure 11, module 4-2 accepts 32 partial products, uses level 4 module 3-2-1 to compress them to 2 data, and sums them through module 3-2-2.

As shown in Figure 12, module 4-3 uses an accumulator with a delay of 2 to accumulate the output of module 4-2 to obtain the fifth output result dxx _.

As _shown in Figure 13 _, the summation unit accepts the _fourth output result d Integral amount), summed and truncated to obtain the filtering result.

Among them, the filter tap pre-operation result is:

When the filter order N =19, let h ₁₉ =0.

Through the structural optimization of the above-mentioned filter, the current situation that the original order N filter needs to use N multipliers is changed to only need to use ( ceil ( N /2)+2) multipliers. The ceil function represents the positive direction. Rounding in the direction of infinity. That is to say, for the 19th and 20th order filters in this embodiment, 19 and 20 multipliers were originally needed. After the structural optimization of this application, only 12 multipliers are needed. The higher the order, the more obvious the benefits.

Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the description and embodiments. They can be applied to various fields suitable for the present invention. For those familiar with the art, they can easily Additional modifications may be made, and the invention is therefore not limited to the specific details and illustrations shown and described herein without departing from the general concept defined by the claims and equivalent scope.

Claims (9)

1. Resource-optimized FIR filter, which is characterized by: The data delay unit is used to perform delay calculation on the input data to obtain real-time delay data a ₀ ~ a _M and b ₀ ~ b ₃ ; A data preprocessing unit, which is used for real-time calculation based on real-time delay data a ₀ ~ a _M and filter tap coefficients to obtain data tap mixing variables; The data tap mixing inner product calculation unit is used for real-time calculation based on the data tap mixing variable to obtain the data tap mixing multiplication component; The data inner product calculation unit is used for real-time calculation based on the real-time delay data b ₀ ~ b ₃ to obtain the data inner product amount; The summation unit is used to calculate the tap coefficient based on the filter, obtain the integral amount within the tap, and store it, and to call the integral amount within the tap, the mixed multiplication component of the data tap and the summation of the integral amount within the data, and to perform the bit width After processing, the output data of the FIR filter is obtained. 2. The resource-optimized FIR filter according to claim 1, characterized in that the generation rules of real-time delay data a ₀ ~ a _M and b ₀ ~ b ₃ are as shown in Formula 1: Formula 1 Among them, x _{( n )} represents the input data at time n ; when the filter order N is an odd number, then let M = N +1, and the tap coefficient h _M =0; when the filter order N is an even number, then Let M = N . 3. The resource-optimized FIR filter as claimed in claim 2, characterized in that the calculation method of the data tap mixing variable is as shown in Formula 2: Formula 2 Among them, h represents the tap coefficient of the filter. 4. The resource-optimized FIR filter according to claim 3, characterized in that the calculation method of the integral amount within the data, the mixed multiplication component of the data tap and the integral amount within the tap is as shown in Formula 3: Formula 3 Among them, d _xx represents the integration amount within the data; d _xh represents the data tap mixing multiplication component; d _hh represents the integration amount within the tap. 5. The resource-optimized FIR filter according to claim 4, characterized in that when the data tap mixed inner product calculation unit and the data inner product calculation unit perform multiplication operations, they also include a precoding sub-module for The radix-4 Booth coding method is used to encode, partial product calculation and mapping each string of data. The encoding, partial product calculation and mapping methods are as shown in Equation 4 and Equation 5 respectively: Formula 4 Among them, X _i , 2 X _i , and Mi all represent the coding results of precoding, and the index i is determined by the input data bit width; Formula 5 Among them, Y _xi represents a single partial product; Y _2xi represents a double partial product; PPT _i represents the partial product mapping result; e _i represents the symbol of PP _i . 6. The resource-optimized FIR filter according to claim 5, characterized in that when the data tap mixed inner product calculation unit and the data inner product calculation unit perform multiplication operations, they also include a compression sub-module for performing the multiplication operation. The partial products output by the precoding sub-module are compressed and summed, as shown in Equation 6: Formula 6 Among them, four pieces of data D ₁ , D ₂ , D ₃ , and D ₄ are input each time and converted into intermediate variables TP ₁ ~ TP ₇ . 7. The implementation method of the resource-optimized FIR filter according to any one of claims 1 to 6, characterized in that it includes the following steps: Step 1: Perform delay calculation on the input data to obtain real-time delay data a ₀ ~ a _M and b ₀ ~ b ₃ ; Step 2: Based on the real-time delay data a ₀ ~ a _M and the filter tap coefficient, real-time calculation is performed to obtain the data tap mixing variable; Step 3: Calculate the data tap mixing variable in real time to obtain the data tap mixing multiplication component; Step 4: Calculate in real time based on the real-time delay data b ₀ ~ b ₃ to obtain the integration amount within the data; Step 5: Based on the calculation of the filter tap coefficient, obtain the integral amount within the tap, and based on the summation of the integral amount within the tap, the mixed multiplication component of the data tap and the integral amount within the data, the output data of the FIR filter is obtained. 8. Electronic equipment, characterized in that it includes: at least one processor, and a memory communicatively connected to the at least one processor, wherein the memory stores instructions that can be executed by the at least one processor, and the The instructions are executed by the at least one processor, so that the at least one processor executes the implementation method of claim 7. 9. A storage medium on which a computer program is stored, characterized in that when the program is executed by a processor, the implementation method of claim 7 is implemented.