CN113010146B - Mixed signal multiplier - Google Patents
Mixed signal multiplier Download PDFInfo
- Publication number
- CN113010146B CN113010146B CN202110245758.1A CN202110245758A CN113010146B CN 113010146 B CN113010146 B CN 113010146B CN 202110245758 A CN202110245758 A CN 202110245758A CN 113010146 B CN113010146 B CN 113010146B
- Authority
- CN
- China
- Prior art keywords
- module
- output
- bit
- input
- configurable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
The invention relates to a mixed signal multiplier, which only comprises 4 components, namely a binary number processing module, a configurable 1-bit addition matrix module, a configurable 1-bit multiplication and addition matrix module and a configurable delay module, and has a simpler structure. And the mixed signal multiplier formed by the design of the components has two inputs and one output. One of the inputs is a 1-bit data stream, the other input is a binary number with a quantized bit width, and the output is a 1-bit data stream, so that the input mixed signal can be processed. Furthermore, the mixed signal multiplier can convert the mixed input signal into a 1-bit operation result finally for output, so that the space occupied by the operation process of the whole multiplier can be reduced, and the operation efficiency is improved.
Description
Technical Field
The invention relates to the field of electronic components, in particular to a mixed signal multiplier.
Background
The delta-sigma analog-to-digital converter outputs a 1-bit data stream, which is typically decimated, filtered, converted to a multi-bit data signal, and then processed using conventional digital signal processing methods. This method has the following disadvantages:
firstly, delay is introduced into decimation filtering, and the larger the decimation rate is, the larger the delay is;
secondly, the conversion into the multi-bit data signal can lead the subsequent signal processing operation (such as addition, subtraction, multiplication and other operations) to have complex structure and occupy larger resources;
thirdly, the data transmission is performed through the multi-bit data lines, which consumes a lot of resources.
The multiplier is one of basic operation units, and is a basic unit for designing various algorithms. However, the multiplier in the prior art requires that the multiplicand and the multiplier be binary numbers expressed by a certain word length, and cannot directly process the mixed signal.
Therefore, it is a technical problem to be solved in the art to provide a mixed signal multiplier capable of directly processing a mixed signal.
Disclosure of Invention
In view of the above disadvantages in the prior art, the present invention provides a mixed signal multiplier with a large signal-to-noise ratio and a small occupied space, so as to process the mixed signal.
In order to achieve the purpose, the invention provides the following scheme:
a mixed signal multiplier comprising: the system comprises a configurable delay module, a binary data processing module, a configurable 1-bit multiplication and addition matrix module and a configurable 1-bit addition matrix module;
the output end of the configurable delay module and the output end of the binary data processing module are both connected with the input end of the configurable 1-bit multiplication and addition matrix module; the output end of the configurable 1-bit multiplication and addition matrix module is connected with the input end of the configurable 1-bit addition matrix module; the output end of the configurable 1-bit addition matrix module is used for outputting an operation result;
the configurable delay module is used for delaying an input 1-bit signal; the binary data processing module is used for converting an input binary signal into a 1bit signal.
Optionally, the configurable delay module is formed by cascading N registers.
Optionally, the binary data processing module includes a register and a plurality of or gates;
the first input end of the OR gate is used for inputting a binary data stream; the output end of the register is connected with the second input end of the OR gate and the data input end of the register after inverting operation; and the output ends of the plurality of OR gates are connected with the input end of the configurable 1-bit multiplication and addition matrix module.
Optionally, the configurable 1-bit multiply-add matrix module includes a first multiplication matrix unit, a second multiplication matrix unit and an add matrix unit;
the output end of the first multiplication matrix unit and the output end of the second multiplication matrix unit are both connected with the input end of the addition matrix unit; the first input end of the first multiplication matrix unit and the first input end of the second multiplication matrix unit are both connected with the output end of the binary data processing module; and the second input end of the first multiplication matrix unit and the second input end of the second multiplication matrix unit are both connected with the output end of the configurable delay module.
Optionally, the first multiplication matrix unit and the second multiplication matrix unit are formed by cascading a plurality of exclusive nor multipliers.
Optionally, the addition matrix unit is formed by cascading a plurality of adders.
Optionally, the configurable 1-bit addition matrix module includes a plurality of adders;
the adders are arranged in a gradient mode, and when the output of the configurable 1-bit multiplication and addition matrix module is N, the value range of the gradient series l formed by the arrangement of the adders is within the range of l E [1, log [ ]2N]The number of the adder in the l stage is 2l-1N is 2mM is a natural number;
the input end of the adder in the first stage is connected with the output end of the configurable 1-bit multiplication and addition matrix module; the output end of the adder in the l stage is connected with the input end of the adder in the l +1 stage.
Optionally, the adder includes: the device comprises an input signal processing module, a state conversion control module and an output generation module;
the input signal processing module is respectively connected with the output generation module and the state conversion control module;
the input signal processing module is used for generating first output data and second output data according to an input 1-bit operand and switching between addition and subtraction; the state conversion control module is used for generating third output data according to the second output data; the output generation module is used for generating a result after addition or subtraction according to the first output data, the second output data and the third output data.
Optionally, the input signal processing module includes: a first 1-bit data input interface and a second 1-bit data input interface;
the first 1-bit data input interface is used for inputting a first operand; the second 1-bit data input interface is used for inputting a second operand.
Preferably, the first output interface of the input signal processing module is connected with the first input interface of the output generating module; a second output interface of the input signal processing module is respectively connected with the input interface of the state conversion control module and a second input interface of the output generation module; and a third input interface of the output generation module is connected with an output interface of the state conversion control module.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the mixed signal multiplier provided by the invention only comprises 4 components, namely a binary number processing module, a configurable 1-bit addition matrix module, a configurable 1-bit multiplication and addition matrix module and a configurable delay module, and has a simpler structure. And the mixed signal multiplier formed by the above component design has two inputs and one output. One of the inputs is a 1-bit data stream, the other input is a binary number with a quantized bit width, the bit width is N, and the output is a 1-bit data stream, so that the input mixed signal can be processed. Furthermore, the mixed signal multiplier can convert the mixed input signal into a 1-bit operation result finally for output, so that the space occupied by the operation process of the whole multiplier can be reduced, and the operation efficiency is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a schematic diagram of a mixed signal multiplier according to the present invention;
fig. 2 is a schematic structural diagram of a configurable delay module provided in an embodiment of the present invention;
FIG. 3 is a block diagram of a binary data processing module according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a configurable 1-bit multiply-add matrix module according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a configurable 1-bit addition matrix module according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an adder according to an embodiment of the present invention;
FIG. 7 is a logic diagram of a state transition control module provided in an embodiment of the present invention;
FIG. 8 is a logic diagram of an output generation module provided in an embodiment of the present invention;
fig. 9 is a logic diagram of an input signal processing module provided in an embodiment of the present invention.
Description of the symbols:
the system comprises a configurable delay module 1, a register in the configurable delay module 1-1, a binary data processing module 2, an OR gate 2-1, a register in the binary data processing module 2-2, a configurable 1-bit multiplication and addition matrix module 3-1, a first multiplication matrix unit 3-1, a second multiplication matrix unit 3-2, an addition matrix unit 3-3, a configurable 1-bit addition matrix module 4, an adder 5, an input signal processing module 5-1, a state conversion control module 5-2 and an output generation module 5-3.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a mixed signal multiplier which has a complex structure and occupies a small space so as to be convenient for processing the mixed signal.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Fig. 1 is a schematic structural diagram of a mixed signal multiplier provided in the present invention, and as shown in fig. 1, a mixed signal multiplier includes: the device comprises a configurable delay module 1, a binary data processing module 2, a configurable 1-bit multiplication and addition matrix module 3 and a configurable 1-bit addition matrix module 4.
The output end of the configurable delay module 1 and the output end of the binary data processing module 2 are both connected with the input end of the configurable 1-bit multiply-add matrix module 3. The output end of the configurable 1-bit multiplication and addition matrix module 3 is connected with the input end of the configurable 1-bit addition matrix module 4. And the output end of the configurable 1-bit addition matrix module 4 is used for outputting an operation result.
The configurable delay module 1 is used for delaying an input 1-bit signal. The binary data processing module 2 is used for converting an input binary signal into a 1-bit signal.
In order to further increase the operation rate of the provided mixed signal multiplier, in the mixed signal multiplier provided by the present invention, the number of the configurable 1-bit multiply-add matrix module 3 can be set according to actual needs.
As a preferred embodiment of the present invention, as shown in fig. 2, the configurable delay module 1 is formed by cascading N registers 1-1.
As another preferred embodiment of the present invention, as shown in fig. 3, the binary data processing block 2 includes a register 2-2 and a plurality of or gates 2-1.
The first input of the or gate 2-1 is used for inputting a binary data stream. And the output end of the register is connected with the second input end of the OR gate and the data input end of the register 2-2 after inverting. And the output ends of the plurality of OR gates 2-1 are connected with the input end of the configurable 1-bit multiplication and addition matrix module 3.
As another preferred embodiment of the present invention, as shown in fig. 4, the configurable 1-bit multiply-add matrix module 3 includes a first multiplication matrix unit 3-1, a second multiplication matrix unit 3-2, and an addition matrix unit 3-3.
The output end of the first multiplication matrix unit 3-1 and the output end of the second multiplication matrix unit 3-2 are both connected with the input end of the addition matrix unit 3-3. The first input end of the first multiplication matrix unit 3-1 and the first input end of the second multiplication matrix unit 3-2 are both connected with the output end of the binary data processing module 2. The second input end of the first multiplication matrix unit 3-1 and the second input end of the second multiplication matrix unit 3-2 are both connected with the output end of the configurable delay module 1.
Preferably, the first multiplication matrix unit 3-1 and the second multiplication matrix unit 3-2 are each formed by cascading a plurality of exclusive nor multipliers.
The addition matrix unit 3-3 is formed by cascading a plurality of adders 5.
As another preferred embodiment of the present invention, as shown in fig. 5, the configurable 1-bit addition matrix module 4 includes a plurality of adders 5.
The adders 5 are arranged in a gradient manner, and when the output of the configurable 1-bit multiplication and addition matrix module 3 is N, the value range of the gradient series l formed by arranging the adders 5 is l E [1, log ∈2N]The number of the adder 5 in the l-th stage is 2l-1N is 2mAnd m is a natural number.
The input end of the adder 5 in the first stage is connected with the output end of the configurable 1-bit multiplication and addition matrix module 3. The output terminal of the adder 5 in the l-th stage is connected to the input terminal of the adder 5 in the l + 1-th stage.
As shown in fig. 6, the adder 5 provided by the present invention specifically includes: an input signal processing module 5-1, a state transition control module 5-2 and an output generation module 5-3.
The input signal processing module 5-1 is connected with the output generating module 5-3 and the state transition control module 5-2 respectively.
The input signal processing module 5-1 is used for generating first output data and second output data according to an input 1-bit operand, and is used for switching between addition and subtraction. The state transition control module 5-2 is configured to generate third output data according to the second output data. The output generation module 5-3 is configured to generate a result of addition or subtraction according to the first output data, the second output data, and the third output data.
Preferably, the input signal processing module 5-1 specifically includes: a first 1-bit data input interface and a second 1-bit data input interface.
The first 1-bit data input interface is used for inputting a first operand; the second 1-bit data input interface is used for inputting a second operand.
Preferably, the first output interface of the input signal processing module is connected with the first input interface of the output generating module. The first output interface of the input signal processing module is used for inputting the AND operation result of the first operand and the third operand into the output generation module. And a second output interface of the input signal processing module is respectively connected with the input interface of the state conversion control module and a second input interface of the output generation module. The second output interface of the input signal processing module is used for inputting the exclusive or operation result of the second operand and the third operand into the state conversion control module. And a third input interface of the output generation module is connected with an output interface of the state conversion control module.
An embodiment is provided below to further illustrate the specific design process of the mixed signal multiplier provided by the present invention.
In the first step, the mathematical expression of the mixed signal multiplier designed by the present invention is determined. According to mathematical expressions, the design of each module of the multi-mixed signal multiplier is facilitated.
The output equation of the mixed signal multiplier can be expressed as:
wherein N is a parameter setting value, and represents the number of multiplicand or multiplied data values that are required to be used when the multiplier performs operation, and N is 2mAnd m is a natural number, which cannot be changed in real time once selected. N is a positive integer representing the nth time, T is the update period of the data stream, u (i) is the multiplicand of the multiplier and is in a 1bit data stream format, i represents the ith time, i is a positive integer and has the value range of i belonging to [ N-N +1, N]U (i) indicates that the value of the multiplicand u from (N-N +1) T to nT is required for calculating the multiplication output z (N) at nT. v is an input of the multiplier, and is the bit width of the quantizationThe specific representation form of the binary data of L is shown in formula (2).
And secondly, designing a module.
According to the output equation of the mixed signal multiplier, the module for designing the mixed signal multiplier mainly comprises: the device comprises a configurable 1-bit addition matrix module 4, a configurable 1-bit multiplication and addition matrix module 3, a configurable delay module 1 and a binary data processing module 2.
(1) Designing a delay configuration module
The delay configuration module delays the 1bit input signal u (i) of the mixed signal multiplier. The module is formed by cascading a plurality of registers 1-1 as shown in fig. 2. The number N-1 of the registers 1-1 can be set according to actual needs.
(2) Design of a binary data processing module 2
One input of the mixed signal multiplier provided by the invention is a binary number with a certain word length L, defined as v, and the quantization bit width of the binary number is L, then v can be expressed as:
wherein the value range v of v belongs to [ -1,1 [ ]]，VjThe bit weight representing a binary number is 2-jThe corresponding digital value of the bit of (1) can only take 0 or 1.
The above v cannot be directly used as the input of the mixed signal multiplier of the present invention, and needs to be further processed by the binary data processing module 2 to obtain a 1-bit data stream v' equivalent to v.
The processing procedure of the binary data processing module 2 is as follows: when inputting VjIf 1, no processing is required and the signal is output as it is. When inputting VjAt 0, it needs to be converted into a square wave with 50% duty cycle as the corresponding output. After the above conversion, the binary multiplier v with the quantization bit width of L is converted into a 1-bit data stream form, as shown in the following formula:
in the formula, n represents nT time, and T is the updating period of 1bit data stream; vj' (n) is an input VjA corresponding output that is refreshed at the update frequency of the bitstream data.
According to the basic principle of the above-mentioned processing procedure of the binary data processing module 2, the specific structure of the binary data processing module 2 is designed, and the specific structure of the binary data processing module 2 is shown in fig. 3.
(3) Design configurable 1bit multiply-add matrix module 3
After the binary processing, the multiplier expression can be converted into:
let, the internal circulation is
The external circulation is
The inner loop is realized by adopting a configurable 1-bit multiplication and addition matrix module 3, the structure of which is shown in figure 4, and the input C of the modulej,j∈[1,L]In FIG. 4, "-" indicates a 1bit AND/OR multiplier,
representing a 1-bit adder 5.
Two inputs A, B of the XNOR gate multiplier are 1bit data stream, and the output Q isoFor a 1-bit data stream, the output and input are in the same or relationship, as shown in the following equation:
(4) design the configurable 1-bit addition matrix module 4
According to the formula (5), the configurable 1-bit addition matrix module 4 is adopted to realize outer circulation, and the basic operation unit of the configurable 1-bit addition matrix module 4 is the 1-bit adder 5 and needs to be connected according to the cascade connection method shown in fig. 5. Wherein, when the configurable 1-bit multiplication and addition matrix module 3 has N inputs, the value range of the series l of the whole configurable 1-bit addition matrix module 4 is l E [1, log ∈2N]On the l-th level, there is 2l-1An adder 5. The output of the adder 5 in the l-th stage serves as the input of the adder 5 in the l + 1-th stage.
The core component of the configurable 1-bit addition matrix module 4 is an adder 5, and the specific design process of the adder 5 specifically includes:
A. the mathematical expression of the adder 5 is determined. The various sub-modules in the adder 5 are connected according to a mathematical expression. In the process of the specific implementation, the adder 1bit data stream is used for outputting.
The mathematical expression of the adder 5 designed by the invention is as follows:
in this equation, X, Y is the two 1-bit inputs to adder 5. CnIs the output carry signal of adder 5 as the output of adder 5. SnThe sum signal of the output of the adder 5 is 1bit data. Sn-1、Sn-2Are respectively SnAnd obtaining data after 1 clock and 2 clock delay. Let Ci＝2Sn-1-Sn-2Is the input carry signal, S, of adder 5n-1、Sn-2And CiThe relationship between them is shown in table 1 below.
TABLE 1
| Sn-1 | Sn-2 | Ci |
| 0 | 0 | 0 |
| 0 | 1 | -1 |
| 1 | 0 | 2 |
| 1 | 1 | 1 |
B. The adder 5 is designed in a block.
In the mixed signal multiplier provided by the invention, each module is realized by being compatible with the expression modes of FPGA and ASIC, and the mixed signal multiplier specifically comprises the following steps:
design of a-state transition control module 5-2
In order to realize the adder 5 designed by the invention by using the minimum logic unit and register resource in the FPGA/ASIC, a state variable is defined, and the current state of the state variable is represented as Q1(n) sub-states are Q1(n +1), the present invention designs Q1(n +1) and input X, Y, Q1The relationship between (n) is shown in table 2 below.
TABLE 2
Q can be obtained by simplifying the carnot diagram1The expression of (n +1) is:
as shown in fig. 7, the state transition control module 5-2 has two inputs and one output. Wherein, one input is 1bit data, the other input is the updating clock of 1bit data, the output is 1bit output Q1(n)。
b. Design of output generation module 5-3
The output generation module 5-3 generates the output signal of the adder 5 designed by the invention, which is 1bit data. Designing the output C of the adder 5nAnd input X, Y, Q1(n) as shown in Table 3 below.
TABLE 3
After the carnot diagram simplification, an output C can be obtainednThe expression of (a) is:
the logic principle of the correspondingly designed output generation module of the invention is shown in fig. 8.
c. Design of input signal processing module 5-1
As shown in FIG. 9, this module has two 1bit inputs, which are operands X, Y. Has a 1bit output as the input of the state transition control module 5-2 and the output generation module 5-3.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (9)
1. A mixed signal multiplier, comprising: the system comprises a configurable delay module, a binary data processing module, a configurable 1-bit multiplication and addition matrix module and a configurable 1-bit addition matrix module;
the output end of the configurable delay module and the output end of the binary data processing module are both connected with the input end of the configurable 1-bit multiplication and addition matrix module; the output end of the configurable 1-bit multiplication and addition matrix module is connected with the input end of the configurable 1-bit addition matrix module; the output end of the configurable 1-bit addition matrix module is used for outputting an operation result;
the configurable delay module is used for delaying an input 1-bit signal; the binary data processing module is used for converting an input binary signal into a 1-bit signal;
the binary data processing module comprises a register and a plurality of OR gates;
the first input end of the OR gate is used for inputting a binary data stream; the output end of the register is connected with the second input end of the OR gate and the data input end of the register after inverting operation; and the output ends of the plurality of OR gates are connected with the input end of the configurable 1-bit multiplication and addition matrix module.
2. The mixed signal multiplier of claim 1 wherein the configurable delay block is formed by cascading N registers.
3. The mixed signal multiplier of claim 1 wherein the configurable 1-bit multiply-add matrix module comprises a first multiplication matrix unit, a second multiplication matrix unit, and an add matrix unit;
the output end of the first multiplication matrix unit and the output end of the second multiplication matrix unit are both connected with the input end of the addition matrix unit; the first input end of the first multiplication matrix unit and the first input end of the second multiplication matrix unit are both connected with the output end of the binary data processing module; and the second input end of the first multiplication matrix unit and the second input end of the second multiplication matrix unit are both connected with the output end of the configurable delay module.
4. The mixed signal multiplier of claim 3 wherein the first multiplication matrix unit and the second multiplication matrix unit are each cascaded from a plurality of exclusive-nor multipliers.
5. The mixed signal multiplier of claim 3 wherein the addition matrix unit is formed by a cascade of a plurality of adders.
6. The mixed signal multiplier of claim 1 wherein the configurable 1-bit addition matrix module comprises a plurality of adders;
the adders are arranged in a gradient mode, and when the output of the configurable 1-bit multiplication and addition matrix module is N, the value range of the gradient series l formed by the arrangement of the adders is within the range of l E [1, log [ ]2N]The number of the adder in the l stage is 2l-1N is 2mM is a natural number;
the input end of the adder in the first stage is connected with the output end of the configurable 1-bit multiplication and addition matrix module; the output end of the adder in the l stage is connected with the input end of the adder in the l +1 stage.
7. The mixed signal multiplier of claim 5 or 6 wherein the adder comprises: the device comprises an input signal processing module, a state conversion control module and an output generation module;
the input signal processing module is respectively connected with the output generation module and the state conversion control module;
the input signal processing module is used for generating first output data and second output data according to an input 1-bit operand and switching between addition and subtraction; the state conversion control module is used for generating third output data according to the second output data; the output generation module is used for generating a result after addition or subtraction according to the first output data, the second output data and the third output data.
8. The mixed signal multiplier of claim 7 wherein the input signal processing module comprises: a first 1-bit data input interface and a second 1-bit data input interface;
the first 1-bit data input interface is used for inputting a first operand; the second 1-bit data input interface is used for inputting a second operand.
9. The mixed signal multiplier of claim 7 wherein the first output interface of the input signal processing module is connected to the first input interface of the output generating module; a second output interface of the input signal processing module is respectively connected with the input interface of the state conversion control module and a second input interface of the output generation module; and a third input interface of the output generation module is connected with an output interface of the state conversion control module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110245758.1A CN113010146B (en) | 2021-03-05 | 2021-03-05 | Mixed signal multiplier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110245758.1A CN113010146B (en) | 2021-03-05 | 2021-03-05 | Mixed signal multiplier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113010146A CN113010146A (en) | 2021-06-22 |
| CN113010146B true CN113010146B (en) | 2022-02-11 |
Family
ID=76406951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110245758.1A Active CN113010146B (en) | 2021-03-05 | 2021-03-05 | Mixed signal multiplier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113010146B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1200821A (en) * | 1995-08-31 | 1998-12-02 | 英特尔公司 | Apparatus for performing multiply-add operations on packed data |
| CN103677735A (en) * | 2012-09-19 | 2014-03-26 | 北京中科晶上科技有限公司 | Data processing device and digital signal processor |
| CN104111816A (en) * | 2014-06-25 | 2014-10-22 | 中国人民解放军国防科学技术大学 | Multifunctional SIMD structure floating point fusion multiplying and adding arithmetic device in GPDSP |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324456C (en) * | 2004-01-09 | 2007-07-04 | 上海交通大学 | Digital signal processor using mixed compression two stage flow multiplicaton addition unit |
| US7562106B2 (en) * | 2004-08-07 | 2009-07-14 | Ternarylogic Llc | Multi-value digital calculating circuits, including multipliers |
| US20110055303A1 (en) * | 2009-09-03 | 2011-03-03 | Azuray Technologies, Inc. | Function Generator |
| US10146506B2 (en) * | 2014-11-11 | 2018-12-04 | Texas Instruments Incorporated | Efficient implementation of a multiplier/accumulator with load |
-
2021
- 2021-03-05 CN CN202110245758.1A patent/CN113010146B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1200821A (en) * | 1995-08-31 | 1998-12-02 | 英特尔公司 | Apparatus for performing multiply-add operations on packed data |
| CN103677735A (en) * | 2012-09-19 | 2014-03-26 | 北京中科晶上科技有限公司 | Data processing device and digital signal processor |
| CN104111816A (en) * | 2014-06-25 | 2014-10-22 | 中国人民解放军国防科学技术大学 | Multifunctional SIMD structure floating point fusion multiplying and adding arithmetic device in GPDSP |
Non-Patent Citations (1)
| Title |
|---|
| 浮点融合乘加部件设计分析与尾数加电路定制设计;李振虎;《中国优秀硕士学位论文全文数据库 信息科技辑》;20150115;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113010146A (en) | 2021-06-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101140511A (en) | Cascaded carry binary adder | |
| Thamizharasan et al. | FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier | |
| Akash et al. | An efficient implementation of FIR filter using high speed adders for signal processing applications | |
| Onizawa et al. | Area/energy-efficient gammatone filters based on stochastic computation | |
| Onizawa et al. | Gammatone filter based on stochastic computation | |
| CN113010146B (en) | Mixed signal multiplier | |
| Kumar et al. | FPGA Implementation of Systolic FIR Filter Using Single-Channel Method | |
| Kumar et al. | Low area VLSI implementation of CSLA for FIR filter design | |
| CN112988111B (en) | Single-bit multiplier | |
| Kumar et al. | Complex multiplier: implementation using efficient algorithms for signal processing application | |
| Rao et al. | Efficient 3-parallel polyphase odd length FIR filter using Brent Kung adder and Booth multiplier for VLSI applications | |
| Johansson | Low power and low complexity shift-and-add based computations | |
| Mahesh et al. | Low area design architecture of xor-mux full adder based discrete wavelet transform | |
| CN113010144B (en) | 1bit plus-minus device | |
| Thamizharasan et al. | An efficient VLSI architecture for FIR filter using computation sharing multiplier | |
| Subathradevi et al. | Delay optimized novel architecture of FIR filter using clustered-retimed MAC unit Cell for DSP applications | |
| Kannan | A Design of Low Power and Area efficient FIR Filter using Modified Carry save Accumulator Method | |
| Adams et al. | An MOS integrated circuit for digital filtering and level detection | |
| Patil et al. | VLSI Implementation of FIR Filter for Discrete Wavelet Transform | |
| Venkateshwarlu et al. | Optimized Design of Power Efficient FIR Filter Using Modified Booth Multiplier | |
| Magesh et al. | Design of Higher Order Matched FIR Filter Using Odd and Even Phase Process | |
| CN219179915U (en) | Polynomial arithmetic circuit and signal processing apparatus | |
| Salah et al. | Configurable Model for Sigmoid and Hyperbolic Tangent Functions | |
| Nair et al. | Optimized FIR filter using distributed parallel architectures for audio application | |
| KR0176829B1 (en) | Higher Order F-Al Filter for Ultra-Scale Integrated Circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |