CN116827285A - Amplifying circuit, control method thereof and sensor - Google Patents
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Abstract
The invention discloses an amplifying circuit, a control method thereof and a sensor. The amplifying circuit includes a first stage amplifier and a second stage amplifier. The first-stage amplifier is used for amplifying the input driving current or driving voltage to obtain a first output signal. The second-stage amplifier is used for amplifying the first output signal to obtain a second output signal. The intermediate processing signal in the second-stage amplifier is returned to the first-stage amplifier, and shares a part of circuit module with the first-stage amplifier. The technical scheme provided by the invention can improve the performance of the chip, but does not increase the power consumption and the area of the chip, thereby controlling the cost of the chip.
Description
Technical Field
The present invention relates to the field of circuit technologies, and in particular, to an amplifying circuit, a control method thereof, and a sensor.
Background
Sensors find great application in the field of industrial detection. The principle is as follows: the sensor converts the physical quantity change into an output of the voltage difference. For example, when the physical quantity changes, the bridge arm resistance changes, so that a non-zero voltage difference is generated at the output of the bridge, and the corresponding physical quantity is measured by measuring the output voltage difference. The signal of resistance change caused by the conventional physical quantity change is relatively weak, and an amplifier is generally used for amplifying the signal, so that the signal to noise ratio is improved. The amplifier circuit is a common circuit of a high-precision signal acquisition system.
The amplifier circuit for the sensor in the prior art relies on increasing the number of amplifiers to increase the amplification factor. However, this increases the power consumption of the chip and the area of the chip, thereby increasing the cost of the chip.
Disclosure of Invention
The invention provides an amplifying circuit, a control method thereof and a sensor, which are used for improving the performance of a chip without increasing the power consumption and the area of the chip, thereby controlling the cost of the chip.
According to an aspect of the present invention, there is provided an amplifying circuit including:
the first-stage amplifier is used for amplifying the input driving current or driving voltage to obtain a first output signal;
the second-stage amplifier is used for amplifying the first output signal to obtain a second output signal;
the intermediate processing signal in the second-stage amplifier is returned to the first-stage amplifier, and shares a part of circuit module with the first-stage amplifier.
According to another aspect of the present invention, there is provided a control method of an amplifying circuit provided in any one of the embodiments of the present invention, including:
in the first stage, the first-stage amplifier is controlled to work so that the first-stage amplifier amplifies input driving current or driving voltage to obtain a first output signal;
in the second stage, controlling the second-stage amplifier to enable the second-stage amplifier to amplify the first output signal to obtain a second output signal;
wherein a part of the circuit module shared by the second-stage amplifier and the first-stage amplifier operates in both the first stage and the second stage.
According to another aspect of the invention, there is provided a sensor comprising an amplifying circuit according to any of the embodiments of the invention.
According to the technical scheme, the two-stage amplifier is arranged in the amplifying circuit, and the two-stage amplifier shares the partial circuit module to process the intermediate signal, so that the driving current or driving voltage signal can be amplified on one hand; on the other hand, the circuit area and the power consumption can be reduced. In summary, the embodiment of the invention can improve the performance of the chip without increasing the power consumption and the area of the chip, thereby controlling the cost of the chip.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of another amplifying circuit according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of another amplifying circuit according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a control timing diagram of an amplifying circuit according to an embodiment of the present invention;
fig. 5 is a flowchart of a control method of an amplifying circuit according to an embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic diagram of an amplifying circuit according to an embodiment of the present invention, and referring to fig. 1, the amplifying circuit 100 includes a first stage amplifier 10 and a second stage amplifier 20. The first stage amplifier 10 is configured to amplify an input driving current or driving voltage to obtain a first output signal VOUT1. The second stage amplifier 20 is configured to amplify the first output signal VOUT1 to obtain a second output signal VOUT. Wherein the intermediate processing signal in the second stage amplifier 20 is returned to the first stage amplifier 10, and shares part of the circuit blocks with the first stage amplifier 10.
Specifically, the drive current or drive voltage signal VDRV is used to provide a drive power supply for the amplifying circuit. Specifically, under the driving of the driving current or the driving voltage signal VDRV, a voltage and a current are generated on the voltage difference output circuit (e.g., bridge), and under the influence of environmental factors (e.g., pressure, temperature, etc.), resistances within the voltage difference output circuit are not uniform, thereby generating a voltage difference at the output terminal of the voltage difference output circuit. The first stage amplifier 10 amplifies the voltage difference to obtain a first output signal VOUT1, which is fed to the second stage amplifier 20. After the first output signal VOUT1 is amplified by the second stage amplifier 20, a first intermediate signal outp2 and a second intermediate signal outn2 are output, and are sent back to a part of circuit modules in the first stage amplifier 10, so as to obtain a second output signal VOUT, thereby completing the amplification of the voltage difference signal.
According to the technical scheme, the two-stage amplifier is arranged in the amplifying circuit 100, and the two-stage amplifier shares part of the circuit module to process the intermediate signal, so that the voltage difference signal can be amplified on one hand; on the other hand, the circuit area and the power consumption can be reduced. In summary, the embodiment of the invention can improve the performance of the chip without increasing the power consumption and the area of the chip, thereby controlling the cost of the chip.
With continued reference to fig. 1, the first stage amplifier 10 may optionally include a first switch array SWin1, a voltage difference output circuit 11, a second switch array SWin2, a first amplifier 12, an output switch array SWout1, and a first low pass filter LPF1 connected in cascade, on the basis of the above embodiments. The second stage amplifier 20 includes a third switch array SWin3, a second amplifier 21, and a second low pass filter LPF2.
The input terminal of the third switch array SWin3 is electrically connected to the first low pass filter LPF1. The input terminal of the second amplifier 21 is electrically connected to the output terminal of the third switch array SWin3, and the output terminal of the second amplifier 21 is connected to the output switch array SWout1 so that the second stage amplifier 20 shares the output switch array SWout1 with the first stage amplifier 10. The input terminal of the second low pass filter LPF2 is electrically connected to the output terminal of the output switch array SWout1.
The voltage difference output circuit 11 may include a bridge or a sensor or the like whose equivalent circuit is a voltage difference output circuit. The voltage difference output circuit 11 includes a first arm resistor R1, a second arm resistor R2, a third arm resistor R3, and a fourth arm resistor R4. The first and/or second amplifier may comprise a fully differential circuit or a comparator circuit or the like, for example, may be an instrumentation amplifier.
Specifically, the driving current or the driving voltage signal VDRV of the voltage difference output circuit 11 is input to the first switch array SWin1, and the first switch array SWin1, the second switch array SWin2, the first amplifier 12, and the output switch array SWout1 together implement a dc chopping function of the circuit. In the first stage, the voltage difference signal generated by the voltage difference output circuit 11 is input to the first amplifier 12 after passing through the second switch array SWin 2. The signal is amplified and subjected to direct current chopping of the output switch array SWout1, and then high-frequency components in the signal are filtered out through the first low-pass filter LPF1, so that a first output signal VOUT1 is obtained. In the second stage, the first output signal VOUT1 is provided to the second amplifier 21 after passing through the third switch array SWin 3. After the signal VIN2 is amplified by the second amplifier 21, a first intermediate signal outp2 and a second intermediate signal outn2 are output. The first intermediate signal outp2 and the second intermediate signal outn2 are sent back to the output switch array SWout1 again, and the output switch array SWout1 processes the signals and outputs the signals to the second low-pass filter LPF2. The high frequency component in the signal is filtered by the second low pass filter LPF2 to obtain the second output signal VOUT, thereby completing amplification of the voltage difference signal.
The first low-pass filter LPF1 may be implemented in a switched-capacitor manner, for example, and thus may function as a low-pass filter for the first stage amplifier 10, as well as a sample-and-hold circuit, sampling and holding the input signal for the second stage amplifier 20. The second low pass filter LPF2 may include a resistor series/parallel capacitor structure, a switched capacitor structure, or the like. In the second low pass filter LPF2 means may be provided for shifting the first intermediate signal outp2 and the second intermediate signal outn2.
In the present embodiment, a first switch array SWin1, a voltage difference output circuit 11, a second switch array SWin2, a first amplifier 12, an output switch array SWout1, and a first low-pass filter LPF1, which are cascade-connected, are provided in the first stage amplifier 10. A third switch array SWin3, a second amplifier 21, and a second low pass filter LPF2 are provided in the second stage amplifier 20. By the arrangement, the performance of the chip can be improved, but the power consumption and the area of the chip are not increased, so that the cost of the chip is controlled.
With continued reference to fig. 1, the first switch array SWin1 and/or the second switch array SWin2 and/or the third switch array SWin3 and/or the output switch array SWout1 may optionally be switched capacitor arrays based on the embodiments described above. The first low-pass filter and/or the second low-pass filter is an RC filter or a switched capacitor filter.
With continued reference to fig. 1, in the foregoing embodiments, optionally, the input terminal of the first switch array SWin1 is connected to a driving current or a driving voltage; the voltage difference output circuit 11 is connected between the first switch array SWin1 and the second switch array SWin 2. The output terminal of the second switch array SWin2 is electrically connected to the input terminal of the first amplifier 12, and the output terminal of the first amplifier 12 is electrically connected to the first input terminal of the output switch array SWout1.
A second input terminal of the output switch array SWout1 is electrically connected to an output terminal of the second amplifier 21; the output terminal of the output switch array SWout1 is electrically connected to both the first low pass filter LPF1 and the second low pass filter LPF2.
Specifically, the driving current or the driving voltage signal VDRV of the voltage difference output circuit 11 is input to the first switch array SWin1, and the first switch array SWin1, the second switch array SWin2, the first amplifier 12, and the output switch array SWout1 together implement a dc chopping function of the circuit. The signal generated by the voltage difference output circuit 11 is input to the first amplifier 12 after passing through the second switch array SWin 2. The signal is amplified and subjected to direct current chopping of the output switch array SWout1, and then high-frequency components in the signal are filtered out through the first low-pass filter LPF1, so that a first output signal VOUT1 is obtained. After the second stage amplifier 20 processes the signal, the output switch array SWout1 outputs the signal to the second low pass filter LPF2. The high frequency component in the signal is filtered by the second low pass filter LPF2 to obtain the second output signal VOUT, thereby completing amplification of the voltage difference signal.
In the present embodiment, by setting the connection relationship among the first switch array SWin1, the voltage difference output circuit 11, the second switch array SWin2, the first amplifier 12, the output switch array SWout1, the first low pass filter LPF1 and the second low pass filter LPF2, the performance of the chip can be improved, but the power consumption and area of the chip are not increased, thereby controlling the cost of the chip.
With continued reference to fig. 1, the first amplifier 12 may optionally include a first operational amplifier OP1, a second operational amplifier OP2, a first resistor Rfg1, a first feedback resistor Rf1, and a second feedback resistor Rf2, based on the above embodiments.
The non-inverting input of the first OP1 and the non-inverting input of the second OP2 are used as inputs of the first amplifier 12. The output of the first OP1 and the output of the second OP2 are used as the output of the first amplifier 12. The first resistor Rfg1 is connected between the inverting input terminal of the first operational amplifier OP1 and the inverting input terminal of the second operational amplifier OP2. The first feedback resistor Rf1 is connected between the output terminal and the inverting input terminal of the first operational amplifier OP 1. The second feedback resistor Rf2 is connected between the output terminal and the inverting input terminal of the second operational amplifier OP2.
With continued reference to fig. 1, the first amplifier 12 may optionally include a third operational amplifier OP3, a fourth operational amplifier OP4, a second resistor Rfg2, a third feedback resistor Rf3, and a fourth feedback resistor Rf4, based on the above embodiments.
The non-inverting input of the third OP3 and the non-inverting input of the fourth OP4 are used as inputs of the first amplifier 12. The output of the third OP3 and the output of the fourth OP4 are used as the output of the first amplifier 12. The second resistor Rfg2 is connected between the inverting input terminal of the third operational amplifier OP3 and the inverting input terminal of the fourth operational amplifier OP 4. The third feedback resistor Rf3 is connected between the output terminal and the inverting input terminal of the third operational amplifier OP 3. The fourth feedback resistor Rf4 is connected between the output terminal and the inverting input terminal of the fourth operational amplifier OP 4.
Fig. 2 is a schematic structural diagram of another amplifying circuit according to an embodiment of the present invention, referring to fig. 2, optionally, the amplifying circuit 100 further includes a logic control module 30 based on the above embodiments. The logic control module 30 is connected to the first switch array SWin1, the second switch array SWin2, the third switch array SWin3, the output switch array SWout1, the first low pass filter LPF1, and the second low pass filter LPF2. The logic control module 30 is used for controlling the timing of the amplifying circuit 100.
Specifically, the driving current or the driving voltage signal VDRV of the voltage difference output circuit 11 is input to the first switch array SWin1, and the first switch array SWin1, the second switch array SWin2, the first amplifier 12, and the output switch array SWout1 together implement a dc chopping function of the circuit. In the first stage, under the control of the clock signals P1ck1, P1ck2, P1ck3 and P1ck4, the first switch array SWin1 selectively connects the ports P1, P2 with the ports P3, P4, P5 and P6, the second switch array SWin2 selectively connects the ports P7, P8 with the ports P3, P4, P5 and P6, and the output switch array SWout1 selectively connects the ports P9, P10 with the ports P11 and P12. The signal generated by the voltage difference output circuit 11 is input to the first amplifier 12 after passing through the second switch array SWin 2. The signal is amplified and subjected to direct current chopping of the output switch array SWout1, and then high-frequency components in the signal are filtered out through the first low-pass filter LPF1, so that a first output signal VOUT1 is obtained. In the second stage, under the control of the clock-driven timing signals P1ck1, P1ck2 and P1ck3, the third switch array SWin3 selectively connects the ports P15 and P16 with the ports P17 and P18, and the first switch array SWin1 selectively connects the ports P13 and P14 with the ports P11 and P12. After the first output signal VOUT1 passes through the third switch array SWin3, the input signal VIN2 is provided to the second amplifier 21. After the signal VIN2 is amplified by the second amplifier 21, a first intermediate signal outp2 and a second intermediate signal outn2 are output. The first intermediate signal outp2 and the second intermediate signal outn2 are sent back to the output switch array SWout1 again, and the output switch array SWout1 processes the signals and outputs the signals to the second low-pass filter LPF2. The high frequency component in the signal is filtered by the second low pass filter LPF2 to obtain the second output signal VOUT, thereby completing amplification of the voltage difference signal.
In the present embodiment, the logic control module 30 is provided in the amplifying circuit 100 to control the timing of the amplifying circuit 100, so that the amplifying circuit 100 can perform the function of amplifying signals, and the power consumption of the circuit can be reduced.
Fig. 3 is a schematic structural diagram of another amplifying circuit according to an embodiment of the present invention, and fig. 4 is a schematic control timing diagram of an amplifying circuit according to an embodiment of the present invention. Referring to fig. 3 and 4, the amplifying circuit 100 may further include control switches SW1 to SW29, as an option, based on the above embodiments. The control timing signals include CH1, CH2, P11, P21, P11b, P21b, P31, P1, P2, P3, P12, P22, P32, disch1, and disch2.
The timing signals P11 and P11b are in an inverse relationship, and the timing signals P21 and P21b are in an inverse relationship. The control switch SW11 and the control switch SW12 are turned on at low level, and the remaining control switches are turned on at high level.
Illustratively, when the timing signal CH1 is high, each of the timing signals P11, P21, P1, and P2 drives a corresponding switch, constituting a modulation switch of the first-stage amplifier 10. When the timing signals P11 and P21 are at high level (the timing signals P11b and P21b are at low level), the corresponding switches are turned on, and the signals are gated by the corresponding switches and amplified by the first amplifier 12. The output signals of the first amplifier 12 are the third output signal outop1 and the fourth output signal outop2, respectively. The third output signal outop1 and the fourth output signal outop2 are sampled to the first capacitor C1 and the second capacitor C2 when the timing signal P1 and the timing signal P2 are at high level, and when the timing signal P31 is at high level, the charges collected by the first capacitor C1 and the second capacitor C2 are redistributed with the fifth capacitor C5 to obtain a fifth output signal vout1P.
The calculation formula of the charge amount Q1 of the first capacitor C1 is as follows:
Q1＝C1*(outop2-outop1)
the calculation formula of the charge amount Q2 of the second capacitor C2 is:
Q2＝C2*(outop2-outop1)
the calculation formula of the fifth output signal vout1p is:
vout1p＝(Q1+Q2)/(C1+C2+C5)＝4*(outop2-outop1)/5
when the first feedback resistor Rf1 and the second feedback resistor Rf2 are equal, the calculation formula of the fifth output signal vout1p is:
when the timing signal P1 and the timing signal P2 are at the high level, the third output signal outop1 and the fourth output signal outop2 are sampled to the third capacitor C3 and the fourth capacitor C4, and when the timing signal P31 is at the high level, the charges collected by the third capacitor C3 and the fourth capacitor C4 are redistributed with the sixth capacitor C6, and according to the connection relationship of the switch, the value of the sixth output signal vout1n is opposite to the phase of the fifth output signal vout1P, and the calculation formula of the sixth output signal vout1n is:
when the timing signal CH2 is at a high level, each of the timing signals P12, P22, P1, and P2 drives a corresponding switch, constituting a modulation switch of the second-stage amplifier 20. When the timing signals P12 and P22 are at high level and the timing signals P1 and P2 are at high level, the corresponding switches are turned on, and the first output signal VOUT1 is gated by the corresponding switches and amplified by the second amplifier 21. The output signals of the second amplifier 21 are the seventh output signal outop3 and the eighth output signal outop4, respectively, the seventh output signal outop3 and the eighth output signal outop4 are sampled to the first capacitor C1 and the second capacitor C2 when the timing signal P1 and the timing signal P2 are at the high level, and when the timing signal P32 is at the high level, the charges collected by the first capacitor C1 and the second capacitor C2 are redistributed with the seventh capacitor C7, so as to obtain the ninth output signal VOUTP. The calculation formula of the ninth output signal VOUTP is:
based on the above formulas, another calculation formula of the ninth output signal VOUTP can be deduced as follows:
when the timing signal P1 and the timing signal P2 are at the high level, the seventh output signal outop3 and the eighth output signal outop4 are sampled to the third capacitor C3 and the fourth capacitor C4, and when the timing signal P32 is at the high level, the charges collected by the third capacitor C3 and the fourth capacitor C4 are re-divided with the eighth capacitor C8, so as to obtain the tenth output signal VOUTN.
In this embodiment, each control switch is controlled by setting each timing signal such that the circuit is enabled only when the corresponding control signal is high, otherwise it is in a sleep state. This arrangement allows the amplifying circuit 100 to perform the function of amplifying a signal on the one hand and to reduce the circuit power consumption on the other hand.
Fig. 5 is a flow chart of a control method of an amplifying circuit according to an embodiment of the present invention, referring to fig. 5, the method includes:
s110, in the first stage, the first-stage amplifier is controlled to work so that the first-stage amplifier amplifies the input driving current or driving voltage to obtain a first output signal.
And S120, in the second stage, controlling the second-stage amplifier so that the second-stage amplifier amplifies the first output signal to obtain a second output signal.
Wherein a part of the circuit module shared by the second-stage amplifier and the first-stage amplifier operates in both the first stage and the second stage.
Specifically, after the driving current or the driving voltage signal is input to the first-stage amplifier, the voltage difference output circuit is driven to generate a voltage difference signal. In the first stage, the first stage amplifier amplifies the voltage difference signal to obtain a first output signal, and the first output signal is sent to the second stage amplifier. In the second stage, the first output signal is amplified by the second stage amplifier, and then the first intermediate signal and the second intermediate signal are output and sent back to a part of circuit modules in the first stage amplifier to obtain a second output signal, so that the amplification of the voltage difference signal is completed.
In the first stage, the technical scheme of the embodiment controls the first-stage amplifier to amplify the voltage difference signal to obtain a first output signal. And in the second stage, controlling the second-stage amplifier to amplify the first output signal output by the first stage to obtain a second output signal. And a part of the circuit module shared by the two-stage amplifiers operates in both the first stage and the second stage. On the one hand, the voltage difference signal can be amplified; on the other hand, the circuit area and the power consumption can be reduced. In summary, the embodiment of the invention can improve the performance of the chip without increasing the power consumption and the area of the chip, thereby controlling the cost of the chip.
Optionally, the first stage amplifier includes a first switch array, a voltage difference output circuit, a second switch array, a first amplifier, an output switch array, and a first low pass filter on the basis of the above embodiments. The second stage amplifier includes a third switch array, a second amplifier, and a second low pass filter. The second stage amplifier shares an output switch array with the first stage amplifier. The output switch array operates in both the first stage and the second stage.
The embodiment of the invention also provides a sensor which comprises the amplifying circuit provided by any embodiment of the invention.
Specifically, when the sensor detects the physical quantity changes such as external air pressure, humidity or magnetic intensity, the output voltage and the input voltage deviate due to the influence of environmental factors on the resistance value in the sensor, and the voltage difference signal is amplified and compared by the amplifying circuit, so that the real physical quantity information is obtained.
The sensor provided by the embodiment of the invention has the beneficial effects of the amplifying circuit or the control method of the amplifying circuit provided by any embodiment of the invention, and the technical principle and the generated beneficial effects are similar and are not repeated.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (10)
1. An amplifying circuit, comprising:
the first-stage amplifier is used for amplifying the input driving current or driving voltage to obtain a first output signal;
the second-stage amplifier is used for amplifying the first output signal to obtain a second output signal;
and the intermediate processing signal in the second-stage amplifier is returned to the first-stage amplifier, and shares part of the circuit module with the first-stage amplifier.
2. The amplifying circuit according to claim 1, wherein the first stage amplifier comprises: the first switch array, the voltage difference output circuit, the second switch array, the first amplifier, the output switch array and the first low-pass filter are connected in cascade;
the second stage amplifier includes:
the input end of the third switch array is electrically connected with the first low-pass filter;
the input end of the second amplifier is electrically connected with the output end of the third switch array, and the output end of the second amplifier is connected to the output switch array so that the second-stage amplifier and the first-stage amplifier share the output switch array;
and the input end of the second low-pass filter is electrically connected with the output end of the output switch array.
3. The amplifying circuit of claim 2, wherein the first switched capacitor array is a switched capacitor array;
and/or, the second switch array is a switch capacitor array;
and/or, the third switch array is a switch capacitor array;
and/or, the output switch array is a switch capacitor array;
and/or, the first low-pass filter is an RC filter or a switched capacitor filter;
and/or, the second low-pass filter is an RC filter or a switched capacitor filter.
4. The amplifying circuit according to claim 2, further comprising:
a logic control module connected to the first switch array, the second switch array, the third switch array, the output switch array, the first low pass filter, and the second low pass filter; the logic control module is used for controlling the time sequence of the amplifying circuit.
5. The amplifying circuit according to claim 2, wherein an input terminal of the first switch array is connected to the driving current or the driving voltage; the voltage difference output circuit is connected between the first switch array and the second switch array;
the output end of the second switch array is electrically connected with the input end of the first amplifier, and the output end of the first amplifier is electrically connected with the first input end of the output switch array;
a second input end of the output switch array is electrically connected with an output end of the second amplifier; the output end of the output switch array is electrically connected with the first low-pass filter and the second low-pass filter at the same time.
6. The amplifying circuit according to claim 2, wherein the first amplifier includes:
the positive phase input end of the first operational amplifier and the positive phase input end of the second operational amplifier are used as input ends of the first amplifier; the output end of the first operational amplifier and the output end of the second operational amplifier are used as the output ends of the first amplifier;
the first resistor is connected between the inverting input end of the first operational amplifier and the inverting input end of the second operational amplifier;
the first feedback resistor is connected between the output end and the inverting input end of the first operational amplifier;
and the second feedback resistor is connected between the output end and the inverting input end of the second operational amplifier.
7. The amplifying circuit according to claim 2, wherein the first amplifier includes:
the positive phase input end of the third operational amplifier and the positive phase input end of the fourth operational amplifier are used as the input ends of the first amplifier; the output end of the third operational amplifier and the output end of the fourth operational amplifier are used as the output ends of the first amplifier;
the second resistor is connected between the inverting input end of the third operational amplifier and the inverting input end of the fourth operational amplifier;
the third feedback resistor is connected between the output end and the inverting input end of the third operational amplifier;
and the fourth feedback resistor is connected between the output end and the inverting input end of the fourth operational amplifier.
8. A control method of the amplifying circuit according to claim 1, comprising:
in a first stage, controlling the first-stage amplifier to work so that the first-stage amplifier amplifies input driving current or driving voltage to obtain a first output signal;
in a second stage, controlling the second-stage amplifier to enable the second-stage amplifier to amplify the first output signal to obtain a second output signal;
wherein a part of the circuit module shared by the second-stage amplifier and the first-stage amplifier operates in both the first stage and the second stage.
9. The method according to claim 8, wherein the first-stage amplifier includes a first switch array, a voltage difference output circuit, a second switch array, a first amplifier, an output switch array, and a first low-pass filter; the second-stage amplifier comprises a third switch array, a second amplifier and a second low-pass filter; the second stage amplifier shares the output switch array with the first stage amplifier;
the output switch array operates in both the first stage and the second stage.
10. A sensor, comprising: an amplifying circuit according to any of claims 1-7.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310781636.3A CN116827285A (en) | 2023-06-29 | 2023-06-29 | Amplifying circuit, control method thereof and sensor |
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| CN202310781636.3A CN116827285A (en) | 2023-06-29 | 2023-06-29 | Amplifying circuit, control method thereof and sensor |
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