CN116825810A

CN116825810A - Semiconductor device and method of forming the same

Info

Publication number: CN116825810A
Application number: CN202310684661.XA
Authority: CN
Inventors: 徐崇威; 潘冠廷; 朱龙琨; 江国诚; 王志豪; 余佳霓
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2022-06-09
Filing date: 2023-06-09
Publication date: 2023-09-29

Abstract

In an embodiment, a device includes: an isolation region on the substrate; a first nanostructure located over the isolation region; a second nanostructure located over the isolation region; a first gate spacer on the first nanostructure; a second gate spacer on the second nanostructure; a dielectric wall positioned between the first gate spacer and the second gate spacer along a first direction in a top view, the dielectric wall being disposed between the first nanostructure and the second nanostructure along a second direction in a top view, the first direction being perpendicular to the second direction; and a gate structure located around the first nanostructure and around the second nanostructure, a first portion of the gate structure filling a first region between the dielectric wall and the first nanostructure, a second portion of the gate structure filling a second region between the dielectric wall and the second nanostructure. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Semiconductor device and method of forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background

Semiconductor devices are used in a variety of electronic applications such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers of materials, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum component size decreases, other problems that should be solved arise.

Disclosure of Invention

Some embodiments of the present application provide a semiconductor device including: an isolation region on the substrate; a first nanostructure located over the isolation region; a second nanostructure located over the isolation region; a first gate spacer on the first nanostructure; a second gate spacer on the second nanostructure; a dielectric wall located between the first gate spacer and the second gate spacer along a first direction in a top view, the dielectric wall being disposed between the first nanostructure and the second nanostructure along a second direction in the top view, the first direction being perpendicular to the second direction; and a gate structure located around the first nanostructure and around the second nanostructure, a first portion of the gate structure filling a first region between the dielectric wall and the first nanostructure, a second portion of the gate structure filling a second region between the dielectric wall and the second nanostructure.

Further embodiments of the present application provide a semiconductor device including: a trench isolation region located on the substrate; a first nanostructure located over the trench isolation region; a second nanostructure located over the trench isolation region; a dielectric wall having a lower portion disposed between the first and second nanostructures and an upper portion overlapping the first and second nanostructures, the upper portion being wider than the lower portion; a gate structure located around the first nanostructure and around the second nanostructure; and a gate isolation region extending through the gate structure, the gate isolation region disposed on the dielectric wall.

Still further embodiments of the present application provide a method of forming a semiconductor device, comprising: forming a first nanostructure and a second nanostructure over the trench isolation region; removing the dummy gate from the first nanostructure and the second nanostructure; after removing the dummy gate, forming a dielectric wall between the first nanostructure and the second nanostructure, the dielectric wall being separated from the first nanostructure by a first opening, the dielectric wall being separated from the second nanostructure by a second opening; depositing a gate dielectric layer over the first nanostructure and the second nanostructure, the gate dielectric layer at least partially filling the first opening and the second opening; and forming a gate electrode layer on the gate dielectric layer, the gate electrode layer being disposed over the dielectric wall.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a nanostructured field effect transistor (nanostructured FET) in a three-dimensional view according to some embodiments.

Fig. 2-31C are views of intermediate stages in the fabrication of a nanostructured FET according to some embodiments.

Fig. 32 is a top view of a nanostructure FET, according to some embodiments.

Fig. 33A-52C are views of intermediate stages in the fabrication of a nanostructured FET according to some embodiments.

Fig. 53 is a top view of a nanostructure FET, according to some embodiments.

Fig. 54A-54C are views of a nanostructure FET, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as "under …," "under …," "lower," "above …," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

According to various embodiments, dielectric walls are formed between adjacent groups of nanostructures. The dielectric walls provide isolation so that adjacent groups of nanostructures can be formed closer together. Thus device density can be improved. Furthermore, a gate structure is formed around the nanostructure and over the dielectric wall. The gate structure is pi-shaped, allowing the same gate structure to control the channel region of adjacent devices. Thus, the number of gate contacts used in a CMOS process may be reduced.

Embodiments are described in particular contexts, including a die of a nanostructured field effect transistor (nanostructured FET). However, the various embodiments may be applied to dies that include other types of transistors (e.g., fin field effect transistors (finfets), planar transistors, etc.) in place of or in combination with nanostructure FETs.

Fig. 1 illustrates examples of nanostructured FETs (e.g., nanowire FETs, nanoplatelet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, full-gate-all-around (GAA) FETs, etc.) according to some embodiments. Fig. 1 is a three-dimensional view with some components of the nanostructure FET omitted for clarity of illustration.

The nanostructure FET includes a nanostructure 66 (e.g., a nanoplatelet, nanowire, etc.) located over a fin 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 66 is a semiconductor component that serves as a channel region for the nanostructure FET. Isolation regions 70, such as Shallow Trench Isolation (STI) regions, are disposed between adjacent fins 62, and fins 62 may protrude above adjacent isolation regions 70 and protrude from between adjacent isolation regions 70. Nanostructures 66 are disposed over and between adjacent isolation regions 70. Although isolation region 70 is depicted/shown as being separate from substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. Further, while the bottom portion of the fin 62 is shown as a single, continuous material with the substrate 50, the bottom portion of the fin 62 and/or the substrate 50 may comprise a single material or multiple materials. In this context, fin 62 refers to the portion that extends between adjacent isolation regions 70.

Gate dielectric 142 is located over the top surface of fin 62 and along the top, sidewalls, and bottom surfaces of nanostructure 66. A gate electrode 144 is located over the gate dielectric 142. Source/drain regions 98 are disposed on fin 62 on opposite sides of gate dielectric 142 and gate electrode 144. The source/drain regions 98 may be referred to individually or collectively as a source or drain, depending on the context. An interlayer dielectric (ILD) 104 is formed over the source/drain regions 98. Contacts (described later) to the source/drain regions 98 will be formed through ILD 104. Source/drain regions 98 may be shared between individual nanostructures 66. For example, adjacent source/drain regions 98 may be electrically connected, such as by epitaxially growing merged source/drain regions 98, or by coupling source/drain regions 98 with the same contacts.

Fig. 1 also shows a reference section for use in later figures. The cross section A-A' is along the longitudinal axis of the gate electrode 144. Section B-B 'is perpendicular to section A-A' and parallel to the longitudinal axis of fin 62 of the nanostructure FET and in the direction of current flow between, for example, source/drain regions 98 of the nanostructure FET. The section C-C 'is parallel to the section B-B' and along the longitudinal axis of the isolation region 70 between adjacent fins 62. Section D-D 'is parallel to section A-A' and extends through source/drain region 98 of the nanostructure FET. For clarity, the following figures refer to these reference sections.

Some embodiments discussed herein are discussed in the context of a nanostructured FET formed using a back gate process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects for use in planar devices such as planar FETs or in fin field effect transistors (finfets). For example, a FinFET may include a semiconductor fin on a substrate, where the semiconductor fin is a semiconductor feature that serves as a channel region for the FinFET. Similarly, a planar FET may include a substrate, where a planar portion of the substrate is a semiconductor component that serves as a channel region for the planar FET.

Fig. 2-31C are views of intermediate stages in the fabrication of a nanostructured FET according to some embodiments. Fig. 2, 3, 4, 5, 6 and 7 are three-dimensional views showing three-dimensional views similar to fig. 1. Fig. 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, 24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A are sectional views shown along a section similar to the reference section A-A' in fig. 1. Fig. 8B, 9B, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, 24B, 25B, 26B, 27B, 28B, 29B, 30B, and 31B are sectional views shown along a section similar to the reference section B-B' in fig. 1. Fig. 8C, 9C, 10C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 19C, 20C, 21C, 22C, 23C, 24C, 25C, 26C, 27C, 28C, 29C, 30C, and 31C are sectional views shown along a section similar to the reference section C-C' in fig. 1. Fig. 10D and 10E are sectional views shown along a section similar to the reference section D-D' in fig. 1.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. An insulating layer is provided over a substrate, typically a silicon or glass substrate. Other substrates, such as multi-layer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or a combination thereof.

The substrate 50 has one or more N-type regions 50N and one or more P-type regions 50P. The N-type region 50N may be used to form an N-type device, such as an NMOS transistor, e.g., an N-type nanostructured FET, and the P-type region 50P may be used to form a P-type device, such as a PMOS transistor, e.g., a P-type nanostructured FET. As will be described in more detail later, the n-type device and the p-type device will be formed in close proximity to each other. Forming the n-type device and the p-type device close together increases device density and allows the gate structures for the devices to be physically and electrically coupled to each other, thereby reducing the number of gate contacts used in the CMOS process. For example, the density may be reduced to 70% of the original density. The channel region in N-type region 50N will be physically separated from the channel region in P-type region 50P by a dielectric wall to prevent shorting of the channel region. Although one P-type region 50P and two N-type regions 50N are shown, any number of N-type regions 50N and P-type regions 50P may be provided.

The devices in N-type region 50N and P-type region 50P may then be interconnected by a metallization layer in the above interconnect structure to form an integrated circuit. The integrated circuit may be a logic device, a memory device, or the like. In some embodiments utilizing a CMOS process, a respective P-type region 50P is disposed between a respective pair of N-type regions 50N. Other acceptable integrated circuits may be formed and the integrated circuit may be provided with N-type region 50N and P-type region 50P in any acceptable manner.

A multi-layer stack 52 is formed over the substrate 50. The multi-layer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layer 54 is formed of a first semiconductor material, and the second semiconductor layer 56 is formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50.

In the illustrated embodiment, and as described in more detail subsequently, the first semiconductor layer 54 will be removed and the second semiconductor layer 56 will be patterned to form channel regions for the nanostructure FET in the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions in N-type region 50N and P-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and be formed simultaneously. The first semiconductor layer 54 is a dummy layer to be removed in a subsequent process to expose top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material having a high etching selectivity with respect to the etching of the second semiconductor layer 56, such as silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for n-type and p-type devices, such as silicon.

The multi-layer stack 52 is shown to include three first semiconductor layers 54 and three second semiconductor layers 56. It should be appreciated that the multi-layer stack 52 may include any number of first and second semiconductor layers 54, 56. Each of the layers of the multi-layer stack 52 may be grown by a process such as Vapor Phase Epitaxy (VPE) or Molecular Beam Epitaxy (MBE), deposited by a process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD), or the like. In some embodiments, some layers of the multi-layer stack 52 (e.g., the second semiconductor layer 56) are formed thinner than other layers of the multi-layer stack 52 (e.g., the first semiconductor layer 54). In some embodiments, the second semiconductor layer 56 has a thickness in the range of 2nm to 6 nm.

In fig. 3, fins 62 are formed in substrate 50 and nanostructures 64, 66 are formed in multilayer stack 52. In some embodiments, the nanostructures 64, 66 and the fins 62 may be formed in the multilayer stack 52 and the substrate 50 by etching trenches in the multilayer stack 52 and the substrate 50, respectively. The etching may be any acceptable etching process, such as Reactive Ion Etching (RIE), neutral Beam Etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The formation of the nanostructures 64, 66 by etching the multilayer stack 52 may further define a first nanostructure 64 by the first semiconductor layer 54 and a second nanostructure 66 by the second semiconductor layer 56.

The fins 62 and nanostructures 64, 66 may be patterned by any suitable method. For example, the fins 62 and nanostructures 64, 66 may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-aligned processes, allowing creation of patterns with, for example, smaller pitches than are obtainable using single, direct photolithography processes. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and then the remaining spacers may be used to pattern the fins 62 and nanostructures 64, 66.

Fin 62 is shown as having substantially equal widths in N-type region 50N and P-type region 50P. In some embodiments, the width of fin 62 in N-type region 50N may be greater than or less than the width of fin 62 in P-type region 50P. Furthermore, while each of the fins 62 and nanostructures 64, 66 are shown as always having a uniform width, in other embodiments, the fins 62 and/or nanostructures 64, 66 may have tapered sidewalls such that the width of each of the fins 62 and/or nanostructures 64, 66 continuously increases in a direction toward the substrate 50. In such embodiments, each of the nanostructures 64, 66 may have a different width and be trapezoidal in shape. In some embodiments, the nanostructures 66 have a width in the range of 10nm to 50 nm.

As will be described in greater detail later, a dielectric wall will be formed between the second nanostructures 66 in the N-type region 50N and the second nanostructures 66 in the adjacent P-type region 50P. Each dielectric wall separates the channel region of the n-type device from the channel region of the p-type device to prevent shorting of the channel region. The second nanostructures 66 in the N-type region 50N may be formed proximate to the second nanostructures 66 in the adjacent P-type region 50P. Distance D between N-type region 50N and second nanostructure 66 in adjacent P-type region 50P ₁ May be smaller than adjacent ones of the same P-type region 50P or the same N-type region 50NDistance D between second nanostructures 66 ₂ . In some embodiments, a distance D between the N-type region 50N and the second nanostructure 66 in the adjacent P-type region 50P ₁ In the range of 20nm to 60 nm. In some embodiments, the distance D between adjacent second nanostructures 66 in the same P-type region 50P or the same N-type region 50N ₂ In the range of 40nm to 60 nm.

In fig. 4, an insulating material 68 is deposited over the substrate 50, the fins 62 and the nanostructures 64, 66 and between adjacent fins 62 and adjacent nanostructures 64, 66. The insulating material 68 may be an oxide, such as silicon oxide, nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, insulating material 68 is silicon oxide formed by an FCVD process. Once the insulating material 68 is formed, an annealing process may be performed. In an embodiment, the insulating material 68 is formed such that an excess of the insulating material 68 covers the nanostructures 64, 66. Although insulating material 68 is shown as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not separately shown) may first be formed along the surfaces of the substrate 50, fin 62, and nanostructures 64, 66. Thereafter, a filler material, such as one of the insulating materials previously described, may be formed over the liner.

A removal process is then applied to the insulating material 68 to remove excess insulating material 68 over the nanostructures 64, 66. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like, may be utilized. The planarization process exposes the nanostructures 64, 66 such that the top surfaces of the nanostructures 64, 66 and the insulating material 68 are level after the planarization process is complete.

In fig. 5, insulating material 68 is recessed to form STI regions 70.STI region 70 is adjacent fin 62. The insulating material 68 is recessed such that upper portions of the fins 62 and/or nanostructures 64, 66 protrude from between adjacent STI regions 70. The upper portion of fin 62 and/or nanostructures 64, 66 is located above STI region 70. Further, the top surface of STI region 70 may have a planar surface (as shown), a convex surface, a concave surface (such as a recess), or a combination thereof. The top surfaces of STI regions 70 may be formed flat, convex, and/or concave by a suitable etch. STI regions 70 may be recessed using an acceptable etching process, such as an etching process selective to the material of insulating material 68 (e.g., etching the material of insulating material 68 at a faster rate than the material of fin 62 and nanostructures 64, 66). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) may be used.

The previously described process is merely one example of how the fins 62 and nanostructures 64, 66 may be formed. In some embodiments, the fins 62 and/or nanostructures 64, 66 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form the fin 62 and/or the nanostructures 64, 66. The epitaxial structure may include alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially grown epitaxial structures, the epitaxially grown material may be doped in situ during growth, which may avoid previous and/or subsequent implants, but in situ doping and implant doping may be used together.

Furthermore, suitable wells (not separately shown) may be formed in fin 62, nanostructures 64, 66, and/or STI region 70. In embodiments with different well types, different implantation steps for N-type region 50N and P-type region 50P may be implemented using a photoresist or other mask (not separately shown). For example, photoresist may be formed over fin 62, nanostructures 64, 66, and STI region 70 in N-type region 50N and P-type region 50P. The photoresist is patterned to expose the P-type region 50P. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the P-type region 50P, and the photoresist may be used as a mask to substantially prevent the n-type impurity implantation into In N-type region 50N. The n-type impurity may be implanted in the region to a level of from 10 ¹³ Atoms/cm ³ To 10 ¹⁴ Atoms/cm ³ Phosphorus, arsenic, antimony, etc. at concentrations in the range of (a). After implantation, the photoresist is removed, such as by an acceptable ashing process.

After or before the implantation of the P-type region 50P, a photoresist or other mask (not separately shown) is formed over the fins 62, nanostructures 64, 66, and STI regions 70 in the P-type region 50P and N-type region 50N. The photoresist is patterned to expose the N-type region 50N. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, a P-type impurity implantation may be performed in the N-type region 50N, and the photoresist may be used as a mask to substantially prevent the P-type impurity from being implanted into the P-type region 50P. The p-type impurity may be implanted in the region to from 10 ¹³ Atoms/cm ³ To 10 ¹⁴ Atoms/cm ³ Boron, boron fluoride, indium, etc. at a concentration in the range of (a). After implantation, the photoresist may be removed, such as by an acceptable ashing process.

After implantation of N-type region 50N and P-type region 50P, an anneal may be performed to repair the implant damage and activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in situ during growth, which may avoid implantation, but in situ doping and implantation doping may be used together.

In fig. 6, a dummy dielectric layer 72 is formed over the fin 62 and/or the nanostructures 64, 66. The dummy dielectric layer 72 may be formed of silicon oxide, silicon nitride, combinations thereof, or the like, which may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. A dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and then planarized, such as by CMP. The dummy gate layer 74 may be formed of a conductive or non-conductive material, and may be selected from the group consisting of amorphous silicon, polysilicon, poly-silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide, and metal. The material of dummy gate layer 74 may be deposited by CVD, physical Vapor Deposition (PVD), sputter deposition, or other techniques for depositing the selected material. The dummy gate layer 74 may be made of other materials having a high etch selectivity with respect to the etch of the insulating material (e.g., STI region 70 and/or dummy dielectric layer 72). A mask layer 76 may be deposited over the dummy gate layer 74. The mask layer 76 may be formed of a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed across the N-type region 50N and the P-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the STI region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and/or the nanostructures 64, 66.

In fig. 7, mask layer 76 is patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 may then be transferred to dummy gate layer 74 and dummy dielectric layer 72 to form dummy gate 84 and dummy dielectric 82, respectively. The dummy gate 84 overlies the respective channel regions of the nanostructures 64, 66. The pattern of the mask 86 may be used to physically separate each of the dummy gates 84 from an adjacent dummy gate 84. The dummy gate 84 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding fin 62. After patterning, the mask 86 may optionally be removed, such as by any acceptable etching technique.

Fig. 8A through 31C illustrate various additional steps in the fabrication of the embodiment device. Fig. 8B, 8C, 9B, 9C, 10B, 10C, 11B, 11C, 12B, 12C, 13B, 13C, 14B, 14C, 15B, 15C, 16B, 16C, 17B, 17C, 26B, 26C, 27B, 27C, 28B, 28C, 29B, 29C, 30B, 30C, 31B, and 31C show components in any of the N-type region 50N and the P-type region 50P. For example, the illustrated structure may be applicable to N-type region 50N and P-type region 50P. Differences in the structure of N-type region 50N and P-type region 50P, if any, are explained in the description of each figure. Fig. 18B, 18C, 19B, 19C, 20B, 20C, 21B, 21C, 22B, and 22C illustrate components in the N-type region 50N. Fig. 23B, 23C, 24B, 24C, 25B, and 25C illustrate components in the P-type region 50P.

In fig. 8A-8C, gate spacers 90 are formed over the nanostructures 64, 66 and STI regions 70 on the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. The gate spacers 90 may be formed by conformally forming one or more dielectric materials and then etching the dielectric materials. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. Other insulating materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, and the like, or combinations thereof, may be performed to pattern the dielectric material. The etching may be anisotropic. The dielectric material (when etched) has portions that remain on the sidewalls of dummy gate 84 (thus forming gate spacers 90). As will be described in more detail later, the dielectric material (when etched) may also have portions left on the sidewalls of the fins 62 and/or nanostructures 64, 66 (thus forming fin spacers 92, see fig. 10D and 10E). After etching, fin spacers 92 and/or gate spacers 90 may have straight sidewalls (as shown) or may have curved sidewalls (not separately shown).

In addition, implantation for lightly doped source/drain (LDD) regions (not separately shown) may be implemented. In embodiments with different device types, similar to the implantation for the wells previously described, a mask, such as photoresist, may be formed over the N-type region 50N while exposing the P-type region 50P, and an appropriate type (e.g., P-type) of impurity may be implanted into the fin 62 and nanostructures 64, 66 exposed in the P-type region 50P. The mask may then be removed. Subsequently, a mask, such as photoresist, may be formed over the P-type region 50P while exposing the N-type region 50N, and an appropriate type of impurity (e.g., N-type) may be implanted into the fin 62 and nanostructures 64, 66 exposed in the N-type region 50N. The mask may then be removed. The n-type impurity may be any of the n-type impurities previously discussed, and the p-type impurity may be any of the p-type impurities previously discussed. Lightly doped source/drain regions may be present in the slave10 ¹⁵ Atoms/cm ³ To 10 ¹⁹ Atoms/cm ³ An impurity concentration within a range of (2). Annealing may be used to repair implant damage and activate implanted impurities.

It should be noted that the previous disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, a different sequence of steps may be utilized, additional spacers may be formed and removed, and the like. In addition, the n-type device and the p-type device may be formed using different structures and steps.

In fig. 9A-9C, source/drain recesses 94 are formed in fin 62, nanostructures 64, 66, and substrate 50. Epitaxial source/drain regions will then be formed in the source/drain recesses 94. The source/drain recesses 94 may extend through the nanostructures 64, 66 and into the substrate 50. In some embodiments, fin 62 may be etched such that the bottom surfaces of source/drain recesses 94 are disposed below the top surfaces of STI regions 70. The source/drain recesses 94 may be formed by etching the fin 62, the nanostructures 64, 66, and the substrate 50 using an anisotropic etching process (such as RIE, NBE, etc.). During the etching process for forming the source/drain recesses 94, the gate spacers 90 and dummy gates 84 mask portions of the fin 62, nanostructures 64, 66, and substrate 50. A single etching process or multiple etching processes may be used to etch each layer of nanostructures 64, 66 and/or fin 62. After the source/drain recesses 94 reach the desired depth, a timed etch process may be used to stop the etching of the source/drain recesses 94.

Optionally, internal spacers 96, such as those exposed by the source/drain recesses 94, are formed on the sidewalls of the remaining portions of the first nanostructures 64. As will be described in more detail later, source/drain regions will then be formed in the source/drain recesses 94, and the first nanostructures 64 will then be replaced with corresponding gate structures. The internal spacers 96 serve as isolation features between subsequently formed source/drain regions and subsequently formed gate structures. In addition, the internal spacers 96 may be used to prevent damage to subsequently formed source/drain regions by a subsequent etching process, such as an etching process for subsequently removing the first nanostructures 64.

As an example of forming the internal spacers 96, the source/drain recesses 94 may be laterally expanded. In particular, the portions of the sidewalls of the first nanostructures 64 exposed by the source/drain recesses 94 may be recessed to form sidewall recesses. Although the sidewalls of the first nanostructures 64 are shown as being straight, the sidewalls may be concave or convex. The sidewalls may be recessed by any acceptable etching process, such as an etching process that is selective to the material of the first nanostructures 64 (e.g., etching the material of the first nanostructures 64 selectively at a faster rate than the material of the second nanostructures 66). The etching may be isotropic. For example, when the second nanostructures 66 are formed of silicon and the first nanostructures 64 are formed of silicon germanium, the etching process may be using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) ₄ OH), and the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas such as Hydrogen Fluoride (HF) gas. In some embodiments, the same etching process may be continuously performed to form the source/drain recesses 94 and recess the sidewalls of the first nanostructures 64. Then, the inner spacers 96 may be formed by conformally forming an insulating material in the source/drain recesses 94 and then etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, but any suitable material may be utilized, such as a low dielectric constant (low-k) material having a k value less than about 3.5. The insulating material may be formed by a deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be a dry etching such as RIE, NBE, or the like.

Although the outer sidewalls of the inner spacers 96 are shown as being flush with the sidewalls of the second nanostructures 66, the outer sidewalls of the inner spacers 96 may extend beyond the sidewalls of the second nanostructures 66 or be recessed from the sidewalls of the second nanostructures 66. In other words, the inner spacer 96 may partially fill, completely fill, or overfill the sidewall recess. Furthermore, while the sidewalls of the inner spacer 96 are shown as being straight, the sidewalls of the inner spacer 96 may be concave or convex.

In fig. 10A-10E, epitaxial source/drain regions 98 are formed in the source/drain recesses 94. In some embodiments, the epitaxial source/drain regions 98 exert stress in the corresponding channel regions of the second nanostructures 66, thereby improving performance. Epitaxial source/drain regions 98 are formed in the source/drain recesses 94 such that each dummy gate 84 is disposed between a respective adjacent pair of epitaxial source/drain regions 98. In some embodiments, gate spacers 90 are used to separate the epitaxial source/drain regions 98 from the dummy gates 84, and internal spacers 96 are used to separate the epitaxial source/drain regions 98 from the nanostructures 64 by an appropriate lateral distance so that the epitaxial source/drain regions 98 do not short to the subsequently formed gates of the resulting nanostructure FET.

Epitaxial source/drain regions 98 in N-type region 50N may be formed by masking P-type region 50P. Epitaxial source/drain regions 98 are then epitaxially grown in source/drain recesses 94 in N-type region 50N. The epitaxial source/drain regions 98 may comprise any acceptable material suitable for use in an n-type nanostructured FET. For example, if the second nanostructure 66 is formed of silicon, the epitaxial source/drain regions 98 may comprise a material that imparts a tensile strain on the second nanostructure 66, such as silicon, silicon carbide, phosphorus doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions 98 in the N-type region 50N may be referred to as "N-type source/drain regions". The epitaxial source/drain regions 98 may have surfaces that are raised from the respective upper surfaces of the nanostructures 64, 66, and may have facets.

Epitaxial source/drain regions 98 in P-type region 50P may be formed by masking N-type region 50N. Epitaxial source/drain regions 98 are then epitaxially grown in source/drain recesses 94 in P-type region 50P. The epitaxial source/drain regions 98 may comprise any acceptable material suitable for use in p-type nanostructured FETs. For example, if the second nanostructure 66 is formed of silicon, the epitaxial source/drain regions 98 may comprise a material that imparts a compressive strain on the first nanostructure 64, such as silicon germanium, boron doped silicon germanium, germanium tin, and the like. The epitaxial source/drain regions 98 in the P-type region 50P may be referred to as "P-type source/drain regions". The epitaxial source/drain regions 98 may also have surfaces that are raised from the corresponding surfaces of the nanostructures 64, 66, and may have facets.

The epitaxial source/drain regions 98, nanostructures 64, 66, and/or fin 62 may be implanted with dopants to form the source/drain regions, similar to the process previously discussed for forming lightly doped source/drain regions, followed by annealing. The source/drain regions may have a thickness of 10 ¹⁹ Atoms/cm ³ And 10 ²¹ Atoms/cm ³ The impurity concentration between them. The n-type and/or p-type impurities for the source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions 98 may be doped in-situ during growth.

Due to the epitaxial process used to form the epitaxial source/drain regions 98, the upper surface of the epitaxial source/drain regions 98 have facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source/drain regions 98 of the same nanostructure FET to merge, as shown in fig. 10D. In other embodiments, adjacent epitaxial source/drain regions 98 remain separated after the epitaxial process is completed, as shown in fig. 10E. In the illustrated embodiment, fin spacers 92 are formed on top surfaces of STI regions 70, thereby blocking epitaxial growth. In some other embodiments, fin spacers 92 may cover portions of the sidewalls of nanostructures 64, 66 and/or fins 62, further blocking epitaxial growth. In another embodiment, the spacer etch used to form gate spacers 90 is adjusted so that fin spacers 92 are not formed, so as to allow epitaxial source/drain regions 98 to extend to the surface of STI regions 70.

Epitaxial source/drain regions 98 may include one or more layers of semiconductor material. For example, the epitaxial source/drain regions 98 may include a liner layer, a main layer, and a finish layer (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of layers of semiconductor material may be used for epitaxial source/drain regions 98. Each of the backing layer, the main layer, and the finish layer may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the backing layer may have a dopant concentration that is less than the main layer and greater than the finish layer. In embodiments where epitaxial source/drain regions 98 comprise three layers of semiconductor material, a liner layer may be deposited, a main layer may be deposited over the liner layer, and a finish layer may be deposited over the main layer. In embodiments where the epitaxial source/drain regions 98 comprise three layers of semiconductor material, a liner layer may be grown in the source/drain recesses 94, a main layer may be grown on the liner layer, and a finish layer may be grown on the main layer.

In fig. 11A-11C, a first ILD 104 is deposited over the epitaxial source/drain regions 98, the gate spacers 90 and the mask 86 (if present) or dummy gate 84. The first ILD 104 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma Enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used.

In some embodiments, a Contact Etch Stop Layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source/drain regions 98, the gate spacers 90, and the mask 86 (if present) or dummy gate 84. CESL 102 may be formed of a dielectric material having a high etch selectivity relative to the etch of first ILD 104, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc.

In fig. 12A-12C, a removal process is performed to bring the top surface of the first ILD 104 flush with the top surfaces of the gate spacers 90 and mask 86 (if present) or dummy gate 84. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like, may be utilized. The planarization process may also remove the mask 86 on the dummy gate 84 and portions of the gate spacers 90 along the sidewalls of the mask 86. After the planarization process, the first ILD 104, gate spacers 90 and the top surface of mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Thus, the top surface of mask 86 (if present) or dummy gate 84 is exposed through first ILD 104.

In fig. 13A-13C, mask 86 (if present) and dummy gate 84 are removed in one or more etching steps to form recess 106. Portions of the dummy dielectric 82 that are located in the recess 106 are also removed. In some embodiments, dummy gate 84 and dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a faster rate than the material of the first ILD 104 and the gate spacer 90. Each recess 106 exposes portions of the nanostructures 64, 66 and/or overlies portions of the nanostructures 64, 66 that serve as channel regions in a subsequently completed nanostructure FET. Portions of the nanostructures 64, 66 that function as channel regions are disposed between adjacent pairs of epitaxial source/drain regions 98. During removal, the dummy dielectric 82 may act as an etch stop layer when the dummy gate 84 is etched. The dummy dielectric 82 may then be removed after the dummy gate 84 is removed.

The remaining portions of the first nanostructures 64 are then removed to form openings 108 in the regions 50I between the second nanostructures 66. The remaining portion of the first nanostructures 64 may be removed by any acceptable etching process that selectively etches the material of the first nanostructures 64 at a faster rate than the material of the second nanostructures 66. The etching may be isotropic. For example, when the first nanostructures 64 are formed of silicon germanium and the second nanostructures 66 are formed of silicon, the etching process may be using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH) ₄ OH), and the like. In some embodiments, a trimming process (not separately shown) is performed to reduce the thickness of the exposed portions of the second nanostructures 66 and expand the openings 108. After the trimming and/or removal process, the exposed portions of the second nanostructures 66 may be rounded. A recess 106 and an opening 108 are located between the gate spacers 90.

Fig. 14A to 27C illustrate a process of forming a gate dielectric layer 112 and a gate electrode layer 114 for a replacement gate in the recess 106 and the opening 108. Specifically, a gate structure is formed in recess 106 and extends across at least one N-type region 50N and adjacent P-type region 50P. A gate structure may be formed around the second nanostructure 66 in the adjacent region 50N, 50P such that the gate structure is coupled to the channel region of the device in the adjacent region 50N, 50P. Such coupling may be advantageous in some CMOS processes. For example, when the nanostructured FET is used to form an inverter, gate, memory, etc., using a single gate structure to control multiple channel regions may allow for a reduced number of gate contacts.

In fig. 14A-14C, a gate dielectric layer 112 is conformally formed over the channel region of the second nanostructure 66 such that it conformally lines the recess 106 and the opening 108. Specifically, gate dielectric layer 112 is formed on the top surface of fin 62; the top, sidewalls, and bottom of the second nanostructures 66; and on the sidewalls of gate spacers 90. The gate dielectric layer 112 wraps around all (e.g., four) sides of the second nanostructure 66. Gate dielectric layer 112 may also be formed on the top surfaces of first ILD 104 and gate spacer 90, and may be formed on the sidewalls of fin 62 (e.g., in embodiments where the top surface of STI region 70 is below the top surface of fin 62). The gate dielectric layer 112 may include an oxide such as silicon oxide or metal oxide, a silicate such as a metal silicate, combinations thereof, multilayers thereof, and the like. The gate dielectric layer 112 may include a high dielectric constant (high k) material having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric layer 112 may include Molecular Beam Deposition (MBD), ALD, PECVD, etc. Although a single layer of gate dielectric layer 112 is shown, the gate dielectric layer 112 may include multiple layers, such as an interfacial layer and an overlying high-k dielectric layer. The interfacial layer may be formed of silicon oxide and the high-k dielectric layer may be formed of hafnium oxide. Gate dielectric layer 112 may comprise any acceptable number of layers.

Fig. 15A-19C illustrate a process of forming dielectric walls 122 (see fig. 19A-19C) between the second nanostructures 66 in the N-type region 50N and the second nanostructures 66 in the adjacent P-type region 50P. Specifically, each dielectric wall 122 is formed in the recess 106 at the boundary of the adjacent pair of regions 50N, 50P. In some embodiments, the dielectric wall 122 is located within 50nm of the boundary of the adjacent regions 50N, 50P. The height of dielectric wall 122 will be less than the height of recess 106 such that a gate electrode subsequently formed in recess 106 extends over dielectric wall 122.

In fig. 15A-15C, a liner layer 120 is conformally formed over the gate dielectric layer 112 such that it conformally lines the recess 106 and the opening 108. The liner layer 120 is formed of a dielectric material that can be selectively etched in a subsequent removal process. Acceptable dielectric materials may include aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbonitride oxide, and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. The liner layer 120 is deposited until it is thick enough to fill the remaining portions of the region 50I between the second nanostructures 66. Specifically, respective portions of the gate dielectric layer 112 encapsulate the respective second nanostructures 66, and respective portions of the liner layer 120 encapsulate the respective portions of the gate dielectric layer 112, thereby completely filling the regions between the respective second nanostructures 66. In some embodiments, the spacer layer 120 has a thickness in the range of 1nm to 6 nm.

In fig. 16A-16C, a liner layer 122A for the dielectric wall is conformally formed on the liner layer 120 such that it conformally lines the recess 106. The pad layer 122A is formed of a dielectric material having a high etching selectivity with respect to etching of the pad layer 120. Acceptable dielectric materials may include oxides such as silicon oxide or aluminum oxide, nitrides such as silicon nitride or aluminum nitride, and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. As will be described in more detail later, a fill layer for the dielectric wall will be selectively deposited on the liner layer 122A in the recess 106, and the liner layer 122A will serve as a seed layer for the selective deposition of the liner layer. The liner layer 122A is thinner and is deposited to a thinner thickness than the subsequently formed fill layer. In some embodiments, the pad layer 122A has a thickness in the range of 1nm to 5 nm.

In FIGS. 17A to 17CThe liner layer 122A is pulled back to remove the portion of the liner layer 122A that is outside the recess 106 and reduce the height of the liner layer 122A in the recess 106. The liner layer 122A may be pulled back and forth with any acceptable etching process that is selective to the liner layer 122A (e.g., the material of the liner layer 122A is selectively etched at a faster rate than the material of the liner layer 120 and the gate dielectric layer 112). The etching process may be isotropic. A mask 124, such as photoresist, may be formed in the recess 106 that serves as an etch mask when etching the pad layer 122A. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. The height of the mask 124 is less than the depth of the recess 106. The height of the mask 124 in the recess 106 determines the height of the liner layer 122A remaining in the recess 106. After etching, the mask 124 may be removed, such as by an acceptable ashing process when the mask 124 is photoresist. As previously indicated, a fill layer for the dielectric walls is selectively deposited over the liner layer 122A. Thus, the height of the liner layer 122A remaining in the recess 106 determines the height of the dielectric wall. Height H of liner layer 122A ₁ Is large enough so that the spacer layer 122A extends over the top surface of the second nanostructure 66. In some embodiments, the pad layer 122A extends a height H in the range of 5nm to 20nm above the top surface of the second nanostructure 66 ₁ 。

In fig. 18A-18C, the pad layer 122A is patterned to remove portions of the pad layer 122A that are located at undesired locations. The liner layer 122A may be patterned with any acceptable etching process that is selective to the liner layer 122A (e.g., the material of the liner layer 122A is selectively etched at a faster rate than the material of the liner layer 120 and the gate dielectric layer 112). The etching process may be isotropic. A mask 126, such as photoresist, may be formed in the recess 106 that serves as an etch mask when etching the pad layer 122A. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. After etching, the mask 126 is removed, such as by an acceptable ashing process when the mask 126 is photoresist. In some embodiments, the ashing process is performed by annealing the mask 126 in an environment comprising nitrogen, hydrogen, or oxygen at a temperature in the range of 150 ℃ to 180 ℃. As will be described in greater detail later, the dielectric wall will extend over portions of the second nanostructures 66 in the N-type region 50N, over portions of the second nanostructures 66 in the adjacent P-type region 50P, and in the regions 50R between the second nanostructures 66 in those adjacent regions 50N, 50P. The liner layer 122A is patterned so that it remains in those areas where dielectric walls are desired. Thus, each portion of the pad layer 122A overlaps a portion of the second nanostructures 66 in the N-type region 50N, overlaps a portion of the second nanostructures 66 in the P-type region 50P, and is located in the region 50R between the second nanostructures 66 in the N-type region 50N and the second nanostructures 66 in the P-type region 50P.

In fig. 19A-19C, a fill layer 122B for the dielectric wall is selectively deposited over the remaining portion of the liner layer 122A. The fill layer 122B may be formed of the same dielectric material (e.g., oxide, nitride, etc.) as the liner layer 122A. The fill layer 122B is formed by a selective deposition process, such as selective Chemical Vapor Deposition (CVD) that forms the desired dielectric material at nucleation sites of the liner layer 122A. The fill layer 122B is selectively deposited over the pad layer 122A until they merge in the region 50R between the second nanostructures 66 in adjacent regions 50N, 50P. After the fill layer 122B is deposited, an etch back may be performed to remove any dielectric material deposited in undesired locations (e.g., not on the liner layer 122A). The etchback may include any acceptable etching process that is selective to the fill layer 122B (e.g., selectively etching the material of the fill layer 122B at a faster rate than the material of the liner layer 120 and the gate dielectric layer 112).

The remainder of each fill layer 122B and underlying liner layer 122A forms dielectric walls 122. In the cross-section of fig. 19A, the dielectric wall 122 has a lower portion in the region 50R between the second nanostructures 66 in adjacent regions 50N, 50P. The dielectric wall 122 has an upper portion that is located above the second nanostructures 66. An upper portion of the dielectric wall 122 overlaps the second nanostructure 66 and is a masking member that protects the second nanostructure 66 during a subsequent gate cutting process. The upper portion of the dielectric wall 122 has a width greater than the dielectric The width of the lower portion of the wall 122. In some embodiments, the upper portion of the dielectric wall 122 has a width W in the range of 30nm to 110nm ₁ And has a height H in the range of 5nm to 20nm ₂ . In some embodiments, the lower portion of the dielectric wall 122 has a width W in the range of 15nm to 50nm ₂ And has a height H in the range of 30nm to 70nm ₃ 。

In fig. 20A-20C, the liner layer 120 is patterned to remove portions of the liner layer 120 in the N-type region 50N. Specifically, the portion of the liner layer 120 not covered by the dielectric wall 122 in the N-type region 50N is removed. Removing portions of the liner layer 120 in the N-type region 50N reforms the openings 108 between the second nanostructures 66 in the N-type region 50N. In addition, removing portions of liner layer 120 in N-type region 50N forms openings 130 between dielectric wall 122 and portions of gate dielectric layer 112 in N-type region 50N. In this step, the portion of the liner layer 120 in the P-type region 50P is not removed. The liner layer 120 may be patterned with any acceptable etching process that is selective to the liner layer 120 (e.g., the material of the liner layer 120 is selectively etched at a faster rate than the material of the dielectric walls 122 and gate dielectric layer 112). The etching process may be isotropic. For example, when the liner layer 120 is formed of aluminum oxide, the etching process may be using ammonium hydroxide (NH ₄ OH), dilute hydrofluoric acid (dHF), and the like. A mask 128, such as photoresist, may be formed in the P-type region 50P that serves as an etch mask when etching the liner layer 120. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques.

In fig. 21A-21C, dielectric wall 122 is optionally trimmed to expand opening 130 in N-type region 50N. Dielectric wall 122 may be trimmed with any acceptable etching process that is selective to dielectric wall 122 (e.g., the material of dielectric wall 122 is selectively etched at a faster rate than the material of gate dielectric layer 112). After trimming, the width of opening 130 may be less than the width of opening 108. The liner layer 120 may (or may not) also be trimmed by etching to trim the dielectric wall 122. The mask 128 used to pattern the liner layer 120 may also be used as an etch mask when trimming the dielectric walls 122 and the liner layer 120 (when applicable). After trimming the dielectric walls 122 and/or the patterned liner layer 120, the mask 128 may be removed, such as by an acceptable ashing process when the mask 128 is photoresist.

In fig. 22A-22C, an N-type work function adjustment layer 114N is conformally formed on the gate dielectric layer 112 such that it conformally lines the recess 106, opening 108, and opening 130 in the N-type region 50N. The N-type work function adjustment layer 114N is formed of an N-type work function material (NWFM) that is suitable for adjusting the work function of the nanostructured FET to a desired amount given the application of the device to be formed, and may be formed by any acceptable deposition process. In some embodiments, the N-type work function adjustment layer 114N is formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like, which may be formed by a deposition process such as ALD, CVD, PVD and the like. In some embodiments, the N-type work function adjustment layer 114N is provided on To->Within a range of (2).

The N-type work function adjustment layer 114N may be formed by a conformal deposition process such that it is deposited over the dielectric wall 122, the liner layer 120, the gate dielectric layer 112, and the gate spacer 90. Because liner layer 120 is removed from N-type region 50N instead of P-type region 50P, N-type work function adjustment layer 114N is formed around second nanostructures 66 in N-type region 50N instead of P-type region 50P.

The N-type work function adjustment layer 114N fills the remainder of the region 50I between the second nanostructures 66 in the N-type region 50N. Specifically, N-type work function adjustment layer 114N is deposited over gate dielectric layer 112 in N-type region 50N until it is thick enough to merge and stitch together in openings 108 and 130. An interface (not separately shown) may be formed by contacting adjacent portions of the N-type work function adjustment layer 114N (e.g., those portions around the second nanostructures 66 in the N-type region 50N). Accordingly, the openings 108 and 130 in the N-type region 50N are completely filled by the respective portions of the gate dielectric layer 112 and the N-type work function adjustment layer 114N. Specifically, respective portions of the gate dielectric layer 112 encapsulate the respective second nanostructures 66 in the N-type region 50N, and respective portions of the N-type work function adjustment layer 114N encapsulate the respective portions of the gate dielectric layer 112, thereby completely filling the regions between the respective second nanostructures 66.

In fig. 23A to 23C, the N-type work function adjustment layer 114N is patterned to remove a portion of the N-type work function adjustment layer 114N in the P-type region 50P. The N-type work function adjustment layer 114N may be patterned with any acceptable etching process that is selective to the N-type work function adjustment layer 114N (e.g., the material of the N-type work function adjustment layer 114N is selectively etched at a faster rate than the material of the dielectric wall 122 and the gate dielectric layer 112). The etching process may be isotropic. A mask 132, such as photoresist, which serves as an etching mask when etching the N-type work function adjustment layer 114N may be formed in the P-type region 50P. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques.

The liner layer 120 is then patterned to remove portions of the liner layer 120 in the P-type region 50P. Removing portions of the liner layer 120 in the P-type region 50P reforms the openings 108 between the second nanostructures 66 in the P-type region 50P. In addition, removing portions of liner layer 120 in P-type region 50P forms openings 130 between dielectric wall 122 and portions of gate dielectric layer 112 in P-type region 50P. The liner layer 120 may be patterned with any acceptable etching process that is selective to the liner layer 120 (e.g., the material of the liner layer 120 is selectively etched at a faster rate than the material of the dielectric walls 122 and gate dielectric layer 112). The etching process may be isotropic. For example, when the liner layer 120 is formed of aluminum oxide, the etching process may be using ammonium hydroxide (NH ₄ OH), dilute hydrofluoric acid (dHF), and the like. The mask 132 used to pattern the N-type work function adjustment layer 114N may also be used as an etch mask when patterning the liner layer 120. The remaining portion of liner layer 120 is located between dielectric wall 122 and STI region 70.

In fig. 24A-24C, dielectric wall 122 is optionally trimmed to expand opening 130 in P-type region 50P. Dielectric wall 122 may be trimmed with any acceptable etching process that is selective to dielectric wall 122 (e.g., the material of dielectric wall 122 is selectively etched at a faster rate than the material of gate dielectric layer 112). After trimming, the width of opening 130 may be less than the width of opening 108. The liner layer 120 may (or may not) also be trimmed by etching to trim the dielectric wall 122. The mask 132 used to pattern the liner layer 120 may also be used as an etch mask when trimming the dielectric wall 122. After patterning the liner layer 120, removing the N-type work function adjustment layer 114N, and/or trimming the dielectric wall 122, the mask 132 may be removed, such as by an acceptable ashing process when the mask 132 is photoresist.

In fig. 25A-25C, a P-type work function adjustment layer 114P is conformally formed on the gate dielectric layer 112 such that it conformally lines the recess 106, opening 108, and opening 130 in the P-type region 50P. The P-type work function adjustment layer 114P is formed of a P-type work function material (PWFM) suitable for adjusting the work function of the nanostructured FET to a desired amount given the application of the device to be formed, and may be formed by any acceptable deposition process. In some embodiments, the P-type work function adjustment layer 114P is formed of titanium nitride, tantalum nitride, combinations thereof, and the like, which may be formed by a deposition process such as PVD, ALD, CVD and the like. In some embodiments, the P-type work function adjustment layer 114P is provided To->Within a range of (2).

The P-type work function adjustment layer 114P may be formed by a conformal deposition process such that it is deposited over the dielectric wall 122, the liner layer 120, the N-type work function adjustment layer 114N, the gate dielectric layer 112, and the gate spacer 90. Because liner layer 120 is removed from P-type region 50P, P-type work function adjustment layer 114P is formed around second nanostructure 66 in P-type region 50P.

The P-type work function adjustment layer 114P fills the remainder of the region 50I between the second nanostructures 66 in the P-type region 50P. Specifically, the P-type work function adjustment layer 114P is deposited over the gate dielectric layer 112 in the P-type region 50P until it is thick enough to merge and stitch together in the openings 108 and 130. An interface (not separately shown) may be formed by contacting adjacent portions of the P-type work function adjustment layer 114P (e.g., those portions around the second nanostructures 66 in the P-type region 50P). Accordingly, the openings 108 and 130 in the P-type region 50P are completely filled by the respective portions of the gate dielectric layer 112 and the P-type work function adjustment layer 114P. Specifically, respective portions of the gate dielectric layer 112 encapsulate the respective second nanostructures 66 in the P-type region 50P, and respective portions of the P-type work function adjustment layer 114P encapsulate the respective portions of the gate dielectric layer 112, thereby completely filling the regions between the respective second nanostructures 66.

In the illustrated embodiment, the P-type work function adjustment layer 114P is formed in the P-type region 50P and the N-type region 50N, and the N-type work function adjustment layer 114N is formed in the N-type region 50N instead of the P-type region 50P. Thus, the resulting gate structure in each region includes different materials and different numbers of layers. The gate structure in N-type region 50N may include more work function adjustment layers than the gate structure in P-type region 50P. Other configurations of work function adjustment layers may be utilized in different regions. For example, the P-type work function adjustment layer 114P may also be patterned to remove portions of the P-type work function adjustment layer 114P in the N-type region 50N, thereby exposing the N-type work function adjustment layer 114N.

In fig. 26A to 26C, the remaining portion of the gate electrode layer is formed in the grooves 106 in the P-type region 50P and the N-type region 50N. In the illustrated embodiment, a fill layer 114F (not shown in fig. 26B-26C, but see fig. 26A) is deposited over the P-type work function adjustment layer 114P and the N-type work function adjustment layer 114N (when exposed). The fill layer 114F may be formed of a conductive material such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like, which may be formed by a deposition process such as CVD, ALD, PECVD, PVD, and the like. The fill layer 114F fills the remainder of the recess 106 in the P-type region 50P and the N-type region 50N. Although not shown separately, it should be understood that other layers, such as glue layers, barrier layers, etc., may be formed under the fill layer 114F.

In fig. 27A-27C, a removal process is performed to remove excess portions of gate dielectric layer 112 and gate electrode layer 114 that are over the top surfaces of first ILD 104 and gate spacer 90, thereby forming gate dielectric 142 and gate electrode 144. In some embodiments, a planarization process, such as Chemical Mechanical Polishing (CMP), an etchback process, combinations thereof, and the like, may be utilized. Gate dielectric layer 112 (when planarized) has portions (thus forming gate dielectric 142) that remain in recess 106 and opening 108. Gate electrode layer 114 (when planarized) has portions (thus forming gate electrode 144) that remain in recess 106, opening 108, and opening 130. Gate spacers 90; CESL 102; a first ILD 104; a gate dielectric 142; and the top surfaces of the gate electrode 144 (e.g., the n-type work function adjustment layer 114N, P type work function adjustment layer 114P and the fill layer 114F; not shown in fig. 27B-27C, but see fig. 27A) are substantially coplanar (within process variations). Gate dielectric 142 and gate electrode 144 form a replacement gate for the resulting nanostructured FET. Each respective pair of gate dielectric 142 and gate electrode 144 may be collectively referred to as a "gate structure each extending along a top, sidewall, and bottom surface of the channel region of the second nanostructure 66. As shown in fig. 27A, gate electrode 144 is a pi-shaped gate electrode extending along the top and side walls of dielectric wall 122. Dielectric wall 122 is disposed on gate dielectric 142. The gate electrode 144 is formed in a pi-shape in a self-aligned manner, avoiding one or more trimming steps due to the previously described process.

Fig. 28A-29C illustrate a process of forming isolation regions 146 (see fig. 29A-29C) to divide (or "cut") gate electrode 144 into a plurality of gate electrode segments. Isolation region 146 may be formed between second nanostructures 66 in N-type region 50N and second nanostructures 66 in adjacent P-type region 50P. Specifically, isolation regions 146 are formed on dielectric wall 122 at the boundary of the adjacent pairs of regions 50N, 50P.

In fig. 28A to 28C, an opening 148 for an isolation region is patterned in the desired gate electrode 144. Any acceptable etching process, such as dry etching, wet etching, and the like, or combinations thereof, may be performed to pattern the openings 148. The etching may be anisotropic. The opening 148 exposes the top surface of the dielectric wall 122 instead of the STI region 70. As previously noted, the width of the upper portion of the dielectric wall 122 is greater than the width of the lower portion of the dielectric wall 122. More specifically, an upper portion of the dielectric wall 122 overlaps the second nanostructure 66 to protect the second nanostructure 66 during etching of the opening 148. Thus, forming dielectric wall 122 increases the process window for cutting gate electrode 144. An upper portion of the dielectric wall 122 is wider than the upper isolation region 146.

In fig. 29A to 29C, isolation regions 146 are formed in the openings 148. Isolation regions 146 may be formed of a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by a deposition process such as CVD, ALD, etc. One or more layers of dielectric material may be deposited in the openings. A removal process may be performed to remove excess portions of the dielectric material that are located above the top surface of gate electrode 144, thereby forming isolation regions 146. Isolation region 146 may (or may not) be formed of the same dielectric material as dielectric wall 122.

In fig. 30A-30C, a second ILD 154 is deposited over the gate spacer 90, CESL 102, first ILD 104, gate dielectric 142, gate electrode 144, and isolation region 146. In some embodiments, the second ILD 154 is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD 154 is formed of a dielectric material such as PSG, BSG, BPSG, USG, which may be formed by any suitable deposition process, such as CVD, PECVD, or the like.

In some embodiments, an Etch Stop Layer (ESL) 152 is formed between the second ILD 154 and the gate spacer 90, CESL 102, first ILD 104, gate dielectric 142, gate electrode 144, and isolation region 146. The ESL 152 may be formed of a dielectric material having a high etch selectivity relative to the etch of the second ILD 154, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc.

In fig. 31A-31C, gate contact 162 and source/drain contact 164 are formed to contact gate electrode 144 and epitaxial source/drain region 98, respectively. The gate contact 162 is physically and electrically coupled to the gate electrode 144. Source/drain contacts 164 are physically and electrically coupled to epitaxial source/drain regions 98.

As an example of forming the gate contact 162 and the source/drain contact 164, an opening for the gate contact 162 is formed through the second ILD 154 and ESL 152, and an opening for the source/drain contact 164 is formed through the second ILD 154, ESL 152, first ILD 104, and CESL 102. The openings may be formed using acceptable photolithography and etching techniques. A liner (not separately shown) such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the opening. The liner may comprise titanium, titanium nitride, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 154. The remaining liner and conductive material form gate contacts 162 and source/drain contacts 164 in the openings. The gate contact 162 and the source/drain contact 164 may be formed in different processes or may be formed in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 162 and the source/drain contact 164 may be formed in different cross-sections, which may avoid contact shorting.

Optionally, a metal-semiconductor alloy region 166 is formed at the interface between the epitaxial source/drain region 98 and the source/drain contact 164. The metal-semiconductor alloy region 166 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanide region formed of a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 166 may be formed prior to the material of the source/drain contact 164 by depositing metal in the opening for the source/drain contact 164 and then performing a thermal annealing process. The metal may be any metal capable of reacting with the semiconductor material (e.g., silicon carbide, silicon germanium, etc.) of epitaxial source/drain regions 98 to form a low resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be formed by a deposition process such as ALD, CVD, PVD. After the thermal annealing process, a cleaning process, such as a wet clean, may be performed to remove any remaining metal from the openings for the source/drain contacts 164, such as from the surface of the metal-semiconductor alloy regions 166. The material of the source/drain contacts 164 may then be formed on the metal-semiconductor alloy regions 166.

As previously noted, the width of the opening 130 may be less than the width of the opening 108 (see fig. 21A-21C and 24A-24C). Because of this, the gate electrode 144 (e.g., work function adjustment layer 114N/114P) has a different thickness at different locations. Specifically, the portion of gate electrode 144 between the vertical pair of nanostructures 66 has a greater thickness than the portion of gate electrode 144 between nanostructures 66 and dielectric wall 122. In some embodiments, the portion of the gate electrode 144 between the vertical pair of nanostructures 66 (e.g., work function adjustment layer 114N/114P) has a thickness T in the range of 2nm to 6nm ₁ And the portion of gate electrode 144 between nanostructure 66 and dielectric wall 122 (e.g., work function adjustment layer 114N/114P) has a thickness T in the range of 2nm to 6nm ₂ Wherein the thickness T ₁ Greater than thickness T ₂ 。

As previously described, the dielectric wall 122 is formed on the liner layer 120. Because of this, etching of the inner spacers 96 may be avoided when patterning the dielectric walls 122. Accordingly, the gate-drain capacitance (C) between the epitaxial source/drain regions 98 and the gate electrode 144 can be reduced _gd ) And leakage, thereby improving the performance of the nanostructured FETs, particularly in AC applications. Furthermore, the gate structure extends around all sides of the nanostructure 66 in the cross-section of fig. 31A, which may improve gate control compared to other devices including dielectric walls, such as a fork-slice structure. The gate structure (including gate dielectric 142 and gate electrode 144) completely fills the respective regions between nanostructure 66 and dielectric wall 122 such that gate dielectric 142 and gate electrode 144 each partially fill the respective regions. Concrete embodiments Gate dielectric 142 partially fills the region between nanostructure 66 and dielectric wall 122, and gate electrode 144 completely fills the remaining portion of the region not filled by gate dielectric 142. In this embodiment, dielectric wall 122 is formed after removal of nanostructure 64 (see fig. 13A-13C), after formation of gate dielectric layer 112 (see fig. 14A-14C), and before formation of gate electrode layer 114 (see fig. 26A-26C).

Fig. 32 is a top view of the nanostructure FET of fig. 31A-31C, shown along reference section E-E' in fig. 31A-31C. In a top view, dielectric walls 122 are disposed between adjacent groups of nanostructures 66 along a first direction (e.g., in the cross-section of fig. 31A). Further, in a top view, the dielectric walls 122 are disposed between adjacent pairs of gate spacers 90 along the second direction (e.g., in the cross-section of fig. 31B or 31C). In a top view, the first direction is perpendicular to the second direction such that both the first direction and the second direction are perpendicular to the major surface of the substrate 50. Gate spacer 90 separates dielectric wall 122 from first ILD 104.

Repeated etching of the liner layer 120 may occur when the dielectric wall 122 is trimmed to extend the opening 130 (described with respect to fig. 21A-21C and 24A-24C). Thus, in top view, the liner layer 120 may be recessed from the sidewalls of the dielectric wall 122. Thus, portions of the gate electrode 144 may be formed in the space previously occupied by the recessed liner layer 120, for example, between the dielectric wall 122 and the gate dielectric 142 along the second direction (e.g., in the cross-section of fig. 31B or 31C).

The materials of dielectric wall 122 may be stitched together during formation. Thus, the dielectric wall 122 has a seam 122S. In some embodiments, in a top view, seam 122 is parallel to the longitudinal axis of the gate structure and perpendicular to the longitudinal axis of nanostructure 66.

Fig. 33A-52C are views of intermediate stages in the fabrication of a nanostructured FET according to some embodiments. Fig. 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, 41A, 42A, 43A, 44A, 45A, 46A, 47A, 48A, 49A, 50A, 51A, and 52A are sectional views shown along a section similar to the reference section A-A' in fig. 1. Fig. 33B, 34B, 35B, 36B, 37B, 38B, 39B, 40B, 41B, 42B, 43B, 44B, 45B, 46B, 47B, 48B, 49B, 50B, 51B, and 52B are sectional views shown along a section similar to the reference section B-B' in fig. 1. Fig. 33C, 34C, 35C, 36C, 37C, 38C, 39C, 40C, 41C, 42C, 43C, 44C, 45C, 46C, 47C, 48C, 49C, 50C, 51C, and 52C are sectional views shown along a section similar to the reference section C-C' in fig. 1.

Fig. 33B, 33C, 34B, 34C, 35B, 35C, 36B, 36C, 37B, 37C, 38B, 38C, 39B, 39C, 40B, 40C, 41B, 41C, 42B, 42C, 43B, 43C, 49B, 49C, 50B, 50C, 51B, 51C, 52B, and 52C show components in any of the N-type region 50N and the P-type region 50P. For example, the illustrated structure may be applicable to N-type region 50N and P-type region 50P. Differences in the structure of N-type region 50N and P-type region 50P, if any, are explained in the description of each figure. Fig. 44B, 44C, 45B, and 45C illustrate components in the N-type region 50N. Fig. 46B, 46C, 47B, 47C, 48B, and 48C illustrate components in the P-type region 50P.

In fig. 33A to 33C, the structures of fig. 12A to 12C are obtained. Mask 86 (if present) is then removed, thereby forming recess 106. The dummy gate 84 is then recessed to extend the recess 106. In some embodiments, the mask 86 is removed and the dummy gate 84 is recessed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a faster rate than the material of the first ILD 104 and the gate spacer 90.

In fig. 34A to 34C, the gate spacer 90 is recessed. In some embodiments, the gate spacer 90 is recessed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the gate spacer 90 at a faster rate than the material of the first ILD 104 and the dummy gate 84. The dummy gate 84 may be used as an etch mask when etching the gate spacer 90.

In fig. 35A to 35C, the remaining portion of the dummy gate 84 is removed. Portions of the dummy dielectric 82 that are located in the recess 106 are also removed. In some embodiments, dummy gate 84 and dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the material of the dummy gate 84 at a faster rate than the material of the first ILD 104 and the gate spacer 90. During removal, the dummy dielectric 82 may act as an etch stop layer when the dummy gate 84 is etched. Then, after removing the dummy gate 84, the dummy dielectric 82 may be removed.

In fig. 36A to 36C, the pad layer 120 is conformally formed in the groove 106. The liner layer 120 may be formed similarly as described with respect to fig. 15A-15C. The liner layer 120 extends along the sidewalls of the CESL 102 exposed by recessing the gate spacers 90. Liner layer 120 may extend over first ILD 104 and gate spacer 90. In some embodiments, the spacer layer 120 has a thickness in the range of 1nm to 5nm, such as in the range of 1.5nm to 5 nm.

An insulating material 202 for the dielectric wall is formed on the liner layer 120. The insulating material 202 is formed of a dielectric material having a high etching selectivity with respect to etching of the liner layer 120. Acceptable dielectric materials may include oxides such as silicon oxide or aluminum oxide, silicon nitride, silicon carbonitride, silicon oxynitride and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD) and the like.

In fig. 37A to 37C, the insulating material 202 is pulled back to remove the insulating material 202 outside the groove 106, and the height of the insulating material 202 in the groove 106 is reduced. The insulating material 202 may be pulled back and forth with any acceptable etching process that is selective to the insulating material 202 (e.g., etching the material of the insulating material 202 selectively at a faster rate than the material of the liner layer 120). The etching process may be isotropic. The insulating material 202 is recessed until the portion of the spacer layer 120 that is above the nanostructures 64, 66 is exposed. After the insulating material 202 reaches a desired height, a timed etch process may be used to stop etching of the insulating material 202.

In fig. 38A-38C, insulating material 202 is patterned to remove portions of insulating material 202 that are located at undesired locations, thereby forming dielectric walls 122. The insulating material 202 may be patterned with any acceptable etching process that is selective to the insulating material 202 (e.g., etching the material of the insulating material 202 selectively at a faster rate than the material of the liner layer 120). The etching process may be isotropic. A mask 204, such as photoresist, that serves as an etch mask when etching the insulating material 202 may be formed in the recess 106. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. After etching, the mask 204 may be removed, such as by an acceptable ashing process when the mask 204 is photoresist. Dielectric wall 122 includes the remaining portion of insulating material 202. Each dielectric wall 122 is located in a region 50R between a second nanostructure 66 in an N-type region 50N and a second nanostructure 66 in an adjacent P-type region 50P.

In fig. 39A-39C, the portion of the liner layer 120 exposed (e.g., uncovered) by the dielectric wall 122 is removed. The liner layer 120 may be removed using any acceptable etching process that is selective to the liner layer 120 (e.g., etching the material of the liner layer 120 selectively at a faster rate than the material of the dielectric wall 122). The etching process may be isotropic. The dielectric wall 122 may be used as an etch mask when etching the liner layer 120.

In fig. 40A-40C, the remaining portions of the first nanostructures 64 are removed to form openings 108 in the region 50I between the second nanostructures 66. The remaining portions of the first nanostructures 64 may be removed similarly as described for fig. 13A-13C.

In fig. 41A-41C, the liner layer 120 is pulled back to remove portions of the liner layer 120 along the sidewalls of the dielectric wall 122. The liner layer 120 may be pulled back and forth with any acceptable etching process that is selective to the liner layer 120 (e.g., etching the liner selectively at a faster rate than the material of the dielectric walls 122 and the nanostructures 66)The material of layer 120). At least some portion of liner layer 120 between dielectric wall 122 and STI region 70 may also be removed. Thus, in cross-section, the liner layer 120 may be recessed from the sidewalls of the dielectric wall 122. After the removal process, the exposed portions of the second nanostructures 66 may be rounded. In addition, removing portions of liner layer 120 forms openings 130 between dielectric walls 122 and nanostructures 66 and gate spacers 90. Dielectric wall 122 may optionally be trimmed to expand opening 130. The dielectric wall 122 may be trimmed similarly as described for fig. 21A-21C and 24A-24C. Width W of opening 130 ₃ May be less than or equal to the width W of the opening 108 ₄ 。

In fig. 42A-42C, a gate dielectric layer 112 is conformally formed over the dielectric wall 122 and the channel region of the second nanostructure 66 such that it conformally lines the recess 106, the opening 108, and the opening 130. Portions of gate dielectric layer 112 may be located between dielectric wall 122 and STI region 70. The gate dielectric layer 112 may be formed similarly as described with respect to fig. 14A-14C. In this embodiment, gate dielectric layer 112 does not completely fill opening 130.

In fig. 43A-43C, sacrificial structures 206 are formed between the nanostructures 66 and the dielectric walls 122, and between the vertical pairs of the nanostructures 66. Sacrificial structure 206 may be formed by conformally depositing a dielectric material in recess 106, opening 108, and opening 130, and then etching the dielectric material to remove portions of the dielectric material that are outside of openings 108 and 130. Acceptable dielectric materials may include aluminum oxide, aluminum nitride, silicon oxide, silicon nitride, silicon carbonitride oxide, and the like, which may be formed by deposition processes such as Chemical Vapor Deposition (CVD), atomic Layer Deposition (ALD), and the like. Any acceptable etching process, such as dry etching, wet etching, and the like, or combinations thereof, may be performed to pattern the dielectric material. The sacrificial structure 206 may be formed of the same dielectric material as the liner layer 120.

In fig. 44A-44C, the sacrificial structure 206 in the N-type region 50N is removed. Removal of sacrificial structure 206 in N-type region 50N reforms openings 108 and 130 in N-type region 50N. In this step, noThe sacrificial structure 206 in the P-type region 50P is removed. Sacrificial structure 206 may be removed using any acceptable etching process that is selective to sacrificial structure 206 (e.g., the material of sacrificial structure 206 is selectively etched at a faster rate than the material of dielectric wall 122 and gate dielectric layer 112). The etching process may be isotropic. For example, when the sacrificial structure 206 is formed of aluminum oxide, the etching process may be using ammonium hydroxide (NH ₄ OH), dilute hydrofluoric acid (dHF), and the like. A mask 208, such as a photoresist, may be formed in the P-type region 50P that serves as an etch mask when etching the sacrificial structure 206. The photoresist may be formed using spin-on techniques and may be patterned using acceptable photolithographic techniques. After removal of the sacrificial structure 206 in the N-type region 50N, the mask 208 may be removed, such as by an acceptable ashing process when the mask 208 is photoresist.

In fig. 45A-45C, an N-type work function adjustment layer 114N is conformally formed on the gate dielectric layer 112 such that it conformally lines the recess 106, opening 108, and opening 130 in the N-type region 50N. The N-type work function adjustment layer 114N may be formed similarly to that described with respect to fig. 22A to 22C. Because the sacrificial structure 206 is removed from the N-type region 50N instead of the P-type region 50P, the N-type work function adjustment layer 114N is formed around the second nanostructures 66 in the N-type region 50N instead of the P-type region 50P. The N-type work function adjustment layer 114N fills the remainder of the region 50I between the second nanostructures 66 in the N-type region 50N.

In fig. 46A to 46C, the N-type work function adjustment layer 114N is patterned to remove a portion of the N-type work function adjustment layer 114N located in the P-type region 50P. The N-type work function adjustment layer 114N may be patterned similarly as described for fig. 23A-23C. A mask 132, such as photoresist, which serves as an etching mask when etching the N-type work function adjustment layer 114N may be formed in the P-type region 50P. The removal of the portion of the N-type work function adjustment layer 114N that is located in the P-type region 50P re-exposes the sacrificial structure 206 in the P-type region 50P.

In fig. 47A-47C, the sacrificial structure 206 in the P-type region 50P is removed. Removal of sacrificial structure 206 in P-type region 50P reforms opening 108 and opening 130 in P-type region 50P. The sacrificial structure 206 may be removed similarly as described with respect to fig. 44A-44C, except that the N-type work function adjustment layer 114N may be used as an etch mask when etching the sacrificial structure 206.

In fig. 48A-48C, a P-type work function adjustment layer 114P is conformally formed on the gate dielectric layer 112 such that it conformally lines the recesses 106, openings 108, and openings 130 in the P-type region 50P. The P-type work function adjustment layer 114P may be formed similarly to that described with respect to fig. 25A to 25C. Because the sacrificial structure 206 is removed from the P-type region 50P, a P-type work function adjustment layer 114P is formed around the second nanostructures 66 in the P-type region 50P. The P-type work function adjustment layer 114P fills the remainder of the region 50I between the second nanostructures 66 in the P-type region 50P.

In the illustrated embodiment, the P-type work function adjustment layer 114P is formed in the P-type region 50P and the N-type region 50N, and the N-type work function adjustment layer 114N is formed in the N-type region 50N instead of the P-type region 50P. Thus, the resulting gate structure in each region includes different materials and different numbers of layers. The gate structure in N-type region 50N may include more work function adjustment layers than the gate structure in P-type region 50P. Other work function tuning layer structures may be utilized in different regions. For example, the P-type work function adjustment layer 114P may also be patterned to remove portions of the P-type work function adjustment layer 114P that are located in the N-type region 50N, thereby exposing the N-type work function adjustment layer 114N.

In fig. 49A to 49C, the remaining portion of the gate electrode layer is formed in the grooves 106 in the P-type region 50P and the N-type region 50N. In the illustrated embodiment, a fill layer 114F (not shown in fig. 49B-49C, but see fig. 49A) is deposited over the P-type work function adjustment layer 114P and the N-type work function adjustment layer 114N (when exposed).

In fig. 50A-50C, a removal process is performed to remove excess portions of gate dielectric layer 112 and gate electrode layer 114 that are over the top surfaces of first ILD 104 and gate spacer 90, thereby forming gate dielectric 142 and gate electrode 144. Excess portions of gate dielectric layer 112 and gate electrode layer 114 may be removed similarly as described with respect to fig. 27A-27C. Further, in this embodiment, portions of the first ILD 104 extending over the top surfaces of the gate spacers 90 are removed. As shown in fig. 50A, the resulting gate structure (including gate dielectric 142 and gate electrode 144) is a pi-shaped gate structure extending along the top and sidewalls of dielectric wall 122. A gate dielectric 142 is disposed on dielectric wall 122. The gate structure is formed in a pi-shape in a self-aligned manner, avoiding one or more trimming steps due to the previously described process.

In fig. 51A-51C, isolation regions 146 may be formed to divide the gate structure (including gate dielectric 142 and gate electrode 144) into a plurality of gate structure segments. Isolation regions 146 may be formed similarly as described with respect to fig. 28A-29C, except that isolation regions 146 may be wider than underlying dielectric wall 122.

In fig. 52A-52C, a second ILD 154 is deposited over the gate spacer 90, CESL 102, first ILD 104, gate dielectric 142, gate electrode 144, and isolation region 146. The second ILD 154 may be formed similar to that described with respect to fig. 30A-30C. In some embodiments, an Etch Stop Layer (ESL) 152 is formed between the second ILD 154 and the gate spacer 90, CESL 102, first ILD 104, gate dielectric 142, gate electrode 144, and isolation region 146. The ESL 152 may be formed similarly to that described with respect to fig. 30A-30C.

In addition, gate contacts 162 and source/drain contacts 164 are formed to contact gate electrode 144 and epitaxial source/drain regions 98, respectively. The gate contact 162 and the source/drain contact 164 may be formed similarly as described for fig. 31A to 31C. Optionally, a metal-semiconductor alloy region 166 is formed at the interface between the epitaxial source/drain region 98 and the source/drain contact 164. The metal-semiconductor alloy region 166 may be formed similarly to that described with respect to fig. 31A to 31C.

As previously noted, the width of the opening 130 may be less than or equal to the width of the opening 108 (see fig. 41A-41C). Thus, the distance D between the nanostructures 66 and the dielectric wall 122 ₃ May be less than or equal to the distance D between the pair of vertical nanostructures 66 ₄ . In some embodiments, distance D ₃ In the range of 1nm to 7nmIn the enclosure and at a distance D ₄ In the range of 5nm to 12 nm. In some embodiments, distance D ₃ Less than the distance D ₄ This may reduce the resistance of the gate structure and enhance device performance. In this embodiment, the opening 130 (see fig. 41A-41C) is partially filled with a gate dielectric 142 and partially filled with a gate electrode 144 (e.g., work function adjustment layer 114N/114P).

As previously described, the dielectric wall 122 is formed on the liner layer 120. Because of this, etching of the inner spacers 96 may be avoided when patterning the dielectric walls 122. Accordingly, the gate-drain capacitance (C) between the epitaxial source/drain regions 98 and the gate electrode 144 can be reduced _gd ) And leakage, thereby improving the performance of the nanostructured FETs, particularly in AC applications. Furthermore, in the cross-section of fig. 52A, the gate structure extends around all sides of the nanostructure 66, which may improve gate control compared to other devices including dielectric walls, such as a fork-slice structure. The gate structure (including gate dielectric 142 and gate electrode 144) completely fills the respective region between nanostructure 66 and dielectric wall 122 such that gate dielectric 142 and gate electrode 144 each partially fill the respective region. In this embodiment, dielectric wall 122 is formed prior to removal of nanostructure 64 (see fig. 40A-40C).

Fig. 53 is a top view of the nanostructure FET of fig. 52A-52C, and is along reference section E-E' in fig. 52A-52C. In this embodiment, gate dielectric 142 also extends along sidewalls of dielectric wall 122. Further, gate dielectric 142 is not located between dielectric wall 122 and gate spacer 90.

Fig. 54A-54C are views of a nanostructure FET, according to some embodiments. This embodiment is similar to the embodiment of fig. 52A-52C except that the opening 130 (see fig. 41A-41C) is completely filled with gate dielectric 142. When trimming dielectric wall 122 (previously described with respect to fig. 41A-41C) is omitted so that opening 130 is smaller, gate dielectric 142 may completely fill opening 130. Thus, gate dielectric 142 completely fills the corresponding region between nanostructure 66 and dielectric wall 122. Although not separately shown in fig. 54A to 54C, the gate electrode 144 may have the structure previously described (e.g., including the work function adjustment layer 114N/114P and the filling layer 114F).

In some embodiments, the portion of gate dielectric 142 between nanostructure 66 and dielectric wall 122 has a thickness T in the range of 2nm to 5nm ₃ . In addition, the gate electrode 144 may have a vertical extension between the gate dielectric 142 and the dielectric wall 122. In some embodiments, the vertically extending portion of the gate electrode 144 has a height H in the range of 0nm to 3nm ₄ 。

Embodiments may realize advantages. Forming dielectric walls 122 between adjacent groups of nanostructures 66 allows adjacent groups of nanostructures 66 to be formed closer together. Thus device density can be improved. In addition, the gate structure around the nanostructures 66 and over the dielectric wall 122 is pi-shaped, allowing the same gate structure to control the channel region of adjacent devices. Thus, the number of gate contacts used in a CMOS process may be reduced.

In an embodiment, a device includes: an isolation region on the substrate; a first nanostructure located over the isolation region; a second nanostructure located over the isolation region; a first gate spacer on the first nanostructure; a second gate spacer on the second nanostructure; a dielectric wall positioned between the first gate spacer and the second gate spacer along a first direction in a top view, the dielectric wall being disposed between the first nanostructure and the second nanostructure along a second direction in a top view, the first direction being perpendicular to the second direction; and a gate structure located around the first nanostructure and around the second nanostructure, a first portion of the gate structure filling a first region between the dielectric wall and the first nanostructure, a second portion of the gate structure filling a second region between the dielectric wall and the second nanostructure. In some embodiments of the device, the gate structure includes a gate dielectric that completely fills the first region and the second region. In some embodiments of the device, the gate structure includes a gate dielectric and a gate electrode, the gate dielectric partially filling the first region and the second region, the gate electrode completely filling the remaining portions of the first region and the second region not filled with the gate dielectric. In some embodiments of the device, the gate structure includes a gate dielectric, and the dielectric wall is disposed on the gate dielectric. In some embodiments of the device, the gate structure includes a gate dielectric disposed on the dielectric wall. In some embodiments, the device further comprises: a liner layer is located between the dielectric wall and the isolation region. In some embodiments of the device, the sidewalls of the liner layer are recessed from the sidewalls of the dielectric wall. In some embodiments, the device further comprises: a p-type source/drain region adjacent to the first nanostructure; and an n-type source/drain region adjacent to the second nanostructure.

In an embodiment, a device includes: a trench isolation region located on the substrate; a first nanostructure over the trench isolation region; a second nanostructure over the trench isolation region; a dielectric wall having a lower portion disposed between the first nanostructure and the second nanostructure and an upper portion overlapping the first nanostructure and the second nanostructure, the upper portion being wider than the lower portion; a gate structure located around the first nanostructure and around the second nanostructure; and a gate isolation region extending through the gate structure, the gate isolation region disposed on the dielectric wall. In some embodiments of the device, the gate structure comprises: a p-type work function adjustment layer encapsulating the first nanostructure; and an n-type work function adjustment layer encapsulating the second nanostructure. In some embodiments of the device, a first portion of the p-type work function adjustment layer completely fills the first region between the first nanostructure pair and a second portion of the p-type work function adjustment layer completely fills the second region between the first nanostructure and the dielectric wall. In some embodiments of the device, the first portion of the p-type work function adjustment layer has a first thickness, the second portion of the p-type work function adjustment layer has a second thickness, and the first thickness is greater than the second thickness. In some embodiments of the device, an upper portion of the dielectric wall is wider than the gate isolation region.

In an embodiment, a method comprises: forming a first nanostructure and a second nanostructure over the trench isolation region; removing the dummy gate from the first nanostructure and the second nanostructure; after removing the dummy gate, forming a dielectric wall between the first nanostructure and the second nanostructure, the dielectric wall being separated from the first nanostructure by a first opening, the dielectric wall being separated from the second nanostructure by a second opening; depositing a gate dielectric layer over the first nanostructure and the second nanostructure, the gate dielectric layer at least partially filling the first opening and the second opening; and forming a gate electrode layer on the gate dielectric layer, the gate electrode layer being disposed over the dielectric wall. In some embodiments of the method, forming the dielectric wall comprises: depositing a liner layer over the gate dielectric layer; depositing a dielectric material on the liner layer; patterning a dielectric material, the dielectric wall comprising a remaining portion of the dielectric material between the first nanostructure and the second nanostructure; and removing portions of the liner layer around the first and second nanostructures to form first and second openings. In some embodiments of the method, a gate electrode layer is formed on the dielectric wall. In some embodiments of the method, a portion of the liner layer remains between the gate dielectric layer and the dielectric wall. In some embodiments of the method, forming the dielectric wall comprises: depositing a liner layer over the first nanostructure, the second nanostructure, and the trench isolation region; depositing a dielectric material on the liner layer; patterning a dielectric material, the dielectric wall comprising a remaining portion of the dielectric material between the first nanostructure and the second nanostructure; and removing portions of the liner layer between the dielectric material and the first nanostructures and between the dielectric material and the second nanostructures to form first and second openings. In some embodiments of the method, a gate dielectric layer is deposited on the dielectric wall. In some embodiments of the method, a portion of the liner layer remains between the trench isolation region and the dielectric wall.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art will appreciate that they may readily use the present invention as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising:

an isolation region on the substrate;

a first nanostructure located over the isolation region;

a second nanostructure located over the isolation region;

a first gate spacer on the first nanostructure;

a second gate spacer on the second nanostructure;

a dielectric wall located between the first gate spacer and the second gate spacer along a first direction in a top view, the dielectric wall being disposed between the first nanostructure and the second nanostructure along a second direction in the top view, the first direction being perpendicular to the second direction; and

A gate structure located around the first nanostructure and around the second nanostructure, a first portion of the gate structure filling a first region between the dielectric wall and the first nanostructure, a second portion of the gate structure filling a second region between the dielectric wall and the second nanostructure.

2. The semiconductor device of claim 1, wherein the gate structure comprises a gate dielectric that completely fills the first region and the second region.

3. The semiconductor device of claim 1, wherein the gate structure comprises a gate dielectric and a gate electrode, the gate dielectric partially filling the first region and the second region, the gate electrode completely filling a remaining portion of the first region and the second region not filled by the gate dielectric.

4. The semiconductor device of claim 1, wherein the gate structure comprises a gate dielectric, the dielectric wall being disposed on the gate dielectric.

5. The semiconductor device of claim 1, wherein the gate structure comprises a gate dielectric disposed on the dielectric wall.

6. The semiconductor device of claim 1, further comprising:

a liner layer is located between the dielectric wall and the isolation region.

7. The semiconductor device of claim 6 wherein sidewalls of the liner layer are recessed from sidewalls of the dielectric wall.

8. The semiconductor device of claim 1, further comprising:

a p-type source/drain region adjacent to the first nanostructure; and

an n-type source/drain region adjacent to the second nanostructure.

9. A semiconductor device, comprising:

a trench isolation region located on the substrate;

a first nanostructure located over the trench isolation region;

a second nanostructure located over the trench isolation region;

a dielectric wall having a lower portion disposed between the first and second nanostructures and an upper portion overlapping the first and second nanostructures, the upper portion being wider than the lower portion;

a gate structure located around the first nanostructure and around the second nanostructure; and

a gate isolation region extending through the gate structure, the gate isolation region disposed on the dielectric wall.

10. A method of forming a semiconductor device, comprising:

forming a first nanostructure and a second nanostructure over the trench isolation region;

removing the dummy gate from the first nanostructure and the second nanostructure;

after removing the dummy gate, forming a dielectric wall between the first nanostructure and the second nanostructure, the dielectric wall being separated from the first nanostructure by a first opening, the dielectric wall being separated from the second nanostructure by a second opening;

depositing a gate dielectric layer over the first nanostructure and the second nanostructure, the gate dielectric layer at least partially filling the first opening and the second opening; and

a gate electrode layer is formed on the gate dielectric layer, the gate electrode layer being disposed over the dielectric wall.