CN113206083A

CN113206083A - Transistor grid and forming method

Info

Publication number: CN113206083A
Application number: CN202011383732.5A
Authority: CN
Inventors: 李欣怡; 洪正隆; 徐志安
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2020-05-15
Filing date: 2020-12-01
Publication date: 2021-08-03

Abstract

The disclosure relates to transistor gates and methods of forming. A device comprising: a first nanostructure; a second nanostructure on the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure includes: a first p-type workfunction metal; a barrier material over the first p-type workfunction metal; and a second p-type workfunction metal over the barrier material, the barrier material physically separating the first p-type workfunction metal from the second p-type workfunction metal.

Description

Transistor grid and forming method

Technical Field

The present disclosure relates generally to transistor gates and methods of forming.

Background

Semiconductor devices are used in various electronic applications such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by: layers of insulating or dielectric, conductive, and semiconductor materials are sequentially deposited over a semiconductor substrate, and the various material layers are patterned using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that should be addressed.

Disclosure of Invention

According to an embodiment of the present disclosure, there is provided a semiconductor device including: a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type workfunction metal; a barrier material over the first p-type workfunction metal; and a second p-type workfunction metal over the barrier material, the barrier material physically separating the first p-type workfunction metal from the second p-type workfunction metal.

According to another embodiment of the present disclosure, there is provided a transistor including: a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode over the gate dielectric, wherein the gate electrode comprises: a p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure; an adhesion layer over the barrier material; and a filler metal over the adhesion layer.

According to still another embodiment of the present disclosure, there is provided a method of forming a semiconductor device, including: depositing a gate dielectric around first and second nanostructures, the first nanostructures disposed over the second nanostructures; depositing a p-type workfunction metal over the gate dielectric, wherein after depositing the p-type workfunction metal, an opening remains between a first portion of the p-type workfunction metal and a second portion of the p-type workfunction metal, the first portion of the p-type workfunction metal and the second portion of the p-type workfunction metal being between the first nanostructure and the second nanostructure; and depositing a barrier material over the p-type work function metal using an Atomic Layer Deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

Drawings

Various aspects of the disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 illustrates an example of a nanostructured field effect transistor (nanofet) in a three-dimensional view according to some embodiments.

Fig. 2, fig. 3, fig. 4, fig. 5, fig. 6A, fig. 6B, fig. 7A, fig. 7B, fig. 8A, fig. 8B, fig. 9A, fig. 9B, fig. 10A, fig. 10B, fig. 11A, fig. 11B, fig. 11C, fig. 12A, fig. 12B, fig. 12C, fig. 12D, fig. 13A, fig. 13B, fig. 13C, fig. 14A, fig. 14B, fig. 15A, fig. 15B, fig. 16A, fig. 16B, fig. 17A, fig. 17B, fig. 18A, fig. 18B, fig. 19A, fig. 19B, fig. 19C, fig. 19D, fig. 20A, fig. 20B, fig. 22A, fig. 22B, fig. 23A, fig. 23B, fig. 23C, fig. 24A, fig. 24B, fig. 24C, fig. 25A, fig. 25B, and fig. 25C are cross-sectional views of intermediate stages of manufacturing nano FETs according to some embodiments.

Fig. 19E is an elemental analysis of a material of a nanofet according to some embodiments.

Fig. 21 is a cross-sectional view of a nanofet according to some embodiments.

Fig. 26A, 26B, and 26C are cross-sectional views of a nanofet according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description that follows, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to readily describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The thickness of the work function metal(s) (WFM) layer in the transistor gate stack affects the threshold voltage (V) of the transistor_TH). Accordingly, it is desirable for the WFM layer to have a relatively uniform thickness to provide reduced threshold voltage variation. Various embodiments provide a semiconductor device including a relatively thin Work Function Metal (WFM) layer and a barrier on the WFM layerAnd a gate stack of the barrier layer. The barrier layer physically separates portions of the WFM layer in various regions of the gate stack (e.g., between adjacent nanostructures of a nanofet). For example, the merged region of the WFM layer may have twice the thickness of the un-merged region of the WFM layer, causing undesirable threshold voltage variations. By separating the WFM layers with barrier layers, threshold voltage variation can be advantageously reduced, thereby improving reliability and performance of the device. In addition, the barrier layer may comprise tungsten deposited using a fluorine-containing precursor. In such embodiments, fluorine from the precursor may diffuse into the gate dielectric layer of the transistor, thereby improving device performance.

Fig. 1 illustrates an example of a nano-FET (e.g., a nanowire FET, a nanosheet FET, etc.) in a three-dimensional view in accordance with some embodiments. The nanofet includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) over a fin 66 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructure 55 serves as a channel region of the nanofet. The nanostructures 55 may include p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above and between adjacent isolation regions 68. Although the isolation region 68 is shown/described as being separate from the substrate 50, as used herein, the term "substrate" may refer to a semiconductor substrate alone or a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom of fin 66 is shown as a single continuous material with substrate 50, the bottom of fin 66 and/or substrate 50 may comprise a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent isolation regions 68.

Gate dielectric 100 is over the top surface of fin 66 and along the top surface, sidewalls, and bottom surface of nanostructure 55. A gate electrode 102 is over the gate dielectric 100. Epitaxial source/drain regions 92 are disposed on gate dielectric layer 96 and fin 66 on opposite sides of gate electrode 98.

Fig. 1 further shows a reference cross section used in subsequent figures. The cross-section a-a' is along the longitudinal axis of the gate electrode 102 and in a direction perpendicular to the direction of current flow between the epitaxial source/drain regions 90 of the nanofet, for example. Cross-section B-B 'is perpendicular to cross-section a-a' and parallel to the longitudinal axis of fin 66 of the nanofet and in the direction of current flow between, for example, epitaxial source/drain regions 90 of the nanofet. Cross section C-C 'is parallel to cross section a-a' and extends through the epitaxial source/drain regions of the nanofet. For clarity, the subsequent figures refer to these reference cross sections.

Some embodiments discussed herein are discussed in the context of a nanofet formed using a gate-last process. In other embodiments, a gate first process may be used. Further, some embodiments contemplate aspects for use in planar devices, such as planar FETs, or fin field effect transistors (finfets).

Fig. 2-25C are cross-sectional views of intermediate stages of fabricating a nanofet according to some embodiments. Fig. 2 to 5, 6A, 13A, 14A, 15A, 16A, 17A, 18A, 19C, 19D, 20A, 21, 22A, 23A, 24A, 25A and 26A show the reference cross section a-a' shown in fig. 1. Fig. 6B, 7B, 8B, 9B, 10B, 11C, 12B, 12D, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 22B, 23B, 24B, 25B, and 26B illustrate a reference cross-section B-B' shown in fig. 1. Fig. 7A, 8A, 9A, 10A, 11A, 12C, 13C, 23C, 24C, 25C and 26C show the reference cross-section C-C' shown in fig. 1.

In fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. Substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a Buried Oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, which is typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon germanium, gallium arsenide phosphide, indium aluminum arsenide, aluminum gallium arsenide, indium gallium phosphide, and/or indium gallium arsenide; or a combination thereof.

The substrate 50 has a region N-type region 50N and a P-type region 50P. The N-type region 50N may be used to form an N-type device, e.g., an NMOS transistor, such as an N-type nanofet, and the P-type region 50P may be used to form a P-type device, e.g., a PMOS transistor, such as a P-type nanosfet. The N-type region 50N may be physically separated from the P-type region 50P (as shown by the spacer 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the N-type region 50N and the P-type region 50P. Although one N-type region 50N and one P-type region 50P are shown, any number of N-type regions 50N and P-type regions 50P may be provided.

Further in fig. 2, a multi-layer stack 64 is formed over the substrate 50. The multi-layer stack 64 includes alternating layers of first semiconductor layers 51A-C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the second semiconductor layer 53 will be removed and the first semiconductor layer 51 patterned to form a channel region of the nanofet in the P-type region 50P. Further, the first semiconductor layer 51 will be removed and the second semiconductor layer 53 patterned to form a channel region of the nano-FET in the N-type region 50N. However, in some embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nano-FET in the N-type region 50N, and the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form a channel region of the nano-FET in the P-type region 50P.

In other embodiments, the first semiconductor layer 51 may be removed and the second semiconductor layer 53 may be patterned to form a channel region of the nano-FET in both the N-type region 50N and the P-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed and the first semiconductor layer 51 may be patterned to form channel regions of the nanofets in both the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions in both the N-type region 50N and the P-type region 50P may have the same material composition (e.g., silicon, etc.) and may be formed simultaneously. Fig. 26A, 26B, and 26C illustrate structures resulting from such embodiments, wherein, for example, the channel regions in both the P-type region 50P and the N-type region 50N comprise silicon.

For illustrative purposes, the multi-layer stack 64 is shown as including three layers of each of the first semiconductor layer 51 and the second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first and second semiconductor layers 51, 53. Each layer in the multi-layer stack 64 may be epitaxially grown using a process such as Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), Vapor Phase Epitaxy (VPE), Molecular Beam Epitaxy (MBE), and the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nano-FET, such as silicon germanium, etc., and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nano-FET, such as silicon, carbon silicon, etc. For illustrative purposes, the multi-layer stack 64 is shown with the lowest semiconductor layer suitable for a p-type nanofet. In some embodiments, the multi-layer stack 64 may be formed such that the bottommost layer is a semiconductor layer suitable for an n-type nanofet.

The first semiconductor material and the second semiconductor material may be materials having high etch selectivity to each other. In this way, in the N-type region 50N, the first semiconductor layer 51 of the first semiconductor material may be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form a channel region of the N-type NSFETS. Similarly, in the P-type region 50P, the second semiconductor layer 53 of the second semiconductor material may be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form a channel region of the P-type NSFETS. In other embodiments, the channel regions in the N-type region 50N and the P-type region 50P may be formed simultaneously and have the same material composition, e.g., silicon germanium, etc. Fig. 26A, 26B, and 26C illustrate structures resulting from such embodiments, wherein, for example, the channel regions in both the P-type region 50P and the N-type region 50N comprise silicon.

Referring now to fig. 3, according to some embodiments, a fin 66 is formed in the substrate 50 and nanostructures 55 are formed in the multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. The etch may be any acceptable etch process such as Reactive Ion Etching (RIE), Neutral Beam Etching (NBE), the like, or combinations thereof. The etching may be anisotropic. Forming nanostructures 55 by etching multilayer stack 64 may further define first nanostructures 52A-C (collectively first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A-C (collectively second nanostructures 54) from second semiconductor layer 53. The first nanostructures 52 and the second nanostructures 54 may be further collectively referred to as nanostructures 55.

Fin 66 and nanostructures 55 may be patterned by any suitable method. For example, fin 66 and nanostructures 55 may be patterned using one or more photolithography processes, including a double patterning process or a multiple patterning process. Typically, a double or multiple patterning process combines a lithographic process and a self-aligned process, allowing for the creation of patterns with, for example, a smaller pitch than is obtainable using a single direct lithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithographic process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the fins 66.

For illustrative purposes, fig. 3 shows fins 66 in N-type region 50N and P-type region 50P as being substantially equal in width. In some embodiments, the width of fin 66 in N-type region 50N may be greater than or less than the width of fin 66 in P-type region 50P. Further, although each of fin 66 and nanostructures 55 are shown as having a consistent width throughout, in other embodiments, fin 66 and/or nanostructures 55 may have tapered (tapered) sidewalls such that the width of each of fin 66 and/or nanostructures 55 continuously increases in a direction toward substrate 50. In such embodiments, each nanostructure 55 may have a different width and be trapezoidal in shape.

In fig. 4, Shallow Trench Isolation (STI) regions 68 are formed adjacent to the fins 66. STI regions 68 may be formed by depositing an insulating material over substrate 50, fins 66, and nanostructures 55 and between adjacent fins 66. The insulating material may be an oxide (e.g., silicon oxide), nitride, or the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (fcvd), or the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In an embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, some embodiments may employ multiple layers. For example, in some embodiments, a liner (not separately shown) may first be formed along the surfaces of substrate 50, fin 66, and nanostructures 55. Thereafter, a fill material such as described above may be formed over the liner.

A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 55. In some embodiments, a planarization process may be employed, such as Chemical Mechanical Polishing (CMP), an etch back process, combinations thereof, and the like. The planarization process exposes the nanostructures 55 such that the top surfaces of the nanostructures 55 and the insulating material are flush after the planarization process is complete.

The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that an upper portion of fin 66 in region 50N and region 50P protrudes from between adjacent STI regions 68. Further, the top surface of STI region 68 may have a flat surface (as shown), a convex surface, a concave surface (e.g., a disk shape), or a combination thereof. The top surface of STI region 68 may be formed flat, convex, and/or concave by appropriate etching. STI regions 68 may be recessed using an acceptable etch process, such as an etch process that is selective to the material of the insulating material (e.g., etches the material of the insulating material at a faster rate than the material of fins 66 and nanostructures 55). For example, oxide removal using, for example, dilute hydrofluoric acid (dHF) acid may be employed.

The process described above with respect to fig. 2-4 is only one example of how fin 66 and nanostructures 55 may be formed. In some embodiments, fin 66 and/or nanostructures 55 may be formed using a mask and epitaxial growth process. For example, a dielectric layer may be formed over the top surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the underlying substrate 50. An epitaxial structure may be epitaxially grown in the trench and the dielectric layer may be recessed such that the epitaxial structure protrudes from the dielectric layer to form fin 66 and/or nanostructure 55. The epitaxial structure may include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments in which an epitaxial structure is epitaxially grown, the epitaxially grown material may be doped in situ during growth, which may avoid prior and/or subsequent implantation, but in situ doping and implantation doping may be used together.

Further, for illustrative purposes only, the first semiconductor layer 51 (and resulting nanostructures 52) and the second semiconductor layer 53 (and resulting nanostructures 54) are shown and discussed herein as including the same material in the P-type region 50P and the N-type region 50N. As such, in some embodiments, one or both of the first and second semiconductor layers 51, 53 may be different materials or may be formed in different orders in the P-type region 50P and the N-type region 50N.

Further in fig. 4, appropriate wells (not separately shown) may be formed in fin 66, nanostructure 55, and/or STI region 68. In embodiments with different well types, different implantation steps for the N-type region 50N and the P-type region 50P may be implemented using a photoresist or other mask (not separately shown). For example, a photoresist may be formed over fin 66 and STI region 68 in N-type region 50N and P-type region 50P. The photoresist is patterned to expose the P-type region 50P. The photoresist may be formed by using a spin-coating technique,and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, N-type impurity implantation is performed in the P-type region 50P, and the photoresist may be used as a mask to substantially prevent N-type impurities from being implanted into the N-type region 50N. The n-type impurity may be phosphorus, arsenic, antimony, or the like, implanted into the region at a concentration of about 10 deg.f¹³Atom/cm³To about 10¹⁴Atom/cm³Within the range of (1). After implantation, the photoresist is removed, for example, by an acceptable ashing process.

A photoresist or other mask (not separately shown) is formed over fin 66, nanostructures 55, and STI region 68 in P-type region 50P and N-type region 50N, either after or before implantation of P-type region 50P. The photoresist is patterned to expose the N-type region 50N. The photoresist may be formed using spin-coating techniques and may be patterned using acceptable photolithographic techniques. Once the photoresist is patterned, P-type impurity implantation may be performed in the N-type region 50N, and the photoresist may be used as a mask to substantially prevent P-type impurities from being implanted into the P-type region 50P. The p-type impurity may be boron, boron fluoride, indium, etc. implanted into the region at a concentration of about 10 deg.f¹⁴Atom/cm³To about 10¹⁴Atom/cm³Within the range of (1). After implantation, the photoresist may be removed, for example, by an acceptable ashing process.

After implantation of the N-type region 50N and the P-type region 50P, an anneal may be performed to repair implantation damage and activate the implanted P-type and/or N-type impurities. In some embodiments, the growth material of the epitaxial fin may be doped in-situ during growth, which may eliminate implantation, but in-situ doping and implant doping may be used together.

In fig. 5, a dummy dielectric layer 70 is formed on fin 66 and/or nanostructure 55. Dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 760, and a mask layer 74 is formed over the dummy gate layer 72. Dummy gate layer 762 may be deposited over dummy dielectric layer 70 and then planarized, for example by CMP. A mask layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive material or a non-conductive material and may be selected from the group consisting of: amorphous silicon, polysilicon (polysilicon), poly-silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 may be deposited by Physical Vapor Deposition (PVD), CVD, sputter deposition, or other techniques for depositing selected materials. The dummy gate layer 72 may be made of other materials having a high etch selectivity with respect to the etching of the isolation regions. The mask layer 74 may comprise, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across N-type region 50N and P-type region 50P. It should be noted that dummy dielectric layer 70 is shown covering only fins 66 and/or nanostructures 55 for illustration purposes only. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI regions 68 such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI regions 68.

Fig. 6A-16B illustrate various additional steps in the fabrication of an embodiment device. Fig. 6A, 7A, 8A, 9A, 10A, 11A, 12C, 13A, 13C, 14A, 15A, and 16A illustrate features in either of the region 50N or the region 50P. In fig. 6A and 6B, mask layer 74 (see fig. 5) may be patterned using acceptable photolithography and etching techniques to form mask 78. The pattern of mask 78 may then be transferred to dummy gate layer 72 and dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. Dummy gate 76 covers the corresponding channel region of fin 66. The pattern of the mask 78 may be used to physically separate each of the dummy gates 76 from adjacent dummy gates 76. Dummy gates 76 may also have a length direction that is substantially perpendicular to the length direction of respective fins 66. .

In fig. 7A and 7B, a first spacer layer 80 and a second spacer layer 82 are formed over the structure shown in fig. 6A and 6B, respectively. The first spacer layer 80 and the second spacer layer 82 are subsequently patterned to serve as spacers for forming self-aligned source/drain regions. In fig. 7A and 7B, a first spacer layer 80 is formed on the top surface of the STI region 68; the top surfaces and sidewalls of fin 66, nanostructure 55, and mask 78; and on sidewalls of dummy gate 76 and dummy gate dielectric layer 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed of a material having a different etch rate from that of the first spacer layer 80, such as silicon oxide, silicon nitride, silicon oxynitride, or the like, and may be deposited by CVD, ALD, or the like.

After the first spacer layer 80 is formed and before the second spacer layer 82 is formed, implantation for lightly doped source/drain (LDD) regions (not separately shown) may be performed. In embodiments with different device types, similar to the implantation discussed above in fig. 4, a mask (e.g., photoresist) may be formed over the N-type region 50N while exposing the P-type region 50P, and an appropriate type (e.g., P-type) of impurity may be implanted into the exposed fins 66 and nanostructures 55 in the P-type region 50P. The mask may then be removed. Subsequently, a mask (e.g., photoresist) may be formed over P-type region 50P while exposing N-type region 50N, and an appropriate type (e.g., N-type) of impurity may be implanted into exposed fin 66 and nanostructures 55 in N-type region 50N. The mask may then be removed. The n-type impurity may be any of the previously discussed n-type impurities and the p-type impurity may be any of the previously discussed p-type impurities. The lightly doped source/drain region may have a thickness of about 1 × 10¹⁵Atom/cm³To about 1X 10¹⁹Atom/cm³An impurity concentration within the range of (1). Annealing may be used to repair implant damage and activate implanted impurities.

In fig. 8A and 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form a first spacer 81 and a second spacer 83. As will be discussed in more detail below, the first and

second spacers

81, 83 serve to self-align subsequently formed source and drain regions, as well as protect the sidewalls of the fin 66 and/or the nanostructures 55 during subsequent processing. The first and second spacer layers 80, 82 may be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), and so forth. In some embodiments, the material of the second spacer layer 82 has a different etch rate than the material of the first spacer layer 80, such that the first spacer layer 80 may serve as an etch stop layer when patterning the second spacer layer 82, and such that the second spacer layer 82 may serve as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 may be etched using an anisotropic etch process, wherein the first spacer layer 80 serves as an etch stop layer, wherein the remaining portions of the second spacer layer 82 form second spacers 83, as shown in fig. 8A. Thereafter, the second spacers 83 are used as a mask while etching the exposed portions of the first spacer layer 80, thereby forming the first spacers 81 as shown in fig. 8A.

As shown in fig. 8A, first and

second spacers

81, 83 are disposed on sidewalls of fin 66 and/or nanostructure 55. As shown in fig. 8B, in some embodiments, the second spacer layer 82 may be removed from over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71, and the first spacers 81 are disposed on sidewalls of the mask 78, the dummy gate 76, and the dummy dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 may remain over the first spacer layer 80 adjacent to the mask 78, the dummy gate 76, and the dummy gate dielectric 71.

Note that the above disclosure generally describes the process of forming the spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be employed, a different sequence of steps may be employed (e.g., the first spacer 81 may be patterned before depositing the second spacer layer 82), additional spacers may be formed and removed, and so on. Further, different structures and steps may be used to form the n-type device and the p-type device.

In fig. 9A and 9B, a first recess 86 is formed in fin 66, nanostructure 55, and substrate 50, according to some embodiments. Epitaxial source/drain regions will subsequently be formed in the first recess 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and into the substrate. As shown in fig. 9A, the top surface of STI region 58 may be flush with the bottom surface of first recess 86. In various embodiments, fin 66 may be etched such that a bottom surface of first recess 86 is disposed below a top surface of STI region 68, and so on. The first recess 86 may be formed by etching the fin 66, the nanostructure 55, and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. First spacers 81, second spacers 83, and mask 78 mask portions of fin 66, nanostructure 55, and substrate 50 during an etch process for forming first recess 86. Each layer of nanostructures 55 and/or fins 66 may be etched using a single etch process or multiple etch processes. A timed etch process may be used to stop etching first recess 86 after first recess 86 reaches a desired depth.

In fig. 10A and 10B, portions of the sidewalls of the layers of the multi-layer stack 64 formed of the first semiconductor material (e.g., the first nanostructures 52) exposed by the first recess 86 are etched to form sidewall recesses 88 in the N-type region 50N, and portions of the sidewalls of the layers of the multi-layer stack 64 formed of the second semiconductor material (e.g., the second nanostructures 54) exposed by the first recess 86 are etched to form sidewall recesses 88 in the P-type region 50P. Although the sidewalls of the first nanostructures 52 and the second nanostructures 54 in the grooves 88 are shown as straight in fig. 10B, the sidewalls may be concave or convex. The sidewalls may be etched using an isotropic etch process (e.g., wet etch, etc.). A mask (not shown) may be used to protect the P-type region 50P while the first nanostructures 52 are etched using an etchant that is selective to the first semiconductor material, such that in the N-type region 50N, the second nanostructures 54 and the substrate 50 remain relatively unetched compared to the first nanostructures 52. Similarly, a mask (not shown) may be used to protect the N-type region 50N while the second nanostructures 54 are etched using an etchant selective to the second semiconductor material, such that in the P-type region 50P, the first nanostructures are compared to the second nanostructures 5452 and the substrate 50 remain relatively unetched. In embodiments where the first nanostructures 52 comprise, for example, SiGe and the second nanostructures 54 comprise, for example, Si or SiC, use may be made of a material utilizing tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)₄OH) or the like, and the sidewalls of the first nanostructures 52 in the N-type region 50N may be etched using a dry etching process utilizing hydrogen fluoride, another fluorine-based gas, or the like, and the sidewalls of the second nanostructures 54 in the P-type region 50P may be etched using a dry etching process utilizing hydrogen fluoride, another fluorine-based gas, or the like.

In fig. 11A-11C, a first interior spacer 90 is formed in the sidewall recess 88. The first internal spacers 90 may be formed by depositing an internal spacer layer (not separately shown) over the structure shown in fig. 10A and 10B. The first interior spacers 90 serve as isolation features between subsequently formed source/drain regions and the gate structure. As will be discussed in more detail below, source/drain regions will be formed in the recesses 86, and the first nanostructures 52 in the N-type region 50N and the second nanostructures 54 in the P-type region 50P will be replaced with corresponding gate structures.

The interior spacer layer can be deposited by a conformal deposition process such as CVD, ALD, etc. The interior spacer layer may comprise a material such as silicon nitride or silicon oxynitride, but any suitable material may be utilized, for example, a low dielectric constant (low-k) material having a k value of less than about 3.5. The interior spacer layer may then be anisotropically etched to form the first interior spacer 90. Although the outer sidewalls of the first interior spacers 90 are shown as being flush with the sidewalls of the second nanostructures 54 in the N-type region 50N and flush with the sidewalls of the first nanostructures 52 in the P-type region 50P, the outer sidewalls of the first interior spacers 90 may extend beyond the sidewalls of the second nanostructures 54 and/or the first nanostructures 52, respectively, or be recessed from the sidewalls of the second nanostructures 54 and/or the first nanostructures 52, respectively.

Further, although the outer sidewall of the first internal spacer 90 is shown as straight in fig. 11B, the outer sidewall of the first internal spacer 90 may be concave or convex. As an example, fig. 11C shows an embodiment in which in the n-type region 50P, the sidewalls of the first nanostructures 52 are concave, the outer sidewalls of the first interior spacers 90 are concave, and the first interior spacers are recessed from the sidewalls of the second nanostructures 54. Also shown is an embodiment in which in the P-type region 50P, the sidewalls of the second nanostructures 54 are concave, the outer sidewalls of the first interior spacers 90 are concave, and the first interior spacers are recessed from the sidewalls of the first nanostructures 52. The inner spacer layer may be etched by an anisotropic etching process such as RIE, NBE, or the like. The first internal spacers 90 may serve to prevent damage to source/drain regions (e.g., epitaxial source/drain regions 92 discussed below with respect to fig. 12A-12C) formed by a subsequent etch process (e.g., an etch process used to form a gate structure).

In fig. 12A-12C, epitaxial source/drain regions 92 are formed in the first recess 86. In some embodiments, the source/drain regions 92 may exert stress on the second nanostructures 54 in the N-type region 50N, as well as on the first nanostructures 52 in the P-type region 50P, thereby improving performance. As shown in fig. 12B, epitaxial source/drain regions 92 are formed in first recesses 86 such that each dummy gate 76 is disposed between a respective adjacent pair of epitaxial source/drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source/drain regions 92 from the dummy gate 72 by an appropriate lateral distance, and the first inner spacers 90 are used to separate the epitaxial source/drain regions 92 from the nanostructures 55 by an appropriate lateral distance, such that the epitaxial source/drain regions 92 do not short the gates of the subsequently formed resulting nanofets.

Epitaxial source/drain regions 92 in N-type region 50N (e.g., NMOS region) may be formed by masking P-type region 50P (e.g., PMOS region). Epitaxial source/drain regions 92 are then epitaxially grown in the first recess 86 in the N-type region 50N. Epitaxial source/drain regions 92 may comprise any acceptable material suitable for n-type nanofets. For example, if the second nanostructures 54 are silicon, the epitaxial source/drain regions 92 may comprise a material that exerts a tensile strain on the second nanostructures 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphorus, and the like. The epitaxial source/drain regions 92 may have surfaces that protrude from respective upper surfaces of the nanostructures 55, and may have facets.

Epitaxial source/drain regions 92 in P-type region 50P (e.g., PMOS region) may be formed by masking N-type region 50N (e.g., NMOS region). Epitaxial source/drain regions 92 are then epitaxially grown in the first recess 86 in the P-type region 50P. Epitaxial source/drain regions 92 may comprise any acceptable material suitable for a p-type nanofet. For example, if the first nanostructures 52 are silicon germanium, the epitaxial source/drain regions 92 may comprise a material that exerts a compressive strain on the first nanostructures 52, such as silicon germanium, boron-doped silicon germanium, germanium tin, or the like. The epitaxial source/drain regions 92 may also have surfaces that are raised from corresponding surfaces of the multi-layer stack 64 and may have facets.

The epitaxial source/drain regions 92, the first nanostructures 52, the second nanostructures 54, and/or the substrate 50 may be implanted with dopants to form source/drain regions, similar to the processes previously discussed for forming lightly doped source/drain regions, and then annealed. The impurity concentration of the source/drain region may be about 1 × 10¹⁹Atom/cm³And about 1X 10²¹Atom/cm³In the meantime. The n-type and/or p-type impurities for the source/drain regions may be any of the previously discussed impurities. In some embodiments, the epitaxial source/drain regions 92 may be doped in-situ during growth.

As a result of the epitaxial process used to form the epitaxial source/drain regions 92 in the N-type region 50N and the P-type region 50P, the upper surface of the epitaxial source/drain regions 92 have facets that extend laterally outward beyond the sidewalls of the nanostructures 55. In some embodiments, these facets cause adjacent epitaxial source/drain regions 92 of the same NSFET to merge, as shown in FIG. 12A. In other embodiments, the adjacent epitaxial source/drain regions 92 remain separated after the epitaxial process is completed, as shown in fig. 12C. In the embodiment shown in fig. 12A and 12C, the first spacers 81 may be formed on the top surface of the STI regions 68, thereby preventing epitaxial growth. In some other embodiments, the first spacer 81 may cover portions of the sidewalls of the nanostructures 55, further preventing epitaxial growth. In some other embodiments, the spacer etch used to form the first spacers 81 may be adjusted to remove the spacer material to allow the epitaxially grown regions to extend to the surface of the STI regions 58.

The epitaxial source/drain regions 92 may include one or more layers of semiconductor material. For example, the epitaxial source/drain regions 92 may include a first layer of semiconductor material 92A, a second layer of semiconductor material 92B, and a third layer of semiconductor material 92C. Any number of layers of semiconductor material may be used for the epitaxial source/drain regions 92. Each of the first, second, and third semiconductor material layers 92A, 92B, and 92C may be formed of a different semiconductor material and may be doped to a different dopant concentration. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration less than the second semiconductor material layer 92B and greater than the third semiconductor material layer 92C. In embodiments in which the epitaxial source/drain regions 92 include three layers of semiconductor material, a first layer of semiconductor material 92A may be deposited, a second layer of semiconductor material 92B may be deposited over the first layer of semiconductor material 92A, and a third layer of semiconductor material 92C may be deposited over the second layer of semiconductor material 92B.

Fig. 12D illustrates an embodiment in which the sidewalls of the first nanostructures 52 in the N-type region 50N and the sidewalls of the second nanostructures 54 in the P-type region 50P are concave, the outer sidewalls of the first interior spacers 90 are concave, and the first interior spacers 90 are recessed from the sidewalls of the second nanostructures 54 and the first nanostructures 52, respectively. As shown in fig. 12D, an epitaxial source/drain region 92 may be formed in contact with the first interior spacer 90 and may extend beyond the sidewalls of the second nanostructures 54 in the N-type region 50N and beyond the sidewalls of the first nanostructures 52 in the P-type region 50P.

In fig. 13A-13C, a first interlayer dielectric (ILD)96 is deposited over the structures shown in fig. 6A, 12B, and 12A, respectively (the process of fig. 7A-12D does not change the cross-section shown in fig. 6A). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (pecvd), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), Undoped Silicate Glass (USG), and the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a Contact Etch Stop Layer (CESL)94 is disposed between the first ILD 96 and the epitaxial source/drain regions 92, the mask 74, and the first spacers 81. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the overlying first ILD 96.

In fig. 14A-14B, a planarization process, such as CMP, may be performed to level the top surface of the first ILD 96 with the top surface of the dummy gate 76 or mask 78. The planarization process may also remove the mask 78 on the dummy gate 76, as well as portions of the first spacers 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within process variations. Thus, the top surface of the dummy gate 72 is exposed by the first ILD 96. In some embodiments, the mask 78 may remain, in which case the planarization process makes the top surface of the first ILD 96 flush with the top surfaces of the mask 78 and the first spacers 81.

In fig. 15A and 15B, dummy gate 72 and mask 74 (if present) are removed in one or more etching steps to form second recess 98. Portions of the dummy gate dielectric 60 in the second recess 98 may also be removed. In some embodiments, the dummy gate 72 and the dummy gate dielectric 60 are removed by an anisotropic dry etch process. For example, the etching process may include a dry etching process using reactive gas (es) that selectively etch the dummy gate 72 at a faster rate than the first ILD 96 or the first spacer 81. Each second recess 98 exposes and/or overlies portions of the nanostructures 55 that serve as channel regions in a subsequently completed nanofet. The portion of the nanostructure 55 that serves as the channel region is disposed between adjacent pairs of the epitaxial source/drain regions 92. During removal, the dummy dielectric layer 60 may serve as an etch stop layer when etching the dummy gate 72. The dummy dielectric layer 60 may then be removed after the dummy gate 72 is removed.

In fig. 16A and 16B, the second nanostructures 54 in the P-type region 50P may be removed by forming a mask (not shown) over the N-type region 50N and performing an isotropic etching process (e.g., wet etching, etc.) using an etchant selective to the material of the second nanostructures 54, while the first nanostructures 52, the substrate 50, and the STI regions 58 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 comprise, for example, SiGe and the first nanostructures 52 comprise, for example, Si or SiC, hydrogen fluoride, another fluorine-based gas, or the like may be used to remove the second nanostructures 54 in the P-type region 50P.

In other embodiments, the channel regions in the N-type region 50N and the P-type region 50P may be formed simultaneously, for example, by removing the first nanostructures 52 in both the N-type region 50N and the P-type region, or by removing the second nanostructures 54 in both the N-type region 50N and the P-type region 50P. In such embodiments, the channel regions of the n-type and p-type NSFETs may have the same material composition, e.g., silicon germanium, etc. Fig. 26A, 26B and 26C show structures resulting from embodiments in which channel regions in both the P-type region 50P and the N-type region 50N are provided by the second nanostructure 54 and comprise, for example, silicon.

In fig. 17A-22B, a gate dielectric layer and a gate electrode are formed for the replacement gate in the second recess 98, according to some embodiments. The gate electrode includes a barrier layer surrounding the WFM layer, which physically separates portions of the WFM layer in certain regions of the gate stack (e.g., between the nanostructures 52/54). Accordingly, the WFM layer may have good thickness uniformity regardless of its position in the gate stack, and may advantageously reduce threshold voltage variation. Further, in some embodiments, the barrier layer comprises tungsten deposited using a fluorine-containing precursor, which allows fluorine to diffuse into the underlying gate dielectric. It has been observed that incorporating fluorine into the gate dielectric can improve the reliability of the device.

The formation of the gate dielectric in N-type region 50N and P-type region 50P may occur simultaneously such that the gate dielectric in each region is formed of the same material, and the formation of the gate electrode may occur simultaneously such that the gate electrode in each region is formed of the same material. In some embodiments, the gate dielectric in each region may be formed by a different process such that the gate dielectric may be a different material and/or have a different number of layers, and/or the gate electrode in each region may be formed by a different process such that the gate electrode may be a different material and/or have a different number of layers. When different processes are used, various masking steps may be used to mask and expose the appropriate areas. In the following description, the gate electrode of the N-type region 50N and the gate electrode of the P-type region 50P are separately formed.

Fig. 17A-20B illustrate forming a gate dielectric 100 and a gate electrode 102 in a P-type region 50P, and may mask an n-type region 50P at least when forming the gate electrode 102 in the P-type region (e.g., as described below with respect to fig. 18A-20B).

In fig. 17A and 17B, a gate dielectric 100 is conformally deposited in the second recess 98 of the P-type region 50P. The gate dielectric 100 includes one or more dielectric layers, such as an oxide, a metal oxide, or the like, or combinations thereof. For example, in some embodiments, the gate dielectric 100 may include a first gate dielectric 101 (e.g., comprising silicon oxide, etc.) and a second gate dielectric 103 (e.g., comprising metal oxide, etc.) over the first gate dielectric 101. In some embodiments, the second gate dielectric 103 comprises a high-k dielectric material, and in such embodiments, the second gate dielectric 103 may have a k value greater than about 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the first gate dielectric 101 may be referred to as an interfacial layer and the second gate dielectric 103 may be referred to as a high-k gate dielectric.

The structure of the gate dielectric 100 may be the same or different in the N-type region 50N and the P-type region 50P. For example, the N-type region 50N may be masked or exposed while the gate dielectric 100 is formed in the P-type region 50P. In embodiments in which the N-type region 50N is exposed, the gate dielectric 100 may be formed simultaneously in the N-type region 50N. The method of forming the gate dielectric 100 may include Molecular Beam Deposition (MBD), ALD, PECVD, and the like.

In fig. 18A and 18B, a conductive material 105 is conformally deposited on the gate dielectric 100 in the P-type region 50P. In some embodiments, conductive material 105 is a p-type WFM, including titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, and the like. The conductive material 105 may be deposited by CVD, ALD, PECVD, PVD, and the like. The conductive material 105 may have a thickness T1 on the surface of the nanostructures 52, and the ratio of the thickness T1 to the distance D1 between adjacent nanostructures 52 may be in the range of about 0.05 to about 0.2. It has been observed that by having a ratio of thickness T1 to distance D1 within this range, undesirable merging of conductive material 105 can be avoided. For example, by keeping the ratio within the above range, the conductive material 105 may remain unmerged. As a result, the thickness of the conductive material 105 in the interior region 50I (e.g., between adjacent nanostructures 52) may be substantially equal to the thickness of the conductive material 105 outside of the interior region 50I. As a result, the threshold voltage variation of the resulting device can be advantageously reduced. For example, the opening 130 remains in the interior region 50I between a first portion of the conductive material 105 (e.g., a portion on the lower surface of the first nanostructure 52) and a second portion of the conductive material 105 (e.g., a portion on the upper surface of the first nanostructure 52).

In fig. 19A, 19B, and 19C, a barrier material 107 is conformally deposited over the conductive material 105. In some embodiments, the barrier material 107 comprises tungsten and is deposited by a deposition process 109. The deposition process 109 may be an ALD process or the like. In some embodiments, the process temperature of the deposition process 109 may be in a range of about 250 ℃ to about 450 ℃. It has been observed that deposition temperatures below about 250 ℃ may result in unacceptably low deposition rates, thereby adversely affecting production yields. It has also been observed that deposition temperatures above 450 ℃ may result in process tool damage (e.g., ALD deposition chamber damage). In some embodiments, the deposition process 109 may be performed at a pressure of about 0.5Torr to about 20 Torr. It has been observed that deposition pressures outside of this range (e.g., less than about 0.5Torr or greater than about 20Torr) may result in an inability to precisely control the deposition process, thereby adversely affecting yield.

Further, the deposition process 109 may include flowing one or more precursors into the deposition chamber, and the one or more precursors may include a fluorine-containing precursor. For example, during the deposition process 109, a first precursor (e.g., WF)₆Etc.) and a second precursor (e.g., SiH₄Etc.) may be sequentially flowed into the process chamber. The first precursor and the second precursor may react with the exposed surface of the wafer to form a monolayer of barrier material 107. In the deposition process 109, a first precursor (e.g., WF)₆Etc.) with a second precursor (e.g., SiH₄Etc.) may be in the range of about 0.75 to about 1.25. In the deposition process 109, the first precursor and the second precursor may be alternately provided into the deposition chamber. The first precursor and the second precursor can each be flowed at a rate of about 30sccm to about 300sccm and each be flowed with a pulse time of about 0.5 seconds to about 60 seconds. It has been observed that by maintaining the precursor ratio, flow rate, and/or pulse time within the above-described ranges during the deposition process 109, a desired fluorine concentration may be achieved in the gate dielectric layer 109.

In some embodiments, the deposition process 109 may cause fluorine to diffuse into the underlying gate dielectric 100. For example, fig. 19C shows a detailed view of region 111 during deposition process 109. By using a fluorine-containing precursor, fluorine particles 113 diffuse through the barrier material 107 and the conductive material 105 into the gate dielectric 100. As a result, fluorine may be present in the conductive material 105 and the gate dielectric 100. This is also shown in fig. 19E, which shows an energy dispersive X-ray spectroscopy (EDS) line scan curve (linescan) along line 115 of fig. 19A and 19B after the deposition process 109 is performed. As shown in fig. 19E, fluorine is present in the conductive material 105 and the gate dielectric 100.

For example, the fluorine concentration in the second gate dielectric layer 103 may be in a range of about 0.5% to about 10% as a result of the deposition process 109. It has been observed that having a fluorine concentration within this range has advantages, such as improved device reliability. For example, when the second gate dielectric layer 103 has a fluorine concentration of less than 0.5%, device reliability may be deteriorated. As another example, when the second gate dielectric 103 has a fluorine concentration greater than 10%, the Capacitance Equivalent Thickness (CET) of the second gate dielectric 103 may deteriorate. By controlling the mixture of the first precursor and the second precursor (e.g., in the ratios, flow rates, and/or pulse times described above), a desired fluorine concentration may be achieved in one or more of the gate dielectrics 100.

The barrier material 107 may fill the remaining portions of the interior region 50I between the first nanostructures 52 (e.g., fill the openings 130, see fig. 18A and 18B). For example, the barrier material 107 may be deposited on the conductive material 105 until it fuses and welds together, and in some embodiments, an interface 107I may be formed by a first portion 107A (e.g., the first barrier material 107A) of the barrier material 107, which interface 107I contacts a second portion 107B (e.g., the second barrier material 107B) of the barrier layer 107 in the region 50I.

Fig. 19D illustrates a detailed cross-sectional view of the interior region 50I between adjacent nanostructures 52, according to some embodiments. In the resulting structure, the stack of materials in the interior region 50I may include: a first portion of the gate dielectric 100 (e.g., the first gate dielectric 100A), a first portion of the conductive material 105 (e.g., the first conductive material 105A) over the gate dielectric 100A, a first blocking material 107A, a second blocking material 107B over the first blocking material 107A and forming an interface with the first blocking material 107A, a second portion of the conductive material 105 (e.g., the second conductive material 105B) over the second blocking material 107B, and a second portion of the gate dielectric 100 (e.g., the second gate dielectric 100B) over the second conductive material 105B. The first gate dielectric 100A includes an interface layer 101A and a high-k gate dielectric 103A, and the second gate dielectric 100B includes an interface layer 101B and a high-k gate dielectric 103B. The first barrier material 107A and the second barrier material 107B physically separate the first conductive material 105A and the second conductive material 105B in the inner region 50I, and may prevent merging of the conductive materials 105. As a result, the thickness of the conductive material 105 in the region 50I may be substantially equal to the thickness of the conductive material 105 outside the region 50I (e.g., within process variations), and threshold voltage variations may be reduced.

In other embodiments, the barrier material 107 may comprise a different material and/or be deposited using a different process. For example, the barrier material 107 includes a conductive material deposited using a process that may or may not use a fluorine-containing precursor.

In fig. 20A and 20B, the remaining portion of the gate electrode 102 is deposited to fill the remaining portion of the second recess 98. For example, an adhesion layer 117 and a fill metal 119 may be deposited over the barrier material 107. The formed gate electrode 102 is formed for a replacement gate and may include a conductive material 105, a barrier material 107, an adhesion layer 117, and a fill metal 119.

In some embodiments, adhesion layer 117 is conformally deposited on barrier material 107 in P-type region 50P. In some embodiments, adhesion layer 117 comprises titanium nitride, tantalum nitride, or the like. Adhesion layer 117 may be deposited by CVD, ALD, PECVD, PVD, and the like. The adhesion layer 117 may alternatively be referred to as a glue layer (glue layer) and improves the adhesion between the barrier material 107 and the overlying fill metal 119, for example.

A fill metal 119 may then be deposited over the adhesion layer 117. In some embodiments, the fill metal 119 comprises cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like, deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 119 may have the same material composition as the barrier material 107. In such embodiments, the fill metal 119 may be deposited using a different process than the barrier material 107. For example, the fill metal 119 may comprise tungsten deposited using a CVD process, and the barrier material 107 may comprise tungsten deposited using an ALD process. It has been observed that CVD provides an improved deposition rate for the fill metal 119, while ALD processes provide improved thickness control for the barrier material 107 for precise deposition in small regions (e.g., in the interior region 50I, see fig. 19A). In some embodiments, the CVD process used to deposit the fill metal 119 may use the same precursors as the ALD process 109. For example, forThe CVD process of the fill metal 119 may include supplying a first precursor (e.g., WF) in a CVD process chamber₆Etc.) and a second precursor (e.g., SiH₄Etc.). In some embodiments, the first precursor and the second precursor may be supplied simultaneously during a CVD process for the fill metal 119, while the first precursor and the second precursor are supplied alternately during the ALD process 109.

In the P-type region 50P, the gate dielectric 100, the conductive material 105, the barrier material 107, the adhesion layer 117, and the fill metal 119 may be formed on the top surface, the sidewalls, and the bottom surface of the first nanostructure 52, respectively. The gate dielectric 100, conductive material 105, barrier material 107, adhesion layer 117, and fill metal 119 may also be deposited on the top surfaces of the first ILD 96, CESL 94, first spacer 81, and STI regions 58. After filling the second recess 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 100, the conductive material 105, the barrier material 107, the adhesion layer 117, and the fill metal 119, which are above the top surface of the first ILD 96. The remainder of the material of gate electrode 102 and gate dielectric 100 thus forms the replacement gate structure of the resulting nanofet. The gate electrode 102 and the gate dielectric 100 may be collectively referred to as a "gate structure".

Although fig. 20A and 20B illustrate the gate dielectric 100 and the gate electrode 102 as having straight sidewalls and right angles, the gate dielectric 100 and the gate electrode 102 may have different configurations. For example, fig. 21 shows a cross-sectional view of a gate dielectric 100 and a gate electrode 102 according to another embodiment. In fig. 21, the same reference numerals denote the same elements as those of fig. 20A and 20B formed using the same process. However, in fig. 21, since the nanostructure 51 has a rounded corner, the gate dielectric 100 and the gate electrode 102 may also have a rounded corner.

Fig. 22A and 22B show the gate stack in the N-type region 50N. Forming the gate stack in the N-type region 50N may include first removing the first nanostructure 52 in the N-type region 50N. A mask (not shown) may be formed over P-type region 50P and an etchant selective to the material of first nanostructure 52, such as a wet etch, may be usedEtc., while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructures 52, to remove the first nanostructures 52. In embodiments where the first nanostructures 52A-52C comprise, for example, SiGe and the second nanostructures 54A-54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH)₄OH) or the like to remove the first nanostructures 52 in the N-type region 50N.

A gate stack is then formed over and around the second nanostructure 54 in the N-type region 50N. The gate stack includes a gate dielectric 100 and a gate electrode 127. In some embodiments, the gate dielectric 100 in the N-type region 50N and the P-type region 50P may be formed simultaneously. Further, at least a part of the gate electrode 127 may be formed before or after forming the gate electrode 102 (see fig. 20A and 20B), and at least a part of the gate electrode 127 may be formed while masking the P-type region 50P. As such, the gate electrode 127 may include a different material than the gate electrode 102. For example, the gate electrode 127 may include a conductive layer 121, a barrier layer 123, and a fill metal 125. Conductive layer 121 may be an n-type workfunction metal (WFM) layer comprising an n-type metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. The conductive layer 121 can be deposited by CVD, ALD, PECVD, PVD, and the like. Barrier layer 123 can include titanium nitride, tantalum nitride, tungsten carbide, combinations thereof, and the like, and barrier layer 123 can further serve as an adhesion layer. The barrier layer 123 may be deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 125 comprises cobalt, ruthenium, aluminum, tungsten, combinations thereof, and the like, deposited by CVD, ALD, PECVD, PVD, and the like. The fill metal 125 may or may not have the same material composition as the fill metal 119 and may or may not be deposited at the same time as the fill metal 119.

After filling the second recesses 98, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric 100 and the gate electrode 127 that are above the top surface of the first ILD 96. The remainder of the material of gate electrode 127 and gate dielectric 100 thus forms the replacement gate structure of the resulting nanofet of N-type region 50N. The CMP process for removing the excess material of the gate electrode 102 in the P-type region 50P and the CMP process for removing the excess material of the gate electrode 127 in the N-type region 50N may be performed simultaneously or separately.

In fig. 23A-23C, the gate structure (including gate dielectric 100, gate electrode 102, and gate electrode 127) is recessed, forming a recess directly above the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material (e.g., silicon nitride, silicon oxynitride, etc.) is filled in the recess and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 96. A subsequently formed gate contact (e.g., gate contact 114 discussed below with reference to fig. 24A and 24B) contacts the top surface of the recessed gate electrode 102 through the gate mask 104.

As further shown in fig. 23A-23C, a second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and may be deposited by any suitable method such as CVD, PECVD, etc.

In fig. 24A-24C, the second ILD 106, first ILD 96, CESL 94 and gate mask 104 are etched to form a third recess 108 exposing the surface of the epitaxial source/drain regions 92 and/or gate structure. The third groove 108 may be formed by etching using an anisotropic etching process (e.g., RIE, NBE, etc.). In some embodiments, the third recess 108 may be etched through the second ILD 106 and the first ILD 96 using a first etch process; a second etch process may be used to etch through the gate mask 104; and then a third etch process may be used to etch through CESL 94. A mask (e.g., photoresist) may be formed over the second ILD 106 and patterned to mask portions of the second ILD 106 from the first and second etch processes. In some embodiments, the etching process may over-etch, and thus, the third recess 108 extends into the epitaxial source/drain region 92 and/or the gate structure, and the bottom of the third recess 108 may be flush (e.g., at the same level or at the same distance from the substrate) or lower (e.g., closer to the substrate) than the epitaxial source/drain region 92 and/or the gate structure. Although fig. 24B shows the third recess 108 exposing the epitaxial source/drain regions 92 and the gate structure with the same cross-section, in various embodiments, the epitaxial source/drain regions 92 and the gate structure may be exposed with different cross-sections, thereby reducing the risk of shorting of subsequently formed contacts.

After the third recess 108 is formed, silicide regions 110 are formed over the epitaxial source/drain regions 92. In some embodiments, the silicide regions 110 are formed by: a metal, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, capable of reacting with the underlying semiconductor material (e.g., silicon germanium, germanium) of the epitaxial source/drain regions 92 to form silicide or germanide regions is first deposited over the exposed portions of the epitaxial source/drain regions 92, and then a thermal annealing process is performed to form the silicide regions 110. Unreacted portions of the deposited metal are then removed, for example by an etching process. Although silicide regions 110 are referred to as silicide regions, silicide regions 110 may also be germanide regions, or silicide-germanide regions (e.g., regions comprising silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness in a range between about 2nm and about 10 nm.

Next, in fig. 25A-C, contacts 112 and 114 (which may also be referred to as contact plugs) are formed in the third recess 108.

Contacts

112 and 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a fill material. For example, in some embodiments,

contacts

112 and 114 each include a barrier layer and a conductive material and are electrically coupled to underlying conductive features (e.g., gate electrode 102, gate electrode 127, and/or silicide region 110 in the illustrated embodiment). Contact 114 is electrically coupled to

gate electrodes

102 and 127 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source/drain contact. The barrier layer may comprise titanium, titanium nitride, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of the second ILD 106.

Fig. 26A-C illustrate cross-sectional views of devices according to some alternative embodiments. Fig. 26A shows the reference section a-a' shown in fig. 1. Fig. 26B shows a reference section B-B' shown in fig. 1. Fig. 26C shows the reference section C-C' shown in fig. 1. In fig. 26A-C, like reference numerals denote like elements formed by the same process as the structure of fig. 25A-C. However, in fig. 26A-C, the channel regions in the N-type region 50N and the P-type region 50P comprise the same material. For example, the second nanostructure 54 comprising silicon provides a channel region for a P-type NSFET in a P-type region 50P and a channel region for an N-type NSFET in an N-type region 50N. The structures of fig. 26A-C may be formed, for example, by: simultaneously removing the first nanostructure 52 from both the P-type region 50P and the N-type region 50N; depositing a gate dielectric 100 and a gate electrode 102 around the second nanostructure 54 in the P-type region 50P; and depositing a gate dielectric 100 and a gate electrode 104 around the first nanostructure 54 in the N-type region 50N.

Various embodiments provide a gate stack including a relatively thin WFM layer and a barrier layer on the WFM layer. The barrier layer physically separates portions of the WFM layer in various regions of the gate stack (e.g., between adjacent nanostructures of a nanofet). By separating the WFM layer from the barrier layer, threshold voltage variation may be advantageously reduced, thereby improving reliability and performance of the device. In addition, the barrier layer may be deposited by a process that provides a fluorine-containing precursor. In such embodiments, fluorine from the precursor may diffuse into the gate dielectric layer of the transistor, thereby improving device performance.

In some embodiments, a device comprises: a first nanostructure; a second nanostructure on the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric. A portion of the gate electrode between the first nanostructure and the second nanostructure includes: a first p-type workfunction metal; a barrier material over the first p-type workfunction metal; and a second p-type workfunction metal over the barrier material, the barrier material physically separating the first p-type workfunction metal from the second p-type workfunction metal. Optionally, in some embodiments, the barrier material comprises tungsten. Optionally, in some embodiments, the first p-type workfunction metal and the second p-type workfunction metal each comprise titanium nitride. Optionally, in some embodiments, the first p-type workfunction metal has a first thickness, the first nanostructure is spaced apart from the second nanostructure by a first distance, and the ratio of the first thickness to the first distance is in the range of 0.05 to 0.2. Optionally, in some embodiments, the first high-k gate dielectric comprises fluorine. Optionally, in some embodiments, the fluorine concentration in the first high-k gate dielectric is in a range of 0.5% to 10%. Optionally, in some embodiments, the gate electrode further comprises an adhesion layer over the barrier material, the adhesion layer not extending between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the adhesion layer has the same material composition as the first p-type workfunction metal.

In some embodiments, a transistor includes: a first nanostructure over a semiconductor substrate; a second nanostructure on the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode over the gate dielectric. The gate electrode includes: a p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure; an adhesion layer over the barrier material; and a filler metal over the adhesion layer. Optionally, in some embodiments, the barrier material comprises a first barrier material and a second barrier material, the first barrier material forming an interface with the second barrier material, the first barrier material and the second barrier material extending into a region between the first nanostructure and the second nanostructure. Optionally, in some embodiments, the barrier material comprises tungsten and the p-type workfunction metal comprises titanium nitride. Optionally, in some embodiments, a ratio of a thickness of the p-type workfunction metal to a distance between the first nanostructure and the second nanostructure is in a range of 0.05 to 0.2. Optionally, in some embodiments, the gate dielectric comprises fluorine. Optionally, in some embodiments, the p-type workfunction metal comprises fluorine. Optionally, in some embodiments, the transistor further comprises an interfacial layer surrounding the first nanostructure and the second nanostructure under the gate dielectric, and the gate dielectric comprises a high-k material.

In some embodiments, a method comprises: depositing a gate dielectric around the first nanostructure and the second nanostructure, the first nanostructure disposed over the second nanostructure; depositing a p-type workfunction metal over the gate dielectric, wherein after depositing the p-type workfunction metal, an opening remains between a first portion of the p-type workfunction metal and a second portion of the p-type workfunction metal, the first portion of the p-type workfunction metal and the second portion of the p-type workfunction metal being between the first nanostructure and the second nanostructure; and depositing a barrier material over the p-type work function metal using an Atomic Layer Deposition (ALD) process, wherein the barrier material fills an opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal. Optionally, in some embodiments, the ALD process includes depositing a barrier material using a fluorine-containing precursor. Optionally, in some embodiments, the fluorine-containing precursor is WF₆. Optionally, in some embodiments, the ALD process includes flowing the fluorine-containing precursor at a rate of 30sccm to 300 sccm. Optionally, in some embodiments, the ALD process comprises flowing the fluorine-containing precursor for a pulse time in a range of 0.5 seconds to 60 seconds.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Example 1 is a semiconductor device including: a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type workfunction metal; a barrier material over the first p-type workfunction metal; and a second p-type workfunction metal over the barrier material, the barrier material physically separating the first p-type workfunction metal from the second p-type workfunction metal.

Example 2 is the device of example 1, wherein the barrier material comprises tungsten.

Example 3 is the device of example 1, wherein the first p-type workfunction metal and the second p-type workfunction metal each comprise titanium nitride.

Example 4 is the device of example 1, wherein the first p-type workfunction metal has a first thickness, the first nanostructure is spaced apart from the second nanostructure by a first distance, and a ratio of the first thickness to the first distance is in the range of 0.05 to 0.2.

Example 5 is the device of example 1, wherein the first high-k gate dielectric comprises fluorine.

Example 6 is the device of example 5, wherein a fluorine concentration in the first high-k gate dielectric is in a range of 0.5% to 10%.

Example 7 is the device of example 1, wherein the gate electrode further includes an adhesion layer over the barrier material, the adhesion layer not extending between the first nanostructure and the second nanostructure.

Example 8 is the device of example 7, wherein the adhesion layer has a same material composition as the first p-type workfunction metal.

Example 9 is a transistor, comprising: a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate dielectric surrounding the first nanostructure and the second nanostructure; and a gate electrode over the gate dielectric, wherein the gate electrode comprises: a p-type work function metal; a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure; an adhesion layer over the barrier material; and a filler metal over the adhesion layer.

Example 10 is the transistor of example 9, wherein the barrier material includes a first barrier material and a second barrier material, the first barrier material forming an interface with the second barrier material, the first barrier material and the second barrier material extending into the region between the first nanostructure and the second nanostructure.

Example 11 is the transistor of example 9, wherein the blocking material comprises tungsten and the p-type workfunction metal comprises titanium nitride.

Example 12 is the transistor of example 9, wherein a ratio of a thickness of the p-type workfunction metal to a distance between the first nanostructure and the second nanostructure is in a range of 0.05 to 0.2.

Example 13 is the transistor of example 9, wherein the gate dielectric includes fluorine.

Example 14 is the transistor of example 9, wherein the p-type workfunction metal comprises fluorine.

Example 15 is the transistor of example 9, further comprising: an interfacial layer underlying the gate dielectric, the interfacial layer surrounding the first and second nanostructures, and the gate dielectric comprising a high-k material.

Example 16 is a method of forming a semiconductor device, comprising: depositing a gate dielectric around first and second nanostructures, the first nanostructures disposed over the second nanostructures; depositing a p-type workfunction metal over the gate dielectric, wherein after depositing the p-type workfunction metal, an opening remains between a first portion of the p-type workfunction metal and a second portion of the p-type workfunction metal, the first portion of the p-type workfunction metal and the second portion of the p-type workfunction metal being between the first nanostructure and the second nanostructure; and depositing a barrier material over the p-type work function metal using an Atomic Layer Deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal.

Example 17 is the method of example 16, wherein the ALD process comprises depositing the barrier material using a fluorine-containing precursor.

Example 18 is the method of example 17, wherein the fluorine-containing precursor is WF₆。

Example 19 is the method of example 17, wherein the ALD process comprises flowing the fluorine-containing precursor at a rate of 30 seem to 300 seem.

Example 20 is the method of example 17, wherein the ALD process comprises flowing the fluorine-containing precursor for a pulse time in a range of 0.5 seconds to 60 seconds.

Claims

1. A semiconductor device, comprising:

a first nanostructure;

a second nanostructure over the first nanostructure;

a first high-k gate dielectric around the first nanostructure;

a second high-k gate dielectric around the second nanostructure; and

a gate electrode over the first high-k gate dielectric and the second high-k gate dielectric, wherein a portion of the gate electrode between the first nanostructure and the second nanostructure comprises:

a first p-type workfunction metal;

a barrier material over the first p-type workfunction metal; and

a second p-type workfunction metal above the barrier material, the barrier material physically separating the first p-type workfunction metal from the second p-type workfunction metal.

2. The device of claim 1, wherein the barrier material comprises tungsten.

3. The device of claim 1 wherein the first and second p-type workfunction metals each comprise titanium nitride.

4. The device of claim 1, wherein the first p-type workfunction metal has a first thickness, the first nanostructure is spaced apart from the second nanostructure by a first distance, and the ratio of the first thickness to the first distance is in the range of 0.05 to 0.2.

5. The device of claim 1, wherein the first high-k gate dielectric comprises fluorine.

6. The device of claim 5, wherein the fluorine concentration in the first high-k gate dielectric is in the range of 0.5% to 10%.

7. The device of claim 1, wherein the gate electrode further comprises an adhesion layer over the barrier material, the adhesion layer not extending between the first nanostructure and the second nanostructure.

8. The device of claim 7, wherein the adhesion layer has the same material composition as the first p-type workfunction metal.

9. A transistor, comprising:

a first nanostructure over a semiconductor substrate;

a second nanostructure over the first nanostructure;

a gate dielectric surrounding the first nanostructure and the second nanostructure; and

a gate electrode over the gate dielectric, wherein the gate electrode comprises:

a p-type work function metal;

a barrier material on the p-type work function metal, the barrier material physically separating a first portion of the p-type work function metal from a second portion of the p-type work function metal in a region between the first nanostructure and the second nanostructure;

an adhesion layer over the barrier material; and

a filler metal over the adhesion layer.

10. A method of forming a semiconductor device, comprising:

depositing a gate dielectric around first and second nanostructures, the first nanostructures disposed over the second nanostructures;

depositing a p-type workfunction metal over the gate dielectric, wherein after depositing the p-type workfunction metal, an opening remains between a first portion of the p-type workfunction metal and a second portion of the p-type workfunction metal, the first portion of the p-type workfunction metal and the second portion of the p-type workfunction metal being between the first nanostructure and the second nanostructure; and

depositing a barrier material over the p-type work function metal using an Atomic Layer Deposition (ALD) process, wherein the barrier material fills the opening between the first portion of the p-type work function metal and the second portion of the p-type work function metal.