CN116820722A

CN116820722A - Task scheduling method, device, chip module, electronic equipment and storage medium

Info

Publication number: CN116820722A
Application number: CN202310785897.2A
Authority: CN
Inventors: 申迪; 闫学文
Original assignee: Beijing Ziguang Zhanrui Communication Technology Co Ltd
Current assignee: Beijing Ziguang Zhanrui Communication Technology Co Ltd
Priority date: 2023-06-29
Filing date: 2023-06-29
Publication date: 2023-09-29

Abstract

The embodiment of the application provides a task scheduling method, a device, a chip module, electronic equipment and a storage medium, which can migrate tasks in a high-temperature core to a low-temperature core by utilizing temperature differences among different cores under the condition that the working temperature of the high-temperature core cannot be timely reduced by the existing temperature control strategy, so that the reliability of task execution in the high-temperature core is ensured. The task scheduling method comprises the following steps: obtaining a first operating temperature of each first type core of the plurality of first type cores; determining a first number of first low temperature cores for which the first operating temperature does not exceed the first temperature threshold, and a second number of first high temperature cores for which the first operating temperature exceeds the first temperature threshold; and in response to the first number and the second number being greater than 0, migrating the target task running in the first high-temperature core to the first low-temperature core, the target task being a part of the tasks running in the first high-temperature core.

Description

Task scheduling method, device, chip module, electronic equipment and storage medium

[ field of technology ]

The embodiment of the application relates to the technical field of chips, in particular to a task scheduling method, a task scheduling device, a chip module, electronic equipment and a storage medium.

[ background Art ]

Currently, processors are designed with a "big core+middle core+little core" architecture, and for any type of core, the related temperature control strategy may limit the maximum operating frequency. In some scenarios, a core of a certain type may be in a high-load operation state, i.e. in a maximum operating frequency, and if the ambient temperature suddenly increases, the above temperature control strategy may not be able to reduce the operating temperature of the core of the current type by reducing the maximum operating frequency of the core of the current type in time, so that an unreliable problem occurs in the execution process of the task running in the core of the current type.

[ application ]

The embodiment of the application provides a task scheduling method, a device, a chip module, electronic equipment and a storage medium, which can migrate tasks in a high-temperature core to a low-temperature core by utilizing temperature differences among different cores under the condition that the working temperature of the high-temperature core cannot be timely reduced by the existing temperature control strategy, so that the reliability of task execution in the high-temperature core is ensured.

In a first aspect, an embodiment of the present application provides a task scheduling method, which is applied to an electronic device, where the electronic device includes at least a plurality of cores of a first type, and the method includes:

Obtaining a first operating temperature of each first type core of the plurality of first type cores;

determining a first number of first low temperature cores for which the first operating temperature does not exceed a first temperature threshold, and a second number of first high temperature cores for which the first operating temperature exceeds the first temperature threshold;

and in response to the first number and the second number being greater than 0, migrating a target task running in the first high-temperature core to the first low-temperature core, the target task being a part of tasks running in the first high-temperature core.

In the embodiment of the application, a plurality of first type cores can be divided into a first high-temperature core and a first low-temperature core according to whether the working temperature of the first type cores exceeds a set threshold value, if both the first high-temperature core and the first low-temperature core exist, part of tasks originally running in the first high-temperature core are migrated to the first low-temperature core, the part of tasks migrated to the first low-temperature core can be considered to be reliably executed, and meanwhile, as part of tasks in the first high-temperature core are migrated, the working temperature of the first high-temperature core is also reduced to a certain extent, so that the rest of tasks in the first high-temperature core can be reliably executed. That is, in the case that the existing temperature control strategy cannot timely reduce the working temperature of the first high-temperature core, the tasks in the high-temperature core are migrated to the low-temperature cores of the same type by utilizing the temperature difference between different cores of the same type, so that the reliability of executing all the tasks in the first high-temperature core is ensured.

Optionally, in response to both the first number and the second number being greater than 0, migrating a target task running in the first high temperature core to the first low temperature core, comprising:

determining a target first low-temperature core with the minimum first working temperature from the first low-temperature cores of the first number in response to the first number being not less than 2 and the second number being greater than 0;

and migrating the target task running in the first high-temperature core to the target first low-temperature core.

In the embodiment of the application, when the number of the first low-temperature cores with the working temperature not exceeding the set threshold is at least two, the first low-temperature core with the lowest working temperature can be selected from the at least two first low-temperature cores, and the first low-temperature core with the lowest working temperature can consider that the load born by the first low-temperature core is the smallest of the at least two first low-temperature cores, so that part of tasks migrated from the first high-temperature core can be preferentially migrated to the first low-temperature core with the lowest working temperature, namely, the tasks are preferentially migrated to the low-temperature cores with the same type and the lowest working temperature, and the part of tasks can be more reliably executed under the condition of ensuring that the residual tasks in the first high-temperature core can be reliably executed.

in response to the first number being not less than 2 and the second number being greater than 0, randomly determining a target first low-temperature core from the first number of first low-temperature cores;

In the embodiment of the application, when the number of the first low-temperature cores with the working temperature not exceeding the set threshold value is at least two, any one first low-temperature core can be rapidly selected from the at least two first low-temperature cores in a random manner, and then part of tasks in the first high-temperature core are migrated to the first low-temperature cores which are determined randomly, so that the part of tasks can be reliably executed under the condition of ensuring that the rest of tasks in the first high-temperature core can be reliably executed.

Optionally, migrating the target task running in the first high-temperature core to the target first low-temperature core includes:

sequencing M tasks running in the first high-temperature core according to the load from large to small, wherein M is a positive integer not less than 2;

Selecting the first N tasks from the M tasks as the target tasks based on a first preset proportion, wherein N is more than 0 and less than M;

and migrating the first N tasks to the target first low-temperature core.

In the embodiment of the application, partial tasks with larger loads in the first high-temperature cores are preferentially migrated to the corresponding first low-temperature cores, namely, the tasks with larger loads are preferentially migrated to the low-temperature cores of the same type, so that the working temperature of the first high-temperature cores can be reduced in a shorter time, and the rest tasks in the first high-temperature cores can be more reliably executed.

Optionally, the electronic device further includes a second type of core, a maximum operating frequency of the second type of core is less than a maximum operating frequency of the first type of core, and after determining that the first operating temperature does not exceed the first number of first high temperature cores of the first temperature threshold, and the first operating temperature exceeds the second number of first low temperature cores of the first temperature threshold, the method further includes:

in response to the first number being equal to 0, migrating the target task running in the first high temperature core to the second type core.

In the embodiment of the application, when the second type core is still present in the electronic device and the maximum working frequency of the second type core is lower than that of the first type core, the working temperature of the second type core can be considered to be lower than that of the first type core, if all of the plurality of first type cores are the first high Wen Hexin, the second type core can be a low-temperature core at this time, and part of tasks running in the first type core can be migrated to the second type core, and under the condition that the rest of tasks in the first high-temperature core can be reliably executed, the part of tasks migrated to the second type core can be reliably executed. That is, when the temperature of the cores of the same type is higher, but there is a temperature difference between the cores of different types, the tasks in the high-temperature core are migrated to the cores of other types, so that the reliability of executing all the tasks in the first high-temperature core is ensured.

Optionally, the second type core is at least two, and before the target task running in the first high-temperature core is migrated to the target second type core in response to the first number being equal to 0, the method further includes:

acquiring a second working temperature of each second type core of the at least two second type cores;

Determining a third number of second cryogenic cores for which the second operating temperature does not exceed a second temperature threshold;

in response to the first number being equal to 0, migrating the target task running in the first high temperature core to a target second type core, comprising:

determining a target second low-temperature core with the minimum second working temperature from the second low-temperature cores of the third number in response to the first number being equal to 0 and the third number being not less than 2;

migrating the target task running in the first high temperature core to the target second low temperature core.

In the embodiment of the application, if all of the plurality of first-type cores are first high-temperature cores and at least two second low-temperature cores exist in the plurality of second-type cores, then the second low-temperature core with the lowest working temperature in the at least two second low-temperature cores can be selected, and the second low-temperature core with the lowest working temperature can consider that the load carried by the second low-temperature core is the smallest in the at least two second low-temperature cores, so that part of tasks migrated from the first high-temperature cores can be preferentially migrated to the second low-temperature core with the lowest working temperature, namely, tasks can be preferentially migrated to other types of low-temperature cores with the lowest working temperature, and the part of tasks can be more reliably executed under the condition that the rest of tasks in the first high-temperature cores can be reliably executed.

Optionally, migrating the target task running in the first high-temperature core to the target second low-temperature core includes:

selecting the first K tasks as the target tasks based on a second preset proportion, wherein K is greater than 0 and less than M;

and migrating the first K tasks to the target second low-temperature core.

In the embodiment of the application, partial tasks with larger loads in the first high-temperature core are preferentially transferred to the corresponding second low-temperature core, namely, the tasks with larger loads are preferentially transferred to other types of low-temperature cores, so that the working temperature of the first high-temperature core can be reduced in a shorter time, and the rest tasks in the first high-temperature core can be more reliably executed.

Determining a third number of second low temperature cores for which the second operating temperature does not exceed a second temperature threshold, and a fourth number of second high temperature cores for which the second operating temperature exceeds the second temperature threshold;

in response to the first number being equal to 0 and the third number being equal to 0, dividing the target task into a number of target subtasks equal to the fourth number;

and respectively migrating the target subtasks to the corresponding target second high-temperature cores.

In the embodiment of the application, if all of the plurality of first type cores are first high-temperature cores and all of the plurality of second type cores are second high-temperature cores, at this time, the target tasks to be migrated in the first high-temperature cores can be divided into target sub-tasks with the same number as the second high-temperature cores, and then each target sub-task is migrated to the corresponding target second high-temperature core, i.e. each second high-temperature core carries a part of the target tasks, so that under the condition of ensuring that the residual tasks in the first high-temperature cores can be reliably executed, the working temperature of a single second high-temperature core is prevented from being too high, and each sub-task can be reliably executed in the corresponding second high-temperature core.

In a second aspect, an embodiment of the present application provides a task scheduling device, provided in an electronic device, where the electronic device includes at least a plurality of cores of a first type, the device includes:

an acquisition unit configured to acquire a first operating temperature of each of the plurality of first-type cores;

a determining unit configured to determine a first number of first low-temperature cores for which the first operating temperature does not exceed a first temperature threshold, and a second number of first high-temperature cores for which the first operating temperature exceeds the first temperature threshold;

and the migration unit is used for migrating the target task running in the first high-temperature core to the first low-temperature core in response to the first number and the second number being larger than 0, wherein the target task is a part of tasks running in the first high-temperature core.

Optionally, the migration unit includes:

a low-temperature core determining subunit, configured to determine, from the first low-temperature cores of the first number, a target first low-temperature core with the minimum first operating temperature in response to the first number being not less than 2 and the second number being greater than 0;

and the migration subunit is used for migrating the target task running in the first high-temperature core to the target first low-temperature core.

Optionally, the migration unit includes:

a low-temperature core determining subunit, configured to randomly determine a target first low-temperature core from the first low-temperature cores of the first number in response to the first number being not less than 2 and the second number being greater than 0;

Optionally, the migration subunit is specifically configured to:

and migrating the first N tasks to the target first low-temperature core.

Optionally, the electronic device further includes a second type core, a maximum operating frequency of the second type core is smaller than a maximum operating frequency of the first type core, and the migration unit is further configured to:

in response to the first number being equal to 0, migrating the target task running in the first high temperature core to a target second type core.

Optionally, the second type core is at least two, and the obtaining unit is further configured to: acquiring a second working temperature of each second type core of the at least two second type cores;

the determining unit is further configured to: determining a third number of second cryogenic cores for which the second operating temperature does not exceed a second temperature threshold;

the migration unit includes:

a low-temperature core determining subunit, configured to determine a target second low-temperature core with a minimum second operating temperature from the second low-temperature cores of the first number in response to the first number being equal to 0 and the third number being not less than 2;

and the migration subunit is used for migrating the target task running in the first high-temperature core to the target second low-temperature core.

Optionally, the migration subunit is specifically configured to:

selecting the first K tasks from the M tasks as the target tasks based on a second preset proportion, wherein K is more than 0 and less than M;

and migrating the first K tasks to the target second low-temperature core.

the determining unit is further configured to: determining a third number of second low temperature cores for which the second operating temperature does not exceed a second temperature threshold, and a fourth number of second high temperature cores for which the second operating temperature exceeds the second temperature threshold;

the migration unit is specifically configured to:

responsive to the first number being equal to 0 and the third number being equal to 0, splitting the target task into a number of target subtasks equal to the fourth number;

In a third aspect, an embodiment of the present application provides a chip module, where the chip module includes a processor and a memory, and the processor is configured to implement the steps of the method according to any embodiment of the first aspect when executing a computer program stored in the memory.

In a fourth aspect, an embodiment of the present application provides an electronic device, the electronic device comprising a processor and a memory, the processor being configured to implement the steps of the method according to any of the embodiments of the first aspect when executing a computer program stored in the memory.

In a fifth aspect, embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the method according to any of the embodiments of the first aspect.

It should be understood that the second to fifth aspects of the embodiments of the present application are consistent with the technical solutions of the first aspect of the embodiments of the present application, and the beneficial effects obtained by each aspect and the corresponding possible implementation manner are similar, and are not repeated.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present specification, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic flow chart of a task allocation method according to an embodiment of the present application;

FIG. 2 is a flowchart illustrating a method for migrating a target task according to an embodiment of the present application;

FIG. 3 is a flowchart illustrating a method for migrating a target task according to an embodiment of the present application;

FIG. 4 is a flowchart illustrating a method for migrating a target task according to an embodiment of the present application;

FIG. 5 is a schematic flow chart of a task allocation method according to an embodiment of the present application;

FIG. 6 is a flowchart illustrating a method for migrating a target task according to an embodiment of the present application;

FIG. 7 is a flowchart illustrating a method for migrating a target task according to an embodiment of the present application;

FIG. 8 is a flowchart illustrating a method for migrating a target task according to an embodiment of the present application;

FIG. 9 is a schematic flow chart of a task allocation method according to an embodiment of the present application;

fig. 10 is a schematic structural diagram of a task scheduling device according to an embodiment of the present application;

fig. 11 is a schematic structural diagram of a chip module according to an embodiment of the present application;

fig. 12 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

[ detailed description ] of the application

For a better understanding of the technical solutions of the present specification, the following detailed description of the embodiments of the present application refers to the accompanying drawings.

It should be understood that the described embodiments are only some, but not all, of the embodiments of the present description. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present disclosure.

The terminology used in the embodiments of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

The terms related to the embodiments of the present application are explained below.

Symmetric multiprocessing (Symmetric MultiProcessing, SMP): refers to a parallel processing technique that allows multiple processors to share the same set of resources (e.g., memory, I/O devices) and execute the same operating system and application programs. In SMP architectures, each processor has the same performance characteristics and access rights, and the coordination between processors is not dependent on a particular task or core type. One key feature of SMPs is that the operating system has global scheduling and management capabilities for the processor.

Heterogeneous multi-core central processor (Central Processing Unit, CPU): the processor architecture realizes the balance of high performance and low power consumption through the combination of 'big core + middle core + small core' and reasonable scheduling. For example, the maximum working frequency of the big core is highest, the computing capacity is strong, the power consumption is highest, and the method is generally applicable to high-performance computing tasks such as 3D games, high-definition video rendering, complex algorithm operation, AI processing and the like; the maximum working frequency, computing power and power consumption of the middle core are between those of the large core and the small core, and the method is generally suitable for conventional computing tasks such as application program starting, multi-task switching, web page browsing and the like. These tasks do not require very powerful computational power, but require fast response, and the kernel can achieve a better performance and performance balance in these scenarios; the maximum working frequency of the small core is minimum, the computing capacity is the weakest, the power consumption is the lowest, and the method is generally suitable for light load computing tasks, such as update notification, heart rate monitoring, mail inspection and the like during system standby. Because these tasks require lower computational power, the microkernel can meet the needs of these scenarios by reducing frequency and power consumption, thereby ensuring longer battery life.

Intelligent power allocation (Intelligent Power Allocation Algorithm, IPA): an algorithm for dynamically managing the power consumption and performance of a processor or system. The algorithm automatically adjusts internal resources of the processor (such as parameters of frequency, voltage and the like of a CPU core) according to real-time task requirements, power consumption limitation and performance targets so as to realize balance of power consumption and performance. The core goal of the intelligent power distribution algorithm is to reduce energy consumption as much as possible and prolong the endurance time of the equipment under the condition of ensuring that the equipment completes the required tasks.

According to the research of the inventor, in the heterogeneous multi-core CPU based on SMP, when a certain core is in the maximum working frequency due to the running of high-load tasks, if the environment temperature suddenly rises, the IPA algorithm can not reduce the working temperature of the current core in time by reducing the maximum working frequency of the current core, so that the problem of unreliable execution of the tasks running in the current core is caused.

In view of this, an embodiment of the present application provides a task scheduling method, in which, by using a temperature difference between different cores of the same type, a task in a high-temperature core is migrated to a low-temperature core of the same type, so that the portion of the task migrated to the low-temperature core can be considered to be reliably executed, and meanwhile, since a portion of the task in the high-temperature core is migrated, a certain degree of reduction in the working temperature of the high-temperature core can occur, that is, an adverse effect on the high-temperature core caused by a sudden increase in the external temperature can be eliminated to a certain extent, so that it is ensured that the remaining tasks in the high-temperature core can also be reliably executed.

The technical scheme provided by the embodiment of the application is described below with reference to the accompanying drawings. Referring to fig. 1, an embodiment of the present application provides a task scheduling method, which is applied to an electronic device, and the electronic device may be a smart phone, a notebook computer, a desktop computer, a tablet computer, a server, etc., and the flow of the method is described as follows:

step 101: a first operating temperature of each of the plurality of first type cores is obtained.

In the embodiment of the application, a plurality of first type cores are arranged in the electronic device, wherein the first type cores can refer to large cores or middle cores in a heterogeneous multi-core architecture. An on-chip temperature sensor is provided on the first type core, so that an operating temperature, e.g., a first operating temperature, of each of the plurality of first type cores is known by reading temperature data of the on-chip temperature sensor. The magnitude of the first operating temperature of each core of the first type obtained here depends on the one hand on the magnitude of the load carried by the core, the lower the first operating temperature of the core when the load is smaller; the higher the load, the higher the first operating temperature of the core, on the other hand, depending on the external ambient temperature, the lower the first operating temperature of the core, when the external ambient temperature is lower; the higher the external ambient temperature, the higher the first operating temperature of the core.

It should be understood that, the first operating temperature of each first type core is acquired in a polling manner, that is, the first operating temperature of each first type core is acquired once every preset time period, and the above-mentioned acquisition of the first operating temperature of each first type core may be considered as the operating temperature acquired at any time in the polling process.

Step 102: a first number of first low temperature cores for which the first operating temperature does not exceed the first temperature threshold and a second number of first high temperature cores for which the first operating temperature exceeds the first temperature threshold are determined.

In the embodiment of the application, the first temperature threshold is preset for the first working temperature of the first type core, and when the first working temperature does not exceed the first temperature threshold, the corresponding first type core can be used as the first low-temperature core, namely, under the condition that the external environment temperature suddenly rises, the current working temperature of the core is still in a normal range due to smaller load of the current task executed by the core, so that the reliable execution of the task can be ensured. When the first working temperature exceeds the first temperature threshold, the corresponding first type core may be used as a first high-temperature core, that is, when the external environment temperature suddenly increases, the current working temperature of the core exceeds the normal range due to the large load of the task currently executed by the core, which may not ensure reliable execution of the task. Therefore, by determining the specific number of the first low-temperature cores and the specific number of the first high-temperature cores, the method can be used as a judging reference for judging whether the tasks in the subsequent first high-temperature cores can migrate to the first low-temperature cores.

Step 103: and in response to both the first number and the second number being greater than 0, migrating the target task running in the first high-temperature core to the first low-temperature core.

In the embodiment of the application, when a plurality of first-type cores simultaneously exist in a first high-temperature core and a first low-temperature core, a target task operated in the first high-temperature core can be migrated into the first low-temperature core, namely, the task in the high-temperature core is migrated to the same type of low-temperature core by utilizing the temperature difference between different cores of the same type, wherein the target task can be part of the tasks in the first high-temperature core. Because the primary load of the first low-temperature core is smaller, the first low-temperature core can completely accept the partial tasks migrated by the first high-temperature core, and the working temperature of the first low-temperature core can still be in a normal range in the process of executing the partial tasks, so that the accepted partial tasks can be reliably executed. Meanwhile, as part of tasks in the first high-temperature core are migrated, the first working temperature of the first high-temperature core is also reduced to a certain extent, so that the rest of tasks in the first high-temperature core can be reliably executed.

In some embodiments, there may be at least two first low-temperature cores in the plurality of first type cores, and then the target task may be migrated to the corresponding first low-temperature cores according to a preset migration policy.

Fig. 2 is a schematic flow chart of a method for migrating a target task according to an embodiment of the present application. Step 103 may be implemented by performing sub-steps 201 and 202:

step 201: and in response to the first number being not less than 2 and the second number being greater than 0, determining a target first low-temperature core with the minimum first operating temperature from the first number of first low-temperature cores.

Step 202: and migrating the target task running in the first high-temperature core to the target first low-temperature core.

In the embodiment of the present application, when the number of the first low-temperature cores whose first working temperature does not exceed the first temperature threshold is at least two, the first low-temperature core with the lowest first working temperature may be selected from the at least two first low-temperature cores. In general, the working temperature of the core is positively correlated with the load, and when the working temperature of the core is low, the load can be considered to be small; conversely, when the core is operating at a higher temperature, it is considered to be more loaded. The first low-temperature core with the lowest working temperature can consider that the load carried by the first low-temperature core is the smallest of at least two first low-temperature cores, so that part of tasks migrated from the first high-temperature core can be preferentially migrated to the first low-temperature core with the lowest working temperature, namely, the tasks are preferentially migrated to the low-temperature cores with the same type and the lowest working temperature, and the migrated part of tasks can be reliably executed in the target first low-temperature core under the condition that the rest tasks in the first high-temperature core can be reliably executed.

For example, taking a first type core as a big core, there are four big cores in the electronic device, namely A1, A2, A3 and A4, where A1 and A2 are first high-temperature cores, A3 and A4 are first low-temperature cores, and the first working temperature of A3 and the first working temperature of A4 are lower, so that the target tasks running in A1 and A2 can be migrated into A3.

Fig. 3 is a schematic flow chart of a method for migrating a target task according to an embodiment of the present application. Step 103 may be implemented by performing sub-steps 301 and 302:

step 301: in response to the first number being not less than 2 and the second number being greater than 0, a target first low temperature core is randomly determined from the first number of first low temperature cores.

Step 302: and migrating the target task running in the first high-temperature core to the target first low-temperature core.

In the embodiment of the application, when the number of the first low-temperature cores of which the first working temperature does not exceed the first temperature threshold is at least two, any one first low-temperature core can be quickly selected from the at least two first low-temperature cores in a random manner, and then part of tasks in the first high-temperature core are migrated to the first low-temperature cores which are determined randomly, so that the part of tasks can be reliably executed under the condition that the rest of tasks in the first high-temperature cores can be reliably executed.

For example, taking a first type of core as a big core, there are four big cores in the electronic device, namely A1, A2, A3 and A4, respectively, where A1 is a first high Wen Hexin, A2, A3 and A4 are first low-temperature cores, and if A2 is taken as a target first low-temperature core through a random algorithm, a target task running in A1 is migrated to A2.

In some embodiments, a plurality of tasks may be executed in the first high-temperature core, and then which tasks are targeted according to a preset screening policy may be migrated to the corresponding first low-temperature core.

Fig. 4 is a schematic flow chart of a method for migrating a target task according to an embodiment of the present application. Step 202 or step 302 may be realized in particular by performing sub-steps 401-403:

step 401: and sequencing M tasks running in the first high-temperature core according to the load from large to small, wherein M is a positive integer not less than 2.

Step 402: and selecting the first N tasks from the M tasks as target tasks based on a first preset proportion, wherein N is greater than 0 and less than M.

Step 403: and migrating the first N tasks to the target first low-temperature core.

In the embodiment of the application, based on the first preset proportion, partial tasks with larger loads in the first high-temperature cores are preferentially migrated to the corresponding first low-temperature cores, namely, the tasks with larger loads are preferentially migrated to the low-temperature cores of the same type, and the working temperature of the first high-temperature cores can be reduced in a shorter time, so that the rest tasks in the first high-temperature cores can be more reliably executed. Of course, after the M tasks are ordered according to the load size, the task corresponding to the first preset number may be selected as the target task based on the first preset number, which is not limited herein.

For example, the first preset proportion is 20%, 5 tasks, namely tasks 1-5, exist in the first high-temperature core, the tasks 2-4-1-3-5 are obtained by sorting according to the load from large to small, and then the number N of the selected target tasks is 5×20% =1, that is, the task 2 is migrated into the corresponding first low-temperature core as the target task.

In some embodiments, in addition to a specific first type of core, a second type of core is provided in the electronic device, where the first type of core differs from the second type of core in that: if the maximum working frequency of the second type core is smaller than the maximum working frequency of the first type core, part of tasks in the first high-temperature core can be migrated to the second type core under the condition that a plurality of first type cores are all judged to be the first high-temperature core.

Fig. 5 is a schematic flow chart of a task scheduling method according to an embodiment of the present application. After step 102 is performed, step 104 may also continue to be performed.

Step 104: in response to the first number being equal to 0, migrating a target task running in the first high temperature core to a second type core.

In the embodiment of the application, the maximum working frequency of the second type core is lower than that of the first type core, so that the working temperature of the second type core is lower than that of the first type core under the same condition. If all of the plurality of first type cores are the first high Wen Hexin, the second type core may be a low temperature core at this time, and a part of tasks running in the first type core may be migrated to the target second type core, where the remaining tasks in the high temperature core may be reliably executed, and the part of tasks migrated to the target second type core may be reliably executed. That is, when the temperature of the cores of the same type is higher, but there is a temperature difference between the cores of different types, the tasks in the first high-temperature core are migrated to the cores of other types, so that the reliability of executing all the tasks in the first high-temperature core is ensured.

It should be appreciated that when the first type core is a large core, the second type core is a medium core; when the first type core is a middle core, the second type core is a small core.

In some embodiments, the electronic device may have at least two cores of the second type, and then the target task may be migrated to the corresponding cores of the second type according to a preset migration policy.

Fig. 6 is a schematic flow chart of a method for migrating a target task according to an embodiment of the present application. Steps 501 and 502 may also be performed before step 104 is performed:

step 501: a second operating temperature of each of the at least two second type cores is obtained.

Step 502: a third number of second low temperature cores for which the second operating temperature does not exceed the second temperature threshold and a fourth number of second high temperature cores for which the second operating temperature exceeds the second temperature threshold are determined.

Step 104 may be implemented by performing sub-steps 503 and 504:

step 503: in response to the first number being equal to 0 and the third number being equal to 0, splitting the target task into a number of target subtasks equal to the fourth number.

Step 504: and respectively migrating the target subtasks to the corresponding target second high-temperature cores.

For example, a first type core includes A1 and A2, and A1 and A2 are each determined as a first high Wen Hexin, a second type core includes B1, B2 and B3, and B1, B2 and B3 are each determined as a second high temperature core, where the target tasks to be migrated in A1 may be divided into 3 sub-tasks [ A1-1, A1-2, A1-3 ], and the target tasks to be migrated in A2 may be divided into 3 sub-tasks [ A2-1, A2-2, A2-3 ], then A1-1 and A2-1 are migrated to B1, A1-2 and A2-2 are migrated to B2, and A1-3 and A2-3 are migrated to B3.

Fig. 7 is a schematic flow chart of a method for migrating a target task according to an embodiment of the present application. Steps 601 and 602 may also be performed before step 104 is performed:

step 601: a second operating temperature of each of the at least two second type cores is obtained.

Step 602: a third number of second cryogenic cores for which the second operating temperature does not exceed a second temperature threshold is determined.

Step 104 may be implemented by executing sub-steps 603 and 604:

step 603: and in response to the first number being equal to 0 and the third number being not less than 2, determining a target second low-temperature core with the smallest second operating temperature from the third number of second low-temperature cores.

Step 604: and migrating the target task running in the first high-temperature core to a target second low-temperature core.

In the embodiment of the application, if all of the plurality of first-type cores are first high-temperature cores and at least two second low-temperature cores exist in the plurality of second-type cores, then the second low-temperature core with the lowest working temperature can be selected from the at least two second low-temperature cores, and the second low-temperature core with the lowest working temperature can consider that the load carried by the second low-temperature core is the smallest of the at least two second low-temperature cores, so that part of tasks migrated from the first high-temperature core can be preferentially migrated to the second low-temperature core with the lowest working temperature, namely, tasks can be preferentially migrated to other types of low-temperature cores with the lowest working temperature, and the part of tasks can be more reliably executed in the second low-temperature cores under the condition that the rest of tasks in the first high-temperature core can be reliably executed.

Of course, when the number of the second low-temperature cores is at least two, the target second low-temperature cores can be determined from the at least two second low-temperature cores through a random algorithm to bear the target task, which is not described herein.

For example, the first type cores in the electronic device are A1 and A2, the second type cores are B1, B2 and B3, when a certain polling is performed, the first operating temperatures of A1 and A2 exceed the first temperature threshold, that is, the first operating temperatures of A1 and A2 are determined to be the first high Wen Hexin, the second operating temperatures of B2 and B3 in the second type cores do not exceed the second temperature threshold, that is, the second operating temperatures of B2 and B3 are determined to be the second low temperature cores, and if the second operating temperature of B3 is lower than the second operating temperature of B2, B3 can be used as the target second low temperature core, and then the target tasks in A1 and A2 are migrated into B3.

In some embodiments, multiple tasks may be run in the first high temperature core, and then which tasks are targeted according to a preset screening policy may be migrated to the corresponding second low temperature core.

Fig. 8 is a schematic flow chart of a method for migrating a target task according to an embodiment of the present application. Step 604 may be implemented by performing sub-steps 701-703:

Step 701: and sequencing M tasks running in the first high-temperature core according to the load from large to small, wherein M is a positive integer not less than 2.

Step 702: and selecting the first K tasks as target tasks based on a second preset proportion, wherein K is greater than 0 and less than M.

Step 703: and migrating the first K tasks to the target second low-temperature core.

In the embodiment of the application, based on the second preset proportion, partial tasks with larger loads in the first high-temperature core are preferentially migrated to the corresponding second low-temperature core, namely, the tasks with larger loads are preferentially migrated to other types of low-temperature cores, so that the working temperature of the first high-temperature core can be reduced in a shorter time, and the rest tasks in the first high-temperature core can be more reliably executed. Of course, after the M tasks are ordered according to the load size, the task corresponding to the first preset number may also be selected as the target task based on the second preset number, which is not particularly limited herein. It should be appreciated that the second preset ratio may be greater than the first preset ratio.

For example, the second preset proportion is 40%, 5 tasks, namely tasks 1-5, exist in the first high-temperature core, the tasks 2-4-1-3-5 are obtained by sorting according to the load from large to small, and then the number N of the selected target tasks is 5×40% =2, that is, the tasks 2 and 4 are used as the target tasks to be migrated into the corresponding second low-temperature core.

Fig. 9 is a schematic flow chart of a task scheduling method in the embodiment of the present application, and the whole scheme is described in detail below.

Step 801: the method comprises the steps of obtaining a first working temperature of a first type core and a second working temperature of a second type core, wherein the first type core is a large core, and the second type core is a middle core.

Step 802: a first number of first low temperature cores whose first operating temperature does not exceed a first temperature threshold and a second number of first high temperature cores whose first operating temperature exceeds the first temperature threshold are determined from the first type of cores.

Step 803: whether the first number and the second number are both greater than 0 is determined, and if both are greater than 0, step 806 is skipped.

Step 804: it is determined whether the first number is equal to 0, if so, the process proceeds to step 807.

Step 805: it is determined whether the second number is equal to 0, if so, the process proceeds to step 808.

It should be understood that the execution sequence of steps 803 to 805 is not particularly limited in the present application.

Step 806: the target tasks in the first high temperature core are migrated into the first low temperature core.

Step 807: the target tasks in the first high temperature core are migrated into the second type core.

Step 808: a third number of second low temperature cores for which the second operating temperature does not exceed the second temperature threshold and a fourth number of second high temperature cores for which the second operating temperature exceeds the second temperature threshold are determined from the second type cores.

Step 809: and judging whether the third quantity and the fourth quantity are both larger than 0, and if so, jumping to the step 811.

Step 810: whether the third number is equal to 0 is determined, if so, the process proceeds to step 812.

It should be understood that the execution sequence of steps 809 to 810 is not particularly limited in the present application.

Step 811: and migrating the target task in the second high-temperature core into the second low-temperature core.

Step 812: the target tasks in the second high temperature core are migrated into a third type of core, wherein the third type of core is a corelet.

Referring to fig. 10, based on the same inventive concept, an embodiment of the present application provides a task scheduling device, where the task scheduling device is disposed in an electronic device, and the electronic device includes at least a plurality of cores of a first type, and the device includes: an acquisition unit 901, a determination unit 902, and a migration unit 903.

An acquisition unit 901 for acquiring a first operating temperature of each of a plurality of first type cores;

a determining unit 902, configured to determine a first number of first low-temperature cores whose first operating temperature does not exceed a first temperature threshold, and a second number of first high-temperature cores whose first operating temperature exceeds the first temperature threshold;

The migration unit 903 is configured to migrate, to the first low-temperature core, a target task running in the first high-temperature core, where the target task is a part of tasks running in the first high-temperature core, in response to the first number and the second number being both greater than 0.

Optionally, the migration unit 903 includes:

a low-temperature core determining subunit, configured to determine, from the first number of first low-temperature cores, a target first low-temperature core with a minimum first operating temperature in response to the first number being not less than 2 and the second number being greater than 0;

Optionally, the migration unit 903 includes:

Optionally, the migration subunit is specifically configured to:

sequencing M tasks running in a first high-temperature core according to the load from large to small, wherein M is a positive integer not less than 2;

Selecting the first N tasks from M tasks as target tasks based on a first preset proportion, wherein N is more than 0 and less than M;

and migrating the first N tasks to the target first low-temperature core.

Optionally, the electronic device further includes a second type core, a maximum operating frequency of the second type core is smaller than a maximum operating frequency of the first type core, and the migration unit 903 is further configured to:

in response to the first number being equal to 0, migrating a target task running in the first high temperature core to a target second type core.

Optionally, the second type core is at least two, and the acquiring unit 901 is further configured to: acquiring a second working temperature of each second type core of the at least two second type cores;

the determining unit 902 is further configured to: determining a third number of second cryogenic cores for which the second operating temperature does not exceed the second temperature threshold;

the migration unit 903 includes:

a low-temperature core determining subunit, configured to determine a target second low-temperature core with a minimum second operating temperature from the first number of second low-temperature cores in response to the first number being equal to 0 and the third number being not less than 2;

Optionally, the migration subunit is specifically configured to:

selecting the first K tasks from the M tasks as target tasks based on a second preset proportion, wherein K is more than 0 and less than M;

and migrating the first K tasks to the target second low-temperature core.

the determining unit 902 is further configured to: determining a third number of second low temperature cores for which the second operating temperature does not exceed the second temperature threshold, and a fourth number of second high temperature cores for which the second operating temperature exceeds the second temperature threshold;

the migration unit 903 specifically is configured to:

Referring to fig. 11, an embodiment of the present application further provides a chip module, where the chip module includes at least one processor 1001, and the processor 1001 is configured to execute a computer program stored in a memory, so as to implement the steps of the task scheduling method shown in fig. 1 to 9 according to the embodiment of the present application.

Alternatively, the processor 1001 may be a central processing unit, a specific ASIC, or one or more integrated circuits for controlling program execution.

Optionally, the chip module may further comprise a memory 1002 coupled to the at least one processor 1001, the memory 1002 may comprise ROM, RAM and disk storage. The memory 1002 is used for storing data required for the operation of the processor 1001, i.e. instructions executable by the at least one processor 1001 are stored, and the at least one processor 1001 performs the method as shown in fig. 1-9 by executing the instructions stored by the memory 1002. Wherein the number of memories 1002 is one or more. Wherein the number of memories 1002 is one or more.

Referring to fig. 12, based on the same inventive concept, an electronic device 100 is further provided in an embodiment of the present application, where the electronic device 100 may include at least one processor, and the at least one processor is configured to execute a computer program stored in a memory, to implement the steps of the task scheduling method shown in fig. 1 to 9 provided in the embodiment of the present application.

In the alternative, the processor may be a central processing unit, a specific ASIC, or one or more integrated circuits for controlling the execution of the program.

Optionally, the electronic device 100 may further include a memory coupled to the at least one processor, the memory may include ROM, RAM, and disk memory. The memory is used for storing data required by the processor to run, i.e. instructions are stored which are executable by at least one processor which, by executing the instructions stored by the memory, performs the method as shown in fig. 1-9. Wherein the number of memories is one or more.

The physical devices corresponding to the obtaining unit 901, the determining unit 902, and the migration unit 903 may be the foregoing processors. The electronic device may be used to perform the methods provided by the embodiments shown in fig. 1-9. Therefore, for the functions that can be implemented by each functional module in the electronic device, reference may be made to corresponding descriptions in the embodiments shown in fig. 1 to 9, which are not repeated.

The electronic device 100 may be an intelligent electronic device such as a smart phone or a tablet computer, and the form of the electronic device is not limited in this embodiment.

By way of example, fig. 12 illustrates a schematic diagram of a structure of the electronic device 100 using a smart phone as an example, and as shown in fig. 12, the electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a universal serial bus (universal serial bus, USB) interface 130, a charge management module 140, a power management module 141, a battery 142, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, a sensor module 180, keys 190, a motor 191, an indicator 192, a camera 193, a display 194, and a subscriber identity card (subscriber identification module, SIM) card interface 195.

It should be understood that the illustrated structure of the embodiment of the present application does not constitute a specific limitation on the electronic device 100. In other embodiments of the application, electronic device 100 may include more or fewer components than shown, or certain components may be combined, or certain components may be split, or different arrangements of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

The processor 110 may include one or more processing units, such as: the processor 110 may include an application processor (application processor, AP), a modem processor, a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processor, ISP), a controller, a video codec, a digital signal processor (digital signal processor, DSP), a baseband processor, and/or a neural network processor (neural-network processing unit, NPU), etc. Wherein the different processing units may be separate devices or may be integrated in one or more processors.

The controller can generate operation control signals according to the instruction operation codes and the time sequence signals to finish the control of instruction fetching and instruction execution.

A memory may also be provided in the processor 110 for storing instructions and data. In some embodiments, the memory in the processor 110 is a cache memory. The memory may hold instructions or data that the processor 110 has just used or recycled. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. Repeated accesses are avoided and the latency of the processor 110 is reduced, thereby improving the efficiency of the system.

In some embodiments, the processor 110 may include one or more interfaces. The interfaces may include an integrated circuit (inter-integrated circuit, I2C) interface, an integrated circuit built-in audio (inter-integrated circuit sound, I2S) interface, a pulse code modulation (pulse code modulation, PCM) interface, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART) interface, a mobile industry processor interface (mobile industry processor interface, MIPI), a general-purpose input/output (GPIO) interface, a subscriber identity module (subscriber identity module, SIM) interface, and/or a universal serial bus (universal serial bus, USB) interface, among others.

The charge management module 140 is configured to receive a charge input from a charger.

The power management module 141 is used for connecting the battery 142, and the charge management module 140 and the processor 110.

In some embodiments, antenna 1 and mobile communication module 150 of electronic device 100 are coupled, and antenna 2 and wireless communication module 160 are coupled, such that electronic device 100 may communicate with a network and other devices through wireless communication techniques. The wireless communication techniques may include the Global System for Mobile communications (global system for mobile communications, GSM), general packet radio service (general packet radio service, GPRS), code division multiple access (code division multiple access, CDMA), wideband code division multiple access (wideband code division multiple access, WCDMA), time division code division multiple access (time-division code division multiple access, TD-SCDMA), long term evolution (long term evolution, LTE), BT, GNSS, WLAN, NFC, FM, and/or IR techniques, among others. The GNSS may include a global satellite positioning system (global positioning system, GPS), a global navigation satellite system (global navigation satellite system, GLONASS), a beidou satellite navigation system (beidou navigation satellite system, BDS), a quasi zenith satellite system (quasi-zenith satellite system, QZSS) and/or a satellite based augmentation system (satellite based augmentation systems, SBAS).

The electronic device 100 implements display functions through a GPU, a display screen 194, an application processor, and the like.

The display screen 194 is used to display images, videos, and the like. The display 194 includes a display panel.

The ISP is used to process data fed back by the camera 193.

The camera 193 is used to capture still images or video.

The digital signal processor is used for processing digital signals, and can process other digital signals besides digital image signals. For example, when the electronic device 100 selects a frequency bin, the digital signal processor is used to fourier transform the frequency bin energy, or the like.

Video codecs are used to compress or decompress digital video. The electronic device 100 may support one or more video codecs. In this way, the electronic device 100 may play or record video in a variety of encoding formats, such as: dynamic picture experts group (moving picture experts group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to enable expansion of the memory capabilities of the electronic device 100. The external memory card communicates with the processor 110 through an external memory interface 120 to implement data storage functions. For example, files such as music, video, etc. are stored in an external memory card.

The internal memory 121 may be used to store computer executable program code including instructions. The internal memory 121 may include a storage program area and a storage data area. The storage program area may store an application program (such as a sound playing function, an image playing function, etc.) required for at least one function of the operating system, etc. The storage data area may store data created during use of the electronic device 100 (e.g., audio data, phonebook, etc.), and so on. In addition, the internal memory 121 may include a high-speed random access memory, and may further include a nonvolatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (universal flash storage, UFS), and the like. The processor 110 performs various functional applications of the electronic device 100 and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor.

The electronic device 100 may implement audio functions through an audio module 170, a speaker 170A, a receiver 170B, a microphone 170C, an earphone interface 170D, an application processor, and the like. Such as music playing, recording, etc.

The audio module 170 is used to convert digital audio information into an analog audio signal output and also to convert an analog audio input into a digital audio signal.

The speaker 170A, also referred to as a "horn," is used to convert audio electrical signals into sound signals.

A receiver 170B, also referred to as a "earpiece", is used to convert the audio electrical signal into a sound signal.

Microphone 170C, also referred to as a "microphone" or "microphone", is used to convert sound signals into electrical signals.

The earphone interface 170D is used to connect a wired earphone. The headset interface 170D may be a USB interface 130 or a 3.5mm open mobile electronic device platform (open mobile terminal platform, OMTP) standard interface, a american cellular telecommunications industry association (cellular telecommunications industry association of the USA, CTIA) standard interface.

The keys 190 include a power-on key, a volume key, etc.

The motor 191 may generate a vibration cue.

The indicator 192 may be an indicator light, may be used to indicate a state of charge, a change in charge, a message indicating a missed call, a notification, etc.

The SIM card interface 195 is used to connect a SIM card. In some embodiments, the electronic device 100 employs esims, i.e.: an embedded SIM card. The eSIM card can be embedded in the electronic device 100 and cannot be separated from the electronic device 100.

Embodiments of the present application also provide a computer storage medium having stored thereon computer instructions which, when run on a computer, cause the computer to perform the method described in fig. 1-9.

The foregoing description of the preferred embodiments is provided for the purpose of illustration only, and is not intended to limit the scope of the disclosure, since any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. A method of task scheduling, for use in an electronic device, the electronic device including at least a plurality of cores of a first type, the method comprising:

2. The method of claim 1, wherein responsive to the first number and the second number both being greater than 0, migrating a target task running in the first high temperature core to the first low temperature core comprises:

3. The method of claim 1, wherein responsive to the first number and the second number both being greater than 0, migrating a target task running in the first high temperature core to the first low temperature core comprises:

4. A method according to any one of claims 2 or 3, wherein migrating the target task running in the first high temperature core to the target first low temperature core comprises: DD231744I

and migrating the first N tasks to the target first low-temperature core.

5. The method of claim 1, wherein the electronic device further comprises a second type of core having a maximum operating frequency that is less than a maximum operating frequency of the first type of core, and wherein after determining that the first operating temperature does not exceed the first number of first high temperature cores of the first temperature threshold and the first operating temperature exceeds the second number of first low temperature cores of the first temperature threshold, the method further comprises:

6. The method of claim 5, wherein the second type of core is at least two, and wherein prior to migrating the target task running in the first high temperature core to a target second type of core in response to the first number being equal to 0, the method further comprises:

7. The method of claim 6, wherein migrating the target task running in the first high temperature core to the target second low temperature core comprises:

DD231744I

And migrating the first K tasks to the target second low-temperature core.

8. The method of claim 5, wherein the second type of core is at least two, and wherein prior to migrating the target task running in the first high temperature core to a target second type of core in response to the first number being equal to 0, the method further comprises:

9. A task scheduling device, disposed in an electronic device, the electronic device including at least a plurality of cores of a first type, the device comprising:

a migration unit configured to migrate a target task running in the first high-temperature core to the first low-temperature core in response to the first number and the second number being both greater than 0, where the target task is DD231744I

A portion of the tasks running in the first high temperature core.

10. A chip module comprising at least one processor and a memory connected to the at least one processor, the at least one processor being configured to implement the steps of the method according to any of claims 1-8 when executing a computer program stored in the memory.

11. An electronic device comprising at least one processor and a memory coupled to the at least one processor, the at least one processor being configured to implement the steps of the method of any of claims 1-8 when executing a computer program stored in the memory.

12. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method according to any of claims 1-8.