CN116820390A - Memory computing device, counter, shift accumulator and memory multiply-add structure - Google Patents
Memory computing device, counter, shift accumulator and memory multiply-add structure Download PDFInfo
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- 208000021386 Sjogren Syndrome Diseases 0.000 claims abstract description 10
- 230000005415 magnetization Effects 0.000 claims description 17
- 230000004888 barrier function Effects 0.000 claims description 16
- 241000934878 Sterculia Species 0.000 claims description 14
- 235000021282 Sterculia Nutrition 0.000 claims description 14
- 229940059107 sterculia Drugs 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 13
- 229910001385 heavy metal Inorganic materials 0.000 claims description 10
- 244000037364 Cinnamomum aromaticum Species 0.000 claims description 7
- 235000014489 Cinnamomum aromaticum Nutrition 0.000 claims description 7
- 230000000694 effects Effects 0.000 claims description 6
- 230000008859 change Effects 0.000 claims description 4
- 238000004364 calculation method Methods 0.000 description 35
- 238000009825 accumulation Methods 0.000 description 13
- 238000006243 chemical reaction Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 238000013528 artificial neural network Methods 0.000 description 9
- 210000000582 semen Anatomy 0.000 description 7
- 239000011159 matrix material Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 241001263603 Stellera Species 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/383—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using magnetic or similar elements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
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- G06F7/523—Multiplying only
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
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Abstract
The application provides a memory device, a counter, a shift accumulator and a memory multiply-add structure, wherein the memory device is formed by adopting a memory device comprising a magnetic track layer and a magnetic recording layer, and the memory device realizes memory by utilizing the characteristic that whether a space seed exists in the region of the magnetic recording layer or not to cause the difference in the resistance state of a magnetic tunnel junction formed by the magnetic track layer and the magnetic recording layer. Compared with the prior art, the memory device disclosed by the application is based on a pure spin electron system of the magnetic Sjogren and has the characteristics of high speed and low power consumption of the spin electron device, and meanwhile, the memory device has small physical size and can realize higher storage density.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a memory device, a counter, a shift accumulator, and a memory multiply-add structure.
Background
Today's computer systems are mainly based on von neumann architecture, characterized in that the memory unit and the arithmetic unit are separated from each other. With the rapid development of artificial intelligence in recent years, the data volume to be processed by a computing system is continuously increased, and due to the problems of storage walls, power consumption walls and the like, the von neumann architecture is more and more difficult to meet the continuously increased computing demands, and has become a main bottleneck of computing intelligence. The integrated memory technology is an important direction for solving the von neumann bottleneck, and the problems of a memory wall and a power consumption wall can be effectively relieved by enabling the memory unit to have the memory and the calculation functions. In the existing integrated architecture of memory and calculation, matrix multiplication and accumulation calculation can be realized by using only one operation through the nonvolatile memory arrays which are arranged in a crossing way. However, such calculation is mainly based on the analog characteristics of the circuit, and noise exists which is difficult to avoid in the calculation result, and the overall calculation accuracy is affected. In addition, the conversion of digital signals and analog signals is required to be continuously carried out in the calculation process, and the energy efficiency ratio is still to be improved.
Disclosure of Invention
The application provides a memory computing device, a counter, a shift accumulator and a memory multiply-add structure, wherein the computing process is completely based on the physical characteristics of the semen cassiae, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network computing can be met; meanwhile, the physical size is small, and higher storage and calculation density can be realized.
In a first aspect, the present application provides a memory device comprising a magnetic track layer and a magnetic recording layer. The magnetic track layer is used for inputting and outputting the semen cassiae and also used for enabling the semen cassiae in the magnetic track layer to exist and move stably. The magnetic recording layer includes a barrier layer laminated on a surface of the magnetic track layer, and a reference layer laminated on the barrier layer. The magnetic track layer and the magnetic recording layer form a magnetic tunnel junction, and the region of the magnetic track layer, which is overlapped with the barrier layer, is a magnetic recording layer region. The magnetization directions of the magnetic track layer and the reference layer are opposite; when the magnetic recording layer area does not exist the stigmine, the resistance state of the magnetic tunnel junction is a high resistance state; when the Sjog seed input into the magnetic track layer moves to the magnetic recording layer area, the Sjog seed input into the magnetic track layer is pinned in the magnetic recording layer area by the magnetic recording layer to change the resistance state of the magnetic tunnel junction from a high resistance state to a low resistance state.
In the above-described scheme, by adopting a memory device comprising a magnetic track layer and a magnetic recording layer, by using whether or not the space in the magnetic recording layer region is provided with the space in the space, and the magnetic tunnel junction formed by the magnetic track layer and the magnetic recording layer has different resistance states, so that the storage is realized. Compared with the prior art, the memory device disclosed by the application is based on a pure spin electron system of the magnetic Sjogren and has the characteristics of high speed and low power consumption of the spin electron device, and meanwhile, the memory device has small physical size and can realize higher storage density.
In a specific embodiment, the memory device further includes an erase region located laterally of the magnetic track layer, the erase region for erasing the space seed therein. The magnetic track layer has a Sjog seed input port and a Sjog seed output port. When fixed stoneley is present in the magnetic recording layer region, the moving stoneley input through the stoneley input port can collide the fixed stoneley to the erase region, and the moving stoneley itself can be output from the stoneley output port. By adding the erasing area on the side surface of the magnetic track layer, one space seed can be output for every two space seeds which are continuously input, the resistance state of the magnetic tunnel junction can be reset, the binary addition rule of every two space seeds can be expressed, the internal accumulation operation can be directly realized, the calculation process is completely based on the physical characteristics of the space seeds, the conversion of digital signals and analog signals is not needed, the requirements of high-precision and low-power-consumption neural network calculation can be met, and the higher calculation density can be realized.
In a specific embodiment, the erase region is provided with a power-on port. When the current flows into the energizing port of the erasing area, the Sjog's seed of the magnetic recording layer area can be output from the Sjog's seed output port; when a current flows through the power-on port of the erase region, the Sjog dial of the magnetic recording layer region can be erased. So as to output or erase the stigman seeds in the memory cell.
In a specific embodiment, the magnetic track layer comprises a heavy metal layer and a magnetic layer, wherein the barrier layer is laminated on the surface of the magnetic layer. The heavy metal layer and the magnetic layer are coupled at the interface to generate a DMI effect, so that the Sjogren in the magnetic track layer can exist stably; the spin orbit moment effect of the heavy metal layer and the magnetic layer drives the movement of the Sjogren in the magnetic orbit layer. The stable existence and movement of the stigman seeds in the magnetic track layer are facilitated.
In a specific embodiment, the magnetic track layer has a T-shaped cross-sectional shape. Two ends of the linear track of the T-shaped magnetic track layer are provided with an energizing port in a distributed manner; the Sjog seed input port and the Sjog seed output port are respectively overlapped with the two power-on ports of the magnetic track layer. And the remaining third ends on the T-shaped magnetic track layer are distributed with erasing areas so as to optimize the structure of the magnetic track layer and the track movement route of the Sjog dial.
In a specific embodiment, the magnetic anisotropy of the magnetic track layer and the reference layer are perpendicular magnetic anisotropies, facilitating pinning movement to the magnetic recording layer region.
In a second aspect, the present application also provides a counter comprising: a plurality of memory devices comprising an erase region, each of the memory devices being sequentially arranged. Between any two adjacent memory computing devices, the output port of the memory computing device is connected with the output port of the memory computing device, so that the memory computing device can move into the memory computing device.
In the above-described scheme, by adopting a memory device comprising a magnetic track layer and a magnetic recording layer, by using whether or not the space in the magnetic recording layer region is provided with the space in the space, and the magnetic tunnel junction formed by the magnetic track layer and the magnetic recording layer has different resistance states, so that the storage is realized. And an erasing area is additionally arranged on the side surface of the magnetic track layer, one space seed is output for each time two space seeds are input for the space seeds which are continuously input, the resistance state of the magnetic tunnel junction is reset, and the space seeds are represented as binary addition rules which are binary one by one, so that the internal accumulation operation can be directly realized, the calculation process is completely carried out based on the physical characteristics of the space seeds, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network calculation can be met. The pure spin electron system based on the magnetic spinelle completely has the characteristics of high speed and low power consumption of the spin electron device, and simultaneously has small physical size, so that higher storage and calculation density can be realized.
In a third aspect, the present application also provides a shift accumulator comprising the counter described above, and at least one additional input port. Each additional input port is connected to the magnetic track layer of one memory device, and at most one additional input port is connected to the magnetic track layer of one memory device, and each additional input port is used for inputting the Sjog dial to the magnetic track layer connected with the additional input port.
In the above-described scheme, by adopting a memory device comprising a magnetic track layer and a magnetic recording layer, by using whether or not the space in the magnetic recording layer region is provided with the space in the space, and the magnetic tunnel junction formed by the magnetic track layer and the magnetic recording layer has different resistance states, so that the storage is realized. And an erasing area is additionally arranged on the side surface of the magnetic track layer, one space seed is output for each time two space seeds are input for the space seeds which are continuously input, the resistance state of the magnetic tunnel junction is reset, and the space seeds are represented as binary addition rules which are binary one by one, so that the internal accumulation operation can be directly realized, the calculation process is completely carried out based on the physical characteristics of the space seeds, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network calculation can be met. The pure spin electron system based on the magnetic spinelle completely has the characteristics of high speed and low power consumption of the spin electron device, and simultaneously has small physical size, so that higher storage and calculation density can be realized.
In a specific embodiment, for each memory device to which additional input ports are connected, the additional input ports and the erase regions are arranged on opposite sides of the magnetic track layer, and the positions of the additional input ports and the erase regions are optimized.
In a specific embodiment, the top or bottom of the magnetic track layer of each memory device is also provided with a shunt port, which is used for keeping the current in the magnetic track layer constant at a set current value, so that the current in the magnetic track layer at the central position is kept unchanged when the reset, shift and accumulation operations are performed, and the normal operation of the device is ensured.
In a fourth aspect, the present application further provides an in-memory multiply-add structure, where the in-memory multiply-add structure includes: any one of the above-mentioned shift accumulators, and a plurality of cells distributed in an array, each memory cell being any one of the above-mentioned memory devices. The method comprises the steps that between any two adjacent memory computing devices in the same column of units, a space input port of one memory computing device is sequentially connected with a space output port of the other memory computing device, so that space in one memory computing device moves into the other memory computing device; and the sigma-delta output port of the memory device at the end position is connected to one additional input port in the shift accumulator. All cells on the same row are interconnected by the same wire to apply the same voltage in all cells of the same row. Each cell is capable of determining whether to generate a sterculia seed based on the magnitude of the voltage applied thereto and the resistance state of the magnetic tunnel junction therein, and flowing the generated sterculia seed into an additional input port connected to the cell after generating the sterculia seed.
In the scheme, the shift accumulator and a plurality of storage units are integrated together, so that binary multiplication, accumulation and shift operations can be completed, and the calculation requirement of vector matrix multiplication can be met. The binary multiplication, accumulation and shift operations are all directly implemented by inner multiplication and addition operation, the calculation process is completely based on the physical characteristics of the semen cassiae, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network calculation can be met. The pure spin electron system based on the magnetic spinelle completely has the characteristics of high speed and low power consumption of the spin electron device, and simultaneously has small physical size, so that higher storage and calculation density can be realized.
In a specific embodiment, each unit can determine whether to generate the sterculia according to the magnitude of the applied voltage and the resistance state of the unit, which is specifically as follows: when the resistance state of the magnetic tunnel junction in the unit is a high resistance state, no high voltage or low voltage is applied to the magnetic tunnel junction, and no Sjog seed is generated on the magnetic track layer; when the resistance state of the magnetic tunnel junction in the cell is a low resistance state, no sterculia seed is generated in the magnetic track layer if a low voltage is applied, and a sterculia seed can be generated in the magnetic track layer if a high voltage is applied. Facilitating the multiplication of each cell.
Drawings
Fig. 1 is a schematic perspective view of a memory device according to an embodiment of the present application;
FIG. 2 is a top view of the memory device shown in FIG. 1;
FIG. 3 is a schematic diagram of the movement of a semen Cassiae;
FIG. 4 is a schematic diagram of another movement of the semen Cassiae;
FIG. 5 is a cross-sectional view of a memory device according to an embodiment of the present application;
FIG. 6 is a diagram of a counter according to an embodiment of the present application;
FIG. 7 is a top view of the counter provided in FIG. 6;
FIG. 8 is a top view of a shifting accumulator according to an embodiment of the present application;
FIG. 9 is a side view of a shifting accumulator according to an embodiment of the present application;
FIG. 10 is a schematic perspective view of a memory multiply-add structure according to an embodiment of the present application;
FIG. 11 is a truth table of a binary multiplication of array cells in a memory multiply-add structure according to an embodiment of the present application.
Reference numerals:
10-memory device 11-magnetic track layer 111-heavy metal layer
112-magnetic layer 12-barrier layer 13-reference layer
14-erase region 15-magnetic recording layer region 20-counter
30-Shift accumulator 31-split port
32-additional input port 40-conductor
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order to facilitate understanding of the memory device provided by the embodiment of the present application, an application scenario of the memory device provided by the embodiment of the present application is first described below, where the memory device is applied to a storage and operation process in a computer field. The memory device is described in detail below with reference to the accompanying drawings.
Referring to fig. 1, 2 and 3, the memory device according to the embodiment of the present application includes a magnetic track layer 11 and a magnetic recording layer. The magnetic track layer 11 is used for inputting and outputting the cassia seeds and also is used for enabling the cassia seeds in the magnetic track layer to exist and move stably. The magnetic recording layer includes a barrier layer 12 laminated on the surface of the magnetic track layer 11, and a reference layer 13 laminated on the barrier layer 12. The magnetic track layer 11 and the magnetic recording layer form a magnetic tunnel junction, and the region of the magnetic track layer 11 overlapping the barrier layer 12 is a magnetic recording layer region 15. The magnetization direction of the magnetic track layer 11 is opposite to that of the reference layer 13; in the absence of the stigmine in the magnetic recording layer region 15, the resistance state of the magnetic tunnel junction is a high resistance state; when the Sjog seed input into the magnetic track layer 11 moves to the magnetic recording layer region 15, it is pinned by the magnetic recording layer in the magnetic recording layer region 15 to change the resistance state of the magnetic tunnel junction from a high resistance state to a low resistance state.
In the above-described scheme, by adopting the memory device comprising the magnetic track layer 11 and the magnetic recording layer, the storage is realized by utilizing the characteristic that the magnetic tunnel junction resistance states of the magnetic track layer 11 and the magnetic recording layer are different due to the presence or absence of the stop seed in the magnetic recording layer region 15. Compared with the prior art, the memory device disclosed by the application is based on a pure spin electron system of the magnetic Sjogren and has the characteristics of high speed and low power consumption of the spin electron device, and meanwhile, the memory device has small physical size and can realize higher storage density. The arrangement of the above structures will be described in detail with reference to the accompanying drawings.
As shown in fig. 1, 2 and 3, the magnetic track layer 11 is used for inputting and outputting the cassia seed, and is also used for stabilizing the existence and movement of the cassia seed therein. When the magnetic track layer 11 is set, the magnetic track layer may include a stink input port and a stink output port, and when the stink needs to be input into the magnetic track layer 11, the stink can be input from the stink input port.
In the case where the stable presence of the spinodal seed inputted thereto is embodied, referring to fig. 5, the magnetic track layer 11 may include a heavy metal layer 111 and a magnetic layer 112 stacked, and the barrier layer 12 is stacked on the surface of the magnetic layer 112. The interface coupling between the heavy metal layer 111 and the magnetic layer 112 generates DMI effect, and the steady existence of the singe seed in the magnetic track layer 11 is enabled. The spin orbit torque effect of the heavy metal layer 111 and the magnetic layer 112 drives the movement of the Sjogren in the magnetic orbit layer 11, so that the Sjogren in the magnetic orbit layer 11 can stably exist and move. Two current-carrying ports may be further provided in the magnetic track layer 11, and a current may be supplied from the two current-carrying ports to the magnetic track layer 11, thereby driving the movement of the schmitt within the magnetic track layer 11. When the structure is specifically set, the input port and the output port of the Sjog seed can be respectively overlapped with the two power-on ports on the magnetic track layer 11, so that the structure of the magnetic track layer 11 is optimized, and the track movement route of the Sjog seed is optimized. The magnetic track layer 11 shown in fig. 1 and 2 has a T-shaped cross-section. Two ends of the linear track of the T-shaped magnetic track layer 11 are provided with an energizing port in a distributed manner, so that the Sjog seed input port and the Sjog seed output port are respectively overlapped with the two energizing ports of the magnetic track layer 11. Specifically, the a port and the B port of the magnetic track layer 11 shown in fig. 2 are respectively provided with an energizing port for energizing the magnetic track layer 11 with electric current. Meanwhile, the end A is also provided with a Sjog seed output port, and the end B is also provided with a Sjog seed input port. When current is introduced into the end A and the end B, the stigman seeds can be driven to move from the end A to the end B. It should be understood that the arrangement of the magnetic track layer 11 is not limited to the arrangement shown above, but other arrangements may be used. For example, the magnetic track layer 11 having a rectangular cross-sectional shape may be used.
With continued reference to fig. 1, when a magnetic recording layer is provided, the magnetic recording layer includes a barrier layer 12 laminated on the surface of a magnetic track layer 11, and a reference layer 13 laminated on the barrier layer 12, wherein the magnetic track layer 11 and the magnetic recording layer form a magnetic tunnel junction. And the magnetization directions of the magnetic track layer 11 and the reference layer 13 are opposite so that the magnetic track layer 11 can pin-fix the sigma seed to a region overlapping the barrier layer 12 when the sigma seed moves to the region. This region is defined as a magnetic recording layer region 15, which is located in the magnetic track layer 11 and overlaps the barrier layer 12. When the magnetization directions of the reference layer 13 and the magnetic track layer 11 are opposite, referring to fig. 5, the magnetic anisotropies of the magnetic track layer 11 and the reference layer 13 can be perpendicular magnetic anisotropies, so that pinning movement to the region 15 of the magnetic recording layer is facilitated. For example, the magnetization direction in the magnetic track layer 11 may be made to be the perpendicular magnetization direction downward, and the magnetization direction in the reference layer 13 may be made to be the perpendicular magnetization direction upward, so that the perpendicular magnetization directions in the magnetic track layer 11 and the reference layer 13 are disposed opposite to each other. Of course, it is also possible to set the magnetization direction in the magnetic track layer 11 to be perpendicular magnetization direction upward and the magnetization direction in the reference layer 13 to be perpendicular magnetization direction downward, so that the perpendicular magnetization directions in the magnetic track layer 11 and the reference layer 13 are disposed opposite to each other.
Referring to fig. 3, in the absence of the stigmine in the magnetic recording layer region 15, the resistance state of the magnetic tunnel junction is a high resistance state, i.e., a high resistance state exhibited by the antiparallel magnetization directions of the reference layer 13 and the magnetic track layer 11. When the Sjog seed input into the magnetic track layer 11 moves to the magnetic recording layer region 15, the Sjog seed is pinned in the magnetic recording layer region 15 by the magnetic recording layer to change the resistance state of the magnetic tunnel junction from a high resistance state to a low resistance state. The input of the spines can be performed from the B port of fig. 2, and when the spines move to the magnetic recording layer region 15, the input spines stay in the magnetic recording layer region 15, and the resistance of the magnetic tunnel junction changes from the high resistance state to the low resistance state. I.e., whether or not the magnetic recording layer region 15 has a stopper at both ends of the magnetic tunnel junction. When the magnetic recording layer region 15 does not contain the stigmine, the magnetic tunnel junction has a large resistance and exhibits a high resistance state; when the magnetic recording layer region 15 has the stigmine, the magnetic tunnel junction has a small resistance and exhibits a low resistance. The resistance state information of the magnetic tunnel junction can be read through either one of the top port of the magnetic recording layer and the magnetic track layer 11. Storage is realized by utilizing the characteristic that the magnetic tunnel junction resistance state formed by the magnetic track layer 11 and the magnetic recording layer is different in size due to the presence or absence of the Sjog seed in the magnetic recording layer region 15. Compared with the prior art, the memory device disclosed by the application is based on a pure spin electron system of the magnetic Sjogren and has the characteristics of high speed and low power consumption of the spin electron device, and meanwhile, the memory device has small physical size and can realize higher storage density.
In addition, as shown in fig. 1 and 2, the memory device may further include an erasing area 14 located at a side of the magnetic track layer 11, and the erasing area 14 is used for erasing the stevensite entered therein, so as to integrate a counting function in the memory device. Specifically, referring to fig. 4, when the fixed spinodal region 15 exists in the magnetic recording layer region 15, if the operation of the spinodal region 11 is continuously performed by the spinodal region on the magnetic track layer 11, the moving spinodal region can collide with the fixed spinodal region originally existing in the magnetic recording layer region 15, and the fixed spinodal region originally existing in the magnetic recording layer region 15 enters the erasing region 14, and the moving spinodal region itself is output from the spinodal output port, so that the spinodal region does not exist in the magnetic recording layer region 15, and the low resistance state of the magnetic tunnel junction is changed into the high resistance state. For example, referring to fig. 4, when the stopper is inputted from the B port, when the stopper is present in the magnetic recording layer region 15, the inputted stopper collides with the stopper pinned to the magnetic recording layer region 15, the stopper originally present in the magnetic recording layer region 15 is pushed into the erase region 14, and is outputted from the a port, and the magnetic tunnel junction is changed from the low resistance state to the high resistance state. That is, when the erasing area 14 is added on the side surface of the magnetic track layer 11, for continuously input space seeds, one space seed is output every two space seeds are input, and the resistance state of the magnetic tunnel junction is reset, which is specifically expressed as a binary addition rule of every two space seeds, so that the internal accumulation operation can be directly implemented, the calculation process is completely based on the physical characteristics of the space seeds, the conversion of digital signals and analog signals is not needed, the requirements of high-precision and low-power-consumption neural network calculation can be met, and the higher calculation density can be realized.
Referring to fig. 1 and 2, when the cross-sectional shape of the magnetic tunnel layer is T-shaped, the remaining third ends of the T-shaped magnetic track layer 11 except for the two ends of the straight track may be distributed with erasing areas 14 to optimize the structure of the magnetic track layer 11 and the track movement path of the stellera seed.
Further, a power-on port may be provided in the erase region 14. When a current flows into the power-on port of the erase region 14, the stopper of the magnetic recording layer region 15 can be outputted from the stopper output port, that is, by inputting a current to the power-on port of the erase region 14, the stopper of the magnetic recording layer region 15 can be outputted from the stopper output port to perform a shift operation. When a current flows through the conduction port of the erase region 14, the stopper of the magnetic recording layer region 15 can be erased, and the stopper of the magnetic recording layer region 15 can be reset directly. Referring to fig. 2, the power-on port may be provided at the C port of the magnetic track layer 11. When a current flows into the C-port, the stopper of the magnetic recording layer region 15 can be outputted from the stopper output port of the magnetic track layer 11. When current flows through the C-port, the sigma-delta of the magnetic recording layer region 15 can be erased. By providing a power-on port in the erase region 14, the stigmas within the memory cell are output or erased.
In addition, an embodiment of the present application further provides a counter, referring to fig. 1, fig. 2, fig. 6 and fig. 7, where the counter includes: a plurality of memory devices 10 each including an erase region 14 arranged in sequence. Between any two adjacent memory devices 10, the output port of the memory device 10 is connected to the output port of the memory device 10, so that the output port of the memory device 10 can move into the output port of the memory device 10. By adopting the memory device 10 comprising the magnetic track layer 11 and the magnetic recording layer, the memory is realized by utilizing the characteristic that the magnetic tunnel junction formed by the magnetic track layer 11 and the magnetic recording layer has different resistance states due to the presence or absence of the Sjog seed in the magnetic recording layer region 15. The erasing area 14 is further added on the side surface of the magnetic track layer 11, for continuously input space seeds, one space seed is output every two space seeds are input, the resistance state of the magnetic tunnel junction is reset, and the binary addition rule is displayed every two times, so that the internal calculation operation can be directly realized, the calculation process is completely carried out based on the physical characteristics of the space seeds, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network calculation can be met. The pure spin electron system based on the magnetic spinelle completely has the characteristics of high speed and low power consumption of the spin electron device, and simultaneously has small physical size, so that higher storage and calculation density can be realized.
As shown in fig. 6 and 7, the plurality of memory devices 10 are sequentially arranged, and the stokes input ports and the stokes output ports of two adjacent memory devices 10 are connected. The singe seed may be input from one memory device 10 to another memory device 10 without conversion. End positions of both sides of the counterEach of which includes two power ports A, B. Wherein the B end is also a Sjog seed input port, and the A end is also a Sjog seed output port. And current is introduced into a A, B port, so that the stigman seeds can move from the end B to the end A. Because of the memory device 10 including the erase region 14, which has the property of going every two times, the counter can count the number of input stigmas. The count results are represented by the resistance states of Magnetic Tunnel Junctions (MTJs) in the memory device 10 in different locations, a low resistance state may represent a binary 1 and a high resistance state may represent a binary 0. The resistance states of the magnetic tunnel junctions at different locations represent bits of a binary number. As shown in FIG. 7, the resistance states of the magnetic tunnel junctions sequentially represent 2 from the B-terminal to the A-terminal 0 ，2 1 ,…，2 n-1 Bits.
Furthermore, the present application provides a shift accumulator, referring to fig. 1, 2, 6, 7 and 8, which includes the counter 20 and at least one additional input port 32. Each additional input port 32 is connected to the magnetic track layer 11 of one memory device 10, and at most one additional input port 32 is connected to the magnetic track layer 11 of one memory device 10, and each additional input port 32 is used for inputting a sigma seed to the magnetic track layer 11 connected thereto. By adopting the memory device 10 comprising the magnetic track layer 11 and the magnetic recording layer, the memory is realized by utilizing the characteristic that the magnetic tunnel junction formed by the magnetic track layer 11 and the magnetic recording layer has different resistance states due to the presence or absence of the Sjog seed in the magnetic recording layer region 15. The erasing area 14 is further added on the side surface of the magnetic track layer 11, for continuously input space seeds, one space seed is output every two space seeds are input, the resistance state of the magnetic tunnel junction is reset, and the binary addition rule of every two space seeds is expressed, so that the internal accumulation operation can be directly realized, the calculation process is completely carried out based on the physical characteristics of the space seeds, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network calculation can be met. The pure spin electron system based on the magnetic spinelle completely has the characteristics of high speed and low power consumption of the spin electron device, and simultaneously has small physical size, so that higher storage and calculation density can be realized.
In setting the additional input ports 32, for each memory device 10 to which the additional input ports 32 are connected, the additional input ports 32 and the erase regions 14 may be arranged on opposite sides of the magnetic track layer 11, optimizing the setting positions of the additional input ports 32 and the erase regions 14.
A shift accumulator as shown in fig. 9, comprising the counter 20 provided above. And n additional input ports 32 are additionally arranged on the counter 20 on the side surface of the magnetic track layer 11 opposite to the erasing area 14, and the n additional input ports 32 are sequentially D 0 -D n-1 . The two end parts of the shift accumulator are respectively provided with a power-on port A and a power-on port B, wherein the end B is also a Stokes input port, and the end A is also a Stokes output port. And current is introduced into the end A, B, so that the stigman seeds can move from the end B to the end A. Port D 0 -D n-1 Is the extra input port 32 of the sigma-delta, and the current input from the extra input port can cause the sigma-delta to enter the magnetic track in the middle position from the extra input port 32. Additional input port 32D 0 -D n-1 The inputs of (a) respectively correspond to different weights, and respectively represent 2 from the end B to the end A 0 ，2 1 ,…， 2 n-1 Bits. The accumulated result is represented by the resistance states of the magnetic tunnel junctions in the different bit memory cells, the low resistance state may represent a binary 1 and the high resistance state may represent a binary 0. The resistance states of the magnetic tunnel junctions at different locations represent bits of a binary number. As shown in FIG. 9, the resistance states of the magnetic tunnel junctions sequentially represent 2 from the B-terminal to the A-terminal 0 ，2 1 ,…，2 n-1 Bits.
Referring to fig. 9, the erase region 14 is provided with power-on ports C in this order 0 -C n-1 . When current flows from the power-on port of the erase region 14, the stigmas within the magnetic tunnel junction in the corresponding memory device 10 may be erased. When current flows into the power-on port of the erase region 14, the corresponding stigma seed in the magnetic tunnel junction in the memory device 10 may be output to the next bit. When C 0 -C n-1 All memory devices when current is simultaneously flowingThe spines in the magnetic tunnel junction in the device 10 are erased and can be considered a reset operation. When C 0 -C n-1 While current is flowing, the stigmas in the magnetic tunnel junctions in all memory devices 10 are shifted left by one bit, which can be considered a shift operation.
Referring to fig. 9, a shunt port 31 may be further disposed on the top or bottom of the magnetic track layer 11 of each memory device 10, so as to keep the current in the magnetic track layer 11 constant at a set current value, so as to keep the current in the magnetic track layer 11 at the central position unchanged during the reset, shift and accumulation operations, and ensure the normal operation of the device.
In addition, the embodiment of the present application further provides a memory multiply-add structure, referring to fig. 1, fig. 2, fig. 6, fig. 7, fig. 8, and fig. 10, where the memory multiply-add structure includes: any one of the above-described shift accumulators 30, and a plurality of cells distributed in an array, each memory cell being any one of the above-described memory devices 10. Between any two adjacent memory devices 10 of the same column unit, the output port of the space seed of one memory device 10 is sequentially connected with the output port of the space seed of the other memory device 10, so that the space seed in one memory device 10 moves into the other memory device 10; and the sigma-delta output port of the memory device 10 in the end position is connected to one additional input port 32 in the shift accumulator 30. All cells on the same row are interconnected by the same wire 40 to apply the same voltage in all cells of the same row. Each cell is able to determine whether to generate a sterculia seed based on the magnitude of the voltage it is applied to and the resistance state of the magnetic tunnel junction within it, and after generating a sterculia seed, flow the generated sterculia seed into an additional input port 32 connected to the cell. By integrating the shift accumulator 30 and the plurality of memory units together, binary multiplication, accumulation and shift operations can be completed, and the computational requirements of vector matrix multiplication can be satisfied. The binary multiplication, accumulation and shift operations are all directly implemented by inner multiplication and addition operation, the calculation process is completely based on the physical characteristics of the semen cassiae, the conversion of digital signals and analog signals is not needed, and the requirements of high-precision and low-power-consumption neural network calculation can be met. The pure spin electron system based on the magnetic spinelle completely has the characteristics of high speed and low power consumption of the spin electron device, and simultaneously has small physical size, so that higher storage and calculation density can be realized.
A memory multiply-add structure as shown in fig. 10, the memory multiply-add result comprising a shift accumulator 30 as shown above and also comprising a plurality of cells arranged in an array in a row-column distribution. Each of which includes the memory device 10 shown above. Referring to fig. 10, the memory device 10 may not be like the T-shaped magnetic track layer 11 shown in fig. 1, but may employ a rectangular magnetic track layer 11 having a rectangular shape. Between the memory devices 10 on the same column, the output ports of the adjacent two memory devices 10 are sequentially connected with the output ports of the adjacent two memory devices, and the output port of the adjacent memory device is connected to an additional input port 32 of the shift accumulator 30. The cells in the same row are all interconnected by the same wire 40 so that the same voltage can be applied across all cells in the same row. Each cell can store weight information by changing the magnetization direction of the reference layer 13. And each cell can decide whether or not to generate a stigman seed on the magnetic track layer 11 therein based on the magnitude of the applied voltage and the weight information. If the applied voltage and the resistance state of the magnetic tunnel junction in memory device 10 are considered to be two inputs, this operation may be considered as a binary multiplication of the voltage applied to conductor 40 and the resistance value of the magnetic tunnel junction in the memory cell. The space-time shifting and accumulating operation of the space-time shifting and accumulating unit can be realized by the space-time shifting and accumulating unit 30, so that the space-time multiplying and accumulating unit can complete the space-time multiplying, accumulating and shifting operation and can meet the calculation requirement of vector matrix multiplication. In addition, referring to fig. 10, the number of memory devices 10 included on the shift accumulator 30 may be made greater than the number of additional input ports 32, thereby preventing errors in operations due to overflow of data bits during accumulation.
Each cell may employ a truth table scheme as shown in fig. 11 when determining whether to generate the stigmine, depending on the magnitude of the applied voltage and its resistance state. Specifically, when the resistance state of the magnetic tunnel junction in the cell is a high resistance state, no stop seed is generated in the magnetic track layer 11 regardless of whether a high voltage or a low voltage is applied. When the resistance state of the magnetic tunnel junction in the cell is a low resistance state, no sterculia seed is generated in the magnetic track layer 11 if a low voltage is applied, and a sterculia seed can be generated in the magnetic track layer 11 if a high voltage is applied. Facilitating the multiplication of each cell. It should be understood that the manner in which each cell determines whether to generate the cassia seed according to the applied voltage and the resistance state thereof is not limited to the above-described manner, and other manners may be adopted.
The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present application should be included in the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.
Claims (12)
1. A memory device, comprising:
the magnetic track layer is used for inputting and outputting the cassia seeds and also used for enabling the cassia seeds in the magnetic track layer to exist and move stably;
a magnetic recording layer including a barrier layer laminated on a surface of the magnetic track layer, and a reference layer laminated on the barrier layer; the magnetic track layer and the magnetic recording layer form a magnetic tunnel junction, and the area overlapped with the barrier layer in the magnetic track layer is a magnetic recording layer area;
the magnetization directions of the magnetic track layer and the reference layer are opposite; when the magnetic recording layer area does not exist the stigmine, the resistance state of the magnetic tunnel junction is a high resistance state; when the Sjog seed input into the magnetic track layer moves to the magnetic recording layer area, the Sjog seed is pinned in the magnetic recording layer area by the magnetic recording layer to change the resistance state of the magnetic tunnel junction from the high resistance state to the low resistance state.
2. The memory device of claim 1, further comprising: an erasing area located at the side of the magnetic track layer for erasing the Sjog seed entered therein;
the magnetic track layer is provided with a Sjog seed input port and a Sjog seed output port;
when fixed stoneley is present in the magnetic recording layer region, the fixed stoneley can be bumped into the erasing region by the moving stoneley input through the stoneley input port, and the moving stoneley can be output from the stoneley output port.
3. The memory device of claim 2, wherein the erase region is provided with a power-on port;
when the current flows into the energizing port of the erasing area, the Sjog dial of the magnetic recording layer area can be output from the Sjog dial output port;
and when the current flows out of the energizing port of the erasing area, the Sjog dial of the magnetic recording layer area can be erased.
4. The memory device of claim 2, wherein the magnetic track layer comprises a stack of heavy metal layers and a magnetic layer, the barrier layer being stacked on a surface of the magnetic layer;
the heavy metal layer and the magnetic layer are coupled at the interface to generate a DMI effect, so that the Sjogren in the magnetic track layer can exist stably;
and the heavy metal layer and the magnetic layer have a spin orbit moment effect to drive the movement of the Sjogren in the magnetic orbit layer.
5. The memory device of claim 2, wherein the magnetic rail layer has a T-shaped cross-sectional shape;
two ends of the linear track of the T-shaped magnetic track layer are provided with an energizing port in a distributed manner; the Sjog seed input port and the Sjog seed output port are respectively overlapped with the two power-on ports of the magnetic track layer;
the erasing area is distributed on the remaining third ends of the T-shaped magnetic track layer.
6. The memory device of claim 2, wherein the magnetic anisotropy of the magnetic rail layer and the reference layer are perpendicular magnetic anisotropies.
7. A counter, comprising: a plurality of sequentially arranged memory devices according to any one of claims 2 to 6;
between any two adjacent memory devices, the output port of the memory device is connected with the output port of the memory device, to enable movement of the streetseed in said one of the memory devices into said other memory device.
8. A shift accumulator, comprising:
the counter of claim 7;
at least one additional input port, each additional input port is connected to the magnetic track layer of one memory device, and at most one additional input port is connected to the magnetic track layer of one memory device, and each additional input port is used for inputting the Sjog dial to the magnetic track layer connected with the additional input port.
9. The shift accumulator of claim 8, wherein for each memory device to which the additional input port is connected, the additional input port is listed on opposite sides of the magnetic track layer from the erase region.
10. The shift accumulator of claim 9, wherein a top or bottom of a magnetic track layer of each memory device is further provided with a shunt port for keeping a current in the magnetic track layer constant at a set current value.
11. A present multiply-add structure, comprising:
a shift accumulator as claimed in any one of claims 8 to 10;
a plurality of cells distributed in an array, wherein each memory cell is a memory device as claimed in any one of claims 1 to 6;
the method comprises the steps that between any two adjacent memory devices in the same column of units, a space input port of one memory device is sequentially connected with a space output port of the other memory device, so that space in the one memory device moves into the other memory device; and a sigma-delta output port of the memory device at an end position, connected to one additional input port in the shift accumulator;
all cells on the same row are interconnected by the same wire to apply the same voltage in all cells of the same row;
each cell can determine whether to generate a sterculia seed based on the magnitude of the voltage applied thereto and the resistance state of the magnetic tunnel junction therein, and after generating the sterculia seed, can flow the generated sterculia seed into an additional input port connected to the cell.
12. The memory multiply-add structure of claim 11, wherein each cell is capable of determining whether to generate a stratoside based on the magnitude of the applied voltage and its resistance state, specifically:
when the resistance state of the magnetic tunnel junction in the unit is a high resistance state, no high voltage or low voltage is applied to the magnetic tunnel junction, and no stigman seeds are generated on the magnetic track layer;
when the resistance state of the magnetic tunnel junction in the unit is a low resistance state, if a low voltage is applied, no stigman seeds are generated in the magnetic track layer; if a high voltage is applied, a stigman seed can be generated in the magnetic track layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210279290.2A CN116820390A (en) | 2022-03-21 | 2022-03-21 | Memory computing device, counter, shift accumulator and memory multiply-add structure |
| PCT/CN2022/082726 WO2023178596A1 (en) | 2022-03-21 | 2022-03-24 | Storage and computing device, counter, shift accumulator, and in-memory multiply-accumulate structure |
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| CN202210279290.2A CN116820390A (en) | 2022-03-21 | 2022-03-21 | Memory computing device, counter, shift accumulator and memory multiply-add structure |
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| JP6712804B2 (en) * | 2016-11-18 | 2020-06-24 | 国立研究開発法人理化学研究所 | Magnetic element, skyrmion memory, central arithmetic processing LSI equipped with skyrmion memory, data recording device, data processing device and data communication device |
| KR101924723B1 (en) * | 2017-06-07 | 2018-12-03 | 재단법인대구경북과학기술원 | Skyrmion Memory Device |
| CN107846215B (en) * | 2017-10-31 | 2020-07-28 | 华中科技大学 | Reconfigurable logic device based on magnetic sigecum |
| CN109902822B (en) * | 2019-03-07 | 2021-04-06 | 北京航空航天大学合肥创新研究院 | Memory computing system and method based on Sgimenk track storage |
| CN111427539B (en) * | 2020-03-20 | 2022-12-23 | 北京航空航天大学 | Random data stream computing system and computing control method based on siganmin |
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